2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
43 * URB - uniform resource buffer. A mid-sized buffer which is
44 * partitioned between the fixed function units and used for passing
45 * values (vertices, primitives, constants) between them.
47 * CURBE - constant URB entry. An urb region (entry) used to hold
48 * constant values which the fixed function units can be instructed to
49 * preload into the GRF when spawning a thread.
51 * VUE - vertex URB entry. An urb entry holding a vertex and usually
52 * a vertex header. The header contains control information and
53 * things like primitive type, Begin/end flags and clip codes.
55 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
56 * unit holding rasterization and interpolation parameters.
58 * GRF - general register file. One of several register files
59 * addressable by programmed threads. The inputs (r0, payload, curbe,
60 * urb) of the thread are preloaded to this area before the thread is
61 * spawned. The registers are individually 8 dwords wide and suitable
62 * for general usage. Registers holding thread input values are not
63 * special and may be overwritten.
65 * MRF - message register file. Threads communicate (and terminate)
66 * by sending messages. Message parameters are placed in contiguous
67 * MRF registers. All program output is via these messages. URB
68 * entries are populated by sending a message to the shared URB
69 * function containing the new data, together with a control word,
70 * often an unmodified copy of R0.
72 * R0 - GRF register 0. Typically holds control information used when
73 * sending messages to other threads.
75 * EU or GEN4 EU: The name of the programmable subsystem of the
76 * i965 hardware. Threads are executed by the EU, the registers
77 * described above are part of the EU architecture.
79 * Fixed function units:
81 * CS - Command streamer. Notional first unit, little software
82 * interaction. Holds the URB entries used for constant data, ie the
85 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
86 * this unit is responsible for pulling vertices out of vertex buffers
87 * in vram and injecting them into the processing pipe as VUEs. If
88 * enabled, it first passes them to a VS thread which is a good place
89 * for the driver to implement any active vertex shader.
91 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
92 * enabled, incoming strips etc are passed to GS threads in individual
93 * line/triangle/point units. The GS thread may perform arbitary
94 * computation and emit whatever primtives with whatever vertices it
95 * chooses. This makes GS an excellent place to implement GL's
96 * unfilled polygon modes, though of course it is capable of much
97 * more. Additionally, GS is used to translate away primitives not
98 * handled by latter units, including Quads and Lineloops.
100 * CS - Clipper. Mesa's clipping algorithms are imported to run on
101 * this unit. The fixed function part performs cliptesting against
102 * the 6 fixed clipplanes and makes descisions on whether or not the
103 * incoming primitive needs to be passed to a thread for clipping.
104 * User clip planes are handled via cooperation with the VS thread.
106 * SF - Strips Fans or Setup: Triangles are prepared for
107 * rasterization. Interpolation coefficients are calculated.
108 * Flatshading and two-side lighting usually performed here.
110 * WM - Windower. Interpolation of vertex attributes performed here.
111 * Fragment shader implemented here. SIMD aspects of EU taken full
112 * advantage of, as pixels are processed in blocks of 16.
114 * CC - Color Calculator. No EU threads associated with this unit.
115 * Handles blending and (presumably) depth and stencil testing.
119 #define BRW_MAX_CURBE (32*16)
125 BRW_STATE_FRAGMENT_PROGRAM
,
126 BRW_STATE_VERTEX_PROGRAM
,
127 BRW_STATE_INPUT_DIMENSIONS
,
128 BRW_STATE_CURBE_OFFSETS
,
129 BRW_STATE_REDUCED_PRIMITIVE
,
132 BRW_STATE_WM_INPUT_DIMENSIONS
,
134 BRW_STATE_WM_SURFACES
,
135 BRW_STATE_VS_BINDING_TABLE
,
136 BRW_STATE_GS_BINDING_TABLE
,
137 BRW_STATE_PS_BINDING_TABLE
,
141 BRW_STATE_NR_WM_SURFACES
,
142 BRW_STATE_NR_VS_SURFACES
,
143 BRW_STATE_INDEX_BUFFER
,
144 BRW_STATE_VS_CONSTBUF
,
145 BRW_STATE_WM_CONSTBUF
,
146 BRW_STATE_PROGRAM_CACHE
,
147 BRW_STATE_STATE_BASE_ADDRESS
,
150 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
151 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
152 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
153 #define BRW_NEW_INPUT_DIMENSIONS (1 << BRW_STATE_INPUT_DIMENSIONS)
154 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
155 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
156 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
157 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
158 #define BRW_NEW_WM_INPUT_DIMENSIONS (1 << BRW_STATE_WM_INPUT_DIMENSIONS)
159 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
160 #define BRW_NEW_WM_SURFACES (1 << BRW_STATE_WM_SURFACES)
161 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
162 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
163 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
164 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
165 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
167 * Used for any batch entry with a relocated pointer that will be used
168 * by any 3D rendering.
170 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
171 /** \see brw.state.depth_region */
172 #define BRW_NEW_NR_WM_SURFACES (1 << BRW_STATE_NR_WM_SURFACES)
173 #define BRW_NEW_NR_VS_SURFACES (1 << BRW_STATE_NR_VS_SURFACES)
174 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
175 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
176 #define BRW_NEW_WM_CONSTBUF (1 << BRW_STATE_WM_CONSTBUF)
177 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
178 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
180 struct brw_state_flags
{
181 /** State update flags signalled by mesa internals */
184 * State update flags signalled as the result of brw_tracked_state updates
187 /** State update flags signalled by brw_state_cache.c searches */
191 enum state_struct_type
{
192 AUB_TRACE_VS_STATE
= 1,
193 AUB_TRACE_GS_STATE
= 2,
194 AUB_TRACE_CLIP_STATE
= 3,
195 AUB_TRACE_SF_STATE
= 4,
196 AUB_TRACE_WM_STATE
= 5,
197 AUB_TRACE_CC_STATE
= 6,
198 AUB_TRACE_CLIP_VP_STATE
= 7,
199 AUB_TRACE_SF_VP_STATE
= 8,
200 AUB_TRACE_CC_VP_STATE
= 0x9,
201 AUB_TRACE_SAMPLER_STATE
= 0xa,
202 AUB_TRACE_KERNEL_INSTRUCTIONS
= 0xb,
203 AUB_TRACE_SCRATCH_SPACE
= 0xc,
204 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= 0xd,
206 AUB_TRACE_SCISSOR_STATE
= 0x15,
207 AUB_TRACE_BLEND_STATE
= 0x16,
208 AUB_TRACE_DEPTH_STENCIL_STATE
= 0x17,
210 /* Not written to .aub files the same way the structures above are. */
211 AUB_TRACE_NO_TYPE
= 0x100,
212 AUB_TRACE_BINDING_TABLE
= 0x101,
213 AUB_TRACE_SURFACE_STATE
= 0x102,
214 AUB_TRACE_VS_CONSTANTS
= 0x103,
215 AUB_TRACE_WM_CONSTANTS
= 0x104,
218 /** Subclass of Mesa vertex program */
219 struct brw_vertex_program
{
220 struct gl_vertex_program program
;
222 GLboolean use_const_buffer
;
226 /** Subclass of Mesa fragment program */
227 struct brw_fragment_program
{
228 struct gl_fragment_program program
;
229 GLuint id
; /**< serial no. to identify frag progs, never re-used */
231 /** for debugging, which texture units are referenced */
232 GLbitfield tex_units_used
;
236 struct gl_shader base
;
238 /** Shader IR transformed for native compile, at link time. */
239 struct exec_list
*ir
;
242 struct brw_shader_program
{
243 struct gl_shader_program base
;
246 enum param_conversion
{
254 /* Data about a particular attempt to compile a program. Note that
255 * there can be many of these, each in a different GL state
256 * corresponding to a different brw_wm_prog_key struct, with different
259 struct brw_wm_prog_data
{
260 GLuint curb_read_length
;
261 GLuint urb_read_length
;
263 GLuint first_curbe_grf
;
264 GLuint first_curbe_grf_16
;
266 GLuint reg_blocks_16
;
267 GLuint total_scratch
;
269 GLuint nr_params
; /**< number of float params/constants */
270 GLuint nr_pull_params
;
273 uint32_t prog_offset_16
;
275 /* Pointer to tracked values (only valid once
276 * _mesa_load_state_parameters has been called at runtime).
278 const float *param
[MAX_UNIFORMS
* 4]; /* should be: BRW_MAX_CURBE */
279 enum param_conversion param_convert
[MAX_UNIFORMS
* 4];
280 const float *pull_param
[MAX_UNIFORMS
* 4];
281 enum param_conversion pull_param_convert
[MAX_UNIFORMS
* 4];
285 * Enum representing the i965-specific vertex results that don't correspond
286 * exactly to any element of gl_vert_result. The values of this enum are
287 * assigned such that they don't conflict with gl_vert_result.
291 BRW_VERT_RESULT_NDC
= VERT_RESULT_MAX
,
292 BRW_VERT_RESULT_HPOS_DUPLICATE
,
293 BRW_VERT_RESULT_CLIP0
,
294 BRW_VERT_RESULT_CLIP1
,
301 * Data structure recording the relationship between the gl_vert_result enum
302 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
303 * single octaword within the VUE (128 bits).
305 * Note that each BRW register contains 256 bits (2 octawords), so when
306 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
307 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
308 * in a vertex shader), each register corresponds to a single VUE slot, since
309 * it contains data for two separate vertices.
313 * Map from gl_vert_result value to VUE slot. For gl_vert_results that are
314 * not stored in a slot (because they are not written, or because
315 * additional processing is applied before storing them in the VUE), the
318 int vert_result_to_slot
[BRW_VERT_RESULT_MAX
];
321 * Map from VUE slot to gl_vert_result value. For slots that do not
322 * directly correspond to a gl_vert_result, the value comes from
325 * For slots that are not in use, the value is BRW_VERT_RESULT_MAX (this
326 * simplifies code that uses the value stored in slot_to_vert_result to
327 * create a bit mask).
329 int slot_to_vert_result
[BRW_VERT_RESULT_MAX
];
332 * Total number of VUE slots in use
337 struct brw_sf_prog_data
{
338 GLuint urb_read_length
;
341 /* Each vertex may have upto 12 attributes, 4 components each,
342 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
345 * Actually we use 4 for each, so call it 12 rows.
347 GLuint urb_entry_size
;
350 struct brw_clip_prog_data
{
351 GLuint curb_read_length
; /* user planes? */
353 GLuint urb_read_length
;
357 struct brw_gs_prog_data
{
358 GLuint urb_read_length
;
362 struct brw_vs_prog_data
{
363 GLuint curb_read_length
;
364 GLuint urb_read_length
;
366 GLbitfield64 outputs_written
;
367 GLuint nr_params
; /**< number of float params/constants */
368 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
369 GLuint total_scratch
;
373 /* Used for calculating urb partitions:
375 GLuint urb_entry_size
;
377 const float *param
[MAX_UNIFORMS
* 4]; /* should be: BRW_MAX_CURBE */
378 const float *pull_param
[MAX_UNIFORMS
* 4];
380 bool uses_new_param_layout
;
384 /* Size == 0 if output either not written, or always [0,0,0,1]
386 struct brw_vs_ouput_sizes
{
387 GLubyte output_size
[VERT_RESULT_MAX
];
391 /** Number of texture sampler units */
392 #define BRW_MAX_TEX_UNIT 16
394 /** Max number of render targets in a shader */
395 #define BRW_MAX_DRAW_BUFFERS 8
398 * Size of our surface binding table for the WM.
399 * This contains pointers to the drawing surfaces and current texture
400 * objects and shader constant buffers (+2).
402 #define BRW_WM_MAX_SURF (BRW_MAX_DRAW_BUFFERS + BRW_MAX_TEX_UNIT + 1)
405 * Helpers to convert drawing buffers, textures and constant buffers
406 * to surface binding table indexes, for WM.
408 #define SURF_INDEX_DRAW(d) (d)
409 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS)
410 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 1 + (t))
413 * Size of surface binding table for the VS.
414 * Only one constant buffer for now.
416 #define BRW_VS_MAX_SURF 1
419 * Only a VS constant buffer
421 #define SURF_INDEX_VERT_CONST_BUFFER 0
426 BRW_DEPTH_STENCIL_STATE
,
427 BRW_COLOR_CALC_STATE
,
435 BRW_SF_UNIT
, /* scissor state on gen6 */
447 struct brw_cache_item
{
449 * Effectively part of the key, cache_id identifies what kind of state
450 * buffer is involved, and also which brw->state.dirty.cache flag should
451 * be set when this cache item is chosen.
453 enum brw_cache_id cache_id
;
454 /** 32-bit hash of the key data */
456 GLuint key_size
; /* for variable-sized keys */
463 struct brw_cache_item
*next
;
469 struct brw_context
*brw
;
471 struct brw_cache_item
**items
;
473 GLuint size
, n_items
;
475 uint32_t next_offset
;
480 /* Considered adding a member to this struct to document which flags
481 * an update might raise so that ordering of the state atoms can be
482 * checked or derived at runtime. Dropped the idea in favor of having
483 * a debug mode where the state is monitored for flags which are
484 * raised that have already been tested against.
486 struct brw_tracked_state
{
487 struct brw_state_flags dirty
;
488 void (*prepare
)( struct brw_context
*brw
);
489 void (*emit
)( struct brw_context
*brw
);
492 /* Flags for brw->state.cache.
494 #define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE)
495 #define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
496 #define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
497 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
498 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
499 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
500 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
501 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
502 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
503 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
504 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
505 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
506 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
507 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
508 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
509 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
510 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
511 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
513 struct brw_cached_batch_item
{
514 struct header
*header
;
516 struct brw_cached_batch_item
*next
;
521 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
522 * be easier if C allowed arrays of packed elements?
524 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
526 struct brw_vertex_buffer
{
527 /** Buffer object containing the uploaded vertex data */
530 /** Byte stride between elements in the uploaded array */
533 struct brw_vertex_element
{
534 const struct gl_client_array
*glarray
;
538 /** The corresponding Mesa vertex attribute */
539 gl_vert_attrib attrib
;
540 /** Size of a complete element */
542 /** Offset of the first element within the buffer object */
548 struct brw_vertex_info
{
549 GLuint sizes
[ATTRIB_BIT_DWORDS
* 2]; /* sizes:2[VERT_ATTRIB_MAX] */
552 struct brw_query_object
{
553 struct gl_query_object Base
;
555 /** Last query BO associated with this query. */
557 /** First index in bo with query data for this object. */
559 /** Last index in bo with query data for this object. */
565 * brw_context is derived from intel_context.
569 struct intel_context intel
; /**< base class, must be first field */
572 GLboolean emit_state_always
;
573 GLboolean has_surface_tile_offset
;
574 GLboolean has_compr4
;
575 GLboolean has_negative_rhw_bug
;
576 GLboolean has_aa_line_parameters
;
578 GLboolean new_vs_backend
;
581 struct brw_state_flags dirty
;
583 * List of buffers accumulated in brw_validate_state to receive
584 * drm_intel_bo_check_aperture treatment before exec, so we can
585 * know if we should flush the batch and try again before
586 * emitting primitives.
588 * This can be a fixed number as we only have a limited number of
589 * objects referenced from the batchbuffer in a primitive emit,
590 * consisting of the vertex buffers, pipelined state pointers,
591 * the CURBE, the depth buffer, and a query BO.
593 drm_intel_bo
*validated_bos
[VERT_ATTRIB_MAX
+ BRW_WM_MAX_SURF
+ 16];
594 unsigned int validated_bo_count
;
597 struct brw_cache cache
;
598 struct brw_cached_batch_item
*cached_batch_items
;
601 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
602 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
607 } current_buffers
[VERT_ATTRIB_MAX
];
609 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
611 GLuint nr_buffers
, nr_current_buffers
;
613 /* Summary of size and varying of active arrays, so we can check
614 * for changes to this state:
616 struct brw_vertex_info info
;
617 unsigned int min_index
, max_index
;
619 /* Offset from start of vertex buffer so we can avoid redefining
620 * the same VB packed over and over again.
622 unsigned int start_vertex_bias
;
627 * Index buffer for this draw_prims call.
629 * Updates are signaled by BRW_NEW_INDICES.
631 const struct _mesa_index_buffer
*ib
;
633 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
637 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
638 * avoid re-uploading the IB packet over and over if we're actually
639 * referencing the same index buffer.
641 unsigned int start_vertex_offset
;
644 /* Active vertex program:
646 const struct gl_vertex_program
*vertex_program
;
647 const struct gl_fragment_program
*fragment_program
;
649 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
650 uint32_t CMD_VF_STATISTICS
;
651 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
652 uint32_t CMD_PIPELINE_SELECT
;
656 /* BRW_NEW_URB_ALLOCATIONS:
659 GLuint vsize
; /* vertex size plus header in urb registers */
660 GLuint csize
; /* constant buffer size in urb registers */
661 GLuint sfsize
; /* setup data size in urb registers */
663 GLboolean constrained
;
665 GLuint max_vs_entries
; /* Maximum number of VS entries */
666 GLuint max_gs_entries
; /* Maximum number of GS entries */
668 GLuint nr_vs_entries
;
669 GLuint nr_gs_entries
;
670 GLuint nr_clip_entries
;
671 GLuint nr_sf_entries
;
672 GLuint nr_cs_entries
;
675 * The length of each URB entry owned by the VS (or GS), as
676 * a number of 1024-bit (128-byte) rows. Should be >= 1.
678 * gen7: Same meaning, but in 512-bit (64-byte) rows.
688 GLuint size
; /* Hardware URB size, in KB. */
692 /* BRW_NEW_CURBE_OFFSETS:
695 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
696 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
703 drm_intel_bo
*curbe_bo
;
704 /** Offset within curbe_bo of space for current curbe entry */
706 /** Offset within curbe_bo of space for next curbe entry */
707 GLuint curbe_next_offset
;
710 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
711 * in brw_curbe.c with the same set of constant data to be uploaded,
712 * so we'd rather not upload new constants in that case (it can cause
713 * a pipeline bubble since only up to 4 can be pipelined at a time).
717 * Allocation for where to calculate the next set of CURBEs.
718 * It's a hot enough path that malloc/free of that data matters.
725 struct brw_vs_prog_data
*prog_data
;
726 int8_t *constant_map
; /* variable array following prog_data */
728 drm_intel_bo
*scratch_bo
;
729 drm_intel_bo
*const_bo
;
730 /** Offset in the program cache to the VS program */
731 uint32_t prog_offset
;
732 uint32_t state_offset
;
734 /** Binding table of pointers to surf_bo entries */
735 uint32_t bind_bo_offset
;
736 uint32_t surf_offset
[BRW_VS_MAX_SURF
];
739 uint32_t push_const_offset
; /* Offset in the batchbuffer */
740 int push_const_size
; /* in 256-bit register increments */
742 /** @{ register allocator */
744 struct ra_regs
*regs
;
747 * Array of the ra classes for the unaligned contiguous register
753 * Mapping for register-allocated objects in *regs to the first
754 * GRF for that object.
756 uint8_t *ra_reg_to_grf
;
761 struct brw_gs_prog_data
*prog_data
;
763 GLboolean prog_active
;
764 /** Offset in the program cache to the CLIP program pre-gen6 */
765 uint32_t prog_offset
;
766 uint32_t state_offset
;
770 struct brw_clip_prog_data
*prog_data
;
772 /** Offset in the program cache to the CLIP program pre-gen6 */
773 uint32_t prog_offset
;
775 /* Offset in the batch to the CLIP state on pre-gen6. */
776 uint32_t state_offset
;
778 /* As of gen6, this is the offset in the batch to the CLIP VP,
786 struct brw_sf_prog_data
*prog_data
;
788 /** Offset in the program cache to the CLIP program pre-gen6 */
789 uint32_t prog_offset
;
790 uint32_t state_offset
;
795 struct brw_wm_prog_data
*prog_data
;
796 struct brw_wm_compile
*compile_data
;
798 /** Input sizes, calculated from active vertex program.
799 * One bit per fragment program input attribute.
801 GLbitfield input_size_masks
[4];
803 /** offsets in the batch to sampler default colors (texture border color)
805 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
810 drm_intel_bo
*scratch_bo
;
812 GLuint sampler_count
;
813 uint32_t sampler_offset
;
815 /** Offset in the program cache to the WM program */
816 uint32_t prog_offset
;
818 /** Binding table of pointers to surf_bo entries */
819 uint32_t bind_bo_offset
;
820 uint32_t surf_offset
[BRW_WM_MAX_SURF
];
821 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
823 drm_intel_bo
*const_bo
; /* pull constant buffer. */
825 * This is offset in the batch to the push constants on gen6.
827 * Pre-gen6, push constants live in the CURBE.
829 uint32_t push_const_offset
;
831 /** @{ register allocator */
833 struct ra_regs
*regs
;
835 /** Array of the ra classes for the unaligned contiguous
836 * register block sizes used.
841 * Mapping for register-allocated objects in *regs to the first
842 * GRF for that object.
844 uint8_t *ra_reg_to_grf
;
847 * ra class for the aligned pairs we use for PLN, which doesn't
848 * appear in *classes.
850 int aligned_pairs_class
;
857 uint32_t state_offset
;
858 uint32_t blend_state_offset
;
859 uint32_t depth_stencil_state_offset
;
864 struct brw_query_object
*obj
;
869 /* Used to give every program string a unique id
873 int num_prepare_atoms
, num_emit_atoms
;
874 struct brw_tracked_state prepare_atoms
[64], emit_atoms
[64];
876 /* If (INTEL_DEBUG & DEBUG_BATCH) */
880 enum state_struct_type type
;
882 int state_batch_count
;
886 #define BRW_PACKCOLOR8888(r,g,b,a) ((r<<24) | (g<<16) | (b<<8) | a)
888 struct brw_instruction_info
{
894 extern const struct brw_instruction_info brw_opcodes
[128];
896 /*======================================================================
899 void brwInitVtbl( struct brw_context
*brw
);
901 /*======================================================================
904 GLboolean
brwCreateContext( int api
,
905 const struct gl_config
*mesaVis
,
906 __DRIcontext
*driContextPriv
,
907 void *sharedContextPrivate
);
909 /*======================================================================
912 void brw_init_queryobj_functions(struct dd_function_table
*functions
);
913 void brw_prepare_query_begin(struct brw_context
*brw
);
914 void brw_emit_query_begin(struct brw_context
*brw
);
915 void brw_emit_query_end(struct brw_context
*brw
);
917 /*======================================================================
920 void brw_debug_batch(struct intel_context
*intel
);
922 /*======================================================================
925 void brw_validate_textures( struct brw_context
*brw
);
928 /*======================================================================
931 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
933 int brw_get_scratch_size(int size
);
934 void brw_get_scratch_bo(struct intel_context
*intel
,
935 drm_intel_bo
**scratch_bo
, int size
);
940 void brw_upload_urb_fence(struct brw_context
*brw
);
944 void brw_upload_cs_urb_state(struct brw_context
*brw
);
947 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
950 void brw_compute_vue_map(struct brw_vue_map
*vue_map
,
951 const struct intel_context
*intel
, int nr_userclip
,
952 bool two_side_color
, GLbitfield64 outputs_written
);
954 /*======================================================================
955 * Inline conversion functions. These are better-typed than the
956 * macros used previously:
958 static INLINE
struct brw_context
*
959 brw_context( struct gl_context
*ctx
)
961 return (struct brw_context
*)ctx
;
964 static INLINE
struct brw_vertex_program
*
965 brw_vertex_program(struct gl_vertex_program
*p
)
967 return (struct brw_vertex_program
*) p
;
970 static INLINE
const struct brw_vertex_program
*
971 brw_vertex_program_const(const struct gl_vertex_program
*p
)
973 return (const struct brw_vertex_program
*) p
;
976 static INLINE
struct brw_fragment_program
*
977 brw_fragment_program(struct gl_fragment_program
*p
)
979 return (struct brw_fragment_program
*) p
;
982 static INLINE
const struct brw_fragment_program
*
983 brw_fragment_program_const(const struct gl_fragment_program
*p
)
985 return (const struct brw_fragment_program
*) p
;
989 float convert_param(enum param_conversion conversion
, const float *param
)
997 switch (conversion
) {
998 case PARAM_NO_CONVERT
:
1000 case PARAM_CONVERT_F2I
:
1003 case PARAM_CONVERT_F2U
:
1006 case PARAM_CONVERT_F2B
:
1012 case PARAM_CONVERT_ZERO
:
1020 * Pre-gen6, the register file of the EUs was shared between threads,
1021 * and each thread used some subset allocated on a 16-register block
1022 * granularity. The unit states wanted these block counts.
1025 brw_register_blocks(int reg_count
)
1027 return ALIGN(reg_count
, 16) / 16 - 1;
1030 static inline uint32_t
1031 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1032 uint32_t prog_offset
)
1034 struct intel_context
*intel
= &brw
->intel
;
1036 if (intel
->gen
>= 5) {
1037 /* Using state base address. */
1041 drm_intel_bo_emit_reloc(intel
->batch
.bo
,
1045 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1047 return brw
->cache
.bo
->offset
+ prog_offset
;
1050 GLboolean
brw_do_cubemap_normalize(struct exec_list
*instructions
);