2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
44 #include "blorp/blorp.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
52 #include <intel_bufmgr.h>
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
64 #include "intel_resolve_map.h"
68 * URB - uniform resource buffer. A mid-sized buffer which is
69 * partitioned between the fixed function units and used for passing
70 * values (vertices, primitives, constants) between them.
72 * CURBE - constant URB entry. An urb region (entry) used to hold
73 * constant values which the fixed function units can be instructed to
74 * preload into the GRF when spawning a thread.
76 * VUE - vertex URB entry. An urb entry holding a vertex and usually
77 * a vertex header. The header contains control information and
78 * things like primitive type, Begin/end flags and clip codes.
80 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
81 * unit holding rasterization and interpolation parameters.
83 * GRF - general register file. One of several register files
84 * addressable by programmed threads. The inputs (r0, payload, curbe,
85 * urb) of the thread are preloaded to this area before the thread is
86 * spawned. The registers are individually 8 dwords wide and suitable
87 * for general usage. Registers holding thread input values are not
88 * special and may be overwritten.
90 * MRF - message register file. Threads communicate (and terminate)
91 * by sending messages. Message parameters are placed in contiguous
92 * MRF registers. All program output is via these messages. URB
93 * entries are populated by sending a message to the shared URB
94 * function containing the new data, together with a control word,
95 * often an unmodified copy of R0.
97 * R0 - GRF register 0. Typically holds control information used when
98 * sending messages to other threads.
100 * EU or GEN4 EU: The name of the programmable subsystem of the
101 * i965 hardware. Threads are executed by the EU, the registers
102 * described above are part of the EU architecture.
104 * Fixed function units:
106 * CS - Command streamer. Notional first unit, little software
107 * interaction. Holds the URB entries used for constant data, ie the
110 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
111 * this unit is responsible for pulling vertices out of vertex buffers
112 * in vram and injecting them into the processing pipe as VUEs. If
113 * enabled, it first passes them to a VS thread which is a good place
114 * for the driver to implement any active vertex shader.
116 * HS - Hull Shader (Tessellation Control Shader)
118 * TE - Tessellation Engine (Tessellation Primitive Generation)
120 * DS - Domain Shader (Tessellation Evaluation Shader)
122 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
123 * enabled, incoming strips etc are passed to GS threads in individual
124 * line/triangle/point units. The GS thread may perform arbitary
125 * computation and emit whatever primtives with whatever vertices it
126 * chooses. This makes GS an excellent place to implement GL's
127 * unfilled polygon modes, though of course it is capable of much
128 * more. Additionally, GS is used to translate away primitives not
129 * handled by latter units, including Quads and Lineloops.
131 * CS - Clipper. Mesa's clipping algorithms are imported to run on
132 * this unit. The fixed function part performs cliptesting against
133 * the 6 fixed clipplanes and makes descisions on whether or not the
134 * incoming primitive needs to be passed to a thread for clipping.
135 * User clip planes are handled via cooperation with the VS thread.
137 * SF - Strips Fans or Setup: Triangles are prepared for
138 * rasterization. Interpolation coefficients are calculated.
139 * Flatshading and two-side lighting usually performed here.
141 * WM - Windower. Interpolation of vertex attributes performed here.
142 * Fragment shader implemented here. SIMD aspects of EU taken full
143 * advantage of, as pixels are processed in blocks of 16.
145 * CC - Color Calculator. No EU threads associated with this unit.
146 * Handles blending and (presumably) depth and stencil testing.
151 struct brw_vs_prog_key
;
152 struct brw_vue_prog_key
;
153 struct brw_wm_prog_key
;
154 struct brw_wm_prog_data
;
155 struct brw_cs_prog_key
;
156 struct brw_cs_prog_data
;
160 BRW_COMPUTE_PIPELINE
,
167 BRW_CACHE_BLORP_PROG
,
170 BRW_CACHE_FF_GS_PROG
,
181 /* brw_cache_ids must come first - see brw_state_cache.c */
182 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
183 BRW_STATE_FRAGMENT_PROGRAM
,
184 BRW_STATE_GEOMETRY_PROGRAM
,
185 BRW_STATE_TESS_PROGRAMS
,
186 BRW_STATE_VERTEX_PROGRAM
,
187 BRW_STATE_CURBE_OFFSETS
,
188 BRW_STATE_REDUCED_PRIMITIVE
,
189 BRW_STATE_PATCH_PRIMITIVE
,
194 BRW_STATE_BINDING_TABLE_POINTERS
,
197 BRW_STATE_DEFAULT_TESS_LEVELS
,
199 BRW_STATE_INDEX_BUFFER
,
200 BRW_STATE_VS_CONSTBUF
,
201 BRW_STATE_TCS_CONSTBUF
,
202 BRW_STATE_TES_CONSTBUF
,
203 BRW_STATE_GS_CONSTBUF
,
204 BRW_STATE_PROGRAM_CACHE
,
205 BRW_STATE_STATE_BASE_ADDRESS
,
206 BRW_STATE_VUE_MAP_GEOM_OUT
,
207 BRW_STATE_TRANSFORM_FEEDBACK
,
208 BRW_STATE_RASTERIZER_DISCARD
,
210 BRW_STATE_UNIFORM_BUFFER
,
211 BRW_STATE_ATOMIC_BUFFER
,
212 BRW_STATE_IMAGE_UNITS
,
213 BRW_STATE_META_IN_PROGRESS
,
214 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
215 BRW_STATE_NUM_SAMPLES
,
216 BRW_STATE_TEXTURE_BUFFER
,
217 BRW_STATE_GEN4_UNIT_STATE
,
221 BRW_STATE_SAMPLER_STATE_TABLE
,
222 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
223 BRW_STATE_COMPUTE_PROGRAM
,
224 BRW_STATE_CS_WORK_GROUPS
,
228 BRW_STATE_VIEWPORT_COUNT
,
233 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
235 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
236 * When the currently bound shader program differs from the previous draw
237 * call, these will be flagged. They cover brw->{stage}_program and
238 * ctx->{Stage}Program->_Current.
240 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
241 * driver perspective. Even if the same shader is bound at the API level,
242 * we may need to switch between multiple versions of that shader to handle
243 * changes in non-orthagonal state.
245 * Additionally, multiple shader programs may have identical vertex shaders
246 * (for example), or compile down to the same code in the backend. We combine
247 * those into a single program cache entry.
249 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
250 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
252 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
253 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
254 * use the normal state upload paths), but the cache is still used. To avoid
255 * polluting the brw_state_cache code with special cases, we retain the dirty
256 * bit for now. It should eventually be removed.
258 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
259 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
260 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
261 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
262 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
263 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
264 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
265 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
266 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
267 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
268 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
269 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
270 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
271 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
272 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
273 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
274 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
275 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
276 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
277 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
278 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
279 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
280 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
281 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
282 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
284 * Used for any batch entry with a relocated pointer that will be used
285 * by any 3D rendering.
287 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
288 /** \see brw.state.depth_region */
289 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
290 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
291 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
292 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
293 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
294 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
295 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
296 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
297 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
298 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
299 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
300 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
301 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
302 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
303 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
304 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
305 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
306 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
307 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
308 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
309 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
310 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
311 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
312 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
313 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
314 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
315 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
316 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
317 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
318 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
320 struct brw_state_flags
{
321 /** State update flags signalled by mesa internals */
324 * State update flags signalled as the result of brw_tracked_state updates
330 /** Subclass of Mesa program */
332 struct gl_program program
;
337 /** Subclass of Mesa fragment program */
338 struct brw_fragment_program
{
339 struct gl_program program
;
340 GLuint id
; /**< serial no. to identify frag progs, never re-used */
344 struct gen4_fragment_program
{
345 struct brw_fragment_program base
;
347 bool contains_flat_varying
;
348 bool contains_noperspective_varying
;
351 * Mapping of varying slots to interpolation modes.
352 * Used Gen4/5 by the clip|sf|wm stages.
354 unsigned char interp_mode
[BRW_VARYING_SLOT_COUNT
];
358 /** Subclass of Mesa compute program */
359 struct brw_compute_program
{
360 struct gl_program program
;
361 unsigned id
; /**< serial no. to identify compute progs, never re-used */
366 struct gl_linked_shader base
;
372 * Bitmask indicating which fragment shader inputs represent varyings (and
373 * hence have to be delivered to the fragment shader by the SF/SBE stage).
375 #define BRW_FS_VARYING_INPUT_MASK \
376 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
377 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
380 struct brw_sf_prog_data
{
381 GLuint urb_read_length
;
384 /* Each vertex may have upto 12 attributes, 4 components each,
385 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
388 * Actually we use 4 for each, so call it 12 rows.
390 GLuint urb_entry_size
;
395 * We always program SF to start reading at an offset of 1 (2 varying slots)
396 * from the start of the vertex URB entry. This causes it to skip:
397 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
398 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
400 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
403 struct brw_clip_prog_data
{
404 GLuint curb_read_length
; /* user planes? */
406 GLuint urb_read_length
;
410 struct brw_ff_gs_prog_data
{
411 GLuint urb_read_length
;
415 * Gen6 transform feedback: Amount by which the streaming vertex buffer
416 * indices should be incremented each time the GS is invoked.
418 unsigned svbi_postincrement_value
;
421 /** Number of texture sampler units */
422 #define BRW_MAX_TEX_UNIT 32
424 /** Max number of render targets in a shader */
425 #define BRW_MAX_DRAW_BUFFERS 8
427 /** Max number of UBOs in a shader */
428 #define BRW_MAX_UBO 14
430 /** Max number of SSBOs in a shader */
431 #define BRW_MAX_SSBO 12
433 /** Max number of atomic counter buffer objects in a shader */
434 #define BRW_MAX_ABO 16
436 /** Max number of image uniforms in a shader */
437 #define BRW_MAX_IMAGES 32
440 * Max number of binding table entries used for stream output.
442 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
443 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
445 * On Gen6, the size of transform feedback data is limited not by the number
446 * of components but by the number of binding table entries we set aside. We
447 * use one binding table entry for a float, one entry for a vector, and one
448 * entry per matrix column. Since the only way we can communicate our
449 * transform feedback capabilities to the client is via
450 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
451 * worst case, in which all the varyings are floats, so we use up one binding
452 * table entry per component. Therefore we need to set aside at least 64
453 * binding table entries for use by transform feedback.
455 * Note: since we don't currently pack varyings, it is currently impossible
456 * for the client to actually use up all of these binding table entries--if
457 * all of their varyings were floats, they would run out of varying slots and
458 * fail to link. But that's a bug, so it seems prudent to go ahead and
459 * allocate the number of binding table entries we will need once the bug is
462 #define BRW_MAX_SOL_BINDINGS 64
464 /** Maximum number of actual buffers used for stream output */
465 #define BRW_MAX_SOL_BUFFERS 4
467 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
468 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
473 2 + /* shader time, pull constants */ \
474 1 /* cs num work groups */)
476 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
479 * Stride in bytes between shader_time entries.
481 * We separate entries by a cacheline to reduce traffic between EUs writing to
484 #define SHADER_TIME_STRIDE 64
486 struct brw_cache_item
{
488 * Effectively part of the key, cache_id identifies what kind of state
489 * buffer is involved, and also which dirty flag should set.
491 enum brw_cache_id cache_id
;
492 /** 32-bit hash of the key data */
494 GLuint key_size
; /* for variable-sized keys */
501 struct brw_cache_item
*next
;
506 struct brw_context
*brw
;
508 struct brw_cache_item
**items
;
510 GLuint size
, n_items
;
512 uint32_t next_offset
;
517 /* Considered adding a member to this struct to document which flags
518 * an update might raise so that ordering of the state atoms can be
519 * checked or derived at runtime. Dropped the idea in favor of having
520 * a debug mode where the state is monitored for flags which are
521 * raised that have already been tested against.
523 struct brw_tracked_state
{
524 struct brw_state_flags dirty
;
525 void (*emit
)( struct brw_context
*brw
);
528 enum shader_time_shader_type
{
539 struct brw_vertex_buffer
{
540 /** Buffer object containing the uploaded vertex data */
544 /** Byte stride between elements in the uploaded array */
548 struct brw_vertex_element
{
549 const struct gl_client_array
*glarray
;
553 /** Offset of the first element within the buffer object */
557 struct brw_query_object
{
558 struct gl_query_object Base
;
560 /** Last query BO associated with this query. */
563 /** Last index in bo with query data for this object. */
566 /** True if we know the batch has been flushed since we ended the query. */
576 struct intel_batchbuffer
{
577 /** Current batchbuffer being queued up. */
579 /** Last BO submitted to the hardware. Used for glFinish(). */
580 drm_intel_bo
*last_bo
;
583 uint16_t emit
, total
;
585 uint16_t reserved_space
;
589 #define BATCH_SZ (8192*sizeof(uint32_t))
591 uint32_t state_batch_offset
;
592 enum brw_gpu_ring ring
;
593 bool needs_sol_reset
;
594 bool state_base_address_emitted
;
602 #define MAX_GS_INPUT_VERTICES 6
604 #define BRW_MAX_XFB_STREAMS 4
606 struct brw_transform_feedback_object
{
607 struct gl_transform_feedback_object base
;
609 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
610 drm_intel_bo
*offset_bo
;
612 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
615 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
616 GLenum primitive_mode
;
619 * Count of primitives generated during this transform feedback operation.
622 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
623 drm_intel_bo
*prim_count_bo
;
624 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
628 * Number of vertices written between last Begin/EndTransformFeedback().
630 * Used to implement DrawTransformFeedback().
632 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
633 bool vertices_written_valid
;
637 * Data shared between each programmable stage in the pipeline (vs, gs, and
640 struct brw_stage_state
642 gl_shader_stage stage
;
643 struct brw_stage_prog_data
*prog_data
;
646 * Optional scratch buffer used to store spilled register values and
647 * variably-indexed GRF arrays.
649 * The contents of this buffer are short-lived so the same memory can be
650 * re-used at will for multiple shader programs (executed by the same fixed
651 * function). However reusing a scratch BO for which shader invocations
652 * are still in flight with a per-thread scratch slot size other than the
653 * original can cause threads with different scratch slot size and FFTID
654 * (which may be executed in parallel depending on the shader stage and
655 * hardware generation) to map to an overlapping region of the scratch
656 * space, which can potentially lead to mutual scratch space corruption.
657 * For that reason if you borrow this scratch buffer you should only be
658 * using the slot size given by the \c per_thread_scratch member below,
659 * unless you're taking additional measures to synchronize thread execution
660 * across slot size changes.
662 drm_intel_bo
*scratch_bo
;
665 * Scratch slot size allocated for each thread in the buffer object given
668 uint32_t per_thread_scratch
;
670 /** Offset in the program cache to the program */
671 uint32_t prog_offset
;
673 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
674 uint32_t state_offset
;
676 uint32_t push_const_offset
; /* Offset in the batchbuffer */
677 int push_const_size
; /* in 256-bit register increments */
679 /* Binding table: pointers to SURFACE_STATE entries. */
680 uint32_t bind_bo_offset
;
681 uint32_t surf_offset
[BRW_MAX_SURFACES
];
683 /** SAMPLER_STATE count and table offset */
684 uint32_t sampler_count
;
685 uint32_t sampler_offset
;
688 enum brw_predicate_state
{
689 /* The first two states are used if we can determine whether to draw
690 * without having to look at the values in the query object buffer. This
691 * will happen if there is no conditional render in progress, if the query
692 * object is already completed or if something else has already added
693 * samples to the preliminary result such as via a BLT command.
695 BRW_PREDICATE_STATE_RENDER
,
696 BRW_PREDICATE_STATE_DONT_RENDER
,
697 /* In this case whether to draw or not depends on the result of an
698 * MI_PREDICATE command so the predicate enable bit needs to be checked.
700 BRW_PREDICATE_STATE_USE_BIT
705 struct gen_l3_config
;
708 * brw_context is derived from gl_context.
712 struct gl_context ctx
; /**< base class, must be first field */
716 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
717 struct gl_renderbuffer
*rb
,
718 uint32_t flags
, unsigned unit
,
719 uint32_t surf_index
);
720 void (*emit_null_surface_state
)(struct brw_context
*brw
,
724 uint32_t *out_offset
);
727 * Send the appropriate state packets to configure depth, stencil, and
728 * HiZ buffers (i965+ only)
730 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
731 struct intel_mipmap_tree
*depth_mt
,
732 uint32_t depth_offset
,
733 uint32_t depthbuffer_format
,
734 uint32_t depth_surface_type
,
735 struct intel_mipmap_tree
*stencil_mt
,
736 bool hiz
, bool separate_stencil
,
737 uint32_t width
, uint32_t height
,
738 uint32_t tile_x
, uint32_t tile_y
);
744 drm_intel_context
*hw_ctx
;
746 /** BO for post-sync nonzero writes for gen6 workaround. */
747 drm_intel_bo
*workaround_bo
;
748 uint8_t pipe_controls_since_last_cs_stall
;
751 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
752 * and would need flushing before being used from another cache domain that
753 * isn't coherent with it (i.e. the sampler).
755 struct set
*render_cache
;
758 * Number of resets observed in the system at context creation.
760 * This is tracked in the context so that we can determine that another
761 * reset has occurred.
763 uint32_t reset_count
;
765 struct intel_batchbuffer batch
;
770 uint32_t next_offset
;
774 * Set if rendering has occurred to the drawable's front buffer.
776 * This is used in the DRI2 case to detect that glFlush should also copy
777 * the contents of the fake front buffer to the real front buffer.
779 bool front_buffer_dirty
;
781 /** Framerate throttling: @{ */
782 drm_intel_bo
*throttle_batch
[2];
784 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
785 * frame of rendering to complete. This gives a very precise cap to the
786 * latency between input and output such that rendering never gets more
787 * than a frame behind the user. (With the caveat that we technically are
788 * not using the SwapBuffers itself as a barrier but the first batch
789 * submitted afterwards, which may be immediately prior to the next
792 bool need_swap_throttle
;
794 /** General throttling, not caught by throttling between SwapBuffers */
795 bool need_flush_throttle
;
805 bool always_flush_batch
;
806 bool always_flush_cache
;
807 bool disable_throttling
;
809 bool dual_color_blend_by_location
;
811 driOptionCache optionCache
;
814 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
816 GLenum reduced_primitive
;
819 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
820 * variable is set, this is the flag indicating to do expensive work that
821 * might lead to a perf_debug() call.
825 uint64_t max_gtt_map_object_size
;
837 bool has_separate_stencil
;
838 bool must_use_separate_stencil
;
841 bool has_surface_tile_offset
;
843 bool has_negative_rhw_bug
;
847 bool use_resource_streamer
;
850 * Whether LRI can be used to write register values from the batch buffer.
852 bool can_do_pipelined_register_writes
;
855 * Some versions of Gen hardware don't do centroid interpolation correctly
856 * on unlit pixels, causing incorrect values for derivatives near triangle
857 * edges. Enabling this flag causes the fragment shader to use
858 * non-centroid interpolation for unlit pixels, at the expense of two extra
859 * fragment shader instructions.
861 bool needs_unlit_centroid_workaround
;
863 struct isl_device isl_dev
;
865 struct blorp_context blorp
;
869 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
872 enum brw_pipeline last_pipeline
;
874 struct brw_cache cache
;
876 /** IDs for meta stencil blit shader programs. */
877 struct gl_shader_program
*meta_stencil_blit_programs
[2];
879 /* Whether a meta-operation is in progress. */
880 bool meta_in_progress
;
882 /* Whether the last depth/stencil packets were both NULL. */
883 bool no_depth_or_stencil
;
885 /* The last PMA stall bits programmed. */
886 uint32_t pma_stall_bits
;
890 /** The value of gl_BaseVertex for the current _mesa_prim. */
893 /** The value of gl_BaseInstance for the current _mesa_prim. */
898 * Buffer and offset used for GL_ARB_shader_draw_parameters
899 * (for now, only gl_BaseVertex).
901 drm_intel_bo
*draw_params_bo
;
902 uint32_t draw_params_offset
;
905 * The value of gl_DrawID for the current _mesa_prim. This always comes
906 * in from it's own vertex buffer since it's not part of the indirect
910 drm_intel_bo
*draw_id_bo
;
911 uint32_t draw_id_offset
;
916 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
917 * an indirect call, and num_work_groups_offset is valid. Otherwise,
918 * num_work_groups is set based on glDispatchCompute.
920 drm_intel_bo
*num_work_groups_bo
;
921 GLintptr num_work_groups_offset
;
922 const GLuint
*num_work_groups
;
926 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
927 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
929 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
933 /* Summary of size and varying of active arrays, so we can check
934 * for changes to this state:
936 bool index_bounds_valid
;
937 unsigned int min_index
, max_index
;
939 /* Offset from start of vertex buffer so we can avoid redefining
940 * the same VB packed over and over again.
942 unsigned int start_vertex_bias
;
945 * Certain vertex attribute formats aren't natively handled by the
946 * hardware and require special VS code to fix up their values.
948 * These bitfields indicate which workarounds are needed.
950 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
955 * Index buffer for this draw_prims call.
957 * Updates are signaled by BRW_NEW_INDICES.
959 const struct _mesa_index_buffer
*ib
;
961 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
966 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
967 * avoid re-uploading the IB packet over and over if we're actually
968 * referencing the same index buffer.
970 unsigned int start_vertex_offset
;
973 /* Active vertex program:
975 const struct gl_program
*vertex_program
;
976 const struct gl_program
*geometry_program
;
977 const struct gl_program
*tess_ctrl_program
;
978 const struct gl_program
*tess_eval_program
;
979 const struct gl_program
*fragment_program
;
980 const struct gl_program
*compute_program
;
983 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
984 * that we don't have to reemit that state every time we change FBOs.
988 /* BRW_NEW_URB_ALLOCATIONS:
991 GLuint vsize
; /* vertex size plus header in urb registers */
992 GLuint gsize
; /* GS output size in urb registers */
993 GLuint hsize
; /* Tessellation control output size in urb registers */
994 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
995 GLuint csize
; /* constant buffer size in urb registers */
996 GLuint sfsize
; /* setup data size in urb registers */
1000 GLuint nr_vs_entries
;
1001 GLuint nr_hs_entries
;
1002 GLuint nr_ds_entries
;
1003 GLuint nr_gs_entries
;
1004 GLuint nr_clip_entries
;
1005 GLuint nr_sf_entries
;
1006 GLuint nr_cs_entries
;
1016 * URB size in the current configuration. The units this is expressed
1017 * in are somewhat inconsistent, see gen_device_info::urb::size.
1019 * FINISHME: Represent the URB size consistently in KB on all platforms.
1023 /* True if the most recently sent _3DSTATE_URB message allocated
1024 * URB space for the GS.
1028 /* True if the most recently sent _3DSTATE_URB message allocated
1029 * URB space for the HS and DS.
1035 /* BRW_NEW_CURBE_OFFSETS:
1038 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1039 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1047 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1048 * for upload to the CURBE.
1050 drm_intel_bo
*curbe_bo
;
1051 /** Offset within curbe_bo of space for current curbe entry */
1052 GLuint curbe_offset
;
1056 * Layout of vertex data exiting the geometry portion of the pipleine.
1057 * This comes from the last enabled shader stage (GS, DS, or VS).
1059 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1061 struct brw_vue_map vue_map_geom_out
;
1064 struct brw_stage_state base
;
1068 struct brw_stage_state base
;
1071 * True if the 3DSTATE_HS command most recently emitted to the 3D
1072 * pipeline enabled the HS; false otherwise.
1078 struct brw_stage_state base
;
1081 * True if the 3DSTATE_DS command most recently emitted to the 3D
1082 * pipeline enabled the DS; false otherwise.
1088 struct brw_stage_state base
;
1091 * True if the 3DSTATE_GS command most recently emitted to the 3D
1092 * pipeline enabled the GS; false otherwise.
1098 struct brw_ff_gs_prog_data
*prog_data
;
1101 /** Offset in the program cache to the CLIP program pre-gen6 */
1102 uint32_t prog_offset
;
1103 uint32_t state_offset
;
1105 uint32_t bind_bo_offset
;
1107 * Surface offsets for the binding table. We only need surfaces to
1108 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1109 * need in this case.
1111 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1115 struct brw_clip_prog_data
*prog_data
;
1117 /** Offset in the program cache to the CLIP program pre-gen6 */
1118 uint32_t prog_offset
;
1120 /* Offset in the batch to the CLIP state on pre-gen6. */
1121 uint32_t state_offset
;
1123 /* As of gen6, this is the offset in the batch to the CLIP VP,
1129 * The number of viewports to use. If gl_ViewportIndex is written,
1130 * we can have up to ctx->Const.MaxViewports viewports. If not,
1131 * the viewport index is always 0, so we can only emit one.
1133 uint8_t viewport_count
;
1138 struct brw_sf_prog_data
*prog_data
;
1140 /** Offset in the program cache to the CLIP program pre-gen6 */
1141 uint32_t prog_offset
;
1142 uint32_t state_offset
;
1144 bool viewport_transform_enable
;
1148 struct brw_stage_state base
;
1153 * Buffer object used in place of multisampled null render targets on
1154 * Gen6. See brw_emit_null_surface_state().
1156 drm_intel_bo
*multisampled_null_render_target_bo
;
1157 uint32_t fast_clear_op
;
1163 struct brw_stage_state base
;
1166 /* RS hardware binding table */
1169 uint32_t next_offset
;
1173 uint32_t state_offset
;
1174 uint32_t blend_state_offset
;
1175 uint32_t depth_stencil_state_offset
;
1180 struct brw_query_object
*obj
;
1185 enum brw_predicate_state state
;
1190 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1191 const int *statistics_registers
;
1193 /** The number of active monitors using OA counters. */
1197 * A buffer object storing OA counter snapshots taken at the start and
1198 * end of each batch (creating "bookends" around the batch).
1200 drm_intel_bo
*bookend_bo
;
1202 /** The number of snapshots written to bookend_bo. */
1203 int bookend_snapshots
;
1206 * An array of monitors whose results haven't yet been assembled based on
1207 * the data in buffer objects.
1209 * These may be active, or have already ended. However, the results
1210 * have not been requested.
1212 struct brw_perf_monitor_object
**unresolved
;
1213 int unresolved_elements
;
1214 int unresolved_array_size
;
1217 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1218 * the counter which MI_REPORT_PERF_COUNT stores there.
1220 const int *oa_snapshot_layout
;
1222 /** Number of 32-bit entries in a hardware counter snapshot. */
1223 int entries_per_oa_snapshot
;
1226 int num_atoms
[BRW_NUM_PIPELINES
];
1227 const struct brw_tracked_state render_atoms
[76];
1228 const struct brw_tracked_state compute_atoms
[11];
1230 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1234 enum aub_state_struct_type type
;
1236 } *state_batch_list
;
1237 int state_batch_count
;
1239 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1240 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1242 /* PrimitiveRestart */
1245 bool enable_cut_index
;
1248 /** Computed depth/stencil/hiz state from the current attached
1249 * renderbuffers, valid only during the drawing state upload loop after
1250 * brw_workaround_depthstencil_alignment().
1253 struct intel_mipmap_tree
*depth_mt
;
1254 struct intel_mipmap_tree
*stencil_mt
;
1256 /* Inter-tile (page-aligned) byte offsets. */
1257 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1258 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1259 uint32_t tile_x
, tile_y
;
1262 uint32_t num_instances
;
1267 const struct gen_l3_config
*config
;
1274 enum shader_time_shader_type
*types
;
1275 struct shader_times
*cumulative
;
1281 struct brw_fast_clear_state
*fast_clear_state
;
1283 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1284 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1285 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1287 * This is needed in case the same underlying buffer is also configured
1288 * to be sampled but with a format that the sampling engine can't treat
1289 * compressed or fast cleared.
1291 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1293 __DRIcontext
*driContext
;
1294 struct intel_screen
*screen
;
1297 /*======================================================================
1300 void brwInitVtbl( struct brw_context
*brw
);
1303 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1305 /*======================================================================
1308 extern const char *const brw_vendor_string
;
1311 brw_get_renderer_string(const struct intel_screen
*screen
);
1314 DRI_CONF_BO_REUSE_DISABLED
,
1315 DRI_CONF_BO_REUSE_ALL
1318 void intel_update_renderbuffers(__DRIcontext
*context
,
1319 __DRIdrawable
*drawable
);
1320 void intel_prepare_render(struct brw_context
*brw
);
1322 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1323 __DRIdrawable
*drawable
);
1325 GLboolean
brwCreateContext(gl_api api
,
1326 const struct gl_config
*mesaVis
,
1327 __DRIcontext
*driContextPriv
,
1328 unsigned major_version
,
1329 unsigned minor_version
,
1333 void *sharedContextPrivate
);
1335 /*======================================================================
1339 brw_meta_resolve_color(struct brw_context
*brw
,
1340 struct intel_mipmap_tree
*mt
);
1342 /*======================================================================
1345 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1346 uint32_t depth_level
,
1347 uint32_t depth_layer
,
1348 struct intel_mipmap_tree
*stencil_mt
,
1349 uint32_t *out_tile_mask_x
,
1350 uint32_t *out_tile_mask_y
);
1351 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1352 GLbitfield clear_mask
);
1354 /* brw_object_purgeable.c */
1355 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1357 /*======================================================================
1360 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1361 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1362 void brw_emit_query_begin(struct brw_context
*brw
);
1363 void brw_emit_query_end(struct brw_context
*brw
);
1364 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1365 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1367 /** gen6_queryobj.c */
1368 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1369 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1370 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1372 /** hsw_queryobj.c */
1373 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1375 /** brw_conditional_render.c */
1376 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1377 bool brw_check_conditional_render(struct brw_context
*brw
);
1379 /** intel_batchbuffer.c */
1380 void brw_load_register_mem(struct brw_context
*brw
,
1383 uint32_t read_domains
, uint32_t write_domain
,
1385 void brw_load_register_mem64(struct brw_context
*brw
,
1388 uint32_t read_domains
, uint32_t write_domain
,
1390 void brw_store_register_mem32(struct brw_context
*brw
,
1391 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1392 void brw_store_register_mem64(struct brw_context
*brw
,
1393 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1394 void brw_load_register_imm32(struct brw_context
*brw
,
1395 uint32_t reg
, uint32_t imm
);
1396 void brw_load_register_imm64(struct brw_context
*brw
,
1397 uint32_t reg
, uint64_t imm
);
1398 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1400 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1402 void brw_store_data_imm32(struct brw_context
*brw
, drm_intel_bo
*bo
,
1403 uint32_t offset
, uint32_t imm
);
1404 void brw_store_data_imm64(struct brw_context
*brw
, drm_intel_bo
*bo
,
1405 uint32_t offset
, uint64_t imm
);
1407 /*======================================================================
1410 void brw_debug_batch(struct brw_context
*brw
);
1411 void brw_annotate_aub(struct brw_context
*brw
);
1413 /*======================================================================
1414 * intel_tex_validate.c
1416 void brw_validate_textures( struct brw_context
*brw
);
1419 /*======================================================================
1423 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1426 perf_debug(" %s %d->%d\n", name
, a
, b
);
1432 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1434 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1436 brw_get_scratch_size(int size
)
1438 return MAX2(1024, util_next_power_of_two(size
));
1440 void brw_get_scratch_bo(struct brw_context
*brw
,
1441 drm_intel_bo
**scratch_bo
, int size
);
1442 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1443 struct brw_stage_state
*stage_state
,
1444 unsigned per_thread_size
,
1445 unsigned thread_count
);
1446 void brw_init_shader_time(struct brw_context
*brw
);
1447 int brw_get_shader_time_index(struct brw_context
*brw
,
1448 struct gl_shader_program
*shader_prog
,
1449 struct gl_program
*prog
,
1450 enum shader_time_shader_type type
);
1451 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1452 void brw_destroy_shader_time(struct brw_context
*brw
);
1456 void brw_upload_urb_fence(struct brw_context
*brw
);
1460 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1462 /* brw_fs_reg_allocate.cpp
1464 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1466 /* brw_vec4_reg_allocate.cpp */
1467 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1470 int brw_disassemble_inst(FILE *file
, const struct gen_device_info
*devinfo
,
1471 struct brw_inst
*inst
, bool is_compacted
);
1474 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1476 /* brw_draw_upload.c */
1477 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1478 const struct gl_client_array
*glarray
);
1480 static inline unsigned
1481 brw_get_index_type(GLenum type
)
1483 assert((type
== GL_UNSIGNED_BYTE
)
1484 || (type
== GL_UNSIGNED_SHORT
)
1485 || (type
== GL_UNSIGNED_INT
));
1487 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1488 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1489 * to map to scale factors of 0, 1, and 2, respectively. These scale
1490 * factors are then left-shfited by 8 to be in the correct position in the
1491 * CMD_INDEX_BUFFER packet.
1493 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1494 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1495 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1497 return (type
- 0x1401) << 7;
1500 void brw_prepare_vertices(struct brw_context
*brw
);
1502 /* brw_wm_surface_state.c */
1503 void brw_init_surface_formats(struct brw_context
*brw
);
1504 void brw_create_constant_surface(struct brw_context
*brw
,
1508 uint32_t *out_offset
);
1509 void brw_create_buffer_surface(struct brw_context
*brw
,
1513 uint32_t *out_offset
);
1514 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1516 uint32_t *surf_offset
);
1518 brw_update_sol_surface(struct brw_context
*brw
,
1519 struct gl_buffer_object
*buffer_obj
,
1520 uint32_t *out_offset
, unsigned num_vector_components
,
1521 unsigned stride_dwords
, unsigned offset_dwords
);
1522 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1523 struct gl_linked_shader
*shader
,
1524 struct brw_stage_state
*stage_state
,
1525 struct brw_stage_prog_data
*prog_data
);
1526 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1527 struct gl_linked_shader
*shader
,
1528 struct brw_stage_state
*stage_state
,
1529 struct brw_stage_prog_data
*prog_data
);
1530 void brw_upload_image_surfaces(struct brw_context
*brw
,
1531 struct gl_linked_shader
*shader
,
1532 struct brw_stage_state
*stage_state
,
1533 struct brw_stage_prog_data
*prog_data
);
1535 /* brw_surface_formats.c */
1536 bool brw_render_target_supported(struct brw_context
*brw
,
1537 struct gl_renderbuffer
*rb
);
1538 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1540 /* brw_performance_monitor.c */
1541 void brw_init_performance_monitors(struct brw_context
*brw
);
1542 void brw_dump_perf_monitors(struct brw_context
*brw
);
1543 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1544 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1546 /* intel_buffer_objects.c */
1547 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1548 const char *bo_name
);
1549 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1550 const char *bo_name
);
1552 /* intel_extensions.c */
1553 extern void intelInitExtensions(struct gl_context
*ctx
);
1556 extern int intel_translate_shadow_compare_func(GLenum func
);
1557 extern int intel_translate_compare_func(GLenum func
);
1558 extern int intel_translate_stencil_op(GLenum op
);
1559 extern int intel_translate_logic_op(GLenum opcode
);
1562 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1565 struct gl_transform_feedback_object
*
1566 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1568 brw_delete_transform_feedback(struct gl_context
*ctx
,
1569 struct gl_transform_feedback_object
*obj
);
1571 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1572 struct gl_transform_feedback_object
*obj
);
1574 brw_end_transform_feedback(struct gl_context
*ctx
,
1575 struct gl_transform_feedback_object
*obj
);
1577 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1578 struct gl_transform_feedback_object
*obj
,
1581 /* gen7_sol_state.c */
1583 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1584 struct gl_transform_feedback_object
*obj
);
1586 gen7_end_transform_feedback(struct gl_context
*ctx
,
1587 struct gl_transform_feedback_object
*obj
);
1589 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1590 struct gl_transform_feedback_object
*obj
);
1592 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1593 struct gl_transform_feedback_object
*obj
);
1597 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1598 struct gl_transform_feedback_object
*obj
);
1600 hsw_end_transform_feedback(struct gl_context
*ctx
,
1601 struct gl_transform_feedback_object
*obj
);
1603 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1604 struct gl_transform_feedback_object
*obj
);
1606 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1607 struct gl_transform_feedback_object
*obj
);
1609 /* brw_blorp_blit.cpp */
1611 brw_blorp_framebuffer(struct brw_context
*brw
,
1612 struct gl_framebuffer
*readFb
,
1613 struct gl_framebuffer
*drawFb
,
1614 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1615 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1616 GLbitfield mask
, GLenum filter
);
1619 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1620 struct gl_renderbuffer
*src_rb
,
1621 struct gl_texture_image
*dst_image
,
1623 int srcX0
, int srcY0
,
1624 int dstX0
, int dstY0
,
1625 int width
, int height
);
1627 /* gen6_multisample_state.c */
1629 gen6_determine_sample_mask(struct brw_context
*brw
);
1632 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1633 unsigned num_samples
);
1635 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1637 gen6_get_sample_position(struct gl_context
*ctx
,
1638 struct gl_framebuffer
*fb
,
1642 gen6_set_sample_maps(struct gl_context
*ctx
);
1644 /* gen8_multisample_state.c */
1645 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1646 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1650 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1651 unsigned hs_size
, unsigned ds_size
,
1652 unsigned gs_size
, unsigned fs_size
);
1655 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1656 bool gs_present
, unsigned gs_size
);
1658 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1659 bool gs_present
, bool tess_present
);
1663 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1665 brw_check_for_reset(struct brw_context
*brw
);
1669 brw_init_compute_functions(struct dd_function_table
*functions
);
1671 /*======================================================================
1672 * Inline conversion functions. These are better-typed than the
1673 * macros used previously:
1675 static inline struct brw_context
*
1676 brw_context( struct gl_context
*ctx
)
1678 return (struct brw_context
*)ctx
;
1681 static inline struct brw_program
*
1682 brw_program(struct gl_program
*p
)
1684 return (struct brw_program
*) p
;
1687 static inline const struct brw_program
*
1688 brw_program_const(const struct gl_program
*p
)
1690 return (const struct brw_program
*) p
;
1693 static inline struct brw_fragment_program
*
1694 brw_fragment_program(struct gl_program
*p
)
1696 return (struct brw_fragment_program
*) p
;
1699 static inline const struct brw_fragment_program
*
1700 brw_fragment_program_const(const struct gl_program
*p
)
1702 return (const struct brw_fragment_program
*) p
;
1705 static inline struct brw_compute_program
*
1706 brw_compute_program(struct gl_program
*p
)
1708 return (struct brw_compute_program
*) p
;
1712 * Pre-gen6, the register file of the EUs was shared between threads,
1713 * and each thread used some subset allocated on a 16-register block
1714 * granularity. The unit states wanted these block counts.
1717 brw_register_blocks(int reg_count
)
1719 return ALIGN(reg_count
, 16) / 16 - 1;
1722 static inline uint32_t
1723 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1724 uint32_t prog_offset
)
1726 if (brw
->gen
>= 5) {
1727 /* Using state base address. */
1731 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1735 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1737 return brw
->cache
.bo
->offset64
+ prog_offset
;
1740 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1741 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1742 struct exec_list
*instructions
);
1744 extern const char * const conditional_modifier
[16];
1745 extern const char *const pred_ctrl_align16
[16];
1748 brw_emit_depthbuffer(struct brw_context
*brw
);
1751 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1752 struct intel_mipmap_tree
*depth_mt
,
1753 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1754 uint32_t depth_surface_type
,
1755 struct intel_mipmap_tree
*stencil_mt
,
1756 bool hiz
, bool separate_stencil
,
1757 uint32_t width
, uint32_t height
,
1758 uint32_t tile_x
, uint32_t tile_y
);
1761 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1762 struct intel_mipmap_tree
*depth_mt
,
1763 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1764 uint32_t depth_surface_type
,
1765 struct intel_mipmap_tree
*stencil_mt
,
1766 bool hiz
, bool separate_stencil
,
1767 uint32_t width
, uint32_t height
,
1768 uint32_t tile_x
, uint32_t tile_y
);
1771 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1772 struct intel_mipmap_tree
*depth_mt
,
1773 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1774 uint32_t depth_surface_type
,
1775 struct intel_mipmap_tree
*stencil_mt
,
1776 bool hiz
, bool separate_stencil
,
1777 uint32_t width
, uint32_t height
,
1778 uint32_t tile_x
, uint32_t tile_y
);
1780 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1781 struct intel_mipmap_tree
*depth_mt
,
1782 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1783 uint32_t depth_surface_type
,
1784 struct intel_mipmap_tree
*stencil_mt
,
1785 bool hiz
, bool separate_stencil
,
1786 uint32_t width
, uint32_t height
,
1787 uint32_t tile_x
, uint32_t tile_y
);
1789 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1790 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
);
1792 uint32_t get_hw_prim_for_gl_prim(int mode
);
1795 gen6_upload_push_constants(struct brw_context
*brw
,
1796 const struct gl_program
*prog
,
1797 const struct brw_stage_prog_data
*prog_data
,
1798 struct brw_stage_state
*stage_state
,
1799 enum aub_state_struct_type type
);
1802 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1803 const struct intel_mipmap_tree
*mt
);
1805 /* brw_pipe_control.c */
1806 int brw_init_pipe_control(struct brw_context
*brw
,
1807 const struct gen_device_info
*info
);
1808 void brw_fini_pipe_control(struct brw_context
*brw
);
1810 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1811 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1812 drm_intel_bo
*bo
, uint32_t offset
,
1813 uint32_t imm_lower
, uint32_t imm_upper
);
1814 void brw_emit_mi_flush(struct brw_context
*brw
);
1815 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1816 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1817 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1818 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1820 /* brw_queryformat.c */
1821 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1822 GLenum internalFormat
, GLenum pname
,