2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "compiler/brw_compiler.h"
43 #include "blorp/blorp.h"
45 #include <brw_bufmgr.h>
47 #include "common/gen_debug.h"
48 #include "intel_screen.h"
49 #include "intel_tex_obj.h"
50 #include "intel_resolve_map.h"
57 * URB - uniform resource buffer. A mid-sized buffer which is
58 * partitioned between the fixed function units and used for passing
59 * values (vertices, primitives, constants) between them.
61 * CURBE - constant URB entry. An urb region (entry) used to hold
62 * constant values which the fixed function units can be instructed to
63 * preload into the GRF when spawning a thread.
65 * VUE - vertex URB entry. An urb entry holding a vertex and usually
66 * a vertex header. The header contains control information and
67 * things like primitive type, Begin/end flags and clip codes.
69 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
70 * unit holding rasterization and interpolation parameters.
72 * GRF - general register file. One of several register files
73 * addressable by programmed threads. The inputs (r0, payload, curbe,
74 * urb) of the thread are preloaded to this area before the thread is
75 * spawned. The registers are individually 8 dwords wide and suitable
76 * for general usage. Registers holding thread input values are not
77 * special and may be overwritten.
79 * MRF - message register file. Threads communicate (and terminate)
80 * by sending messages. Message parameters are placed in contiguous
81 * MRF registers. All program output is via these messages. URB
82 * entries are populated by sending a message to the shared URB
83 * function containing the new data, together with a control word,
84 * often an unmodified copy of R0.
86 * R0 - GRF register 0. Typically holds control information used when
87 * sending messages to other threads.
89 * EU or GEN4 EU: The name of the programmable subsystem of the
90 * i965 hardware. Threads are executed by the EU, the registers
91 * described above are part of the EU architecture.
93 * Fixed function units:
95 * CS - Command streamer. Notional first unit, little software
96 * interaction. Holds the URB entries used for constant data, ie the
99 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
100 * this unit is responsible for pulling vertices out of vertex buffers
101 * in vram and injecting them into the processing pipe as VUEs. If
102 * enabled, it first passes them to a VS thread which is a good place
103 * for the driver to implement any active vertex shader.
105 * HS - Hull Shader (Tessellation Control Shader)
107 * TE - Tessellation Engine (Tessellation Primitive Generation)
109 * DS - Domain Shader (Tessellation Evaluation Shader)
111 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
112 * enabled, incoming strips etc are passed to GS threads in individual
113 * line/triangle/point units. The GS thread may perform arbitary
114 * computation and emit whatever primtives with whatever vertices it
115 * chooses. This makes GS an excellent place to implement GL's
116 * unfilled polygon modes, though of course it is capable of much
117 * more. Additionally, GS is used to translate away primitives not
118 * handled by latter units, including Quads and Lineloops.
120 * CS - Clipper. Mesa's clipping algorithms are imported to run on
121 * this unit. The fixed function part performs cliptesting against
122 * the 6 fixed clipplanes and makes descisions on whether or not the
123 * incoming primitive needs to be passed to a thread for clipping.
124 * User clip planes are handled via cooperation with the VS thread.
126 * SF - Strips Fans or Setup: Triangles are prepared for
127 * rasterization. Interpolation coefficients are calculated.
128 * Flatshading and two-side lighting usually performed here.
130 * WM - Windower. Interpolation of vertex attributes performed here.
131 * Fragment shader implemented here. SIMD aspects of EU taken full
132 * advantage of, as pixels are processed in blocks of 16.
134 * CC - Color Calculator. No EU threads associated with this unit.
135 * Handles blending and (presumably) depth and stencil testing.
140 struct brw_vs_prog_key
;
141 struct brw_vue_prog_key
;
142 struct brw_wm_prog_key
;
143 struct brw_wm_prog_data
;
144 struct brw_cs_prog_key
;
145 struct brw_cs_prog_data
;
149 BRW_COMPUTE_PIPELINE
,
156 BRW_CACHE_BLORP_PROG
,
159 BRW_CACHE_FF_GS_PROG
,
170 /* brw_cache_ids must come first - see brw_program_cache.c */
171 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
172 BRW_STATE_FRAGMENT_PROGRAM
,
173 BRW_STATE_GEOMETRY_PROGRAM
,
174 BRW_STATE_TESS_PROGRAMS
,
175 BRW_STATE_VERTEX_PROGRAM
,
176 BRW_STATE_REDUCED_PRIMITIVE
,
177 BRW_STATE_PATCH_PRIMITIVE
,
182 BRW_STATE_BINDING_TABLE_POINTERS
,
185 BRW_STATE_DEFAULT_TESS_LEVELS
,
187 BRW_STATE_INDEX_BUFFER
,
188 BRW_STATE_VS_CONSTBUF
,
189 BRW_STATE_TCS_CONSTBUF
,
190 BRW_STATE_TES_CONSTBUF
,
191 BRW_STATE_GS_CONSTBUF
,
192 BRW_STATE_PROGRAM_CACHE
,
193 BRW_STATE_STATE_BASE_ADDRESS
,
194 BRW_STATE_VUE_MAP_GEOM_OUT
,
195 BRW_STATE_TRANSFORM_FEEDBACK
,
196 BRW_STATE_RASTERIZER_DISCARD
,
198 BRW_STATE_UNIFORM_BUFFER
,
199 BRW_STATE_ATOMIC_BUFFER
,
200 BRW_STATE_IMAGE_UNITS
,
201 BRW_STATE_META_IN_PROGRESS
,
202 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
203 BRW_STATE_NUM_SAMPLES
,
204 BRW_STATE_TEXTURE_BUFFER
,
205 BRW_STATE_GEN4_UNIT_STATE
,
209 BRW_STATE_SAMPLER_STATE_TABLE
,
210 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
211 BRW_STATE_COMPUTE_PROGRAM
,
212 BRW_STATE_CS_WORK_GROUPS
,
216 BRW_STATE_VIEWPORT_COUNT
,
217 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
222 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
224 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
225 * When the currently bound shader program differs from the previous draw
226 * call, these will be flagged. They cover brw->{stage}_program and
227 * ctx->{Stage}Program->_Current.
229 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
230 * driver perspective. Even if the same shader is bound at the API level,
231 * we may need to switch between multiple versions of that shader to handle
232 * changes in non-orthagonal state.
234 * Additionally, multiple shader programs may have identical vertex shaders
235 * (for example), or compile down to the same code in the backend. We combine
236 * those into a single program cache entry.
238 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
239 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
241 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
242 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
243 * use the normal state upload paths), but the cache is still used. To avoid
244 * polluting the brw_program_cache code with special cases, we retain the
245 * dirty bit for now. It should eventually be removed.
247 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
248 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
249 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
250 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
251 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
252 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
253 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
254 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
255 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
256 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
257 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
258 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
259 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
260 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
261 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
262 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
263 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
264 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
265 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
266 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
267 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
268 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
269 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
270 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
272 * Used for any batch entry with a relocated pointer that will be used
273 * by any 3D rendering.
275 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
276 /** \see brw.state.depth_region */
277 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
278 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
279 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
280 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
281 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
282 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
283 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
284 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
285 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
286 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
287 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
288 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
289 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
290 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
291 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
292 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
293 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
294 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
295 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
296 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
297 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
298 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
299 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
300 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
301 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
302 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
303 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
304 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
305 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
306 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
307 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
309 struct brw_state_flags
{
310 /** State update flags signalled by mesa internals */
313 * State update flags signalled as the result of brw_tracked_state updates
319 /** Subclass of Mesa program */
321 struct gl_program program
;
328 struct brw_sf_prog_data
{
329 GLuint urb_read_length
;
332 /* Each vertex may have upto 12 attributes, 4 components each,
333 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
336 * Actually we use 4 for each, so call it 12 rows.
338 GLuint urb_entry_size
;
342 struct brw_clip_prog_data
{
343 GLuint curb_read_length
; /* user planes? */
345 GLuint urb_read_length
;
349 struct brw_ff_gs_prog_data
{
350 GLuint urb_read_length
;
354 * Gen6 transform feedback: Amount by which the streaming vertex buffer
355 * indices should be incremented each time the GS is invoked.
357 unsigned svbi_postincrement_value
;
360 /** Number of texture sampler units */
361 #define BRW_MAX_TEX_UNIT 32
363 /** Max number of UBOs in a shader */
364 #define BRW_MAX_UBO 14
366 /** Max number of SSBOs in a shader */
367 #define BRW_MAX_SSBO 12
369 /** Max number of atomic counter buffer objects in a shader */
370 #define BRW_MAX_ABO 16
372 /** Max number of image uniforms in a shader */
373 #define BRW_MAX_IMAGES 32
375 /** Maximum number of actual buffers used for stream output */
376 #define BRW_MAX_SOL_BUFFERS 4
378 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
379 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
384 2 + /* shader time, pull constants */ \
385 1 /* cs num work groups */)
388 struct brw_context
*brw
;
390 struct brw_cache_item
**items
;
392 GLuint size
, n_items
;
394 uint32_t next_offset
;
398 /* Considered adding a member to this struct to document which flags
399 * an update might raise so that ordering of the state atoms can be
400 * checked or derived at runtime. Dropped the idea in favor of having
401 * a debug mode where the state is monitored for flags which are
402 * raised that have already been tested against.
404 struct brw_tracked_state
{
405 struct brw_state_flags dirty
;
406 void (*emit
)( struct brw_context
*brw
);
409 enum shader_time_shader_type
{
420 struct brw_vertex_buffer
{
421 /** Buffer object containing the uploaded vertex data */
425 /** Byte stride between elements in the uploaded array */
429 struct brw_vertex_element
{
430 const struct gl_vertex_array
*glarray
;
434 /** Offset of the first element within the buffer object */
438 struct brw_query_object
{
439 struct gl_query_object Base
;
441 /** Last query BO associated with this query. */
444 /** Last index in bo with query data for this object. */
447 /** True if we know the batch has been flushed since we ended the query. */
457 struct intel_batchbuffer
{
458 /** Current batchbuffer being queued up. */
460 /** Last BO submitted to the hardware. Used for glFinish(). */
461 struct brw_bo
*last_bo
;
464 uint16_t emit
, total
;
466 uint16_t reserved_space
;
470 #define BATCH_SZ (8192*sizeof(uint32_t))
472 uint32_t state_batch_offset
;
473 enum brw_gpu_ring ring
;
474 bool needs_sol_reset
;
475 bool state_base_address_emitted
;
477 struct drm_i915_gem_relocation_entry
*relocs
;
479 int reloc_array_size
;
480 /** The validation list */
481 struct drm_i915_gem_exec_object2
*exec_objects
;
482 struct brw_bo
**exec_bos
;
485 /** The amount of aperture space (in bytes) used by all exec_bos */
494 /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */
495 struct hash_table
*state_batch_sizes
;
498 #define BRW_MAX_XFB_STREAMS 4
500 struct brw_transform_feedback_object
{
501 struct gl_transform_feedback_object base
;
503 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
504 struct brw_bo
*offset_bo
;
506 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
509 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
510 GLenum primitive_mode
;
513 * The maximum number of vertices that we can write without overflowing
514 * any of the buffers currently being used for transform feedback.
519 * Count of primitives generated during this transform feedback operation.
522 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
523 struct brw_bo
*prim_count_bo
;
524 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
528 * Number of vertices written between last Begin/EndTransformFeedback().
530 * Used to implement DrawTransformFeedback().
532 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
533 bool vertices_written_valid
;
537 * Data shared between each programmable stage in the pipeline (vs, gs, and
540 struct brw_stage_state
542 gl_shader_stage stage
;
543 struct brw_stage_prog_data
*prog_data
;
546 * Optional scratch buffer used to store spilled register values and
547 * variably-indexed GRF arrays.
549 * The contents of this buffer are short-lived so the same memory can be
550 * re-used at will for multiple shader programs (executed by the same fixed
551 * function). However reusing a scratch BO for which shader invocations
552 * are still in flight with a per-thread scratch slot size other than the
553 * original can cause threads with different scratch slot size and FFTID
554 * (which may be executed in parallel depending on the shader stage and
555 * hardware generation) to map to an overlapping region of the scratch
556 * space, which can potentially lead to mutual scratch space corruption.
557 * For that reason if you borrow this scratch buffer you should only be
558 * using the slot size given by the \c per_thread_scratch member below,
559 * unless you're taking additional measures to synchronize thread execution
560 * across slot size changes.
562 struct brw_bo
*scratch_bo
;
565 * Scratch slot size allocated for each thread in the buffer object given
568 uint32_t per_thread_scratch
;
570 /** Offset in the program cache to the program */
571 uint32_t prog_offset
;
573 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
574 uint32_t state_offset
;
576 uint32_t push_const_offset
; /* Offset in the batchbuffer */
577 int push_const_size
; /* in 256-bit register increments */
579 /* Binding table: pointers to SURFACE_STATE entries. */
580 uint32_t bind_bo_offset
;
581 uint32_t surf_offset
[BRW_MAX_SURFACES
];
583 /** SAMPLER_STATE count and table offset */
584 uint32_t sampler_count
;
585 uint32_t sampler_offset
;
588 enum brw_predicate_state
{
589 /* The first two states are used if we can determine whether to draw
590 * without having to look at the values in the query object buffer. This
591 * will happen if there is no conditional render in progress, if the query
592 * object is already completed or if something else has already added
593 * samples to the preliminary result such as via a BLT command.
595 BRW_PREDICATE_STATE_RENDER
,
596 BRW_PREDICATE_STATE_DONT_RENDER
,
597 /* In this case whether to draw or not depends on the result of an
598 * MI_PREDICATE command so the predicate enable bit needs to be checked.
600 BRW_PREDICATE_STATE_USE_BIT
605 struct gen_l3_config
;
607 enum brw_query_kind
{
612 struct brw_perf_query_info
614 enum brw_query_kind kind
;
617 struct brw_perf_query_counter
*counters
;
622 uint64_t oa_metrics_set_id
;
625 /* For indexing into the accumulator[] ... */
627 int gpu_clock_offset
;
634 * brw_context is derived from gl_context.
638 struct gl_context ctx
; /**< base class, must be first field */
642 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
643 struct gl_renderbuffer
*rb
,
644 uint32_t flags
, unsigned unit
,
645 uint32_t surf_index
);
646 void (*emit_null_surface_state
)(struct brw_context
*brw
,
650 uint32_t *out_offset
);
653 * Send the appropriate state packets to configure depth, stencil, and
654 * HiZ buffers (i965+ only)
656 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
657 struct intel_mipmap_tree
*depth_mt
,
658 uint32_t depth_offset
,
659 uint32_t depthbuffer_format
,
660 uint32_t depth_surface_type
,
661 struct intel_mipmap_tree
*stencil_mt
,
662 bool hiz
, bool separate_stencil
,
663 uint32_t width
, uint32_t height
,
664 uint32_t tile_x
, uint32_t tile_y
);
668 struct brw_bufmgr
*bufmgr
;
672 /** BO for post-sync nonzero writes for gen6 workaround. */
673 struct brw_bo
*workaround_bo
;
674 uint8_t pipe_controls_since_last_cs_stall
;
677 * Set of struct brw_bo * that have been rendered to within this batchbuffer
678 * and would need flushing before being used from another cache domain that
679 * isn't coherent with it (i.e. the sampler).
681 struct set
*render_cache
;
684 * Number of resets observed in the system at context creation.
686 * This is tracked in the context so that we can determine that another
687 * reset has occurred.
689 uint32_t reset_count
;
691 struct intel_batchbuffer batch
;
696 uint32_t next_offset
;
700 * Set if rendering has occurred to the drawable's front buffer.
702 * This is used in the DRI2 case to detect that glFlush should also copy
703 * the contents of the fake front buffer to the real front buffer.
705 bool front_buffer_dirty
;
707 /** Framerate throttling: @{ */
708 struct brw_bo
*throttle_batch
[2];
710 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
711 * frame of rendering to complete. This gives a very precise cap to the
712 * latency between input and output such that rendering never gets more
713 * than a frame behind the user. (With the caveat that we technically are
714 * not using the SwapBuffers itself as a barrier but the first batch
715 * submitted afterwards, which may be immediately prior to the next
718 bool need_swap_throttle
;
720 /** General throttling, not caught by throttling between SwapBuffers */
721 bool need_flush_throttle
;
731 bool always_flush_batch
;
732 bool always_flush_cache
;
733 bool disable_throttling
;
735 bool dual_color_blend_by_location
;
737 driOptionCache optionCache
;
740 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
742 GLenum reduced_primitive
;
745 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
746 * variable is set, this is the flag indicating to do expensive work that
747 * might lead to a perf_debug() call.
751 uint64_t max_gtt_map_object_size
;
763 bool has_separate_stencil
;
764 bool must_use_separate_stencil
;
767 bool has_surface_tile_offset
;
769 bool has_negative_rhw_bug
;
773 bool use_resource_streamer
;
776 * Some versions of Gen hardware don't do centroid interpolation correctly
777 * on unlit pixels, causing incorrect values for derivatives near triangle
778 * edges. Enabling this flag causes the fragment shader to use
779 * non-centroid interpolation for unlit pixels, at the expense of two extra
780 * fragment shader instructions.
782 bool needs_unlit_centroid_workaround
;
784 struct isl_device isl_dev
;
786 struct blorp_context blorp
;
790 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
793 enum brw_pipeline last_pipeline
;
795 struct brw_cache cache
;
797 /** IDs for meta stencil blit shader programs. */
798 struct gl_shader_program
*meta_stencil_blit_programs
[2];
800 /* Whether a meta-operation is in progress. */
801 bool meta_in_progress
;
803 /* Whether the last depth/stencil packets were both NULL. */
804 bool no_depth_or_stencil
;
806 /* The last PMA stall bits programmed. */
807 uint32_t pma_stall_bits
;
811 /** The value of gl_BaseVertex for the current _mesa_prim. */
814 /** The value of gl_BaseInstance for the current _mesa_prim. */
819 * Buffer and offset used for GL_ARB_shader_draw_parameters
820 * (for now, only gl_BaseVertex).
822 struct brw_bo
*draw_params_bo
;
823 uint32_t draw_params_offset
;
826 * The value of gl_DrawID for the current _mesa_prim. This always comes
827 * in from it's own vertex buffer since it's not part of the indirect
831 struct brw_bo
*draw_id_bo
;
832 uint32_t draw_id_offset
;
837 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
838 * an indirect call, and num_work_groups_offset is valid. Otherwise,
839 * num_work_groups is set based on glDispatchCompute.
841 struct brw_bo
*num_work_groups_bo
;
842 GLintptr num_work_groups_offset
;
843 const GLuint
*num_work_groups
;
847 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
848 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
850 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
854 /* Summary of size and varying of active arrays, so we can check
855 * for changes to this state:
857 bool index_bounds_valid
;
858 unsigned int min_index
, max_index
;
860 /* Offset from start of vertex buffer so we can avoid redefining
861 * the same VB packed over and over again.
863 unsigned int start_vertex_bias
;
866 * Certain vertex attribute formats aren't natively handled by the
867 * hardware and require special VS code to fix up their values.
869 * These bitfields indicate which workarounds are needed.
871 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
876 * Index buffer for this draw_prims call.
878 * Updates are signaled by BRW_NEW_INDICES.
880 const struct _mesa_index_buffer
*ib
;
882 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
887 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
888 * avoid re-uploading the IB packet over and over if we're actually
889 * referencing the same index buffer.
891 unsigned int start_vertex_offset
;
894 /* Active vertex program:
896 const struct gl_program
*vertex_program
;
897 const struct gl_program
*geometry_program
;
898 const struct gl_program
*tess_ctrl_program
;
899 const struct gl_program
*tess_eval_program
;
900 const struct gl_program
*fragment_program
;
901 const struct gl_program
*compute_program
;
904 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
905 * that we don't have to reemit that state every time we change FBOs.
909 /* BRW_NEW_URB_ALLOCATIONS:
912 GLuint vsize
; /* vertex size plus header in urb registers */
913 GLuint gsize
; /* GS output size in urb registers */
914 GLuint hsize
; /* Tessellation control output size in urb registers */
915 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
916 GLuint csize
; /* constant buffer size in urb registers */
917 GLuint sfsize
; /* setup data size in urb registers */
921 GLuint nr_vs_entries
;
922 GLuint nr_hs_entries
;
923 GLuint nr_ds_entries
;
924 GLuint nr_gs_entries
;
925 GLuint nr_clip_entries
;
926 GLuint nr_sf_entries
;
927 GLuint nr_cs_entries
;
937 * URB size in the current configuration. The units this is expressed
938 * in are somewhat inconsistent, see gen_device_info::urb::size.
940 * FINISHME: Represent the URB size consistently in KB on all platforms.
944 /* True if the most recently sent _3DSTATE_URB message allocated
945 * URB space for the GS.
949 /* True if the most recently sent _3DSTATE_URB message allocated
950 * URB space for the HS and DS.
956 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
958 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
959 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
967 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
968 * for upload to the CURBE.
970 struct brw_bo
*curbe_bo
;
971 /** Offset within curbe_bo of space for current curbe entry */
976 * Layout of vertex data exiting the geometry portion of the pipleine.
977 * This comes from the last enabled shader stage (GS, DS, or VS).
979 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
981 struct brw_vue_map vue_map_geom_out
;
984 struct brw_stage_state base
;
988 struct brw_stage_state base
;
991 * True if the 3DSTATE_HS command most recently emitted to the 3D
992 * pipeline enabled the HS; false otherwise.
998 struct brw_stage_state base
;
1001 * True if the 3DSTATE_DS command most recently emitted to the 3D
1002 * pipeline enabled the DS; false otherwise.
1008 struct brw_stage_state base
;
1011 * True if the 3DSTATE_GS command most recently emitted to the 3D
1012 * pipeline enabled the GS; false otherwise.
1018 struct brw_ff_gs_prog_data
*prog_data
;
1021 /** Offset in the program cache to the CLIP program pre-gen6 */
1022 uint32_t prog_offset
;
1023 uint32_t state_offset
;
1025 uint32_t bind_bo_offset
;
1027 * Surface offsets for the binding table. We only need surfaces to
1028 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1029 * need in this case.
1031 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1035 struct brw_clip_prog_data
*prog_data
;
1037 /** Offset in the program cache to the CLIP program pre-gen6 */
1038 uint32_t prog_offset
;
1040 /* Offset in the batch to the CLIP state on pre-gen6. */
1041 uint32_t state_offset
;
1043 /* As of gen6, this is the offset in the batch to the CLIP VP,
1049 * The number of viewports to use. If gl_ViewportIndex is written,
1050 * we can have up to ctx->Const.MaxViewports viewports. If not,
1051 * the viewport index is always 0, so we can only emit one.
1053 uint8_t viewport_count
;
1058 struct brw_sf_prog_data
*prog_data
;
1060 /** Offset in the program cache to the CLIP program pre-gen6 */
1061 uint32_t prog_offset
;
1062 uint32_t state_offset
;
1067 struct brw_stage_state base
;
1072 * Buffer object used in place of multisampled null render targets on
1073 * Gen6. See brw_emit_null_surface_state().
1075 struct brw_bo
*multisampled_null_render_target_bo
;
1076 uint32_t fast_clear_op
;
1082 struct brw_stage_state base
;
1086 uint32_t state_offset
;
1087 uint32_t blend_state_offset
;
1088 uint32_t depth_stencil_state_offset
;
1093 struct brw_query_object
*obj
;
1098 enum brw_predicate_state state
;
1103 /* Variables referenced in the XML meta data for OA performance
1104 * counters, e.g in the normalization equations.
1106 * All uint64_t for consistent operand types in generated code
1109 uint64_t timestamp_frequency
; /** $GpuTimestampFrequency */
1110 uint64_t n_eus
; /** $EuCoresTotalCount */
1111 uint64_t n_eu_slices
; /** $EuSlicesTotalCount */
1112 uint64_t subslice_mask
; /** $SubsliceMask */
1113 uint64_t gt_min_freq
; /** $GpuMinFrequency */
1114 uint64_t gt_max_freq
; /** $GpuMaxFrequency */
1117 /* OA metric sets, indexed by GUID, as know by Mesa at build time,
1118 * to cross-reference with the GUIDs of configs advertised by the
1121 struct hash_table
*oa_metrics_table
;
1123 struct brw_perf_query_info
*queries
;
1126 /* The i915 perf stream we open to setup + enable the OA counters */
1129 /* An i915 perf stream fd gives exclusive access to the OA unit that will
1130 * report counter snapshots for a specific counter set/profile in a
1131 * specific layout/format so we can only start OA queries that are
1132 * compatible with the currently open fd...
1134 int current_oa_metrics_set_id
;
1135 int current_oa_format
;
1137 /* List of buffers containing OA reports */
1138 struct exec_list sample_buffers
;
1140 /* Cached list of empty sample buffers */
1141 struct exec_list free_sample_buffers
;
1143 int n_active_oa_queries
;
1144 int n_active_pipeline_stats_queries
;
1146 /* The number of queries depending on running OA counters which
1147 * extends beyond brw_end_perf_query() since we need to wait until
1148 * the last MI_RPC command has parsed by the GPU.
1150 * Accurate accounting is important here as emitting an
1151 * MI_REPORT_PERF_COUNT command while the OA unit is disabled will
1152 * effectively hang the gpu.
1156 /* To help catch an spurious problem with the hardware or perf
1157 * forwarding samples, we emit each MI_REPORT_PERF_COUNT command
1158 * with a unique ID that we can explicitly check for...
1160 int next_query_start_report_id
;
1163 * An array of queries whose results haven't yet been assembled
1164 * based on the data in buffer objects.
1166 * These may be active, or have already ended. However, the
1167 * results have not been requested.
1169 struct brw_perf_query_object
**unaccumulated
;
1170 int unaccumulated_elements
;
1171 int unaccumulated_array_size
;
1173 /* The total number of query objects so we can relinquish
1174 * our exclusive access to perf if the application deletes
1175 * all of its objects. (NB: We only disable perf while
1176 * there are no active queries)
1178 int n_query_instances
;
1181 int num_atoms
[BRW_NUM_PIPELINES
];
1182 const struct brw_tracked_state render_atoms
[76];
1183 const struct brw_tracked_state compute_atoms
[11];
1185 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1186 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1188 /* PrimitiveRestart */
1191 bool enable_cut_index
;
1194 /** Computed depth/stencil/hiz state from the current attached
1195 * renderbuffers, valid only during the drawing state upload loop after
1196 * brw_workaround_depthstencil_alignment().
1199 struct intel_mipmap_tree
*depth_mt
;
1200 struct intel_mipmap_tree
*stencil_mt
;
1202 /* Inter-tile (page-aligned) byte offsets. */
1203 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1204 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1205 uint32_t tile_x
, tile_y
;
1208 uint32_t num_instances
;
1213 const struct gen_l3_config
*config
;
1220 enum shader_time_shader_type
*types
;
1221 struct shader_times
*cumulative
;
1227 struct brw_fast_clear_state
*fast_clear_state
;
1229 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1230 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1231 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1233 * This is needed in case the same underlying buffer is also configured
1234 * to be sampled but with a format that the sampling engine can't treat
1235 * compressed or fast cleared.
1237 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1239 __DRIcontext
*driContext
;
1240 struct intel_screen
*screen
;
1244 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1246 /*======================================================================
1249 extern const char *const brw_vendor_string
;
1252 brw_get_renderer_string(const struct intel_screen
*screen
);
1255 DRI_CONF_BO_REUSE_DISABLED
,
1256 DRI_CONF_BO_REUSE_ALL
1259 void intel_update_renderbuffers(__DRIcontext
*context
,
1260 __DRIdrawable
*drawable
);
1261 void intel_prepare_render(struct brw_context
*brw
);
1263 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1264 __DRIdrawable
*drawable
);
1266 GLboolean
brwCreateContext(gl_api api
,
1267 const struct gl_config
*mesaVis
,
1268 __DRIcontext
*driContextPriv
,
1269 unsigned major_version
,
1270 unsigned minor_version
,
1274 void *sharedContextPrivate
);
1276 /*======================================================================
1280 brw_meta_resolve_color(struct brw_context
*brw
,
1281 struct intel_mipmap_tree
*mt
);
1283 /*======================================================================
1286 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1287 GLbitfield clear_mask
);
1289 /* brw_object_purgeable.c */
1290 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1292 /*======================================================================
1295 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1296 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1297 void brw_emit_query_begin(struct brw_context
*brw
);
1298 void brw_emit_query_end(struct brw_context
*brw
);
1299 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1300 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1301 uint64_t brw_timebase_scale(struct brw_context
*brw
, uint64_t gpu_timestamp
);
1302 uint64_t brw_raw_timestamp_delta(struct brw_context
*brw
,
1303 uint64_t time0
, uint64_t time1
);
1305 /** gen6_queryobj.c */
1306 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1307 void brw_write_timestamp(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1308 void brw_write_depth_count(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1310 /** hsw_queryobj.c */
1311 void hsw_overflow_result_to_gpr0(struct brw_context
*brw
,
1312 struct brw_query_object
*query
,
1314 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1316 /** brw_conditional_render.c */
1317 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1318 bool brw_check_conditional_render(struct brw_context
*brw
);
1320 /** intel_batchbuffer.c */
1321 void brw_load_register_mem(struct brw_context
*brw
,
1324 uint32_t read_domains
, uint32_t write_domain
,
1326 void brw_load_register_mem64(struct brw_context
*brw
,
1329 uint32_t read_domains
, uint32_t write_domain
,
1331 void brw_store_register_mem32(struct brw_context
*brw
,
1332 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1333 void brw_store_register_mem64(struct brw_context
*brw
,
1334 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1335 void brw_load_register_imm32(struct brw_context
*brw
,
1336 uint32_t reg
, uint32_t imm
);
1337 void brw_load_register_imm64(struct brw_context
*brw
,
1338 uint32_t reg
, uint64_t imm
);
1339 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1341 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1343 void brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1344 uint32_t offset
, uint32_t imm
);
1345 void brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1346 uint32_t offset
, uint64_t imm
);
1348 /*======================================================================
1349 * intel_tex_validate.c
1351 void brw_validate_textures( struct brw_context
*brw
);
1354 /*======================================================================
1358 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1361 perf_debug(" %s %d->%d\n", name
, a
, b
);
1367 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1369 void brw_get_scratch_bo(struct brw_context
*brw
,
1370 struct brw_bo
**scratch_bo
, int size
);
1371 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1372 struct brw_stage_state
*stage_state
,
1373 unsigned per_thread_size
,
1374 unsigned thread_count
);
1375 void brw_init_shader_time(struct brw_context
*brw
);
1376 int brw_get_shader_time_index(struct brw_context
*brw
,
1377 struct gl_program
*prog
,
1378 enum shader_time_shader_type type
,
1380 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1381 void brw_destroy_shader_time(struct brw_context
*brw
);
1385 void brw_upload_urb_fence(struct brw_context
*brw
);
1389 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1392 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1394 /* brw_draw_upload.c */
1395 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1396 const struct gl_vertex_array
*glarray
);
1398 static inline unsigned
1399 brw_get_index_type(unsigned index_size
)
1401 /* The hw needs 0x00, 0x01, and 0x02 for ubyte, ushort, and uint,
1404 return index_size
>> 1;
1407 void brw_prepare_vertices(struct brw_context
*brw
);
1409 /* brw_wm_surface_state.c */
1410 void brw_init_surface_formats(struct brw_context
*brw
);
1411 void brw_create_constant_surface(struct brw_context
*brw
,
1415 uint32_t *out_offset
);
1416 void brw_create_buffer_surface(struct brw_context
*brw
,
1420 uint32_t *out_offset
);
1421 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1423 uint32_t *surf_offset
);
1425 brw_update_sol_surface(struct brw_context
*brw
,
1426 struct gl_buffer_object
*buffer_obj
,
1427 uint32_t *out_offset
, unsigned num_vector_components
,
1428 unsigned stride_dwords
, unsigned offset_dwords
);
1429 void brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1430 struct brw_stage_state
*stage_state
,
1431 struct brw_stage_prog_data
*prog_data
);
1432 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1433 const struct gl_program
*prog
,
1434 struct brw_stage_state
*stage_state
,
1435 struct brw_stage_prog_data
*prog_data
);
1436 void brw_upload_image_surfaces(struct brw_context
*brw
,
1437 const struct gl_program
*prog
,
1438 struct brw_stage_state
*stage_state
,
1439 struct brw_stage_prog_data
*prog_data
);
1441 /* brw_surface_formats.c */
1442 bool brw_render_target_supported(struct brw_context
*brw
,
1443 struct gl_renderbuffer
*rb
);
1444 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1446 /* brw_performance_query.c */
1447 void brw_init_performance_queries(struct brw_context
*brw
);
1449 /* intel_extensions.c */
1450 extern void intelInitExtensions(struct gl_context
*ctx
);
1453 extern int intel_translate_shadow_compare_func(GLenum func
);
1454 extern int intel_translate_compare_func(GLenum func
);
1455 extern int intel_translate_stencil_op(GLenum op
);
1456 extern int intel_translate_logic_op(GLenum opcode
);
1459 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1462 struct gl_transform_feedback_object
*
1463 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1465 brw_delete_transform_feedback(struct gl_context
*ctx
,
1466 struct gl_transform_feedback_object
*obj
);
1468 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1469 struct gl_transform_feedback_object
*obj
);
1471 brw_end_transform_feedback(struct gl_context
*ctx
,
1472 struct gl_transform_feedback_object
*obj
);
1474 brw_pause_transform_feedback(struct gl_context
*ctx
,
1475 struct gl_transform_feedback_object
*obj
);
1477 brw_resume_transform_feedback(struct gl_context
*ctx
,
1478 struct gl_transform_feedback_object
*obj
);
1480 brw_save_primitives_written_counters(struct brw_context
*brw
,
1481 struct brw_transform_feedback_object
*obj
);
1483 brw_compute_xfb_vertices_written(struct brw_context
*brw
,
1484 struct brw_transform_feedback_object
*obj
);
1486 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1487 struct gl_transform_feedback_object
*obj
,
1490 /* gen7_sol_state.c */
1492 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1493 struct gl_transform_feedback_object
*obj
);
1495 gen7_end_transform_feedback(struct gl_context
*ctx
,
1496 struct gl_transform_feedback_object
*obj
);
1498 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1499 struct gl_transform_feedback_object
*obj
);
1501 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1502 struct gl_transform_feedback_object
*obj
);
1506 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1507 struct gl_transform_feedback_object
*obj
);
1509 hsw_end_transform_feedback(struct gl_context
*ctx
,
1510 struct gl_transform_feedback_object
*obj
);
1512 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1513 struct gl_transform_feedback_object
*obj
);
1515 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1516 struct gl_transform_feedback_object
*obj
);
1518 /* brw_blorp_blit.cpp */
1520 brw_blorp_framebuffer(struct brw_context
*brw
,
1521 struct gl_framebuffer
*readFb
,
1522 struct gl_framebuffer
*drawFb
,
1523 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1524 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1525 GLbitfield mask
, GLenum filter
);
1528 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1529 struct gl_renderbuffer
*src_rb
,
1530 struct gl_texture_image
*dst_image
,
1532 int srcX0
, int srcY0
,
1533 int dstX0
, int dstY0
,
1534 int width
, int height
);
1537 gen6_get_sample_position(struct gl_context
*ctx
,
1538 struct gl_framebuffer
*fb
,
1542 gen6_set_sample_maps(struct gl_context
*ctx
);
1544 /* gen8_multisample_state.c */
1545 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1546 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1550 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1551 unsigned hs_size
, unsigned ds_size
,
1552 unsigned gs_size
, unsigned fs_size
);
1555 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1556 bool gs_present
, unsigned gs_size
);
1558 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1559 bool gs_present
, bool tess_present
);
1563 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1565 brw_check_for_reset(struct brw_context
*brw
);
1569 brw_init_compute_functions(struct dd_function_table
*functions
);
1571 /*======================================================================
1572 * Inline conversion functions. These are better-typed than the
1573 * macros used previously:
1575 static inline struct brw_context
*
1576 brw_context( struct gl_context
*ctx
)
1578 return (struct brw_context
*)ctx
;
1581 static inline struct brw_program
*
1582 brw_program(struct gl_program
*p
)
1584 return (struct brw_program
*) p
;
1587 static inline const struct brw_program
*
1588 brw_program_const(const struct gl_program
*p
)
1590 return (const struct brw_program
*) p
;
1594 brw_depth_writes_enabled(const struct brw_context
*brw
)
1596 const struct gl_context
*ctx
= &brw
->ctx
;
1598 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1599 * because it would just overwrite the existing depth value with itself.
1601 * These bonus depth writes not only use bandwidth, but they also can
1602 * prevent early depth processing. For example, if the pixel shader
1603 * discards, the hardware must invoke the to determine whether or not
1604 * to do the depth write. If writes are disabled, we may still be able
1605 * to do the depth test before the shader, and skip the shader execution.
1607 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1608 * a programming note saying to disable depth writes for EQUAL.
1610 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1614 brw_emit_depthbuffer(struct brw_context
*brw
);
1617 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1618 struct intel_mipmap_tree
*depth_mt
,
1619 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1620 uint32_t depth_surface_type
,
1621 struct intel_mipmap_tree
*stencil_mt
,
1622 bool hiz
, bool separate_stencil
,
1623 uint32_t width
, uint32_t height
,
1624 uint32_t tile_x
, uint32_t tile_y
);
1627 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1628 struct intel_mipmap_tree
*depth_mt
,
1629 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1630 uint32_t depth_surface_type
,
1631 struct intel_mipmap_tree
*stencil_mt
,
1632 bool hiz
, bool separate_stencil
,
1633 uint32_t width
, uint32_t height
,
1634 uint32_t tile_x
, uint32_t tile_y
);
1637 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1638 struct intel_mipmap_tree
*depth_mt
,
1639 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1640 uint32_t depth_surface_type
,
1641 struct intel_mipmap_tree
*stencil_mt
,
1642 bool hiz
, bool separate_stencil
,
1643 uint32_t width
, uint32_t height
,
1644 uint32_t tile_x
, uint32_t tile_y
);
1646 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1647 struct intel_mipmap_tree
*depth_mt
,
1648 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1649 uint32_t depth_surface_type
,
1650 struct intel_mipmap_tree
*stencil_mt
,
1651 bool hiz
, bool separate_stencil
,
1652 uint32_t width
, uint32_t height
,
1653 uint32_t tile_x
, uint32_t tile_y
);
1655 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1656 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
);
1658 uint32_t get_hw_prim_for_gl_prim(int mode
);
1661 gen6_upload_push_constants(struct brw_context
*brw
,
1662 const struct gl_program
*prog
,
1663 const struct brw_stage_prog_data
*prog_data
,
1664 struct brw_stage_state
*stage_state
);
1667 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1668 const struct intel_mipmap_tree
*mt
);
1670 /* brw_pipe_control.c */
1671 int brw_init_pipe_control(struct brw_context
*brw
,
1672 const struct gen_device_info
*info
);
1673 void brw_fini_pipe_control(struct brw_context
*brw
);
1675 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1676 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1677 struct brw_bo
*bo
, uint32_t offset
,
1678 uint32_t imm_lower
, uint32_t imm_upper
);
1679 void brw_emit_mi_flush(struct brw_context
*brw
);
1680 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1681 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1682 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1683 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1685 /* brw_queryformat.c */
1686 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1687 GLenum internalFormat
, GLenum pname
,