2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
46 /* Evil hack for using libdrm in a c++ compiler. */
51 #include <intel_bufmgr.h>
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
67 * URB - uniform resource buffer. A mid-sized buffer which is
68 * partitioned between the fixed function units and used for passing
69 * values (vertices, primitives, constants) between them.
71 * CURBE - constant URB entry. An urb region (entry) used to hold
72 * constant values which the fixed function units can be instructed to
73 * preload into the GRF when spawning a thread.
75 * VUE - vertex URB entry. An urb entry holding a vertex and usually
76 * a vertex header. The header contains control information and
77 * things like primitive type, Begin/end flags and clip codes.
79 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
80 * unit holding rasterization and interpolation parameters.
82 * GRF - general register file. One of several register files
83 * addressable by programmed threads. The inputs (r0, payload, curbe,
84 * urb) of the thread are preloaded to this area before the thread is
85 * spawned. The registers are individually 8 dwords wide and suitable
86 * for general usage. Registers holding thread input values are not
87 * special and may be overwritten.
89 * MRF - message register file. Threads communicate (and terminate)
90 * by sending messages. Message parameters are placed in contiguous
91 * MRF registers. All program output is via these messages. URB
92 * entries are populated by sending a message to the shared URB
93 * function containing the new data, together with a control word,
94 * often an unmodified copy of R0.
96 * R0 - GRF register 0. Typically holds control information used when
97 * sending messages to other threads.
99 * EU or GEN4 EU: The name of the programmable subsystem of the
100 * i965 hardware. Threads are executed by the EU, the registers
101 * described above are part of the EU architecture.
103 * Fixed function units:
105 * CS - Command streamer. Notional first unit, little software
106 * interaction. Holds the URB entries used for constant data, ie the
109 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
110 * this unit is responsible for pulling vertices out of vertex buffers
111 * in vram and injecting them into the processing pipe as VUEs. If
112 * enabled, it first passes them to a VS thread which is a good place
113 * for the driver to implement any active vertex shader.
115 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
116 * enabled, incoming strips etc are passed to GS threads in individual
117 * line/triangle/point units. The GS thread may perform arbitary
118 * computation and emit whatever primtives with whatever vertices it
119 * chooses. This makes GS an excellent place to implement GL's
120 * unfilled polygon modes, though of course it is capable of much
121 * more. Additionally, GS is used to translate away primitives not
122 * handled by latter units, including Quads and Lineloops.
124 * CS - Clipper. Mesa's clipping algorithms are imported to run on
125 * this unit. The fixed function part performs cliptesting against
126 * the 6 fixed clipplanes and makes descisions on whether or not the
127 * incoming primitive needs to be passed to a thread for clipping.
128 * User clip planes are handled via cooperation with the VS thread.
130 * SF - Strips Fans or Setup: Triangles are prepared for
131 * rasterization. Interpolation coefficients are calculated.
132 * Flatshading and two-side lighting usually performed here.
134 * WM - Windower. Interpolation of vertex attributes performed here.
135 * Fragment shader implemented here. SIMD aspects of EU taken full
136 * advantage of, as pixels are processed in blocks of 16.
138 * CC - Color Calculator. No EU threads associated with this unit.
139 * Handles blending and (presumably) depth and stencil testing.
142 #define BRW_MAX_CURBE (32*16)
145 struct brw_instruction
;
146 struct brw_vs_prog_key
;
147 struct brw_vec4_prog_key
;
148 struct brw_wm_prog_key
;
149 struct brw_wm_prog_data
;
153 BRW_STATE_FRAGMENT_PROGRAM
,
154 BRW_STATE_GEOMETRY_PROGRAM
,
155 BRW_STATE_VERTEX_PROGRAM
,
156 BRW_STATE_CURBE_OFFSETS
,
157 BRW_STATE_REDUCED_PRIMITIVE
,
162 BRW_STATE_VS_BINDING_TABLE
,
163 BRW_STATE_GS_BINDING_TABLE
,
164 BRW_STATE_PS_BINDING_TABLE
,
168 BRW_STATE_INDEX_BUFFER
,
169 BRW_STATE_VS_CONSTBUF
,
170 BRW_STATE_GS_CONSTBUF
,
171 BRW_STATE_PROGRAM_CACHE
,
172 BRW_STATE_STATE_BASE_ADDRESS
,
173 BRW_STATE_VUE_MAP_VS
,
174 BRW_STATE_VUE_MAP_GEOM_OUT
,
175 BRW_STATE_TRANSFORM_FEEDBACK
,
176 BRW_STATE_RASTERIZER_DISCARD
,
178 BRW_STATE_UNIFORM_BUFFER
,
179 BRW_STATE_ATOMIC_BUFFER
,
180 BRW_STATE_META_IN_PROGRESS
,
181 BRW_STATE_INTERPOLATION_MAP
,
182 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
186 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
187 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
188 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
189 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
190 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
191 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
192 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
193 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
194 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
195 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
196 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
197 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
198 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
199 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
200 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
202 * Used for any batch entry with a relocated pointer that will be used
203 * by any 3D rendering.
205 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
206 /** \see brw.state.depth_region */
207 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
208 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
209 #define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
210 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
211 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
212 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
213 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
214 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
215 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
216 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
217 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
218 #define BRW_NEW_ATOMIC_BUFFER (1 << BRW_STATE_ATOMIC_BUFFER)
219 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
220 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
221 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
223 struct brw_state_flags
{
224 /** State update flags signalled by mesa internals */
227 * State update flags signalled as the result of brw_tracked_state updates
230 /** State update flags signalled by brw_state_cache.c searches */
234 #define AUB_TRACE_TYPE_MASK 0x0000ff00
235 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
236 #define AUB_TRACE_TYPE_BATCH (1 << 8)
237 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
238 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
239 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
240 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
241 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
242 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
243 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
244 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
245 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
246 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
249 * state_struct_type enum values are encoded with the top 16 bits representing
250 * the type to be delivered to the .aub file, and the bottom 16 bits
251 * representing the subtype. This macro performs the encoding.
253 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
255 enum state_struct_type
{
256 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
257 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
258 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
259 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
260 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
261 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
262 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
263 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
264 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
265 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
266 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
267 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
268 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
270 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
271 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
272 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
274 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
275 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
276 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
277 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
278 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
282 * Decode a state_struct_type value to determine the type that should be
283 * stored in the .aub file.
285 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
287 return (ss_type
& 0xFFFF0000) >> 16;
291 * Decode a state_struct_type value to determine the subtype that should be
292 * stored in the .aub file.
294 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
296 return ss_type
& 0xFFFF;
299 /** Subclass of Mesa vertex program */
300 struct brw_vertex_program
{
301 struct gl_vertex_program program
;
306 /** Subclass of Mesa geometry program */
307 struct brw_geometry_program
{
308 struct gl_geometry_program program
;
309 unsigned id
; /**< serial no. to identify geom progs, never re-used */
313 /** Subclass of Mesa fragment program */
314 struct brw_fragment_program
{
315 struct gl_fragment_program program
;
316 GLuint id
; /**< serial no. to identify frag progs, never re-used */
320 struct gl_shader base
;
325 /* Note: If adding fields that need anything besides a normal memcmp() for
326 * comparing them, be sure to go fix the the stage-specific
327 * prog_data_compare().
329 struct brw_stage_prog_data
{
331 /** size of our binding table. */
335 * surface indices for the various groups of surfaces
337 uint32_t pull_constants_start
;
338 uint32_t texture_start
;
339 uint32_t gather_texture_start
;
342 uint32_t shader_time_start
;
347 /* Data about a particular attempt to compile a program. Note that
348 * there can be many of these, each in a different GL state
349 * corresponding to a different brw_wm_prog_key struct, with different
352 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
355 struct brw_wm_prog_data
{
356 struct brw_stage_prog_data base
;
358 GLuint curb_read_length
;
359 GLuint num_varying_inputs
;
361 GLuint first_curbe_grf
;
362 GLuint first_curbe_grf_16
;
364 GLuint reg_blocks_16
;
365 GLuint total_scratch
;
369 * surface indices the WM-specific surfaces
371 uint32_t render_target_start
;
375 GLuint nr_params
; /**< number of float params/constants */
376 GLuint nr_pull_params
;
378 bool uses_pos_offset
;
380 uint32_t prog_offset_16
;
383 * Mask of which interpolation modes are required by the fragment shader.
384 * Used in hardware setup on gen6+.
386 uint32_t barycentric_interp_modes
;
389 * Map from gl_varying_slot to the position within the FS setup data
390 * payload where the varying's attribute vertex deltas should be delivered.
391 * For varying slots that are not used by the FS, the value is -1.
393 int urb_setup
[VARYING_SLOT_MAX
];
395 /* Pointers to tracked values (only valid once
396 * _mesa_load_state_parameters has been called at runtime).
398 * These must be the last fields of the struct (see
399 * brw_wm_prog_data_compare()).
402 const float **pull_param
;
406 * Enum representing the i965-specific vertex results that don't correspond
407 * exactly to any element of gl_varying_slot. The values of this enum are
408 * assigned such that they don't conflict with gl_varying_slot.
412 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
413 BRW_VARYING_SLOT_PAD
,
415 * Technically this is not a varying but just a placeholder that
416 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
417 * builtin variable to be compiled correctly. see compile_sf_prog() for
420 BRW_VARYING_SLOT_PNTC
,
421 BRW_VARYING_SLOT_COUNT
426 * Data structure recording the relationship between the gl_varying_slot enum
427 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
428 * single octaword within the VUE (128 bits).
430 * Note that each BRW register contains 256 bits (2 octawords), so when
431 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
432 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
433 * in a vertex shader), each register corresponds to a single VUE slot, since
434 * it contains data for two separate vertices.
438 * Bitfield representing all varying slots that are (a) stored in this VUE
439 * map, and (b) actually written by the shader. Does not include any of
440 * the additional varying slots defined in brw_varying_slot.
442 GLbitfield64 slots_valid
;
445 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
446 * not stored in a slot (because they are not written, or because
447 * additional processing is applied before storing them in the VUE), the
450 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
453 * Map from VUE slot to gl_varying_slot value. For slots that do not
454 * directly correspond to a gl_varying_slot, the value comes from
457 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
458 * simplifies code that uses the value stored in slot_to_varying to
459 * create a bit mask).
461 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
464 * Total number of VUE slots in use
470 * Convert a VUE slot number into a byte offset within the VUE.
472 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
478 * Convert a vertex output (brw_varying_slot) into a byte offset within the
481 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
484 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
487 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
488 GLbitfield64 slots_valid
);
492 * Bitmask indicating which fragment shader inputs represent varyings (and
493 * hence have to be delivered to the fragment shader by the SF/SBE stage).
495 #define BRW_FS_VARYING_INPUT_MASK \
496 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
497 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
501 * Mapping of VUE map slots to interpolation modes.
503 struct interpolation_mode_map
{
504 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
507 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
509 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
510 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
516 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
518 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
519 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
526 struct brw_sf_prog_data
{
527 GLuint urb_read_length
;
530 /* Each vertex may have upto 12 attributes, 4 components each,
531 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
534 * Actually we use 4 for each, so call it 12 rows.
536 GLuint urb_entry_size
;
541 * We always program SF to start reading at an offset of 1 (2 varying slots)
542 * from the start of the vertex URB entry. This causes it to skip:
543 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
544 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
546 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
549 struct brw_clip_prog_data
{
550 GLuint curb_read_length
; /* user planes? */
552 GLuint urb_read_length
;
556 struct brw_ff_gs_prog_data
{
557 GLuint urb_read_length
;
561 * Gen6 transform feedback: Amount by which the streaming vertex buffer
562 * indices should be incremented each time the GS is invoked.
564 unsigned svbi_postincrement_value
;
568 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
571 struct brw_vec4_prog_data
{
572 struct brw_stage_prog_data base
;
573 struct brw_vue_map vue_map
;
576 * Register where the thread expects to find input data from the URB
577 * (typically uniforms, followed by per-vertex inputs).
579 unsigned dispatch_grf_start_reg
;
581 GLuint curb_read_length
;
582 GLuint urb_read_length
;
584 GLuint nr_params
; /**< number of float params/constants */
585 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
586 GLuint total_scratch
;
588 /* Used for calculating urb partitions. In the VS, this is the size of the
589 * URB entry used for both input and output to the thread. In the GS, this
590 * is the size of the URB entry used for output.
592 GLuint urb_entry_size
;
594 /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
596 const float **pull_param
;
600 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
603 struct brw_vs_prog_data
{
604 struct brw_vec4_prog_data base
;
606 GLbitfield64 inputs_read
;
612 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
615 struct brw_gs_prog_data
617 struct brw_vec4_prog_data base
;
620 * Size of an output vertex, measured in HWORDS (32 bytes).
622 unsigned output_vertex_size_hwords
;
624 unsigned output_topology
;
627 * Size of the control data (cut bits or StreamID bits), in hwords (32
628 * bytes). 0 if there is no control data.
630 unsigned control_data_header_size_hwords
;
633 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
634 * if the control data is StreamID bits, or
635 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
636 * Ignored if control_data_header_size is 0.
638 unsigned control_data_format
;
640 bool include_primitive_id
;
643 * True if the thread should be dispatched in DUAL_INSTANCE mode, false if
644 * it should be dispatched in DUAL_OBJECT mode.
646 bool dual_instanced_dispatch
;
649 /** Number of texture sampler units */
650 #define BRW_MAX_TEX_UNIT 32
652 /** Max number of render targets in a shader */
653 #define BRW_MAX_DRAW_BUFFERS 8
655 /** Max number of atomic counter buffer objects in a shader */
656 #define BRW_MAX_ABO 16
659 * Max number of binding table entries used for stream output.
661 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
662 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
664 * On Gen6, the size of transform feedback data is limited not by the number
665 * of components but by the number of binding table entries we set aside. We
666 * use one binding table entry for a float, one entry for a vector, and one
667 * entry per matrix column. Since the only way we can communicate our
668 * transform feedback capabilities to the client is via
669 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
670 * worst case, in which all the varyings are floats, so we use up one binding
671 * table entry per component. Therefore we need to set aside at least 64
672 * binding table entries for use by transform feedback.
674 * Note: since we don't currently pack varyings, it is currently impossible
675 * for the client to actually use up all of these binding table entries--if
676 * all of their varyings were floats, they would run out of varying slots and
677 * fail to link. But that's a bug, so it seems prudent to go ahead and
678 * allocate the number of binding table entries we will need once the bug is
681 #define BRW_MAX_SOL_BINDINGS 64
683 /** Maximum number of actual buffers used for stream output */
684 #define BRW_MAX_SOL_BUFFERS 4
686 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
687 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
690 2 /* shader time, pull constants */)
692 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
693 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
696 * Stride in bytes between shader_time entries.
698 * We separate entries by a cacheline to reduce traffic between EUs writing to
701 #define SHADER_TIME_STRIDE 64
708 BRW_BLORP_CONST_COLOR_PROG
,
713 BRW_SF_UNIT
, /* scissor state on gen6 */
726 struct brw_cache_item
{
728 * Effectively part of the key, cache_id identifies what kind of state
729 * buffer is involved, and also which brw->state.dirty.cache flag should
730 * be set when this cache item is chosen.
732 enum brw_cache_id cache_id
;
733 /** 32-bit hash of the key data */
735 GLuint key_size
; /* for variable-sized keys */
742 struct brw_cache_item
*next
;
746 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
747 typedef void (*cache_aux_free_func
)(const void *aux
);
750 struct brw_context
*brw
;
752 struct brw_cache_item
**items
;
754 GLuint size
, n_items
;
756 uint32_t next_offset
;
760 * Optional functions used in determining whether the prog_data for a new
761 * cache item matches an existing cache item (in case there's relevant data
762 * outside of the prog_data). If NULL, a plain memcmp is done.
764 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
765 /** Optional functions for freeing other pointers attached to a prog_data. */
766 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
770 /* Considered adding a member to this struct to document which flags
771 * an update might raise so that ordering of the state atoms can be
772 * checked or derived at runtime. Dropped the idea in favor of having
773 * a debug mode where the state is monitored for flags which are
774 * raised that have already been tested against.
776 struct brw_tracked_state
{
777 struct brw_state_flags dirty
;
778 void (*emit
)( struct brw_context
*brw
);
781 enum shader_time_shader_type
{
797 /* Flags for brw->state.cache.
799 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
800 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
801 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
802 #define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
803 #define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
804 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
805 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
806 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
807 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
808 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
809 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
810 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
811 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
812 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
813 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
814 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
815 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
816 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
818 struct brw_cached_batch_item
{
819 struct header
*header
;
821 struct brw_cached_batch_item
*next
;
824 struct brw_vertex_buffer
{
825 /** Buffer object containing the uploaded vertex data */
828 /** Byte stride between elements in the uploaded array */
832 struct brw_vertex_element
{
833 const struct gl_client_array
*glarray
;
837 /** The corresponding Mesa vertex attribute */
838 gl_vert_attrib attrib
;
839 /** Offset of the first element within the buffer object */
843 struct brw_query_object
{
844 struct gl_query_object Base
;
846 /** Last query BO associated with this query. */
849 /** Last index in bo with query data for this object. */
853 struct intel_sync_object
{
854 struct gl_sync_object Base
;
856 /** Batch associated with this sync object */
866 struct intel_batchbuffer
{
867 /** Current batchbuffer being queued up. */
869 /** Last BO submitted to the hardware. Used for glFinish(). */
870 drm_intel_bo
*last_bo
;
871 /** BO for post-sync nonzero writes for gen6 workaround. */
872 drm_intel_bo
*workaround_bo
;
873 bool need_workaround_flush
;
875 struct cached_batch_item
*cached_items
;
877 uint16_t emit
, total
;
878 uint16_t used
, reserved_space
;
881 #define BATCH_SZ (8192*sizeof(uint32_t))
883 uint32_t state_batch_offset
;
884 enum brw_gpu_ring ring
;
885 bool needs_sol_reset
;
893 #define BRW_MAX_XFB_STREAMS 4
895 struct brw_transform_feedback_object
{
896 struct gl_transform_feedback_object base
;
898 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
899 drm_intel_bo
*offset_bo
;
901 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
902 GLenum primitive_mode
;
905 * Count of primitives generated during this transform feedback operation.
908 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
909 drm_intel_bo
*prim_count_bo
;
910 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
914 * Number of vertices written between last Begin/EndTransformFeedback().
916 * Used to implement DrawTransformFeedback().
918 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
919 bool vertices_written_valid
;
923 * Data shared between each programmable stage in the pipeline (vs, gs, and
926 struct brw_stage_state
928 struct brw_stage_prog_data
*prog_data
;
931 * Optional scratch buffer used to store spilled register values and
932 * variably-indexed GRF arrays.
934 drm_intel_bo
*scratch_bo
;
936 /** Pull constant buffer */
937 drm_intel_bo
*const_bo
;
939 /** Offset in the program cache to the program */
940 uint32_t prog_offset
;
942 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
943 uint32_t state_offset
;
945 uint32_t push_const_offset
; /* Offset in the batchbuffer */
946 int push_const_size
; /* in 256-bit register increments */
948 /* Binding table: pointers to SURFACE_STATE entries. */
949 uint32_t bind_bo_offset
;
950 uint32_t surf_offset
[BRW_MAX_SURFACES
];
952 /** SAMPLER_STATE count and table offset */
953 uint32_t sampler_count
;
954 uint32_t sampler_offset
;
956 /** Offsets in the batch to sampler default colors (texture border color) */
957 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
962 * brw_context is derived from gl_context.
966 struct gl_context ctx
; /**< base class, must be first field */
970 void (*update_texture_surface
)(struct gl_context
*ctx
,
972 uint32_t *surf_offset
,
974 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
975 struct gl_renderbuffer
*rb
,
978 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
981 void (*create_raw_surface
)(struct brw_context
*brw
,
985 uint32_t *out_offset
,
987 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
988 uint32_t *out_offset
,
990 unsigned buffer_offset
,
991 unsigned surface_format
,
992 unsigned buffer_size
,
997 /** Upload a SAMPLER_STATE table. */
998 void (*upload_sampler_state_table
)(struct brw_context
*brw
,
999 struct gl_program
*prog
,
1000 uint32_t sampler_count
,
1001 uint32_t *sst_offset
,
1002 uint32_t *sdc_offset
);
1005 * Send the appropriate state packets to configure depth, stencil, and
1006 * HiZ buffers (i965+ only)
1008 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
1009 struct intel_mipmap_tree
*depth_mt
,
1010 uint32_t depth_offset
,
1011 uint32_t depthbuffer_format
,
1012 uint32_t depth_surface_type
,
1013 struct intel_mipmap_tree
*stencil_mt
,
1014 bool hiz
, bool separate_stencil
,
1015 uint32_t width
, uint32_t height
,
1016 uint32_t tile_x
, uint32_t tile_y
);
1022 drm_intel_context
*hw_ctx
;
1025 * Number of resets observed in the system at context creation.
1027 * This is tracked in the context so that we can determine that another
1028 * reset has occured.
1030 uint32_t reset_count
;
1032 struct intel_batchbuffer batch
;
1038 uint32_t buffer_len
;
1039 uint32_t buffer_offset
;
1044 * Set if rendering has occured to the drawable's front buffer.
1046 * This is used in the DRI2 case to detect that glFlush should also copy
1047 * the contents of the fake front buffer to the real front buffer.
1049 bool front_buffer_dirty
;
1052 * Track whether front-buffer rendering is currently enabled
1054 * A separate flag is used to track this in order to support MRT more
1057 bool is_front_buffer_rendering
;
1060 * Track whether front-buffer is the current read target.
1062 * This is closely associated with is_front_buffer_rendering, but may
1063 * be set separately. The DRI2 fake front buffer must be referenced
1066 bool is_front_buffer_reading
;
1068 /** Framerate throttling: @{ */
1069 drm_intel_bo
*first_post_swapbuffers_batch
;
1080 bool always_flush_batch
;
1081 bool always_flush_cache
;
1082 bool disable_throttling
;
1084 bool disable_derivative_optimization
;
1086 driOptionCache optionCache
;
1089 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1091 GLenum reduced_primitive
;
1094 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1095 * variable is set, this is the flag indicating to do expensive work that
1096 * might lead to a perf_debug() call.
1100 uint32_t max_gtt_map_object_size
;
1110 bool has_separate_stencil
;
1111 bool must_use_separate_stencil
;
1114 bool has_surface_tile_offset
;
1116 bool has_negative_rhw_bug
;
1120 * Some versions of Gen hardware don't do centroid interpolation correctly
1121 * on unlit pixels, causing incorrect values for derivatives near triangle
1122 * edges. Enabling this flag causes the fragment shader to use
1123 * non-centroid interpolation for unlit pixels, at the expense of two extra
1124 * fragment shader instructions.
1126 bool needs_unlit_centroid_workaround
;
1130 struct brw_state_flags dirty
;
1133 struct brw_cache cache
;
1134 struct brw_cached_batch_item
*cached_batch_items
;
1136 /* Whether a meta-operation is in progress. */
1137 bool meta_in_progress
;
1140 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1141 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1143 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1147 /* Summary of size and varying of active arrays, so we can check
1148 * for changes to this state:
1150 unsigned int min_index
, max_index
;
1152 /* Offset from start of vertex buffer so we can avoid redefining
1153 * the same VB packed over and over again.
1155 unsigned int start_vertex_bias
;
1160 * Index buffer for this draw_prims call.
1162 * Updates are signaled by BRW_NEW_INDICES.
1164 const struct _mesa_index_buffer
*ib
;
1166 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1170 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1171 * avoid re-uploading the IB packet over and over if we're actually
1172 * referencing the same index buffer.
1174 unsigned int start_vertex_offset
;
1177 /* Active vertex program:
1179 const struct gl_vertex_program
*vertex_program
;
1180 const struct gl_geometry_program
*geometry_program
;
1181 const struct gl_fragment_program
*fragment_program
;
1183 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
1184 uint32_t CMD_VF_STATISTICS
;
1185 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
1186 uint32_t CMD_PIPELINE_SELECT
;
1189 * Platform specific constants containing the maximum number of threads
1190 * for each pipeline stage.
1196 /* BRW_NEW_URB_ALLOCATIONS:
1199 GLuint vsize
; /* vertex size plus header in urb registers */
1200 GLuint csize
; /* constant buffer size in urb registers */
1201 GLuint sfsize
; /* setup data size in urb registers */
1205 GLuint min_vs_entries
; /* Minimum number of VS entries */
1206 GLuint max_vs_entries
; /* Maximum number of VS entries */
1207 GLuint max_gs_entries
; /* Maximum number of GS entries */
1209 GLuint nr_vs_entries
;
1210 GLuint nr_gs_entries
;
1211 GLuint nr_clip_entries
;
1212 GLuint nr_sf_entries
;
1213 GLuint nr_cs_entries
;
1220 GLuint size
; /* Hardware URB size, in KB. */
1222 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1223 * URB space for the GS.
1225 bool gen6_gs_previously_active
;
1229 /* BRW_NEW_CURBE_OFFSETS:
1232 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1233 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1240 drm_intel_bo
*curbe_bo
;
1241 /** Offset within curbe_bo of space for current curbe entry */
1242 GLuint curbe_offset
;
1243 /** Offset within curbe_bo of space for next curbe entry */
1244 GLuint curbe_next_offset
;
1247 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
1248 * in brw_curbe.c with the same set of constant data to be uploaded,
1249 * so we'd rather not upload new constants in that case (it can cause
1250 * a pipeline bubble since only up to 4 can be pipelined at a time).
1254 * Allocation for where to calculate the next set of CURBEs.
1255 * It's a hot enough path that malloc/free of that data matters.
1262 * Layout of vertex data exiting the vertex shader.
1264 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1266 struct brw_vue_map vue_map_vs
;
1269 * Layout of vertex data exiting the geometry portion of the pipleine.
1270 * This comes from the geometry shader if one exists, otherwise from the
1273 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1275 struct brw_vue_map vue_map_geom_out
;
1278 * Data structures used by all vec4 program compiles (not specific to any
1279 * particular program).
1282 struct ra_regs
*regs
;
1285 * Array of the ra classes for the unaligned contiguous register
1291 * Mapping for register-allocated objects in *regs to the first
1292 * GRF for that object.
1294 uint8_t *ra_reg_to_grf
;
1298 struct brw_stage_state base
;
1299 struct brw_vs_prog_data
*prog_data
;
1303 struct brw_stage_state base
;
1304 struct brw_gs_prog_data
*prog_data
;
1307 * True if the 3DSTATE_GS command most recently emitted to the 3D
1308 * pipeline enabled the GS; false otherwise.
1314 struct brw_ff_gs_prog_data
*prog_data
;
1317 /** Offset in the program cache to the CLIP program pre-gen6 */
1318 uint32_t prog_offset
;
1319 uint32_t state_offset
;
1321 uint32_t bind_bo_offset
;
1322 uint32_t surf_offset
[BRW_MAX_GEN6_GS_SURFACES
];
1326 struct brw_clip_prog_data
*prog_data
;
1328 /** Offset in the program cache to the CLIP program pre-gen6 */
1329 uint32_t prog_offset
;
1331 /* Offset in the batch to the CLIP state on pre-gen6. */
1332 uint32_t state_offset
;
1334 /* As of gen6, this is the offset in the batch to the CLIP VP,
1342 struct brw_sf_prog_data
*prog_data
;
1344 /** Offset in the program cache to the CLIP program pre-gen6 */
1345 uint32_t prog_offset
;
1346 uint32_t state_offset
;
1351 struct brw_stage_state base
;
1352 struct brw_wm_prog_data
*prog_data
;
1357 * Buffer object used in place of multisampled null render targets on
1358 * Gen6. See brw_update_null_renderbuffer_surface().
1360 drm_intel_bo
*multisampled_null_render_target_bo
;
1363 struct ra_regs
*regs
;
1366 * Array of the ra classes for the unaligned contiguous register
1367 * block sizes used, indexed by register size.
1372 * Mapping for register-allocated objects in *regs to the first
1373 * GRF for that object.
1375 uint8_t *ra_reg_to_grf
;
1378 * ra class for the aligned pairs we use for PLN, which doesn't
1379 * appear in *classes.
1381 int aligned_pairs_class
;
1387 uint32_t state_offset
;
1388 uint32_t blend_state_offset
;
1389 uint32_t depth_stencil_state_offset
;
1394 struct brw_query_object
*obj
;
1399 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1400 const int *statistics_registers
;
1402 /** The number of active monitors using OA counters. */
1406 * A buffer object storing OA counter snapshots taken at the start and
1407 * end of each batch (creating "bookends" around the batch).
1409 drm_intel_bo
*bookend_bo
;
1411 /** The number of snapshots written to bookend_bo. */
1412 int bookend_snapshots
;
1415 * An array of monitors whose results haven't yet been assembled based on
1416 * the data in buffer objects.
1418 * These may be active, or have already ended. However, the results
1419 * have not been requested.
1421 struct brw_perf_monitor_object
**unresolved
;
1422 int unresolved_elements
;
1423 int unresolved_array_size
;
1426 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1427 * the counter which MI_REPORT_PERF_COUNT stores there.
1429 const int *oa_snapshot_layout
;
1431 /** Number of 32-bit entries in a hardware counter snapshot. */
1432 int entries_per_oa_snapshot
;
1436 const struct brw_tracked_state
**atoms
;
1438 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1442 enum state_struct_type type
;
1443 } *state_batch_list
;
1444 int state_batch_count
;
1446 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1447 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1449 /* Interpolation modes, one byte per vue slot.
1450 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1452 struct interpolation_mode_map interpolation_mode
;
1454 /* PrimitiveRestart */
1457 bool enable_cut_index
;
1460 /** Computed depth/stencil/hiz state from the current attached
1461 * renderbuffers, valid only during the drawing state upload loop after
1462 * brw_workaround_depthstencil_alignment().
1465 struct intel_mipmap_tree
*depth_mt
;
1466 struct intel_mipmap_tree
*stencil_mt
;
1468 /* Inter-tile (page-aligned) byte offsets. */
1469 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1470 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1471 uint32_t tile_x
, tile_y
;
1474 uint32_t num_instances
;
1479 struct gl_shader_program
**shader_programs
;
1480 struct gl_program
**programs
;
1481 enum shader_time_shader_type
*types
;
1482 uint64_t *cumulative
;
1488 __DRIcontext
*driContext
;
1489 struct intel_screen
*intelScreen
;
1493 is_power_of_two(uint32_t value
)
1495 return (value
& (value
- 1)) == 0;
1498 /*======================================================================
1501 void brwInitVtbl( struct brw_context
*brw
);
1504 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1506 /*======================================================================
1509 extern const char *const brw_vendor_string
;
1511 extern const char *brw_get_renderer_string(unsigned deviceID
);
1513 extern void intelFinish(struct gl_context
* ctx
);
1516 DRI_CONF_BO_REUSE_DISABLED
,
1517 DRI_CONF_BO_REUSE_ALL
1520 void intel_update_renderbuffers(__DRIcontext
*context
,
1521 __DRIdrawable
*drawable
);
1522 void intel_prepare_render(struct brw_context
*brw
);
1524 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1525 __DRIdrawable
*drawable
);
1527 GLboolean
brwCreateContext(gl_api api
,
1528 const struct gl_config
*mesaVis
,
1529 __DRIcontext
*driContextPriv
,
1530 unsigned major_version
,
1531 unsigned minor_version
,
1535 void *sharedContextPrivate
);
1537 /*======================================================================
1540 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1541 uint32_t depth_level
,
1542 uint32_t depth_layer
,
1543 struct intel_mipmap_tree
*stencil_mt
,
1544 uint32_t *out_tile_mask_x
,
1545 uint32_t *out_tile_mask_y
);
1546 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1547 GLbitfield clear_mask
);
1549 /* brw_object_purgeable.c */
1550 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1552 /*======================================================================
1555 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1556 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1557 void brw_emit_query_begin(struct brw_context
*brw
);
1558 void brw_emit_query_end(struct brw_context
*brw
);
1560 /** gen6_queryobj.c */
1561 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1562 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1563 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1564 void brw_store_register_mem64(struct brw_context
*brw
,
1565 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1567 /*======================================================================
1570 void brw_debug_batch(struct brw_context
*brw
);
1571 void brw_annotate_aub(struct brw_context
*brw
);
1573 /*======================================================================
1576 void brw_validate_textures( struct brw_context
*brw
);
1579 /*======================================================================
1582 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1584 int brw_get_scratch_size(int size
);
1585 void brw_get_scratch_bo(struct brw_context
*brw
,
1586 drm_intel_bo
**scratch_bo
, int size
);
1587 void brw_init_shader_time(struct brw_context
*brw
);
1588 int brw_get_shader_time_index(struct brw_context
*brw
,
1589 struct gl_shader_program
*shader_prog
,
1590 struct gl_program
*prog
,
1591 enum shader_time_shader_type type
);
1592 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1593 void brw_destroy_shader_time(struct brw_context
*brw
);
1597 void brw_upload_urb_fence(struct brw_context
*brw
);
1601 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1603 /* brw_fs_reg_allocate.cpp
1605 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1607 /* brw_vec4_reg_allocate.cpp */
1608 void brw_vec4_alloc_reg_set(struct brw_context
*brw
);
1611 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1614 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1616 /* brw_draw_upload.c */
1617 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1618 const struct gl_client_array
*glarray
);
1619 unsigned brw_get_index_type(GLenum type
);
1620 void brw_prepare_vertices(struct brw_context
*brw
);
1622 /* brw_wm_surface_state.c */
1623 void brw_init_surface_formats(struct brw_context
*brw
);
1624 void brw_create_constant_surface(struct brw_context
*brw
,
1628 uint32_t *out_offset
,
1630 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1632 uint32_t *surf_offset
);
1634 brw_update_sol_surface(struct brw_context
*brw
,
1635 struct gl_buffer_object
*buffer_obj
,
1636 uint32_t *out_offset
, unsigned num_vector_components
,
1637 unsigned stride_dwords
, unsigned offset_dwords
);
1638 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1639 struct gl_shader
*shader
,
1640 struct brw_stage_state
*stage_state
,
1641 struct brw_stage_prog_data
*prog_data
);
1642 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1643 struct gl_shader_program
*prog
,
1644 struct brw_stage_state
*stage_state
,
1645 struct brw_stage_prog_data
*prog_data
);
1647 /* brw_surface_formats.c */
1648 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, mesa_format format
);
1649 bool brw_render_target_supported(struct brw_context
*brw
,
1650 struct gl_renderbuffer
*rb
);
1652 /* brw_performance_monitor.c */
1653 void brw_init_performance_monitors(struct brw_context
*brw
);
1654 void brw_dump_perf_monitors(struct brw_context
*brw
);
1655 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1656 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1658 /* intel_extensions.c */
1659 extern void intelInitExtensions(struct gl_context
*ctx
);
1662 extern int intel_translate_shadow_compare_func(GLenum func
);
1663 extern int intel_translate_compare_func(GLenum func
);
1664 extern int intel_translate_stencil_op(GLenum op
);
1665 extern int intel_translate_logic_op(GLenum opcode
);
1667 /* intel_syncobj.c */
1668 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1671 struct gl_transform_feedback_object
*
1672 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1674 brw_delete_transform_feedback(struct gl_context
*ctx
,
1675 struct gl_transform_feedback_object
*obj
);
1677 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1678 struct gl_transform_feedback_object
*obj
);
1680 brw_end_transform_feedback(struct gl_context
*ctx
,
1681 struct gl_transform_feedback_object
*obj
);
1683 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1684 struct gl_transform_feedback_object
*obj
,
1687 /* gen7_sol_state.c */
1689 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1690 struct gl_transform_feedback_object
*obj
);
1692 gen7_end_transform_feedback(struct gl_context
*ctx
,
1693 struct gl_transform_feedback_object
*obj
);
1695 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1696 struct gl_transform_feedback_object
*obj
);
1698 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1699 struct gl_transform_feedback_object
*obj
);
1701 /* brw_blorp_blit.cpp */
1703 brw_blorp_framebuffer(struct brw_context
*brw
,
1704 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1705 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1706 GLbitfield mask
, GLenum filter
);
1709 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1710 struct gl_renderbuffer
*src_rb
,
1711 struct gl_texture_image
*dst_image
,
1713 int srcX0
, int srcY0
,
1714 int dstX0
, int dstY0
,
1715 int width
, int height
);
1717 /* gen6_multisample_state.c */
1719 gen6_determine_sample_mask(struct brw_context
*brw
);
1722 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1723 unsigned num_samples
);
1725 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1727 gen6_get_sample_position(struct gl_context
*ctx
,
1728 struct gl_framebuffer
*fb
,
1734 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1735 unsigned gs_size
, unsigned fs_size
);
1738 gen7_emit_urb_state(struct brw_context
*brw
,
1739 unsigned nr_vs_entries
, unsigned vs_size
,
1740 unsigned vs_start
, unsigned nr_gs_entries
,
1741 unsigned gs_size
, unsigned gs_start
);
1746 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1748 /*======================================================================
1749 * Inline conversion functions. These are better-typed than the
1750 * macros used previously:
1752 static inline struct brw_context
*
1753 brw_context( struct gl_context
*ctx
)
1755 return (struct brw_context
*)ctx
;
1758 static inline struct brw_vertex_program
*
1759 brw_vertex_program(struct gl_vertex_program
*p
)
1761 return (struct brw_vertex_program
*) p
;
1764 static inline const struct brw_vertex_program
*
1765 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1767 return (const struct brw_vertex_program
*) p
;
1770 static inline struct brw_geometry_program
*
1771 brw_geometry_program(struct gl_geometry_program
*p
)
1773 return (struct brw_geometry_program
*) p
;
1776 static inline struct brw_fragment_program
*
1777 brw_fragment_program(struct gl_fragment_program
*p
)
1779 return (struct brw_fragment_program
*) p
;
1782 static inline const struct brw_fragment_program
*
1783 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1785 return (const struct brw_fragment_program
*) p
;
1789 * Pre-gen6, the register file of the EUs was shared between threads,
1790 * and each thread used some subset allocated on a 16-register block
1791 * granularity. The unit states wanted these block counts.
1794 brw_register_blocks(int reg_count
)
1796 return ALIGN(reg_count
, 16) / 16 - 1;
1799 static inline uint32_t
1800 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1801 uint32_t prog_offset
)
1803 if (brw
->gen
>= 5) {
1804 /* Using state base address. */
1808 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1812 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1814 return brw
->cache
.bo
->offset64
+ prog_offset
;
1817 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1818 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1819 struct exec_list
*instructions
);
1820 bool brw_do_lower_offset_arrays(struct exec_list
*instructions
);
1821 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1823 struct opcode_desc
{
1829 extern const struct opcode_desc opcode_descs
[128];
1830 extern const char * const conditional_modifier
[16];
1831 extern const char * const reg_encoding
[8];
1834 brw_emit_depthbuffer(struct brw_context
*brw
);
1837 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1838 struct intel_mipmap_tree
*depth_mt
,
1839 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1840 uint32_t depth_surface_type
,
1841 struct intel_mipmap_tree
*stencil_mt
,
1842 bool hiz
, bool separate_stencil
,
1843 uint32_t width
, uint32_t height
,
1844 uint32_t tile_x
, uint32_t tile_y
);
1847 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1848 struct intel_mipmap_tree
*depth_mt
,
1849 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1850 uint32_t depth_surface_type
,
1851 struct intel_mipmap_tree
*stencil_mt
,
1852 bool hiz
, bool separate_stencil
,
1853 uint32_t width
, uint32_t height
,
1854 uint32_t tile_x
, uint32_t tile_y
);
1856 extern const GLuint prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1];
1859 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1860 struct brw_vec4_prog_key
*key
,
1861 bool program_uses_clip_distance
);
1864 gen6_upload_vec4_push_constants(struct brw_context
*brw
,
1865 const struct gl_program
*prog
,
1866 const struct brw_vec4_prog_data
*prog_data
,
1867 struct brw_stage_state
*stage_state
,
1868 enum state_struct_type type
);
1870 /* ================================================================
1871 * From linux kernel i386 header files, copes with odd sizes better
1872 * than COPY_DWORDS would:
1873 * XXX Put this in src/mesa/main/imports.h ???
1875 #if defined(i386) || defined(__i386__)
1876 static inline void * __memcpy(void * to
, const void * from
, size_t n
)
1879 __asm__
__volatile__(
1884 "1:\ttestb $1,%b4\n\t"
1888 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1889 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1894 #define __memcpy(a,b,c) memcpy(a,b,c)