2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "compiler/brw_compiler.h"
43 #include "blorp/blorp.h"
45 #include <brw_bufmgr.h>
47 #include "common/gen_debug.h"
48 #include "intel_screen.h"
49 #include "intel_tex_obj.h"
50 #include "intel_resolve_map.h"
57 * URB - uniform resource buffer. A mid-sized buffer which is
58 * partitioned between the fixed function units and used for passing
59 * values (vertices, primitives, constants) between them.
61 * CURBE - constant URB entry. An urb region (entry) used to hold
62 * constant values which the fixed function units can be instructed to
63 * preload into the GRF when spawning a thread.
65 * VUE - vertex URB entry. An urb entry holding a vertex and usually
66 * a vertex header. The header contains control information and
67 * things like primitive type, Begin/end flags and clip codes.
69 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
70 * unit holding rasterization and interpolation parameters.
72 * GRF - general register file. One of several register files
73 * addressable by programmed threads. The inputs (r0, payload, curbe,
74 * urb) of the thread are preloaded to this area before the thread is
75 * spawned. The registers are individually 8 dwords wide and suitable
76 * for general usage. Registers holding thread input values are not
77 * special and may be overwritten.
79 * MRF - message register file. Threads communicate (and terminate)
80 * by sending messages. Message parameters are placed in contiguous
81 * MRF registers. All program output is via these messages. URB
82 * entries are populated by sending a message to the shared URB
83 * function containing the new data, together with a control word,
84 * often an unmodified copy of R0.
86 * R0 - GRF register 0. Typically holds control information used when
87 * sending messages to other threads.
89 * EU or GEN4 EU: The name of the programmable subsystem of the
90 * i965 hardware. Threads are executed by the EU, the registers
91 * described above are part of the EU architecture.
93 * Fixed function units:
95 * CS - Command streamer. Notional first unit, little software
96 * interaction. Holds the URB entries used for constant data, ie the
99 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
100 * this unit is responsible for pulling vertices out of vertex buffers
101 * in vram and injecting them into the processing pipe as VUEs. If
102 * enabled, it first passes them to a VS thread which is a good place
103 * for the driver to implement any active vertex shader.
105 * HS - Hull Shader (Tessellation Control Shader)
107 * TE - Tessellation Engine (Tessellation Primitive Generation)
109 * DS - Domain Shader (Tessellation Evaluation Shader)
111 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
112 * enabled, incoming strips etc are passed to GS threads in individual
113 * line/triangle/point units. The GS thread may perform arbitary
114 * computation and emit whatever primtives with whatever vertices it
115 * chooses. This makes GS an excellent place to implement GL's
116 * unfilled polygon modes, though of course it is capable of much
117 * more. Additionally, GS is used to translate away primitives not
118 * handled by latter units, including Quads and Lineloops.
120 * CS - Clipper. Mesa's clipping algorithms are imported to run on
121 * this unit. The fixed function part performs cliptesting against
122 * the 6 fixed clipplanes and makes descisions on whether or not the
123 * incoming primitive needs to be passed to a thread for clipping.
124 * User clip planes are handled via cooperation with the VS thread.
126 * SF - Strips Fans or Setup: Triangles are prepared for
127 * rasterization. Interpolation coefficients are calculated.
128 * Flatshading and two-side lighting usually performed here.
130 * WM - Windower. Interpolation of vertex attributes performed here.
131 * Fragment shader implemented here. SIMD aspects of EU taken full
132 * advantage of, as pixels are processed in blocks of 16.
134 * CC - Color Calculator. No EU threads associated with this unit.
135 * Handles blending and (presumably) depth and stencil testing.
140 struct brw_vs_prog_key
;
141 struct brw_vue_prog_key
;
142 struct brw_wm_prog_key
;
143 struct brw_wm_prog_data
;
144 struct brw_cs_prog_key
;
145 struct brw_cs_prog_data
;
149 BRW_COMPUTE_PIPELINE
,
156 BRW_CACHE_BLORP_PROG
,
159 BRW_CACHE_FF_GS_PROG
,
170 /* brw_cache_ids must come first - see brw_program_cache.c */
171 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
172 BRW_STATE_FRAGMENT_PROGRAM
,
173 BRW_STATE_GEOMETRY_PROGRAM
,
174 BRW_STATE_TESS_PROGRAMS
,
175 BRW_STATE_VERTEX_PROGRAM
,
176 BRW_STATE_REDUCED_PRIMITIVE
,
177 BRW_STATE_PATCH_PRIMITIVE
,
182 BRW_STATE_BINDING_TABLE_POINTERS
,
185 BRW_STATE_DEFAULT_TESS_LEVELS
,
187 BRW_STATE_INDEX_BUFFER
,
188 BRW_STATE_VS_CONSTBUF
,
189 BRW_STATE_TCS_CONSTBUF
,
190 BRW_STATE_TES_CONSTBUF
,
191 BRW_STATE_GS_CONSTBUF
,
192 BRW_STATE_PROGRAM_CACHE
,
193 BRW_STATE_STATE_BASE_ADDRESS
,
194 BRW_STATE_VUE_MAP_GEOM_OUT
,
195 BRW_STATE_TRANSFORM_FEEDBACK
,
196 BRW_STATE_RASTERIZER_DISCARD
,
198 BRW_STATE_UNIFORM_BUFFER
,
199 BRW_STATE_ATOMIC_BUFFER
,
200 BRW_STATE_IMAGE_UNITS
,
201 BRW_STATE_META_IN_PROGRESS
,
202 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
203 BRW_STATE_NUM_SAMPLES
,
204 BRW_STATE_TEXTURE_BUFFER
,
205 BRW_STATE_GEN4_UNIT_STATE
,
209 BRW_STATE_SAMPLER_STATE_TABLE
,
210 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
211 BRW_STATE_COMPUTE_PROGRAM
,
212 BRW_STATE_CS_WORK_GROUPS
,
216 BRW_STATE_VIEWPORT_COUNT
,
217 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
222 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
224 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
225 * When the currently bound shader program differs from the previous draw
226 * call, these will be flagged. They cover brw->{stage}_program and
227 * ctx->{Stage}Program->_Current.
229 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
230 * driver perspective. Even if the same shader is bound at the API level,
231 * we may need to switch between multiple versions of that shader to handle
232 * changes in non-orthagonal state.
234 * Additionally, multiple shader programs may have identical vertex shaders
235 * (for example), or compile down to the same code in the backend. We combine
236 * those into a single program cache entry.
238 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
239 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
241 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
242 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
243 * use the normal state upload paths), but the cache is still used. To avoid
244 * polluting the brw_program_cache code with special cases, we retain the
245 * dirty bit for now. It should eventually be removed.
247 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
248 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
249 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
250 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
251 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
252 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
253 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
254 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
255 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
256 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
257 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
258 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
259 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
260 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
261 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
262 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
263 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
264 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
265 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
266 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
267 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
268 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
269 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
270 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
272 * Used for any batch entry with a relocated pointer that will be used
273 * by any 3D rendering.
275 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
276 /** \see brw.state.depth_region */
277 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
278 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
279 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
280 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
281 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
282 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
283 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
284 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
285 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
286 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
287 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
288 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
289 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
290 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
291 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
292 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
293 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
294 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
295 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
296 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
297 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
298 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
299 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
300 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
301 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
302 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
303 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
304 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
305 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
306 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
307 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
309 struct brw_state_flags
{
310 /** State update flags signalled by mesa internals */
313 * State update flags signalled as the result of brw_tracked_state updates
319 /** Subclass of Mesa program */
321 struct gl_program program
;
328 struct brw_ff_gs_prog_data
{
329 GLuint urb_read_length
;
333 * Gen6 transform feedback: Amount by which the streaming vertex buffer
334 * indices should be incremented each time the GS is invoked.
336 unsigned svbi_postincrement_value
;
339 /** Number of texture sampler units */
340 #define BRW_MAX_TEX_UNIT 32
342 /** Max number of UBOs in a shader */
343 #define BRW_MAX_UBO 14
345 /** Max number of SSBOs in a shader */
346 #define BRW_MAX_SSBO 12
348 /** Max number of atomic counter buffer objects in a shader */
349 #define BRW_MAX_ABO 16
351 /** Max number of image uniforms in a shader */
352 #define BRW_MAX_IMAGES 32
354 /** Maximum number of actual buffers used for stream output */
355 #define BRW_MAX_SOL_BUFFERS 4
357 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
358 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
363 2 + /* shader time, pull constants */ \
364 1 /* cs num work groups */)
367 struct brw_context
*brw
;
369 struct brw_cache_item
**items
;
372 GLuint size
, n_items
;
374 uint32_t next_offset
;
378 /* Considered adding a member to this struct to document which flags
379 * an update might raise so that ordering of the state atoms can be
380 * checked or derived at runtime. Dropped the idea in favor of having
381 * a debug mode where the state is monitored for flags which are
382 * raised that have already been tested against.
384 struct brw_tracked_state
{
385 struct brw_state_flags dirty
;
386 void (*emit
)( struct brw_context
*brw
);
389 enum shader_time_shader_type
{
400 struct brw_vertex_buffer
{
401 /** Buffer object containing the uploaded vertex data */
405 /** Byte stride between elements in the uploaded array */
409 struct brw_vertex_element
{
410 const struct gl_vertex_array
*glarray
;
414 /** Offset of the first element within the buffer object */
418 struct brw_query_object
{
419 struct gl_query_object Base
;
421 /** Last query BO associated with this query. */
424 /** Last index in bo with query data for this object. */
427 /** True if we know the batch has been flushed since we ended the query. */
437 struct intel_batchbuffer
{
438 /** Current batchbuffer being queued up. */
440 /** Last BO submitted to the hardware. Used for glFinish(). */
441 struct brw_bo
*last_bo
;
444 uint16_t emit
, total
;
446 uint16_t reserved_space
;
450 #define BATCH_SZ (8192*sizeof(uint32_t))
452 uint32_t state_batch_offset
;
453 enum brw_gpu_ring ring
;
454 bool needs_sol_reset
;
455 bool state_base_address_emitted
;
457 struct drm_i915_gem_relocation_entry
*relocs
;
459 int reloc_array_size
;
460 /** The validation list */
461 struct drm_i915_gem_exec_object2
*exec_objects
;
462 struct brw_bo
**exec_bos
;
465 /** The amount of aperture space (in bytes) used by all exec_bos */
474 /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */
475 struct hash_table
*state_batch_sizes
;
478 #define BRW_MAX_XFB_STREAMS 4
480 struct brw_transform_feedback_object
{
481 struct gl_transform_feedback_object base
;
483 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
484 struct brw_bo
*offset_bo
;
486 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
489 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
490 GLenum primitive_mode
;
493 * The maximum number of vertices that we can write without overflowing
494 * any of the buffers currently being used for transform feedback.
499 * Count of primitives generated during this transform feedback operation.
502 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
503 struct brw_bo
*prim_count_bo
;
504 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
508 * Number of vertices written between last Begin/EndTransformFeedback().
510 * Used to implement DrawTransformFeedback().
512 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
513 bool vertices_written_valid
;
517 * Data shared between each programmable stage in the pipeline (vs, gs, and
520 struct brw_stage_state
522 gl_shader_stage stage
;
523 struct brw_stage_prog_data
*prog_data
;
526 * Optional scratch buffer used to store spilled register values and
527 * variably-indexed GRF arrays.
529 * The contents of this buffer are short-lived so the same memory can be
530 * re-used at will for multiple shader programs (executed by the same fixed
531 * function). However reusing a scratch BO for which shader invocations
532 * are still in flight with a per-thread scratch slot size other than the
533 * original can cause threads with different scratch slot size and FFTID
534 * (which may be executed in parallel depending on the shader stage and
535 * hardware generation) to map to an overlapping region of the scratch
536 * space, which can potentially lead to mutual scratch space corruption.
537 * For that reason if you borrow this scratch buffer you should only be
538 * using the slot size given by the \c per_thread_scratch member below,
539 * unless you're taking additional measures to synchronize thread execution
540 * across slot size changes.
542 struct brw_bo
*scratch_bo
;
545 * Scratch slot size allocated for each thread in the buffer object given
548 uint32_t per_thread_scratch
;
550 /** Offset in the program cache to the program */
551 uint32_t prog_offset
;
553 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
554 uint32_t state_offset
;
556 uint32_t push_const_offset
; /* Offset in the batchbuffer */
557 int push_const_size
; /* in 256-bit register increments */
559 /* Binding table: pointers to SURFACE_STATE entries. */
560 uint32_t bind_bo_offset
;
561 uint32_t surf_offset
[BRW_MAX_SURFACES
];
563 /** SAMPLER_STATE count and table offset */
564 uint32_t sampler_count
;
565 uint32_t sampler_offset
;
568 enum brw_predicate_state
{
569 /* The first two states are used if we can determine whether to draw
570 * without having to look at the values in the query object buffer. This
571 * will happen if there is no conditional render in progress, if the query
572 * object is already completed or if something else has already added
573 * samples to the preliminary result such as via a BLT command.
575 BRW_PREDICATE_STATE_RENDER
,
576 BRW_PREDICATE_STATE_DONT_RENDER
,
577 /* In this case whether to draw or not depends on the result of an
578 * MI_PREDICATE command so the predicate enable bit needs to be checked.
580 BRW_PREDICATE_STATE_USE_BIT
585 struct gen_l3_config
;
587 enum brw_query_kind
{
592 struct brw_perf_query_info
594 enum brw_query_kind kind
;
597 struct brw_perf_query_counter
*counters
;
602 uint64_t oa_metrics_set_id
;
605 /* For indexing into the accumulator[] ... */
607 int gpu_clock_offset
;
614 * brw_context is derived from gl_context.
618 struct gl_context ctx
; /**< base class, must be first field */
622 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
623 struct gl_renderbuffer
*rb
,
624 uint32_t flags
, unsigned unit
,
625 uint32_t surf_index
);
626 void (*emit_null_surface_state
)(struct brw_context
*brw
,
630 uint32_t *out_offset
);
633 * Send the appropriate state packets to configure depth, stencil, and
634 * HiZ buffers (i965+ only)
636 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
637 struct intel_mipmap_tree
*depth_mt
,
638 uint32_t depth_offset
,
639 uint32_t depthbuffer_format
,
640 uint32_t depth_surface_type
,
641 struct intel_mipmap_tree
*stencil_mt
,
642 bool hiz
, bool separate_stencil
,
643 uint32_t width
, uint32_t height
,
644 uint32_t tile_x
, uint32_t tile_y
);
648 struct brw_bufmgr
*bufmgr
;
652 /** BO for post-sync nonzero writes for gen6 workaround. */
653 struct brw_bo
*workaround_bo
;
654 uint8_t pipe_controls_since_last_cs_stall
;
657 * Set of struct brw_bo * that have been rendered to within this batchbuffer
658 * and would need flushing before being used from another cache domain that
659 * isn't coherent with it (i.e. the sampler).
661 struct set
*render_cache
;
664 * Number of resets observed in the system at context creation.
666 * This is tracked in the context so that we can determine that another
667 * reset has occurred.
669 uint32_t reset_count
;
671 struct intel_batchbuffer batch
;
677 uint32_t next_offset
;
681 * Set if rendering has occurred to the drawable's front buffer.
683 * This is used in the DRI2 case to detect that glFlush should also copy
684 * the contents of the fake front buffer to the real front buffer.
686 bool front_buffer_dirty
;
688 /** Framerate throttling: @{ */
689 struct brw_bo
*throttle_batch
[2];
691 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
692 * frame of rendering to complete. This gives a very precise cap to the
693 * latency between input and output such that rendering never gets more
694 * than a frame behind the user. (With the caveat that we technically are
695 * not using the SwapBuffers itself as a barrier but the first batch
696 * submitted afterwards, which may be immediately prior to the next
699 bool need_swap_throttle
;
701 /** General throttling, not caught by throttling between SwapBuffers */
702 bool need_flush_throttle
;
712 bool always_flush_batch
;
713 bool always_flush_cache
;
714 bool disable_throttling
;
716 bool dual_color_blend_by_location
;
718 driOptionCache optionCache
;
721 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
723 GLenum reduced_primitive
;
726 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
727 * variable is set, this is the flag indicating to do expensive work that
728 * might lead to a perf_debug() call.
732 uint64_t max_gtt_map_object_size
;
744 bool has_separate_stencil
;
745 bool must_use_separate_stencil
;
748 bool has_surface_tile_offset
;
750 bool has_negative_rhw_bug
;
754 bool use_resource_streamer
;
757 * Some versions of Gen hardware don't do centroid interpolation correctly
758 * on unlit pixels, causing incorrect values for derivatives near triangle
759 * edges. Enabling this flag causes the fragment shader to use
760 * non-centroid interpolation for unlit pixels, at the expense of two extra
761 * fragment shader instructions.
763 bool needs_unlit_centroid_workaround
;
765 struct isl_device isl_dev
;
767 struct blorp_context blorp
;
771 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
774 enum brw_pipeline last_pipeline
;
776 struct brw_cache cache
;
778 /** IDs for meta stencil blit shader programs. */
779 struct gl_shader_program
*meta_stencil_blit_programs
[2];
781 /* Whether a meta-operation is in progress. */
782 bool meta_in_progress
;
784 /* Whether the last depth/stencil packets were both NULL. */
785 bool no_depth_or_stencil
;
787 /* The last PMA stall bits programmed. */
788 uint32_t pma_stall_bits
;
792 /** The value of gl_BaseVertex for the current _mesa_prim. */
795 /** The value of gl_BaseInstance for the current _mesa_prim. */
800 * Buffer and offset used for GL_ARB_shader_draw_parameters
801 * (for now, only gl_BaseVertex).
803 struct brw_bo
*draw_params_bo
;
804 uint32_t draw_params_offset
;
807 * The value of gl_DrawID for the current _mesa_prim. This always comes
808 * in from it's own vertex buffer since it's not part of the indirect
812 struct brw_bo
*draw_id_bo
;
813 uint32_t draw_id_offset
;
818 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
819 * an indirect call, and num_work_groups_offset is valid. Otherwise,
820 * num_work_groups is set based on glDispatchCompute.
822 struct brw_bo
*num_work_groups_bo
;
823 GLintptr num_work_groups_offset
;
824 const GLuint
*num_work_groups
;
828 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
829 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
831 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
835 /* Summary of size and varying of active arrays, so we can check
836 * for changes to this state:
838 bool index_bounds_valid
;
839 unsigned int min_index
, max_index
;
841 /* Offset from start of vertex buffer so we can avoid redefining
842 * the same VB packed over and over again.
844 unsigned int start_vertex_bias
;
847 * Certain vertex attribute formats aren't natively handled by the
848 * hardware and require special VS code to fix up their values.
850 * These bitfields indicate which workarounds are needed.
852 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
857 * Index buffer for this draw_prims call.
859 * Updates are signaled by BRW_NEW_INDICES.
861 const struct _mesa_index_buffer
*ib
;
863 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
868 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
869 * avoid re-uploading the IB packet over and over if we're actually
870 * referencing the same index buffer.
872 unsigned int start_vertex_offset
;
875 /* Active vertex program:
877 const struct gl_program
*vertex_program
;
878 const struct gl_program
*geometry_program
;
879 const struct gl_program
*tess_ctrl_program
;
880 const struct gl_program
*tess_eval_program
;
881 const struct gl_program
*fragment_program
;
882 const struct gl_program
*compute_program
;
885 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
886 * that we don't have to reemit that state every time we change FBOs.
890 /* BRW_NEW_URB_ALLOCATIONS:
893 GLuint vsize
; /* vertex size plus header in urb registers */
894 GLuint gsize
; /* GS output size in urb registers */
895 GLuint hsize
; /* Tessellation control output size in urb registers */
896 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
897 GLuint csize
; /* constant buffer size in urb registers */
898 GLuint sfsize
; /* setup data size in urb registers */
902 GLuint nr_vs_entries
;
903 GLuint nr_hs_entries
;
904 GLuint nr_ds_entries
;
905 GLuint nr_gs_entries
;
906 GLuint nr_clip_entries
;
907 GLuint nr_sf_entries
;
908 GLuint nr_cs_entries
;
918 * URB size in the current configuration. The units this is expressed
919 * in are somewhat inconsistent, see gen_device_info::urb::size.
921 * FINISHME: Represent the URB size consistently in KB on all platforms.
925 /* True if the most recently sent _3DSTATE_URB message allocated
926 * URB space for the GS.
930 /* True if the most recently sent _3DSTATE_URB message allocated
931 * URB space for the HS and DS.
937 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
939 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
940 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
948 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
949 * for upload to the CURBE.
951 struct brw_bo
*curbe_bo
;
952 /** Offset within curbe_bo of space for current curbe entry */
957 * Layout of vertex data exiting the geometry portion of the pipleine.
958 * This comes from the last enabled shader stage (GS, DS, or VS).
960 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
962 struct brw_vue_map vue_map_geom_out
;
965 struct brw_stage_state base
;
969 struct brw_stage_state base
;
972 * True if the 3DSTATE_HS command most recently emitted to the 3D
973 * pipeline enabled the HS; false otherwise.
979 struct brw_stage_state base
;
982 * True if the 3DSTATE_DS command most recently emitted to the 3D
983 * pipeline enabled the DS; false otherwise.
989 struct brw_stage_state base
;
992 * True if the 3DSTATE_GS command most recently emitted to the 3D
993 * pipeline enabled the GS; false otherwise.
999 struct brw_ff_gs_prog_data
*prog_data
;
1002 /** Offset in the program cache to the CLIP program pre-gen6 */
1003 uint32_t prog_offset
;
1004 uint32_t state_offset
;
1006 uint32_t bind_bo_offset
;
1008 * Surface offsets for the binding table. We only need surfaces to
1009 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1010 * need in this case.
1012 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1016 struct brw_clip_prog_data
*prog_data
;
1018 /** Offset in the program cache to the CLIP program pre-gen6 */
1019 uint32_t prog_offset
;
1021 /* Offset in the batch to the CLIP state on pre-gen6. */
1022 uint32_t state_offset
;
1024 /* As of gen6, this is the offset in the batch to the CLIP VP,
1030 * The number of viewports to use. If gl_ViewportIndex is written,
1031 * we can have up to ctx->Const.MaxViewports viewports. If not,
1032 * the viewport index is always 0, so we can only emit one.
1034 uint8_t viewport_count
;
1039 struct brw_sf_prog_data
*prog_data
;
1041 /** Offset in the program cache to the CLIP program pre-gen6 */
1042 uint32_t prog_offset
;
1043 uint32_t state_offset
;
1048 struct brw_stage_state base
;
1053 * Buffer object used in place of multisampled null render targets on
1054 * Gen6. See brw_emit_null_surface_state().
1056 struct brw_bo
*multisampled_null_render_target_bo
;
1057 uint32_t fast_clear_op
;
1063 struct brw_stage_state base
;
1067 uint32_t state_offset
;
1068 uint32_t blend_state_offset
;
1069 uint32_t depth_stencil_state_offset
;
1074 struct brw_query_object
*obj
;
1079 enum brw_predicate_state state
;
1084 /* Variables referenced in the XML meta data for OA performance
1085 * counters, e.g in the normalization equations.
1087 * All uint64_t for consistent operand types in generated code
1090 uint64_t timestamp_frequency
; /** $GpuTimestampFrequency */
1091 uint64_t n_eus
; /** $EuCoresTotalCount */
1092 uint64_t n_eu_slices
; /** $EuSlicesTotalCount */
1093 uint64_t subslice_mask
; /** $SubsliceMask */
1094 uint64_t gt_min_freq
; /** $GpuMinFrequency */
1095 uint64_t gt_max_freq
; /** $GpuMaxFrequency */
1098 /* OA metric sets, indexed by GUID, as know by Mesa at build time,
1099 * to cross-reference with the GUIDs of configs advertised by the
1102 struct hash_table
*oa_metrics_table
;
1104 struct brw_perf_query_info
*queries
;
1107 /* The i915 perf stream we open to setup + enable the OA counters */
1110 /* An i915 perf stream fd gives exclusive access to the OA unit that will
1111 * report counter snapshots for a specific counter set/profile in a
1112 * specific layout/format so we can only start OA queries that are
1113 * compatible with the currently open fd...
1115 int current_oa_metrics_set_id
;
1116 int current_oa_format
;
1118 /* List of buffers containing OA reports */
1119 struct exec_list sample_buffers
;
1121 /* Cached list of empty sample buffers */
1122 struct exec_list free_sample_buffers
;
1124 int n_active_oa_queries
;
1125 int n_active_pipeline_stats_queries
;
1127 /* The number of queries depending on running OA counters which
1128 * extends beyond brw_end_perf_query() since we need to wait until
1129 * the last MI_RPC command has parsed by the GPU.
1131 * Accurate accounting is important here as emitting an
1132 * MI_REPORT_PERF_COUNT command while the OA unit is disabled will
1133 * effectively hang the gpu.
1137 /* To help catch an spurious problem with the hardware or perf
1138 * forwarding samples, we emit each MI_REPORT_PERF_COUNT command
1139 * with a unique ID that we can explicitly check for...
1141 int next_query_start_report_id
;
1144 * An array of queries whose results haven't yet been assembled
1145 * based on the data in buffer objects.
1147 * These may be active, or have already ended. However, the
1148 * results have not been requested.
1150 struct brw_perf_query_object
**unaccumulated
;
1151 int unaccumulated_elements
;
1152 int unaccumulated_array_size
;
1154 /* The total number of query objects so we can relinquish
1155 * our exclusive access to perf if the application deletes
1156 * all of its objects. (NB: We only disable perf while
1157 * there are no active queries)
1159 int n_query_instances
;
1162 int num_atoms
[BRW_NUM_PIPELINES
];
1163 const struct brw_tracked_state render_atoms
[76];
1164 const struct brw_tracked_state compute_atoms
[11];
1166 enum isl_format render_target_format
[MESA_FORMAT_COUNT
];
1167 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1169 /* PrimitiveRestart */
1172 bool enable_cut_index
;
1175 /** Computed depth/stencil/hiz state from the current attached
1176 * renderbuffers, valid only during the drawing state upload loop after
1177 * brw_workaround_depthstencil_alignment().
1180 struct intel_mipmap_tree
*depth_mt
;
1181 struct intel_mipmap_tree
*stencil_mt
;
1183 /* Inter-tile (page-aligned) byte offsets. */
1184 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1185 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1186 uint32_t tile_x
, tile_y
;
1189 uint32_t num_instances
;
1194 const struct gen_l3_config
*config
;
1201 enum shader_time_shader_type
*types
;
1202 struct shader_times
*cumulative
;
1208 struct brw_fast_clear_state
*fast_clear_state
;
1210 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1211 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1212 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1214 * This is needed in case the same underlying buffer is also configured
1215 * to be sampled but with a format that the sampling engine can't treat
1216 * compressed or fast cleared.
1218 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1220 __DRIcontext
*driContext
;
1221 struct intel_screen
*screen
;
1225 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1227 /*======================================================================
1230 extern const char *const brw_vendor_string
;
1233 brw_get_renderer_string(const struct intel_screen
*screen
);
1236 DRI_CONF_BO_REUSE_DISABLED
,
1237 DRI_CONF_BO_REUSE_ALL
1240 void intel_update_renderbuffers(__DRIcontext
*context
,
1241 __DRIdrawable
*drawable
);
1242 void intel_prepare_render(struct brw_context
*brw
);
1244 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1245 __DRIdrawable
*drawable
);
1247 GLboolean
brwCreateContext(gl_api api
,
1248 const struct gl_config
*mesaVis
,
1249 __DRIcontext
*driContextPriv
,
1250 unsigned major_version
,
1251 unsigned minor_version
,
1255 void *sharedContextPrivate
);
1257 /*======================================================================
1261 brw_meta_resolve_color(struct brw_context
*brw
,
1262 struct intel_mipmap_tree
*mt
);
1264 /*======================================================================
1267 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1268 GLbitfield clear_mask
);
1270 /* brw_object_purgeable.c */
1271 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1273 /*======================================================================
1276 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1277 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1278 void brw_emit_query_begin(struct brw_context
*brw
);
1279 void brw_emit_query_end(struct brw_context
*brw
);
1280 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1281 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1282 uint64_t brw_timebase_scale(struct brw_context
*brw
, uint64_t gpu_timestamp
);
1283 uint64_t brw_raw_timestamp_delta(struct brw_context
*brw
,
1284 uint64_t time0
, uint64_t time1
);
1286 /** gen6_queryobj.c */
1287 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1288 void brw_write_timestamp(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1289 void brw_write_depth_count(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1291 /** hsw_queryobj.c */
1292 void hsw_overflow_result_to_gpr0(struct brw_context
*brw
,
1293 struct brw_query_object
*query
,
1295 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1297 /** brw_conditional_render.c */
1298 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1299 bool brw_check_conditional_render(struct brw_context
*brw
);
1301 /** intel_batchbuffer.c */
1302 void brw_load_register_mem(struct brw_context
*brw
,
1305 uint32_t read_domains
, uint32_t write_domain
,
1307 void brw_load_register_mem64(struct brw_context
*brw
,
1310 uint32_t read_domains
, uint32_t write_domain
,
1312 void brw_store_register_mem32(struct brw_context
*brw
,
1313 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1314 void brw_store_register_mem64(struct brw_context
*brw
,
1315 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1316 void brw_load_register_imm32(struct brw_context
*brw
,
1317 uint32_t reg
, uint32_t imm
);
1318 void brw_load_register_imm64(struct brw_context
*brw
,
1319 uint32_t reg
, uint64_t imm
);
1320 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1322 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1324 void brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1325 uint32_t offset
, uint32_t imm
);
1326 void brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1327 uint32_t offset
, uint64_t imm
);
1329 /*======================================================================
1330 * intel_tex_validate.c
1332 void brw_validate_textures( struct brw_context
*brw
);
1335 /*======================================================================
1339 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1342 perf_debug(" %s %d->%d\n", name
, a
, b
);
1348 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1350 void brw_get_scratch_bo(struct brw_context
*brw
,
1351 struct brw_bo
**scratch_bo
, int size
);
1352 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1353 struct brw_stage_state
*stage_state
,
1354 unsigned per_thread_size
,
1355 unsigned thread_count
);
1356 void brw_init_shader_time(struct brw_context
*brw
);
1357 int brw_get_shader_time_index(struct brw_context
*brw
,
1358 struct gl_program
*prog
,
1359 enum shader_time_shader_type type
,
1361 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1362 void brw_destroy_shader_time(struct brw_context
*brw
);
1366 void brw_calculate_urb_fence(struct brw_context
*brw
, unsigned csize
,
1367 unsigned vsize
, unsigned sfsize
);
1368 void brw_upload_urb_fence(struct brw_context
*brw
);
1372 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1375 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1377 /* brw_draw_upload.c */
1378 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1379 const struct gl_vertex_array
*glarray
);
1381 static inline unsigned
1382 brw_get_index_type(unsigned index_size
)
1384 /* The hw needs 0x00, 0x01, and 0x02 for ubyte, ushort, and uint,
1387 return index_size
>> 1;
1390 void brw_prepare_vertices(struct brw_context
*brw
);
1392 /* brw_wm_surface_state.c */
1393 void brw_create_constant_surface(struct brw_context
*brw
,
1397 uint32_t *out_offset
);
1398 void brw_create_buffer_surface(struct brw_context
*brw
,
1402 uint32_t *out_offset
);
1403 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1405 uint32_t *surf_offset
);
1407 brw_update_sol_surface(struct brw_context
*brw
,
1408 struct gl_buffer_object
*buffer_obj
,
1409 uint32_t *out_offset
, unsigned num_vector_components
,
1410 unsigned stride_dwords
, unsigned offset_dwords
);
1411 void brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1412 struct brw_stage_state
*stage_state
,
1413 struct brw_stage_prog_data
*prog_data
);
1414 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1415 const struct gl_program
*prog
,
1416 struct brw_stage_state
*stage_state
,
1417 struct brw_stage_prog_data
*prog_data
);
1418 void brw_upload_image_surfaces(struct brw_context
*brw
,
1419 const struct gl_program
*prog
,
1420 struct brw_stage_state
*stage_state
,
1421 struct brw_stage_prog_data
*prog_data
);
1423 /* brw_surface_formats.c */
1424 void brw_init_surface_formats(struct brw_context
*brw
);
1425 bool brw_render_target_supported(struct brw_context
*brw
,
1426 struct gl_renderbuffer
*rb
);
1427 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1429 /* brw_performance_query.c */
1430 void brw_init_performance_queries(struct brw_context
*brw
);
1432 /* intel_extensions.c */
1433 extern void intelInitExtensions(struct gl_context
*ctx
);
1436 extern int intel_translate_shadow_compare_func(GLenum func
);
1437 extern int intel_translate_compare_func(GLenum func
);
1438 extern int intel_translate_stencil_op(GLenum op
);
1439 extern int intel_translate_logic_op(GLenum opcode
);
1442 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1445 struct gl_transform_feedback_object
*
1446 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1448 brw_delete_transform_feedback(struct gl_context
*ctx
,
1449 struct gl_transform_feedback_object
*obj
);
1451 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1452 struct gl_transform_feedback_object
*obj
);
1454 brw_end_transform_feedback(struct gl_context
*ctx
,
1455 struct gl_transform_feedback_object
*obj
);
1457 brw_pause_transform_feedback(struct gl_context
*ctx
,
1458 struct gl_transform_feedback_object
*obj
);
1460 brw_resume_transform_feedback(struct gl_context
*ctx
,
1461 struct gl_transform_feedback_object
*obj
);
1463 brw_save_primitives_written_counters(struct brw_context
*brw
,
1464 struct brw_transform_feedback_object
*obj
);
1466 brw_compute_xfb_vertices_written(struct brw_context
*brw
,
1467 struct brw_transform_feedback_object
*obj
);
1469 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1470 struct gl_transform_feedback_object
*obj
,
1473 /* gen7_sol_state.c */
1475 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1476 struct gl_transform_feedback_object
*obj
);
1478 gen7_end_transform_feedback(struct gl_context
*ctx
,
1479 struct gl_transform_feedback_object
*obj
);
1481 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1482 struct gl_transform_feedback_object
*obj
);
1484 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1485 struct gl_transform_feedback_object
*obj
);
1489 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1490 struct gl_transform_feedback_object
*obj
);
1492 hsw_end_transform_feedback(struct gl_context
*ctx
,
1493 struct gl_transform_feedback_object
*obj
);
1495 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1496 struct gl_transform_feedback_object
*obj
);
1498 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1499 struct gl_transform_feedback_object
*obj
);
1501 /* brw_blorp_blit.cpp */
1503 brw_blorp_framebuffer(struct brw_context
*brw
,
1504 struct gl_framebuffer
*readFb
,
1505 struct gl_framebuffer
*drawFb
,
1506 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1507 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1508 GLbitfield mask
, GLenum filter
);
1511 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1512 struct gl_renderbuffer
*src_rb
,
1513 struct gl_texture_image
*dst_image
,
1515 int srcX0
, int srcY0
,
1516 int dstX0
, int dstY0
,
1517 int width
, int height
);
1520 gen6_get_sample_position(struct gl_context
*ctx
,
1521 struct gl_framebuffer
*fb
,
1525 gen6_set_sample_maps(struct gl_context
*ctx
);
1527 /* gen8_multisample_state.c */
1528 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1529 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1533 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1534 unsigned hs_size
, unsigned ds_size
,
1535 unsigned gs_size
, unsigned fs_size
);
1538 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1539 bool gs_present
, unsigned gs_size
);
1541 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1542 bool gs_present
, bool tess_present
);
1546 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1548 brw_check_for_reset(struct brw_context
*brw
);
1552 brw_init_compute_functions(struct dd_function_table
*functions
);
1554 /*======================================================================
1555 * Inline conversion functions. These are better-typed than the
1556 * macros used previously:
1558 static inline struct brw_context
*
1559 brw_context( struct gl_context
*ctx
)
1561 return (struct brw_context
*)ctx
;
1564 static inline struct brw_program
*
1565 brw_program(struct gl_program
*p
)
1567 return (struct brw_program
*) p
;
1570 static inline const struct brw_program
*
1571 brw_program_const(const struct gl_program
*p
)
1573 return (const struct brw_program
*) p
;
1577 brw_depth_writes_enabled(const struct brw_context
*brw
)
1579 const struct gl_context
*ctx
= &brw
->ctx
;
1581 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1582 * because it would just overwrite the existing depth value with itself.
1584 * These bonus depth writes not only use bandwidth, but they also can
1585 * prevent early depth processing. For example, if the pixel shader
1586 * discards, the hardware must invoke the to determine whether or not
1587 * to do the depth write. If writes are disabled, we may still be able
1588 * to do the depth test before the shader, and skip the shader execution.
1590 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1591 * a programming note saying to disable depth writes for EQUAL.
1593 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1597 brw_emit_depthbuffer(struct brw_context
*brw
);
1600 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1601 struct intel_mipmap_tree
*depth_mt
,
1602 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1603 uint32_t depth_surface_type
,
1604 struct intel_mipmap_tree
*stencil_mt
,
1605 bool hiz
, bool separate_stencil
,
1606 uint32_t width
, uint32_t height
,
1607 uint32_t tile_x
, uint32_t tile_y
);
1610 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1611 struct intel_mipmap_tree
*depth_mt
,
1612 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1613 uint32_t depth_surface_type
,
1614 struct intel_mipmap_tree
*stencil_mt
,
1615 bool hiz
, bool separate_stencil
,
1616 uint32_t width
, uint32_t height
,
1617 uint32_t tile_x
, uint32_t tile_y
);
1620 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1621 struct intel_mipmap_tree
*depth_mt
,
1622 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1623 uint32_t depth_surface_type
,
1624 struct intel_mipmap_tree
*stencil_mt
,
1625 bool hiz
, bool separate_stencil
,
1626 uint32_t width
, uint32_t height
,
1627 uint32_t tile_x
, uint32_t tile_y
);
1629 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1630 struct intel_mipmap_tree
*depth_mt
,
1631 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1632 uint32_t depth_surface_type
,
1633 struct intel_mipmap_tree
*stencil_mt
,
1634 bool hiz
, bool separate_stencil
,
1635 uint32_t width
, uint32_t height
,
1636 uint32_t tile_x
, uint32_t tile_y
);
1638 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1639 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
);
1641 uint32_t get_hw_prim_for_gl_prim(int mode
);
1644 gen6_upload_push_constants(struct brw_context
*brw
,
1645 const struct gl_program
*prog
,
1646 const struct brw_stage_prog_data
*prog_data
,
1647 struct brw_stage_state
*stage_state
);
1650 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1651 const struct intel_mipmap_tree
*mt
);
1653 /* brw_pipe_control.c */
1654 int brw_init_pipe_control(struct brw_context
*brw
,
1655 const struct gen_device_info
*info
);
1656 void brw_fini_pipe_control(struct brw_context
*brw
);
1658 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1659 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1660 struct brw_bo
*bo
, uint32_t offset
,
1661 uint32_t imm_lower
, uint32_t imm_upper
);
1662 void brw_emit_mi_flush(struct brw_context
*brw
);
1663 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1664 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1665 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1666 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1668 /* brw_queryformat.c */
1669 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1670 GLenum internalFormat
, GLenum pname
,