2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "compiler/brw_compiler.h"
43 #include "blorp/blorp.h"
45 #include <brw_bufmgr.h>
47 #include "common/gen_debug.h"
48 #include "intel_screen.h"
49 #include "intel_tex_obj.h"
50 #include "intel_resolve_map.h"
57 * URB - uniform resource buffer. A mid-sized buffer which is
58 * partitioned between the fixed function units and used for passing
59 * values (vertices, primitives, constants) between them.
61 * CURBE - constant URB entry. An urb region (entry) used to hold
62 * constant values which the fixed function units can be instructed to
63 * preload into the GRF when spawning a thread.
65 * VUE - vertex URB entry. An urb entry holding a vertex and usually
66 * a vertex header. The header contains control information and
67 * things like primitive type, Begin/end flags and clip codes.
69 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
70 * unit holding rasterization and interpolation parameters.
72 * GRF - general register file. One of several register files
73 * addressable by programmed threads. The inputs (r0, payload, curbe,
74 * urb) of the thread are preloaded to this area before the thread is
75 * spawned. The registers are individually 8 dwords wide and suitable
76 * for general usage. Registers holding thread input values are not
77 * special and may be overwritten.
79 * MRF - message register file. Threads communicate (and terminate)
80 * by sending messages. Message parameters are placed in contiguous
81 * MRF registers. All program output is via these messages. URB
82 * entries are populated by sending a message to the shared URB
83 * function containing the new data, together with a control word,
84 * often an unmodified copy of R0.
86 * R0 - GRF register 0. Typically holds control information used when
87 * sending messages to other threads.
89 * EU or GEN4 EU: The name of the programmable subsystem of the
90 * i965 hardware. Threads are executed by the EU, the registers
91 * described above are part of the EU architecture.
93 * Fixed function units:
95 * CS - Command streamer. Notional first unit, little software
96 * interaction. Holds the URB entries used for constant data, ie the
99 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
100 * this unit is responsible for pulling vertices out of vertex buffers
101 * in vram and injecting them into the processing pipe as VUEs. If
102 * enabled, it first passes them to a VS thread which is a good place
103 * for the driver to implement any active vertex shader.
105 * HS - Hull Shader (Tessellation Control Shader)
107 * TE - Tessellation Engine (Tessellation Primitive Generation)
109 * DS - Domain Shader (Tessellation Evaluation Shader)
111 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
112 * enabled, incoming strips etc are passed to GS threads in individual
113 * line/triangle/point units. The GS thread may perform arbitary
114 * computation and emit whatever primtives with whatever vertices it
115 * chooses. This makes GS an excellent place to implement GL's
116 * unfilled polygon modes, though of course it is capable of much
117 * more. Additionally, GS is used to translate away primitives not
118 * handled by latter units, including Quads and Lineloops.
120 * CS - Clipper. Mesa's clipping algorithms are imported to run on
121 * this unit. The fixed function part performs cliptesting against
122 * the 6 fixed clipplanes and makes descisions on whether or not the
123 * incoming primitive needs to be passed to a thread for clipping.
124 * User clip planes are handled via cooperation with the VS thread.
126 * SF - Strips Fans or Setup: Triangles are prepared for
127 * rasterization. Interpolation coefficients are calculated.
128 * Flatshading and two-side lighting usually performed here.
130 * WM - Windower. Interpolation of vertex attributes performed here.
131 * Fragment shader implemented here. SIMD aspects of EU taken full
132 * advantage of, as pixels are processed in blocks of 16.
134 * CC - Color Calculator. No EU threads associated with this unit.
135 * Handles blending and (presumably) depth and stencil testing.
140 struct brw_vs_prog_key
;
141 struct brw_vue_prog_key
;
142 struct brw_wm_prog_key
;
143 struct brw_wm_prog_data
;
144 struct brw_cs_prog_key
;
145 struct brw_cs_prog_data
;
149 BRW_COMPUTE_PIPELINE
,
156 BRW_CACHE_BLORP_PROG
,
159 BRW_CACHE_FF_GS_PROG
,
170 /* brw_cache_ids must come first - see brw_program_cache.c */
171 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
172 BRW_STATE_FRAGMENT_PROGRAM
,
173 BRW_STATE_GEOMETRY_PROGRAM
,
174 BRW_STATE_TESS_PROGRAMS
,
175 BRW_STATE_VERTEX_PROGRAM
,
176 BRW_STATE_CURBE_OFFSETS
,
177 BRW_STATE_REDUCED_PRIMITIVE
,
178 BRW_STATE_PATCH_PRIMITIVE
,
183 BRW_STATE_BINDING_TABLE_POINTERS
,
186 BRW_STATE_DEFAULT_TESS_LEVELS
,
188 BRW_STATE_INDEX_BUFFER
,
189 BRW_STATE_VS_CONSTBUF
,
190 BRW_STATE_TCS_CONSTBUF
,
191 BRW_STATE_TES_CONSTBUF
,
192 BRW_STATE_GS_CONSTBUF
,
193 BRW_STATE_PROGRAM_CACHE
,
194 BRW_STATE_STATE_BASE_ADDRESS
,
195 BRW_STATE_VUE_MAP_GEOM_OUT
,
196 BRW_STATE_TRANSFORM_FEEDBACK
,
197 BRW_STATE_RASTERIZER_DISCARD
,
199 BRW_STATE_UNIFORM_BUFFER
,
200 BRW_STATE_ATOMIC_BUFFER
,
201 BRW_STATE_IMAGE_UNITS
,
202 BRW_STATE_META_IN_PROGRESS
,
203 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
204 BRW_STATE_NUM_SAMPLES
,
205 BRW_STATE_TEXTURE_BUFFER
,
206 BRW_STATE_GEN4_UNIT_STATE
,
210 BRW_STATE_SAMPLER_STATE_TABLE
,
211 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
212 BRW_STATE_COMPUTE_PROGRAM
,
213 BRW_STATE_CS_WORK_GROUPS
,
217 BRW_STATE_VIEWPORT_COUNT
,
218 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
223 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
225 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
226 * When the currently bound shader program differs from the previous draw
227 * call, these will be flagged. They cover brw->{stage}_program and
228 * ctx->{Stage}Program->_Current.
230 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
231 * driver perspective. Even if the same shader is bound at the API level,
232 * we may need to switch between multiple versions of that shader to handle
233 * changes in non-orthagonal state.
235 * Additionally, multiple shader programs may have identical vertex shaders
236 * (for example), or compile down to the same code in the backend. We combine
237 * those into a single program cache entry.
239 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
240 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
242 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
243 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
244 * use the normal state upload paths), but the cache is still used. To avoid
245 * polluting the brw_program_cache code with special cases, we retain the
246 * dirty bit for now. It should eventually be removed.
248 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
249 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
250 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
251 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
252 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
253 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
254 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
255 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
256 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
257 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
258 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
259 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
260 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
261 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
262 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
263 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
264 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
265 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
266 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
267 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
268 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
269 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
270 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
271 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
272 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
274 * Used for any batch entry with a relocated pointer that will be used
275 * by any 3D rendering.
277 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
278 /** \see brw.state.depth_region */
279 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
280 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
281 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
282 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
283 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
284 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
285 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
286 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
287 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
288 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
289 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
290 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
291 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
292 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
293 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
294 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
295 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
296 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
297 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
298 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
299 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
300 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
301 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
302 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
303 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
304 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
305 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
306 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
307 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
308 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
309 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
311 struct brw_state_flags
{
312 /** State update flags signalled by mesa internals */
315 * State update flags signalled as the result of brw_tracked_state updates
321 /** Subclass of Mesa program */
323 struct gl_program program
;
330 struct brw_sf_prog_data
{
331 GLuint urb_read_length
;
334 /* Each vertex may have upto 12 attributes, 4 components each,
335 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
338 * Actually we use 4 for each, so call it 12 rows.
340 GLuint urb_entry_size
;
344 struct brw_clip_prog_data
{
345 GLuint curb_read_length
; /* user planes? */
347 GLuint urb_read_length
;
351 struct brw_ff_gs_prog_data
{
352 GLuint urb_read_length
;
356 * Gen6 transform feedback: Amount by which the streaming vertex buffer
357 * indices should be incremented each time the GS is invoked.
359 unsigned svbi_postincrement_value
;
362 /** Number of texture sampler units */
363 #define BRW_MAX_TEX_UNIT 32
365 /** Max number of UBOs in a shader */
366 #define BRW_MAX_UBO 14
368 /** Max number of SSBOs in a shader */
369 #define BRW_MAX_SSBO 12
371 /** Max number of atomic counter buffer objects in a shader */
372 #define BRW_MAX_ABO 16
374 /** Max number of image uniforms in a shader */
375 #define BRW_MAX_IMAGES 32
377 /** Maximum number of actual buffers used for stream output */
378 #define BRW_MAX_SOL_BUFFERS 4
380 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
381 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
386 2 + /* shader time, pull constants */ \
387 1 /* cs num work groups */)
390 struct brw_context
*brw
;
392 struct brw_cache_item
**items
;
394 GLuint size
, n_items
;
396 uint32_t next_offset
;
401 /* Considered adding a member to this struct to document which flags
402 * an update might raise so that ordering of the state atoms can be
403 * checked or derived at runtime. Dropped the idea in favor of having
404 * a debug mode where the state is monitored for flags which are
405 * raised that have already been tested against.
407 struct brw_tracked_state
{
408 struct brw_state_flags dirty
;
409 void (*emit
)( struct brw_context
*brw
);
412 enum shader_time_shader_type
{
423 struct brw_vertex_buffer
{
424 /** Buffer object containing the uploaded vertex data */
428 /** Byte stride between elements in the uploaded array */
432 struct brw_vertex_element
{
433 const struct gl_vertex_array
*glarray
;
437 /** Offset of the first element within the buffer object */
441 struct brw_query_object
{
442 struct gl_query_object Base
;
444 /** Last query BO associated with this query. */
447 /** Last index in bo with query data for this object. */
450 /** True if we know the batch has been flushed since we ended the query. */
460 struct intel_batchbuffer
{
461 /** Current batchbuffer being queued up. */
463 /** Last BO submitted to the hardware. Used for glFinish(). */
464 drm_bacon_bo
*last_bo
;
467 uint16_t emit
, total
;
469 uint16_t reserved_space
;
473 #define BATCH_SZ (8192*sizeof(uint32_t))
475 uint32_t state_batch_offset
;
476 enum brw_gpu_ring ring
;
477 bool needs_sol_reset
;
478 bool state_base_address_emitted
;
480 struct drm_i915_gem_relocation_entry
*relocs
;
482 int reloc_array_size
;
483 /** The validation list */
484 struct drm_i915_gem_exec_object2
*exec_objects
;
485 drm_bacon_bo
**exec_bos
;
488 /** The amount of aperture space (in bytes) used by all exec_bos */
497 /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */
498 struct hash_table
*state_batch_sizes
;
501 #define BRW_MAX_XFB_STREAMS 4
503 struct brw_transform_feedback_object
{
504 struct gl_transform_feedback_object base
;
506 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
507 drm_bacon_bo
*offset_bo
;
509 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
512 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
513 GLenum primitive_mode
;
516 * The maximum number of vertices that we can write without overflowing
517 * any of the buffers currently being used for transform feedback.
522 * Count of primitives generated during this transform feedback operation.
525 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
526 drm_bacon_bo
*prim_count_bo
;
527 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
531 * Number of vertices written between last Begin/EndTransformFeedback().
533 * Used to implement DrawTransformFeedback().
535 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
536 bool vertices_written_valid
;
540 * Data shared between each programmable stage in the pipeline (vs, gs, and
543 struct brw_stage_state
545 gl_shader_stage stage
;
546 struct brw_stage_prog_data
*prog_data
;
549 * Optional scratch buffer used to store spilled register values and
550 * variably-indexed GRF arrays.
552 * The contents of this buffer are short-lived so the same memory can be
553 * re-used at will for multiple shader programs (executed by the same fixed
554 * function). However reusing a scratch BO for which shader invocations
555 * are still in flight with a per-thread scratch slot size other than the
556 * original can cause threads with different scratch slot size and FFTID
557 * (which may be executed in parallel depending on the shader stage and
558 * hardware generation) to map to an overlapping region of the scratch
559 * space, which can potentially lead to mutual scratch space corruption.
560 * For that reason if you borrow this scratch buffer you should only be
561 * using the slot size given by the \c per_thread_scratch member below,
562 * unless you're taking additional measures to synchronize thread execution
563 * across slot size changes.
565 drm_bacon_bo
*scratch_bo
;
568 * Scratch slot size allocated for each thread in the buffer object given
571 uint32_t per_thread_scratch
;
573 /** Offset in the program cache to the program */
574 uint32_t prog_offset
;
576 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
577 uint32_t state_offset
;
579 uint32_t push_const_offset
; /* Offset in the batchbuffer */
580 int push_const_size
; /* in 256-bit register increments */
582 /* Binding table: pointers to SURFACE_STATE entries. */
583 uint32_t bind_bo_offset
;
584 uint32_t surf_offset
[BRW_MAX_SURFACES
];
586 /** SAMPLER_STATE count and table offset */
587 uint32_t sampler_count
;
588 uint32_t sampler_offset
;
591 enum brw_predicate_state
{
592 /* The first two states are used if we can determine whether to draw
593 * without having to look at the values in the query object buffer. This
594 * will happen if there is no conditional render in progress, if the query
595 * object is already completed or if something else has already added
596 * samples to the preliminary result such as via a BLT command.
598 BRW_PREDICATE_STATE_RENDER
,
599 BRW_PREDICATE_STATE_DONT_RENDER
,
600 /* In this case whether to draw or not depends on the result of an
601 * MI_PREDICATE command so the predicate enable bit needs to be checked.
603 BRW_PREDICATE_STATE_USE_BIT
608 struct gen_l3_config
;
610 enum brw_query_kind
{
615 struct brw_perf_query_info
617 enum brw_query_kind kind
;
620 struct brw_perf_query_counter
*counters
;
625 uint64_t oa_metrics_set_id
;
628 /* For indexing into the accumulator[] ... */
630 int gpu_clock_offset
;
637 * brw_context is derived from gl_context.
641 struct gl_context ctx
; /**< base class, must be first field */
645 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
646 struct gl_renderbuffer
*rb
,
647 uint32_t flags
, unsigned unit
,
648 uint32_t surf_index
);
649 void (*emit_null_surface_state
)(struct brw_context
*brw
,
653 uint32_t *out_offset
);
656 * Send the appropriate state packets to configure depth, stencil, and
657 * HiZ buffers (i965+ only)
659 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
660 struct intel_mipmap_tree
*depth_mt
,
661 uint32_t depth_offset
,
662 uint32_t depthbuffer_format
,
663 uint32_t depth_surface_type
,
664 struct intel_mipmap_tree
*stencil_mt
,
665 bool hiz
, bool separate_stencil
,
666 uint32_t width
, uint32_t height
,
667 uint32_t tile_x
, uint32_t tile_y
);
671 struct brw_bufmgr
*bufmgr
;
675 /** BO for post-sync nonzero writes for gen6 workaround. */
676 drm_bacon_bo
*workaround_bo
;
677 uint8_t pipe_controls_since_last_cs_stall
;
680 * Set of drm_bacon_bo * that have been rendered to within this batchbuffer
681 * and would need flushing before being used from another cache domain that
682 * isn't coherent with it (i.e. the sampler).
684 struct set
*render_cache
;
687 * Number of resets observed in the system at context creation.
689 * This is tracked in the context so that we can determine that another
690 * reset has occurred.
692 uint32_t reset_count
;
694 struct intel_batchbuffer batch
;
699 uint32_t next_offset
;
703 * Set if rendering has occurred to the drawable's front buffer.
705 * This is used in the DRI2 case to detect that glFlush should also copy
706 * the contents of the fake front buffer to the real front buffer.
708 bool front_buffer_dirty
;
710 /** Framerate throttling: @{ */
711 drm_bacon_bo
*throttle_batch
[2];
713 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
714 * frame of rendering to complete. This gives a very precise cap to the
715 * latency between input and output such that rendering never gets more
716 * than a frame behind the user. (With the caveat that we technically are
717 * not using the SwapBuffers itself as a barrier but the first batch
718 * submitted afterwards, which may be immediately prior to the next
721 bool need_swap_throttle
;
723 /** General throttling, not caught by throttling between SwapBuffers */
724 bool need_flush_throttle
;
734 bool always_flush_batch
;
735 bool always_flush_cache
;
736 bool disable_throttling
;
738 bool dual_color_blend_by_location
;
740 driOptionCache optionCache
;
743 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
745 GLenum reduced_primitive
;
748 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
749 * variable is set, this is the flag indicating to do expensive work that
750 * might lead to a perf_debug() call.
754 uint64_t max_gtt_map_object_size
;
766 bool has_separate_stencil
;
767 bool must_use_separate_stencil
;
770 bool has_surface_tile_offset
;
772 bool has_negative_rhw_bug
;
776 bool use_resource_streamer
;
779 * Some versions of Gen hardware don't do centroid interpolation correctly
780 * on unlit pixels, causing incorrect values for derivatives near triangle
781 * edges. Enabling this flag causes the fragment shader to use
782 * non-centroid interpolation for unlit pixels, at the expense of two extra
783 * fragment shader instructions.
785 bool needs_unlit_centroid_workaround
;
787 struct isl_device isl_dev
;
789 struct blorp_context blorp
;
793 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
796 enum brw_pipeline last_pipeline
;
798 struct brw_cache cache
;
800 /** IDs for meta stencil blit shader programs. */
801 struct gl_shader_program
*meta_stencil_blit_programs
[2];
803 /* Whether a meta-operation is in progress. */
804 bool meta_in_progress
;
806 /* Whether the last depth/stencil packets were both NULL. */
807 bool no_depth_or_stencil
;
809 /* The last PMA stall bits programmed. */
810 uint32_t pma_stall_bits
;
814 /** The value of gl_BaseVertex for the current _mesa_prim. */
817 /** The value of gl_BaseInstance for the current _mesa_prim. */
822 * Buffer and offset used for GL_ARB_shader_draw_parameters
823 * (for now, only gl_BaseVertex).
825 drm_bacon_bo
*draw_params_bo
;
826 uint32_t draw_params_offset
;
829 * The value of gl_DrawID for the current _mesa_prim. This always comes
830 * in from it's own vertex buffer since it's not part of the indirect
834 drm_bacon_bo
*draw_id_bo
;
835 uint32_t draw_id_offset
;
840 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
841 * an indirect call, and num_work_groups_offset is valid. Otherwise,
842 * num_work_groups is set based on glDispatchCompute.
844 drm_bacon_bo
*num_work_groups_bo
;
845 GLintptr num_work_groups_offset
;
846 const GLuint
*num_work_groups
;
850 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
851 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
853 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
857 /* Summary of size and varying of active arrays, so we can check
858 * for changes to this state:
860 bool index_bounds_valid
;
861 unsigned int min_index
, max_index
;
863 /* Offset from start of vertex buffer so we can avoid redefining
864 * the same VB packed over and over again.
866 unsigned int start_vertex_bias
;
869 * Certain vertex attribute formats aren't natively handled by the
870 * hardware and require special VS code to fix up their values.
872 * These bitfields indicate which workarounds are needed.
874 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
879 * Index buffer for this draw_prims call.
881 * Updates are signaled by BRW_NEW_INDICES.
883 const struct _mesa_index_buffer
*ib
;
885 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
890 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
891 * avoid re-uploading the IB packet over and over if we're actually
892 * referencing the same index buffer.
894 unsigned int start_vertex_offset
;
897 /* Active vertex program:
899 const struct gl_program
*vertex_program
;
900 const struct gl_program
*geometry_program
;
901 const struct gl_program
*tess_ctrl_program
;
902 const struct gl_program
*tess_eval_program
;
903 const struct gl_program
*fragment_program
;
904 const struct gl_program
*compute_program
;
907 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
908 * that we don't have to reemit that state every time we change FBOs.
912 /* BRW_NEW_URB_ALLOCATIONS:
915 GLuint vsize
; /* vertex size plus header in urb registers */
916 GLuint gsize
; /* GS output size in urb registers */
917 GLuint hsize
; /* Tessellation control output size in urb registers */
918 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
919 GLuint csize
; /* constant buffer size in urb registers */
920 GLuint sfsize
; /* setup data size in urb registers */
924 GLuint nr_vs_entries
;
925 GLuint nr_hs_entries
;
926 GLuint nr_ds_entries
;
927 GLuint nr_gs_entries
;
928 GLuint nr_clip_entries
;
929 GLuint nr_sf_entries
;
930 GLuint nr_cs_entries
;
940 * URB size in the current configuration. The units this is expressed
941 * in are somewhat inconsistent, see gen_device_info::urb::size.
943 * FINISHME: Represent the URB size consistently in KB on all platforms.
947 /* True if the most recently sent _3DSTATE_URB message allocated
948 * URB space for the GS.
952 /* True if the most recently sent _3DSTATE_URB message allocated
953 * URB space for the HS and DS.
959 /* BRW_NEW_CURBE_OFFSETS:
962 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
963 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
971 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
972 * for upload to the CURBE.
974 drm_bacon_bo
*curbe_bo
;
975 /** Offset within curbe_bo of space for current curbe entry */
980 * Layout of vertex data exiting the geometry portion of the pipleine.
981 * This comes from the last enabled shader stage (GS, DS, or VS).
983 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
985 struct brw_vue_map vue_map_geom_out
;
988 struct brw_stage_state base
;
992 struct brw_stage_state base
;
995 * True if the 3DSTATE_HS command most recently emitted to the 3D
996 * pipeline enabled the HS; false otherwise.
1002 struct brw_stage_state base
;
1005 * True if the 3DSTATE_DS command most recently emitted to the 3D
1006 * pipeline enabled the DS; false otherwise.
1012 struct brw_stage_state base
;
1015 * True if the 3DSTATE_GS command most recently emitted to the 3D
1016 * pipeline enabled the GS; false otherwise.
1022 struct brw_ff_gs_prog_data
*prog_data
;
1025 /** Offset in the program cache to the CLIP program pre-gen6 */
1026 uint32_t prog_offset
;
1027 uint32_t state_offset
;
1029 uint32_t bind_bo_offset
;
1031 * Surface offsets for the binding table. We only need surfaces to
1032 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1033 * need in this case.
1035 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1039 struct brw_clip_prog_data
*prog_data
;
1041 /** Offset in the program cache to the CLIP program pre-gen6 */
1042 uint32_t prog_offset
;
1044 /* Offset in the batch to the CLIP state on pre-gen6. */
1045 uint32_t state_offset
;
1047 /* As of gen6, this is the offset in the batch to the CLIP VP,
1053 * The number of viewports to use. If gl_ViewportIndex is written,
1054 * we can have up to ctx->Const.MaxViewports viewports. If not,
1055 * the viewport index is always 0, so we can only emit one.
1057 uint8_t viewport_count
;
1062 struct brw_sf_prog_data
*prog_data
;
1064 /** Offset in the program cache to the CLIP program pre-gen6 */
1065 uint32_t prog_offset
;
1066 uint32_t state_offset
;
1068 bool viewport_transform_enable
;
1072 struct brw_stage_state base
;
1077 * Buffer object used in place of multisampled null render targets on
1078 * Gen6. See brw_emit_null_surface_state().
1080 drm_bacon_bo
*multisampled_null_render_target_bo
;
1081 uint32_t fast_clear_op
;
1087 struct brw_stage_state base
;
1091 uint32_t state_offset
;
1092 uint32_t blend_state_offset
;
1093 uint32_t depth_stencil_state_offset
;
1098 struct brw_query_object
*obj
;
1103 enum brw_predicate_state state
;
1108 /* Variables referenced in the XML meta data for OA performance
1109 * counters, e.g in the normalization equations.
1111 * All uint64_t for consistent operand types in generated code
1114 uint64_t timestamp_frequency
; /** $GpuTimestampFrequency */
1115 uint64_t n_eus
; /** $EuCoresTotalCount */
1116 uint64_t n_eu_slices
; /** $EuSlicesTotalCount */
1117 uint64_t subslice_mask
; /** $SubsliceMask */
1118 uint64_t gt_min_freq
; /** $GpuMinFrequency */
1119 uint64_t gt_max_freq
; /** $GpuMaxFrequency */
1122 /* OA metric sets, indexed by GUID, as know by Mesa at build time,
1123 * to cross-reference with the GUIDs of configs advertised by the
1126 struct hash_table
*oa_metrics_table
;
1128 struct brw_perf_query_info
*queries
;
1131 /* The i915 perf stream we open to setup + enable the OA counters */
1134 /* An i915 perf stream fd gives exclusive access to the OA unit that will
1135 * report counter snapshots for a specific counter set/profile in a
1136 * specific layout/format so we can only start OA queries that are
1137 * compatible with the currently open fd...
1139 int current_oa_metrics_set_id
;
1140 int current_oa_format
;
1142 /* List of buffers containing OA reports */
1143 struct exec_list sample_buffers
;
1145 /* Cached list of empty sample buffers */
1146 struct exec_list free_sample_buffers
;
1148 int n_active_oa_queries
;
1149 int n_active_pipeline_stats_queries
;
1151 /* The number of queries depending on running OA counters which
1152 * extends beyond brw_end_perf_query() since we need to wait until
1153 * the last MI_RPC command has parsed by the GPU.
1155 * Accurate accounting is important here as emitting an
1156 * MI_REPORT_PERF_COUNT command while the OA unit is disabled will
1157 * effectively hang the gpu.
1161 /* To help catch an spurious problem with the hardware or perf
1162 * forwarding samples, we emit each MI_REPORT_PERF_COUNT command
1163 * with a unique ID that we can explicitly check for...
1165 int next_query_start_report_id
;
1168 * An array of queries whose results haven't yet been assembled
1169 * based on the data in buffer objects.
1171 * These may be active, or have already ended. However, the
1172 * results have not been requested.
1174 struct brw_perf_query_object
**unaccumulated
;
1175 int unaccumulated_elements
;
1176 int unaccumulated_array_size
;
1178 /* The total number of query objects so we can relinquish
1179 * our exclusive access to perf if the application deletes
1180 * all of its objects. (NB: We only disable perf while
1181 * there are no active queries)
1183 int n_query_instances
;
1186 int num_atoms
[BRW_NUM_PIPELINES
];
1187 const struct brw_tracked_state render_atoms
[76];
1188 const struct brw_tracked_state compute_atoms
[11];
1190 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1191 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1193 /* PrimitiveRestart */
1196 bool enable_cut_index
;
1199 /** Computed depth/stencil/hiz state from the current attached
1200 * renderbuffers, valid only during the drawing state upload loop after
1201 * brw_workaround_depthstencil_alignment().
1204 struct intel_mipmap_tree
*depth_mt
;
1205 struct intel_mipmap_tree
*stencil_mt
;
1207 /* Inter-tile (page-aligned) byte offsets. */
1208 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1209 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1210 uint32_t tile_x
, tile_y
;
1213 uint32_t num_instances
;
1218 const struct gen_l3_config
*config
;
1225 enum shader_time_shader_type
*types
;
1226 struct shader_times
*cumulative
;
1232 struct brw_fast_clear_state
*fast_clear_state
;
1234 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1235 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1236 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1238 * This is needed in case the same underlying buffer is also configured
1239 * to be sampled but with a format that the sampling engine can't treat
1240 * compressed or fast cleared.
1242 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1244 __DRIcontext
*driContext
;
1245 struct intel_screen
*screen
;
1249 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1251 /*======================================================================
1254 extern const char *const brw_vendor_string
;
1257 brw_get_renderer_string(const struct intel_screen
*screen
);
1260 DRI_CONF_BO_REUSE_DISABLED
,
1261 DRI_CONF_BO_REUSE_ALL
1264 void intel_update_renderbuffers(__DRIcontext
*context
,
1265 __DRIdrawable
*drawable
);
1266 void intel_prepare_render(struct brw_context
*brw
);
1268 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1269 __DRIdrawable
*drawable
);
1271 GLboolean
brwCreateContext(gl_api api
,
1272 const struct gl_config
*mesaVis
,
1273 __DRIcontext
*driContextPriv
,
1274 unsigned major_version
,
1275 unsigned minor_version
,
1279 void *sharedContextPrivate
);
1281 /*======================================================================
1285 brw_meta_resolve_color(struct brw_context
*brw
,
1286 struct intel_mipmap_tree
*mt
);
1288 /*======================================================================
1291 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1292 GLbitfield clear_mask
);
1294 /* brw_object_purgeable.c */
1295 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1297 /*======================================================================
1300 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1301 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1302 void brw_emit_query_begin(struct brw_context
*brw
);
1303 void brw_emit_query_end(struct brw_context
*brw
);
1304 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1305 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1306 uint64_t brw_timebase_scale(struct brw_context
*brw
, uint64_t gpu_timestamp
);
1307 uint64_t brw_raw_timestamp_delta(struct brw_context
*brw
,
1308 uint64_t time0
, uint64_t time1
);
1310 /** gen6_queryobj.c */
1311 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1312 void brw_write_timestamp(struct brw_context
*brw
, drm_bacon_bo
*bo
, int idx
);
1313 void brw_write_depth_count(struct brw_context
*brw
, drm_bacon_bo
*bo
, int idx
);
1315 /** hsw_queryobj.c */
1316 void hsw_overflow_result_to_gpr0(struct brw_context
*brw
,
1317 struct brw_query_object
*query
,
1319 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1321 /** brw_conditional_render.c */
1322 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1323 bool brw_check_conditional_render(struct brw_context
*brw
);
1325 /** intel_batchbuffer.c */
1326 void brw_load_register_mem(struct brw_context
*brw
,
1329 uint32_t read_domains
, uint32_t write_domain
,
1331 void brw_load_register_mem64(struct brw_context
*brw
,
1334 uint32_t read_domains
, uint32_t write_domain
,
1336 void brw_store_register_mem32(struct brw_context
*brw
,
1337 drm_bacon_bo
*bo
, uint32_t reg
, uint32_t offset
);
1338 void brw_store_register_mem64(struct brw_context
*brw
,
1339 drm_bacon_bo
*bo
, uint32_t reg
, uint32_t offset
);
1340 void brw_load_register_imm32(struct brw_context
*brw
,
1341 uint32_t reg
, uint32_t imm
);
1342 void brw_load_register_imm64(struct brw_context
*brw
,
1343 uint32_t reg
, uint64_t imm
);
1344 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1346 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1348 void brw_store_data_imm32(struct brw_context
*brw
, drm_bacon_bo
*bo
,
1349 uint32_t offset
, uint32_t imm
);
1350 void brw_store_data_imm64(struct brw_context
*brw
, drm_bacon_bo
*bo
,
1351 uint32_t offset
, uint64_t imm
);
1353 /*======================================================================
1354 * intel_tex_validate.c
1356 void brw_validate_textures( struct brw_context
*brw
);
1359 /*======================================================================
1363 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1366 perf_debug(" %s %d->%d\n", name
, a
, b
);
1372 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1374 void brw_get_scratch_bo(struct brw_context
*brw
,
1375 drm_bacon_bo
**scratch_bo
, int size
);
1376 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1377 struct brw_stage_state
*stage_state
,
1378 unsigned per_thread_size
,
1379 unsigned thread_count
);
1380 void brw_init_shader_time(struct brw_context
*brw
);
1381 int brw_get_shader_time_index(struct brw_context
*brw
,
1382 struct gl_program
*prog
,
1383 enum shader_time_shader_type type
,
1385 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1386 void brw_destroy_shader_time(struct brw_context
*brw
);
1390 void brw_upload_urb_fence(struct brw_context
*brw
);
1394 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1397 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1399 /* brw_draw_upload.c */
1400 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1401 const struct gl_vertex_array
*glarray
);
1403 static inline unsigned
1404 brw_get_index_type(GLenum type
)
1406 assert((type
== GL_UNSIGNED_BYTE
)
1407 || (type
== GL_UNSIGNED_SHORT
)
1408 || (type
== GL_UNSIGNED_INT
));
1410 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1411 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1412 * to map to scale factors of 0, 1, and 2, respectively. These scale
1413 * factors are then left-shfited by 8 to be in the correct position in the
1414 * CMD_INDEX_BUFFER packet.
1416 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1417 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1418 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1420 return (type
- 0x1401) << 7;
1423 void brw_prepare_vertices(struct brw_context
*brw
);
1425 /* brw_wm_surface_state.c */
1426 void brw_init_surface_formats(struct brw_context
*brw
);
1427 void brw_create_constant_surface(struct brw_context
*brw
,
1431 uint32_t *out_offset
);
1432 void brw_create_buffer_surface(struct brw_context
*brw
,
1436 uint32_t *out_offset
);
1437 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1439 uint32_t *surf_offset
);
1441 brw_update_sol_surface(struct brw_context
*brw
,
1442 struct gl_buffer_object
*buffer_obj
,
1443 uint32_t *out_offset
, unsigned num_vector_components
,
1444 unsigned stride_dwords
, unsigned offset_dwords
);
1445 void brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1446 struct brw_stage_state
*stage_state
,
1447 struct brw_stage_prog_data
*prog_data
);
1448 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1449 const struct gl_program
*prog
,
1450 struct brw_stage_state
*stage_state
,
1451 struct brw_stage_prog_data
*prog_data
);
1452 void brw_upload_image_surfaces(struct brw_context
*brw
,
1453 const struct gl_program
*prog
,
1454 struct brw_stage_state
*stage_state
,
1455 struct brw_stage_prog_data
*prog_data
);
1457 /* brw_surface_formats.c */
1458 bool brw_render_target_supported(struct brw_context
*brw
,
1459 struct gl_renderbuffer
*rb
);
1460 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1462 /* brw_performance_query.c */
1463 void brw_init_performance_queries(struct brw_context
*brw
);
1465 /* intel_buffer_objects.c */
1466 int brw_bo_map(struct brw_context
*brw
, drm_bacon_bo
*bo
, int write_enable
,
1467 const char *bo_name
);
1468 int brw_bo_map_gtt(struct brw_context
*brw
, drm_bacon_bo
*bo
,
1469 const char *bo_name
);
1471 /* intel_extensions.c */
1472 extern void intelInitExtensions(struct gl_context
*ctx
);
1475 extern int intel_translate_shadow_compare_func(GLenum func
);
1476 extern int intel_translate_compare_func(GLenum func
);
1477 extern int intel_translate_stencil_op(GLenum op
);
1478 extern int intel_translate_logic_op(GLenum opcode
);
1481 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1484 struct gl_transform_feedback_object
*
1485 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1487 brw_delete_transform_feedback(struct gl_context
*ctx
,
1488 struct gl_transform_feedback_object
*obj
);
1490 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1491 struct gl_transform_feedback_object
*obj
);
1493 brw_end_transform_feedback(struct gl_context
*ctx
,
1494 struct gl_transform_feedback_object
*obj
);
1496 brw_pause_transform_feedback(struct gl_context
*ctx
,
1497 struct gl_transform_feedback_object
*obj
);
1499 brw_resume_transform_feedback(struct gl_context
*ctx
,
1500 struct gl_transform_feedback_object
*obj
);
1502 brw_save_primitives_written_counters(struct brw_context
*brw
,
1503 struct brw_transform_feedback_object
*obj
);
1505 brw_compute_xfb_vertices_written(struct brw_context
*brw
,
1506 struct brw_transform_feedback_object
*obj
);
1508 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1509 struct gl_transform_feedback_object
*obj
,
1512 /* gen7_sol_state.c */
1514 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1515 struct gl_transform_feedback_object
*obj
);
1517 gen7_end_transform_feedback(struct gl_context
*ctx
,
1518 struct gl_transform_feedback_object
*obj
);
1520 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1521 struct gl_transform_feedback_object
*obj
);
1523 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1524 struct gl_transform_feedback_object
*obj
);
1528 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1529 struct gl_transform_feedback_object
*obj
);
1531 hsw_end_transform_feedback(struct gl_context
*ctx
,
1532 struct gl_transform_feedback_object
*obj
);
1534 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1535 struct gl_transform_feedback_object
*obj
);
1537 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1538 struct gl_transform_feedback_object
*obj
);
1540 /* brw_blorp_blit.cpp */
1542 brw_blorp_framebuffer(struct brw_context
*brw
,
1543 struct gl_framebuffer
*readFb
,
1544 struct gl_framebuffer
*drawFb
,
1545 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1546 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1547 GLbitfield mask
, GLenum filter
);
1550 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1551 struct gl_renderbuffer
*src_rb
,
1552 struct gl_texture_image
*dst_image
,
1554 int srcX0
, int srcY0
,
1555 int dstX0
, int dstY0
,
1556 int width
, int height
);
1558 /* gen6_multisample_state.c */
1560 gen6_determine_sample_mask(struct brw_context
*brw
);
1563 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1564 unsigned num_samples
);
1566 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1568 gen6_get_sample_position(struct gl_context
*ctx
,
1569 struct gl_framebuffer
*fb
,
1573 gen6_set_sample_maps(struct gl_context
*ctx
);
1575 /* gen8_multisample_state.c */
1576 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1577 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1581 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1582 unsigned hs_size
, unsigned ds_size
,
1583 unsigned gs_size
, unsigned fs_size
);
1586 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1587 bool gs_present
, unsigned gs_size
);
1589 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1590 bool gs_present
, bool tess_present
);
1594 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1596 brw_check_for_reset(struct brw_context
*brw
);
1600 brw_init_compute_functions(struct dd_function_table
*functions
);
1602 /*======================================================================
1603 * Inline conversion functions. These are better-typed than the
1604 * macros used previously:
1606 static inline struct brw_context
*
1607 brw_context( struct gl_context
*ctx
)
1609 return (struct brw_context
*)ctx
;
1612 static inline struct brw_program
*
1613 brw_program(struct gl_program
*p
)
1615 return (struct brw_program
*) p
;
1618 static inline const struct brw_program
*
1619 brw_program_const(const struct gl_program
*p
)
1621 return (const struct brw_program
*) p
;
1625 brw_depth_writes_enabled(const struct brw_context
*brw
)
1627 const struct gl_context
*ctx
= &brw
->ctx
;
1629 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1630 * because it would just overwrite the existing depth value with itself.
1632 * These bonus depth writes not only use bandwidth, but they also can
1633 * prevent early depth processing. For example, if the pixel shader
1634 * discards, the hardware must invoke the to determine whether or not
1635 * to do the depth write. If writes are disabled, we may still be able
1636 * to do the depth test before the shader, and skip the shader execution.
1638 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1639 * a programming note saying to disable depth writes for EQUAL.
1641 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1645 brw_emit_depthbuffer(struct brw_context
*brw
);
1648 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1649 struct intel_mipmap_tree
*depth_mt
,
1650 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1651 uint32_t depth_surface_type
,
1652 struct intel_mipmap_tree
*stencil_mt
,
1653 bool hiz
, bool separate_stencil
,
1654 uint32_t width
, uint32_t height
,
1655 uint32_t tile_x
, uint32_t tile_y
);
1658 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1659 struct intel_mipmap_tree
*depth_mt
,
1660 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1661 uint32_t depth_surface_type
,
1662 struct intel_mipmap_tree
*stencil_mt
,
1663 bool hiz
, bool separate_stencil
,
1664 uint32_t width
, uint32_t height
,
1665 uint32_t tile_x
, uint32_t tile_y
);
1668 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1669 struct intel_mipmap_tree
*depth_mt
,
1670 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1671 uint32_t depth_surface_type
,
1672 struct intel_mipmap_tree
*stencil_mt
,
1673 bool hiz
, bool separate_stencil
,
1674 uint32_t width
, uint32_t height
,
1675 uint32_t tile_x
, uint32_t tile_y
);
1677 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1678 struct intel_mipmap_tree
*depth_mt
,
1679 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1680 uint32_t depth_surface_type
,
1681 struct intel_mipmap_tree
*stencil_mt
,
1682 bool hiz
, bool separate_stencil
,
1683 uint32_t width
, uint32_t height
,
1684 uint32_t tile_x
, uint32_t tile_y
);
1686 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1687 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
);
1689 uint32_t get_hw_prim_for_gl_prim(int mode
);
1692 gen6_upload_push_constants(struct brw_context
*brw
,
1693 const struct gl_program
*prog
,
1694 const struct brw_stage_prog_data
*prog_data
,
1695 struct brw_stage_state
*stage_state
);
1698 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1699 const struct intel_mipmap_tree
*mt
);
1701 /* brw_pipe_control.c */
1702 int brw_init_pipe_control(struct brw_context
*brw
,
1703 const struct gen_device_info
*info
);
1704 void brw_fini_pipe_control(struct brw_context
*brw
);
1706 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1707 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1708 drm_bacon_bo
*bo
, uint32_t offset
,
1709 uint32_t imm_lower
, uint32_t imm_upper
);
1710 void brw_emit_mi_flush(struct brw_context
*brw
);
1711 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1712 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1713 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1714 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1716 /* brw_queryformat.c */
1717 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1718 GLenum internalFormat
, GLenum pname
,