2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
47 * URB - uniform resource buffer. A mid-sized buffer which is
48 * partitioned between the fixed function units and used for passing
49 * values (vertices, primitives, constants) between them.
51 * CURBE - constant URB entry. An urb region (entry) used to hold
52 * constant values which the fixed function units can be instructed to
53 * preload into the GRF when spawning a thread.
55 * VUE - vertex URB entry. An urb entry holding a vertex and usually
56 * a vertex header. The header contains control information and
57 * things like primitive type, Begin/end flags and clip codes.
59 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
60 * unit holding rasterization and interpolation parameters.
62 * GRF - general register file. One of several register files
63 * addressable by programmed threads. The inputs (r0, payload, curbe,
64 * urb) of the thread are preloaded to this area before the thread is
65 * spawned. The registers are individually 8 dwords wide and suitable
66 * for general usage. Registers holding thread input values are not
67 * special and may be overwritten.
69 * MRF - message register file. Threads communicate (and terminate)
70 * by sending messages. Message parameters are placed in contiguous
71 * MRF registers. All program output is via these messages. URB
72 * entries are populated by sending a message to the shared URB
73 * function containing the new data, together with a control word,
74 * often an unmodified copy of R0.
76 * R0 - GRF register 0. Typically holds control information used when
77 * sending messages to other threads.
79 * EU or GEN4 EU: The name of the programmable subsystem of the
80 * i965 hardware. Threads are executed by the EU, the registers
81 * described above are part of the EU architecture.
83 * Fixed function units:
85 * CS - Command streamer. Notional first unit, little software
86 * interaction. Holds the URB entries used for constant data, ie the
89 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
90 * this unit is responsible for pulling vertices out of vertex buffers
91 * in vram and injecting them into the processing pipe as VUEs. If
92 * enabled, it first passes them to a VS thread which is a good place
93 * for the driver to implement any active vertex shader.
95 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
96 * enabled, incoming strips etc are passed to GS threads in individual
97 * line/triangle/point units. The GS thread may perform arbitary
98 * computation and emit whatever primtives with whatever vertices it
99 * chooses. This makes GS an excellent place to implement GL's
100 * unfilled polygon modes, though of course it is capable of much
101 * more. Additionally, GS is used to translate away primitives not
102 * handled by latter units, including Quads and Lineloops.
104 * CS - Clipper. Mesa's clipping algorithms are imported to run on
105 * this unit. The fixed function part performs cliptesting against
106 * the 6 fixed clipplanes and makes descisions on whether or not the
107 * incoming primitive needs to be passed to a thread for clipping.
108 * User clip planes are handled via cooperation with the VS thread.
110 * SF - Strips Fans or Setup: Triangles are prepared for
111 * rasterization. Interpolation coefficients are calculated.
112 * Flatshading and two-side lighting usually performed here.
114 * WM - Windower. Interpolation of vertex attributes performed here.
115 * Fragment shader implemented here. SIMD aspects of EU taken full
116 * advantage of, as pixels are processed in blocks of 16.
118 * CC - Color Calculator. No EU threads associated with this unit.
119 * Handles blending and (presumably) depth and stencil testing.
123 #define BRW_MAX_CURBE (32*16)
126 struct brw_instruction
;
127 struct brw_vs_prog_key
;
128 struct brw_wm_prog_key
;
129 struct brw_wm_prog_data
;
133 BRW_STATE_FRAGMENT_PROGRAM
,
134 BRW_STATE_VERTEX_PROGRAM
,
135 BRW_STATE_CURBE_OFFSETS
,
136 BRW_STATE_REDUCED_PRIMITIVE
,
141 BRW_STATE_VS_BINDING_TABLE
,
142 BRW_STATE_GS_BINDING_TABLE
,
143 BRW_STATE_PS_BINDING_TABLE
,
147 BRW_STATE_INDEX_BUFFER
,
148 BRW_STATE_VS_CONSTBUF
,
149 BRW_STATE_PROGRAM_CACHE
,
150 BRW_STATE_STATE_BASE_ADDRESS
,
151 BRW_STATE_VUE_MAP_GEOM_OUT
,
152 BRW_STATE_TRANSFORM_FEEDBACK
,
153 BRW_STATE_RASTERIZER_DISCARD
,
155 BRW_STATE_UNIFORM_BUFFER
,
156 BRW_STATE_META_IN_PROGRESS
,
157 BRW_STATE_INTERPOLATION_MAP
,
161 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
162 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
163 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
164 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
165 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
166 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
167 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
168 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
169 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
170 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
171 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
172 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
173 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
174 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
176 * Used for any batch entry with a relocated pointer that will be used
177 * by any 3D rendering.
179 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
180 /** \see brw.state.depth_region */
181 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
182 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
183 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
184 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
185 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
186 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
187 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
188 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
189 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
190 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
191 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
193 struct brw_state_flags
{
194 /** State update flags signalled by mesa internals */
197 * State update flags signalled as the result of brw_tracked_state updates
200 /** State update flags signalled by brw_state_cache.c searches */
204 #define AUB_TRACE_TYPE_MASK 0x0000ff00
205 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
206 #define AUB_TRACE_TYPE_BATCH (1 << 8)
207 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
208 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
209 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
210 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
211 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
212 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
213 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
214 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
215 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
216 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
219 * state_struct_type enum values are encoded with the top 16 bits representing
220 * the type to be delivered to the .aub file, and the bottom 16 bits
221 * representing the subtype. This macro performs the encoding.
223 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
225 enum state_struct_type
{
226 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
227 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
228 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
229 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
230 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
231 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
232 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
233 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
234 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
235 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
236 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
237 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
238 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
240 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
241 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
242 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
244 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
245 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
246 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
247 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
248 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
252 * Decode a state_struct_type value to determine the type that should be
253 * stored in the .aub file.
255 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
257 return (ss_type
& 0xFFFF0000) >> 16;
261 * Decode a state_struct_type value to determine the subtype that should be
262 * stored in the .aub file.
264 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
266 return ss_type
& 0xFFFF;
269 /** Subclass of Mesa vertex program */
270 struct brw_vertex_program
{
271 struct gl_vertex_program program
;
276 /** Subclass of Mesa fragment program */
277 struct brw_fragment_program
{
278 struct gl_fragment_program program
;
279 GLuint id
; /**< serial no. to identify frag progs, never re-used */
283 struct gl_shader base
;
287 /** Shader IR transformed for native compile, at link time. */
288 struct exec_list
*ir
;
291 /* Data about a particular attempt to compile a program. Note that
292 * there can be many of these, each in a different GL state
293 * corresponding to a different brw_wm_prog_key struct, with different
296 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
299 struct brw_wm_prog_data
{
300 GLuint curb_read_length
;
301 GLuint urb_read_length
;
303 GLuint first_curbe_grf
;
304 GLuint first_curbe_grf_16
;
306 GLuint reg_blocks_16
;
307 GLuint total_scratch
;
309 unsigned binding_table_size
;
311 GLuint nr_params
; /**< number of float params/constants */
312 GLuint nr_pull_params
;
315 uint32_t prog_offset_16
;
318 * Mask of which interpolation modes are required by the fragment shader.
319 * Used in hardware setup on gen6+.
321 uint32_t barycentric_interp_modes
;
323 /* Pointers to tracked values (only valid once
324 * _mesa_load_state_parameters has been called at runtime).
326 * These must be the last fields of the struct (see
327 * brw_wm_prog_data_compare()).
330 const float **pull_param
;
334 * Enum representing the i965-specific vertex results that don't correspond
335 * exactly to any element of gl_varying_slot. The values of this enum are
336 * assigned such that they don't conflict with gl_varying_slot.
340 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
341 BRW_VARYING_SLOT_PAD
,
343 * Technically this is not a varying but just a placeholder that
344 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
345 * builtin variable to be compiled correctly. see compile_sf_prog() for
348 BRW_VARYING_SLOT_PNTC
,
349 BRW_VARYING_SLOT_COUNT
354 * Data structure recording the relationship between the gl_varying_slot enum
355 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
356 * single octaword within the VUE (128 bits).
358 * Note that each BRW register contains 256 bits (2 octawords), so when
359 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
360 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
361 * in a vertex shader), each register corresponds to a single VUE slot, since
362 * it contains data for two separate vertices.
366 * Bitfield representing all varying slots that are (a) stored in this VUE
367 * map, and (b) actually written by the shader. Does not include any of
368 * the additional varying slots defined in brw_varying_slot.
370 GLbitfield64 slots_valid
;
373 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
374 * not stored in a slot (because they are not written, or because
375 * additional processing is applied before storing them in the VUE), the
378 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
381 * Map from VUE slot to gl_varying_slot value. For slots that do not
382 * directly correspond to a gl_varying_slot, the value comes from
385 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
386 * simplifies code that uses the value stored in slot_to_varying to
387 * create a bit mask).
389 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
392 * Total number of VUE slots in use
398 * Convert a VUE slot number into a byte offset within the VUE.
400 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
406 * Convert a vertex output (brw_varying_slot) into a byte offset within the
409 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
412 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
415 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
416 GLbitfield64 slots_valid
, bool userclip_active
);
420 * Mapping of VUE map slots to interpolation modes.
422 struct interpolation_mode_map
{
423 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
426 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
428 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
429 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
435 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
437 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
438 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
445 struct brw_sf_prog_data
{
446 GLuint urb_read_length
;
449 /* Each vertex may have upto 12 attributes, 4 components each,
450 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
453 * Actually we use 4 for each, so call it 12 rows.
455 GLuint urb_entry_size
;
458 struct brw_clip_prog_data
{
459 GLuint curb_read_length
; /* user planes? */
461 GLuint urb_read_length
;
465 struct brw_gs_prog_data
{
466 GLuint urb_read_length
;
470 * Gen6 transform feedback: Amount by which the streaming vertex buffer
471 * indices should be incremented each time the GS is invoked.
473 unsigned svbi_postincrement_value
;
477 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
480 struct brw_vec4_prog_data
{
481 struct brw_vue_map vue_map
;
483 GLuint curb_read_length
;
484 GLuint urb_read_length
;
486 GLuint nr_params
; /**< number of float params/constants */
487 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
488 GLuint total_scratch
;
490 /* Used for calculating urb partitions. In the VS, this is the size of the
491 * URB entry used for both input and output to the thread. In the GS, this
492 * is the size of the URB entry used for output.
494 GLuint urb_entry_size
;
498 /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
500 const float **pull_param
;
504 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
507 struct brw_vs_prog_data
{
508 struct brw_vec4_prog_data base
;
510 GLbitfield64 inputs_read
;
515 /** Number of texture sampler units */
516 #define BRW_MAX_TEX_UNIT 16
518 /** Max number of render targets in a shader */
519 #define BRW_MAX_DRAW_BUFFERS 8
522 * Max number of binding table entries used for stream output.
524 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
525 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
527 * On Gen6, the size of transform feedback data is limited not by the number
528 * of components but by the number of binding table entries we set aside. We
529 * use one binding table entry for a float, one entry for a vector, and one
530 * entry per matrix column. Since the only way we can communicate our
531 * transform feedback capabilities to the client is via
532 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
533 * worst case, in which all the varyings are floats, so we use up one binding
534 * table entry per component. Therefore we need to set aside at least 64
535 * binding table entries for use by transform feedback.
537 * Note: since we don't currently pack varyings, it is currently impossible
538 * for the client to actually use up all of these binding table entries--if
539 * all of their varyings were floats, they would run out of varying slots and
540 * fail to link. But that's a bug, so it seems prudent to go ahead and
541 * allocate the number of binding table entries we will need once the bug is
544 #define BRW_MAX_SOL_BINDINGS 64
546 /** Maximum number of actual buffers used for stream output */
547 #define BRW_MAX_SOL_BUFFERS 4
549 #define BRW_MAX_WM_UBOS 12
550 #define BRW_MAX_VS_UBOS 12
553 * Helpers to create Surface Binding Table indexes for draw buffers,
554 * textures, and constant buffers.
556 * Shader threads access surfaces via numeric handles, rather than directly
557 * using pointers. The binding table maps these numeric handles to the
558 * address of the actual buffer.
560 * For example, a shader might ask to sample from "surface 7." In this case,
561 * bind[7] would contain a pointer to a texture.
563 * Currently, our WM binding tables are (arbitrarily) programmed as follows:
565 * +-------------------------------+
566 * | 0 | Draw buffer 0 |
569 * | 7 | Draw buffer 7 |
570 * |-----|-------------------------|
571 * | 8 | WM Pull Constant Buffer |
572 * |-----|-------------------------|
576 * | 24 | Texture 15 |
577 * |-----|-------------------------|
582 * +-------------------------------+
584 * Our VS binding tables are programmed as follows:
586 * +-----+-------------------------+
587 * | 0 | VS Pull Constant Buffer |
588 * +-----+-------------------------+
592 * | 16 | Texture 15 |
593 * +-----+-------------------------+
598 * +-------------------------------+
600 * Our (gen6) GS binding tables are programmed as follows:
602 * +-----+-------------------------+
603 * | 0 | SOL Binding 0 |
606 * | 63 | SOL Binding 63 |
607 * +-----+-------------------------+
609 #define SURF_INDEX_DRAW(d) (d)
610 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
611 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
612 #define SURF_INDEX_WM_UBO(u) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)
613 #define SURF_INDEX_WM_SHADER_TIME (SURF_INDEX_WM_UBO(12))
614 /** Maximum size of the binding table. */
615 #define BRW_MAX_WM_SURFACES (SURF_INDEX_WM_SHADER_TIME + 1)
617 #define SURF_INDEX_VERT_CONST_BUFFER (0)
618 #define SURF_INDEX_VS_TEXTURE(t) (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t))
619 #define SURF_INDEX_VS_UBO(u) (SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT) + u)
620 #define SURF_INDEX_VS_SHADER_TIME (SURF_INDEX_VS_UBO(12))
621 #define BRW_MAX_VS_SURFACES (SURF_INDEX_VS_SHADER_TIME + 1)
623 #define SURF_INDEX_SOL_BINDING(t) ((t))
624 #define BRW_MAX_GS_SURFACES SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
627 * Stride in bytes between shader_time entries.
629 * We separate entries by a cacheline to reduce traffic between EUs writing to
632 #define SHADER_TIME_STRIDE 64
639 BRW_BLORP_CONST_COLOR_PROG
,
644 BRW_SF_UNIT
, /* scissor state on gen6 */
656 struct brw_cache_item
{
658 * Effectively part of the key, cache_id identifies what kind of state
659 * buffer is involved, and also which brw->state.dirty.cache flag should
660 * be set when this cache item is chosen.
662 enum brw_cache_id cache_id
;
663 /** 32-bit hash of the key data */
665 GLuint key_size
; /* for variable-sized keys */
672 struct brw_cache_item
*next
;
676 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
,
677 int aux_size
, const void *key
);
678 typedef void (*cache_aux_free_func
)(const void *aux
);
681 struct brw_context
*brw
;
683 struct brw_cache_item
**items
;
685 GLuint size
, n_items
;
687 uint32_t next_offset
;
691 * Optional functions used in determining whether the prog_data for a new
692 * cache item matches an existing cache item (in case there's relevant data
693 * outside of the prog_data). If NULL, a plain memcmp is done.
695 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
696 /** Optional functions for freeing other pointers attached to a prog_data. */
697 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
701 /* Considered adding a member to this struct to document which flags
702 * an update might raise so that ordering of the state atoms can be
703 * checked or derived at runtime. Dropped the idea in favor of having
704 * a debug mode where the state is monitored for flags which are
705 * raised that have already been tested against.
707 struct brw_tracked_state
{
708 struct brw_state_flags dirty
;
709 void (*emit
)( struct brw_context
*brw
);
712 enum shader_time_shader_type
{
725 /* Flags for brw->state.cache.
727 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
728 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
729 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
730 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
731 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
732 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
733 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
734 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
735 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
736 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
737 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
738 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
739 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
740 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
741 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
743 struct brw_cached_batch_item
{
744 struct header
*header
;
746 struct brw_cached_batch_item
*next
;
751 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
752 * be easier if C allowed arrays of packed elements?
754 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
756 struct brw_vertex_buffer
{
757 /** Buffer object containing the uploaded vertex data */
760 /** Byte stride between elements in the uploaded array */
764 struct brw_vertex_element
{
765 const struct gl_client_array
*glarray
;
769 /** The corresponding Mesa vertex attribute */
770 gl_vert_attrib attrib
;
771 /** Offset of the first element within the buffer object */
775 struct brw_query_object
{
776 struct gl_query_object Base
;
778 /** Last query BO associated with this query. */
781 /** Last index in bo with query data for this object. */
787 * brw_context is derived from gl_context.
791 struct gl_context ctx
; /**< base class, must be first field */
795 void (*destroy
) (struct brw_context
* brw
);
796 void (*finish_batch
) (struct brw_context
* brw
);
797 void (*new_batch
) (struct brw_context
* brw
);
799 void (*update_texture_surface
)(struct gl_context
*ctx
,
801 uint32_t *binding_table
,
802 unsigned surf_index
);
803 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
804 struct gl_renderbuffer
*rb
,
807 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
809 void (*create_constant_surface
)(struct brw_context
*brw
,
813 uint32_t *out_offset
,
816 /** Upload a SAMPLER_STATE table. */
817 void (*upload_sampler_state_table
)(struct brw_context
*brw
,
818 struct gl_program
*prog
,
819 uint32_t sampler_count
,
820 uint32_t *sst_offset
,
821 uint32_t *sdc_offset
);
824 * Send the appropriate state packets to configure depth, stencil, and
825 * HiZ buffers (i965+ only)
827 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
828 struct intel_mipmap_tree
*depth_mt
,
829 uint32_t depth_offset
,
830 uint32_t depthbuffer_format
,
831 uint32_t depth_surface_type
,
832 struct intel_mipmap_tree
*stencil_mt
,
833 bool hiz
, bool separate_stencil
,
834 uint32_t width
, uint32_t height
,
835 uint32_t tile_x
, uint32_t tile_y
);
841 drm_intel_context
*hw_ctx
;
843 struct intel_batchbuffer batch
;
850 uint32_t buffer_offset
;
855 * Set if rendering has occured to the drawable's front buffer.
857 * This is used in the DRI2 case to detect that glFlush should also copy
858 * the contents of the fake front buffer to the real front buffer.
860 bool front_buffer_dirty
;
863 * Track whether front-buffer rendering is currently enabled
865 * A separate flag is used to track this in order to support MRT more
868 bool is_front_buffer_rendering
;
871 * Track whether front-buffer is the current read target.
873 * This is closely associated with is_front_buffer_rendering, but may
874 * be set separately. The DRI2 fake front buffer must be referenced
877 bool is_front_buffer_reading
;
879 /** Framerate throttling: @{ */
880 drm_intel_bo
*first_post_swapbuffers_batch
;
891 bool always_flush_batch
;
892 bool always_flush_cache
;
893 bool disable_throttling
;
896 driOptionCache optionCache
;
899 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
901 GLenum reduced_primitive
;
904 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
905 * variable is set, this is the flag indicating to do expensive work that
906 * might lead to a perf_debug() call.
910 uint32_t max_gtt_map_object_size
;
912 bool emit_state_always
;
922 bool has_separate_stencil
;
923 bool must_use_separate_stencil
;
926 bool has_surface_tile_offset
;
928 bool has_negative_rhw_bug
;
929 bool has_aa_line_parameters
;
933 * Some versions of Gen hardware don't do centroid interpolation correctly
934 * on unlit pixels, causing incorrect values for derivatives near triangle
935 * edges. Enabling this flag causes the fragment shader to use
936 * non-centroid interpolation for unlit pixels, at the expense of two extra
937 * fragment shader instructions.
939 bool needs_unlit_centroid_workaround
;
943 struct brw_state_flags dirty
;
946 struct brw_cache cache
;
947 struct brw_cached_batch_item
*cached_batch_items
;
949 /* Whether a meta-operation is in progress. */
950 bool meta_in_progress
;
953 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
954 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
956 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
960 /* Summary of size and varying of active arrays, so we can check
961 * for changes to this state:
963 unsigned int min_index
, max_index
;
965 /* Offset from start of vertex buffer so we can avoid redefining
966 * the same VB packed over and over again.
968 unsigned int start_vertex_bias
;
973 * Index buffer for this draw_prims call.
975 * Updates are signaled by BRW_NEW_INDICES.
977 const struct _mesa_index_buffer
*ib
;
979 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
983 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
984 * avoid re-uploading the IB packet over and over if we're actually
985 * referencing the same index buffer.
987 unsigned int start_vertex_offset
;
990 /* Active vertex program:
992 const struct gl_vertex_program
*vertex_program
;
993 const struct gl_fragment_program
*fragment_program
;
995 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
996 uint32_t CMD_VF_STATISTICS
;
997 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
998 uint32_t CMD_PIPELINE_SELECT
;
1001 * Platform specific constants containing the maximum number of threads
1002 * for each pipeline stage.
1008 /* BRW_NEW_URB_ALLOCATIONS:
1011 GLuint vsize
; /* vertex size plus header in urb registers */
1012 GLuint csize
; /* constant buffer size in urb registers */
1013 GLuint sfsize
; /* setup data size in urb registers */
1017 GLuint max_vs_entries
; /* Maximum number of VS entries */
1018 GLuint max_gs_entries
; /* Maximum number of GS entries */
1020 GLuint nr_vs_entries
;
1021 GLuint nr_gs_entries
;
1022 GLuint nr_clip_entries
;
1023 GLuint nr_sf_entries
;
1024 GLuint nr_cs_entries
;
1031 GLuint size
; /* Hardware URB size, in KB. */
1033 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1034 * URB space for the GS.
1036 bool gen6_gs_previously_active
;
1040 /* BRW_NEW_CURBE_OFFSETS:
1043 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1044 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1051 drm_intel_bo
*curbe_bo
;
1052 /** Offset within curbe_bo of space for current curbe entry */
1053 GLuint curbe_offset
;
1054 /** Offset within curbe_bo of space for next curbe entry */
1055 GLuint curbe_next_offset
;
1058 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
1059 * in brw_curbe.c with the same set of constant data to be uploaded,
1060 * so we'd rather not upload new constants in that case (it can cause
1061 * a pipeline bubble since only up to 4 can be pipelined at a time).
1065 * Allocation for where to calculate the next set of CURBEs.
1066 * It's a hot enough path that malloc/free of that data matters.
1073 * Layout of vertex data exiting the geometry portion of the pipleine.
1074 * This comes from the geometry shader if one exists, otherwise from the
1077 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1079 struct brw_vue_map vue_map_geom_out
;
1082 struct brw_vs_prog_data
*prog_data
;
1084 drm_intel_bo
*scratch_bo
;
1085 drm_intel_bo
*const_bo
;
1086 /** Offset in the program cache to the VS program */
1087 uint32_t prog_offset
;
1088 uint32_t state_offset
;
1090 uint32_t push_const_offset
; /* Offset in the batchbuffer */
1091 int push_const_size
; /* in 256-bit register increments */
1093 /** @{ register allocator */
1095 struct ra_regs
*regs
;
1098 * Array of the ra classes for the unaligned contiguous register
1104 * Mapping for register-allocated objects in *regs to the first
1105 * GRF for that object.
1107 uint8_t *ra_reg_to_grf
;
1110 uint32_t bind_bo_offset
;
1111 uint32_t surf_offset
[BRW_MAX_VS_SURFACES
];
1113 /** SAMPLER_STATE count and table offset */
1114 uint32_t sampler_count
;
1115 uint32_t sampler_offset
;
1117 /** Offsets in the batch to sampler default colors (texture border color)
1119 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
1123 struct brw_gs_prog_data
*prog_data
;
1126 /** Offset in the program cache to the CLIP program pre-gen6 */
1127 uint32_t prog_offset
;
1128 uint32_t state_offset
;
1130 uint32_t bind_bo_offset
;
1131 uint32_t surf_offset
[BRW_MAX_GS_SURFACES
];
1135 struct brw_clip_prog_data
*prog_data
;
1137 /** Offset in the program cache to the CLIP program pre-gen6 */
1138 uint32_t prog_offset
;
1140 /* Offset in the batch to the CLIP state on pre-gen6. */
1141 uint32_t state_offset
;
1143 /* As of gen6, this is the offset in the batch to the CLIP VP,
1151 struct brw_sf_prog_data
*prog_data
;
1153 /** Offset in the program cache to the CLIP program pre-gen6 */
1154 uint32_t prog_offset
;
1155 uint32_t state_offset
;
1160 struct brw_wm_prog_data
*prog_data
;
1164 drm_intel_bo
*scratch_bo
;
1167 * Buffer object used in place of multisampled null render targets on
1168 * Gen6. See brw_update_null_renderbuffer_surface().
1170 drm_intel_bo
*multisampled_null_render_target_bo
;
1172 /** Offset in the program cache to the WM program */
1173 uint32_t prog_offset
;
1175 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
1177 drm_intel_bo
*const_bo
; /* pull constant buffer. */
1179 * This is offset in the batch to the push constants on gen6.
1181 * Pre-gen6, push constants live in the CURBE.
1183 uint32_t push_const_offset
;
1185 /** Binding table of pointers to surf_bo entries */
1186 uint32_t bind_bo_offset
;
1187 uint32_t surf_offset
[BRW_MAX_WM_SURFACES
];
1189 /** SAMPLER_STATE count and table offset */
1190 uint32_t sampler_count
;
1191 uint32_t sampler_offset
;
1193 /** Offsets in the batch to sampler default colors (texture border color)
1195 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
1198 struct ra_regs
*regs
;
1200 /** Array of the ra classes for the unaligned contiguous
1201 * register block sizes used.
1206 * Mapping for register-allocated objects in *regs to the first
1207 * GRF for that object.
1209 uint8_t *ra_reg_to_grf
;
1212 * ra class for the aligned pairs we use for PLN, which doesn't
1213 * appear in *classes.
1215 int aligned_pairs_class
;
1221 uint32_t state_offset
;
1222 uint32_t blend_state_offset
;
1223 uint32_t depth_stencil_state_offset
;
1228 struct brw_query_object
*obj
;
1233 const struct brw_tracked_state
**atoms
;
1235 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1239 enum state_struct_type type
;
1240 } *state_batch_list
;
1241 int state_batch_count
;
1243 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1244 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1246 /* Interpolation modes, one byte per vue slot.
1247 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1249 struct interpolation_mode_map interpolation_mode
;
1251 /* PrimitiveRestart */
1254 bool enable_cut_index
;
1257 /** Computed depth/stencil/hiz state from the current attached
1258 * renderbuffers, valid only during the drawing state upload loop after
1259 * brw_workaround_depthstencil_alignment().
1262 struct intel_mipmap_tree
*depth_mt
;
1263 struct intel_mipmap_tree
*stencil_mt
;
1265 /* Inter-tile (page-aligned) byte offsets. */
1266 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1267 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1268 uint32_t tile_x
, tile_y
;
1271 uint32_t num_instances
;
1276 struct gl_shader_program
**shader_programs
;
1277 struct gl_program
**programs
;
1278 enum shader_time_shader_type
*types
;
1279 uint64_t *cumulative
;
1285 __DRIcontext
*driContext
;
1286 struct intel_screen
*intelScreen
;
1287 void (*saved_viewport
)(struct gl_context
*ctx
,
1288 GLint x
, GLint y
, GLsizei width
, GLsizei height
);
1291 /*======================================================================
1294 void brwInitVtbl( struct brw_context
*brw
);
1296 /*======================================================================
1299 bool brwCreateContext(int api
,
1300 const struct gl_config
*mesaVis
,
1301 __DRIcontext
*driContextPriv
,
1302 unsigned major_version
,
1303 unsigned minor_version
,
1306 void *sharedContextPrivate
);
1308 /*======================================================================
1311 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1312 uint32_t depth_level
,
1313 uint32_t depth_layer
,
1314 struct intel_mipmap_tree
*stencil_mt
,
1315 uint32_t *out_tile_mask_x
,
1316 uint32_t *out_tile_mask_y
);
1317 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1318 GLbitfield clear_mask
);
1320 /* brw_object_purgeable.c */
1321 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1323 /*======================================================================
1326 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1327 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1328 void brw_emit_query_begin(struct brw_context
*brw
);
1329 void brw_emit_query_end(struct brw_context
*brw
);
1331 /** gen6_queryobj.c */
1332 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1334 /*======================================================================
1337 void brw_debug_batch(struct brw_context
*brw
);
1338 void brw_annotate_aub(struct brw_context
*brw
);
1340 /*======================================================================
1343 void brw_validate_textures( struct brw_context
*brw
);
1346 /*======================================================================
1349 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1351 int brw_get_scratch_size(int size
);
1352 void brw_get_scratch_bo(struct brw_context
*brw
,
1353 drm_intel_bo
**scratch_bo
, int size
);
1354 void brw_init_shader_time(struct brw_context
*brw
);
1355 int brw_get_shader_time_index(struct brw_context
*brw
,
1356 struct gl_shader_program
*shader_prog
,
1357 struct gl_program
*prog
,
1358 enum shader_time_shader_type type
);
1359 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1360 void brw_destroy_shader_time(struct brw_context
*brw
);
1364 void brw_upload_urb_fence(struct brw_context
*brw
);
1368 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1370 /* brw_fs_reg_allocate.cpp
1372 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1375 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1378 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1380 /* brw_draw_upload.c */
1381 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1382 const struct gl_client_array
*glarray
);
1383 unsigned brw_get_index_type(GLenum type
);
1385 /* brw_wm_surface_state.c */
1386 void brw_init_surface_formats(struct brw_context
*brw
);
1388 brw_update_sol_surface(struct brw_context
*brw
,
1389 struct gl_buffer_object
*buffer_obj
,
1390 uint32_t *out_offset
, unsigned num_vector_components
,
1391 unsigned stride_dwords
, unsigned offset_dwords
);
1392 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1393 struct gl_shader
*shader
,
1394 uint32_t *surf_offsets
);
1396 /* brw_surface_formats.c */
1397 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, gl_format format
);
1398 bool brw_render_target_supported(struct brw_context
*brw
,
1399 struct gl_renderbuffer
*rb
);
1403 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1404 struct gl_transform_feedback_object
*obj
);
1406 brw_end_transform_feedback(struct gl_context
*ctx
,
1407 struct gl_transform_feedback_object
*obj
);
1409 /* gen7_sol_state.c */
1411 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1412 struct gl_transform_feedback_object
*obj
);
1414 gen7_end_transform_feedback(struct gl_context
*ctx
,
1415 struct gl_transform_feedback_object
*obj
);
1417 /* brw_blorp_blit.cpp */
1419 brw_blorp_framebuffer(struct brw_context
*brw
,
1420 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1421 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1422 GLbitfield mask
, GLenum filter
);
1425 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1426 struct gl_renderbuffer
*src_rb
,
1427 struct gl_texture_image
*dst_image
,
1429 int srcX0
, int srcY0
,
1430 int dstX0
, int dstY0
,
1431 int width
, int height
);
1433 /* gen6_multisample_state.c */
1435 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1436 unsigned num_samples
);
1438 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
,
1439 unsigned num_samples
, float coverage
,
1440 bool coverage_invert
, unsigned sample_mask
);
1442 gen6_get_sample_position(struct gl_context
*ctx
,
1443 struct gl_framebuffer
*fb
,
1449 gen7_allocate_push_constants(struct brw_context
*brw
);
1452 gen7_emit_urb_state(struct brw_context
*brw
, GLuint nr_vs_entries
,
1453 GLuint vs_size
, GLuint vs_start
);
1457 /*======================================================================
1458 * Inline conversion functions. These are better-typed than the
1459 * macros used previously:
1461 static INLINE
struct brw_context
*
1462 brw_context( struct gl_context
*ctx
)
1464 return (struct brw_context
*)ctx
;
1467 static INLINE
struct brw_vertex_program
*
1468 brw_vertex_program(struct gl_vertex_program
*p
)
1470 return (struct brw_vertex_program
*) p
;
1473 static INLINE
const struct brw_vertex_program
*
1474 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1476 return (const struct brw_vertex_program
*) p
;
1479 static INLINE
struct brw_fragment_program
*
1480 brw_fragment_program(struct gl_fragment_program
*p
)
1482 return (struct brw_fragment_program
*) p
;
1485 static INLINE
const struct brw_fragment_program
*
1486 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1488 return (const struct brw_fragment_program
*) p
;
1492 * Pre-gen6, the register file of the EUs was shared between threads,
1493 * and each thread used some subset allocated on a 16-register block
1494 * granularity. The unit states wanted these block counts.
1497 brw_register_blocks(int reg_count
)
1499 return ALIGN(reg_count
, 16) / 16 - 1;
1502 static inline uint32_t
1503 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1504 uint32_t prog_offset
)
1506 if (brw
->gen
>= 5) {
1507 /* Using state base address. */
1511 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1515 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1517 return brw
->cache
.bo
->offset
+ prog_offset
;
1520 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1521 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1522 struct exec_list
*instructions
);
1524 struct opcode_desc
{
1530 extern const struct opcode_desc opcode_descs
[128];
1533 brw_emit_depthbuffer(struct brw_context
*brw
);
1536 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1537 struct intel_mipmap_tree
*depth_mt
,
1538 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1539 uint32_t depth_surface_type
,
1540 struct intel_mipmap_tree
*stencil_mt
,
1541 bool hiz
, bool separate_stencil
,
1542 uint32_t width
, uint32_t height
,
1543 uint32_t tile_x
, uint32_t tile_y
);
1546 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1547 struct intel_mipmap_tree
*depth_mt
,
1548 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1549 uint32_t depth_surface_type
,
1550 struct intel_mipmap_tree
*stencil_mt
,
1551 bool hiz
, bool separate_stencil
,
1552 uint32_t width
, uint32_t height
,
1553 uint32_t tile_x
, uint32_t tile_y
);