2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "compiler/brw_compiler.h"
41 #include "intel_aub.h"
44 #include "blorp/blorp.h"
46 #include <intel_bufmgr.h>
48 #include "common/gen_debug.h"
49 #include "intel_screen.h"
50 #include "intel_tex_obj.h"
51 #include "intel_resolve_map.h"
58 * URB - uniform resource buffer. A mid-sized buffer which is
59 * partitioned between the fixed function units and used for passing
60 * values (vertices, primitives, constants) between them.
62 * CURBE - constant URB entry. An urb region (entry) used to hold
63 * constant values which the fixed function units can be instructed to
64 * preload into the GRF when spawning a thread.
66 * VUE - vertex URB entry. An urb entry holding a vertex and usually
67 * a vertex header. The header contains control information and
68 * things like primitive type, Begin/end flags and clip codes.
70 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
71 * unit holding rasterization and interpolation parameters.
73 * GRF - general register file. One of several register files
74 * addressable by programmed threads. The inputs (r0, payload, curbe,
75 * urb) of the thread are preloaded to this area before the thread is
76 * spawned. The registers are individually 8 dwords wide and suitable
77 * for general usage. Registers holding thread input values are not
78 * special and may be overwritten.
80 * MRF - message register file. Threads communicate (and terminate)
81 * by sending messages. Message parameters are placed in contiguous
82 * MRF registers. All program output is via these messages. URB
83 * entries are populated by sending a message to the shared URB
84 * function containing the new data, together with a control word,
85 * often an unmodified copy of R0.
87 * R0 - GRF register 0. Typically holds control information used when
88 * sending messages to other threads.
90 * EU or GEN4 EU: The name of the programmable subsystem of the
91 * i965 hardware. Threads are executed by the EU, the registers
92 * described above are part of the EU architecture.
94 * Fixed function units:
96 * CS - Command streamer. Notional first unit, little software
97 * interaction. Holds the URB entries used for constant data, ie the
100 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
101 * this unit is responsible for pulling vertices out of vertex buffers
102 * in vram and injecting them into the processing pipe as VUEs. If
103 * enabled, it first passes them to a VS thread which is a good place
104 * for the driver to implement any active vertex shader.
106 * HS - Hull Shader (Tessellation Control Shader)
108 * TE - Tessellation Engine (Tessellation Primitive Generation)
110 * DS - Domain Shader (Tessellation Evaluation Shader)
112 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
113 * enabled, incoming strips etc are passed to GS threads in individual
114 * line/triangle/point units. The GS thread may perform arbitary
115 * computation and emit whatever primtives with whatever vertices it
116 * chooses. This makes GS an excellent place to implement GL's
117 * unfilled polygon modes, though of course it is capable of much
118 * more. Additionally, GS is used to translate away primitives not
119 * handled by latter units, including Quads and Lineloops.
121 * CS - Clipper. Mesa's clipping algorithms are imported to run on
122 * this unit. The fixed function part performs cliptesting against
123 * the 6 fixed clipplanes and makes descisions on whether or not the
124 * incoming primitive needs to be passed to a thread for clipping.
125 * User clip planes are handled via cooperation with the VS thread.
127 * SF - Strips Fans or Setup: Triangles are prepared for
128 * rasterization. Interpolation coefficients are calculated.
129 * Flatshading and two-side lighting usually performed here.
131 * WM - Windower. Interpolation of vertex attributes performed here.
132 * Fragment shader implemented here. SIMD aspects of EU taken full
133 * advantage of, as pixels are processed in blocks of 16.
135 * CC - Color Calculator. No EU threads associated with this unit.
136 * Handles blending and (presumably) depth and stencil testing.
141 struct brw_vs_prog_key
;
142 struct brw_vue_prog_key
;
143 struct brw_wm_prog_key
;
144 struct brw_wm_prog_data
;
145 struct brw_cs_prog_key
;
146 struct brw_cs_prog_data
;
150 BRW_COMPUTE_PIPELINE
,
157 BRW_CACHE_BLORP_PROG
,
160 BRW_CACHE_FF_GS_PROG
,
171 /* brw_cache_ids must come first - see brw_program_cache.c */
172 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
173 BRW_STATE_FRAGMENT_PROGRAM
,
174 BRW_STATE_GEOMETRY_PROGRAM
,
175 BRW_STATE_TESS_PROGRAMS
,
176 BRW_STATE_VERTEX_PROGRAM
,
177 BRW_STATE_CURBE_OFFSETS
,
178 BRW_STATE_REDUCED_PRIMITIVE
,
179 BRW_STATE_PATCH_PRIMITIVE
,
184 BRW_STATE_BINDING_TABLE_POINTERS
,
187 BRW_STATE_DEFAULT_TESS_LEVELS
,
189 BRW_STATE_INDEX_BUFFER
,
190 BRW_STATE_VS_CONSTBUF
,
191 BRW_STATE_TCS_CONSTBUF
,
192 BRW_STATE_TES_CONSTBUF
,
193 BRW_STATE_GS_CONSTBUF
,
194 BRW_STATE_PROGRAM_CACHE
,
195 BRW_STATE_STATE_BASE_ADDRESS
,
196 BRW_STATE_VUE_MAP_GEOM_OUT
,
197 BRW_STATE_TRANSFORM_FEEDBACK
,
198 BRW_STATE_RASTERIZER_DISCARD
,
200 BRW_STATE_UNIFORM_BUFFER
,
201 BRW_STATE_ATOMIC_BUFFER
,
202 BRW_STATE_IMAGE_UNITS
,
203 BRW_STATE_META_IN_PROGRESS
,
204 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
205 BRW_STATE_NUM_SAMPLES
,
206 BRW_STATE_TEXTURE_BUFFER
,
207 BRW_STATE_GEN4_UNIT_STATE
,
211 BRW_STATE_SAMPLER_STATE_TABLE
,
212 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
213 BRW_STATE_COMPUTE_PROGRAM
,
214 BRW_STATE_CS_WORK_GROUPS
,
218 BRW_STATE_VIEWPORT_COUNT
,
219 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
224 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
226 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
227 * When the currently bound shader program differs from the previous draw
228 * call, these will be flagged. They cover brw->{stage}_program and
229 * ctx->{Stage}Program->_Current.
231 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
232 * driver perspective. Even if the same shader is bound at the API level,
233 * we may need to switch between multiple versions of that shader to handle
234 * changes in non-orthagonal state.
236 * Additionally, multiple shader programs may have identical vertex shaders
237 * (for example), or compile down to the same code in the backend. We combine
238 * those into a single program cache entry.
240 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
241 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
243 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
244 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
245 * use the normal state upload paths), but the cache is still used. To avoid
246 * polluting the brw_program_cache code with special cases, we retain the
247 * dirty bit for now. It should eventually be removed.
249 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
250 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
251 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
252 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
253 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
254 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
255 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
256 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
257 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
258 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
259 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
260 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
261 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
262 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
263 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
264 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
265 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
266 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
267 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
268 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
269 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
270 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
271 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
272 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
273 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
275 * Used for any batch entry with a relocated pointer that will be used
276 * by any 3D rendering.
278 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
279 /** \see brw.state.depth_region */
280 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
281 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
282 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
283 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
284 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
285 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
286 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
287 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
288 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
289 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
290 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
291 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
292 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
293 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
294 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
295 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
296 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
297 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
298 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
299 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
300 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
301 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
302 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
303 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
304 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
305 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
306 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
307 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
308 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
309 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
310 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
312 struct brw_state_flags
{
313 /** State update flags signalled by mesa internals */
316 * State update flags signalled as the result of brw_tracked_state updates
322 /** Subclass of Mesa program */
324 struct gl_program program
;
331 struct brw_sf_prog_data
{
332 GLuint urb_read_length
;
335 /* Each vertex may have upto 12 attributes, 4 components each,
336 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
339 * Actually we use 4 for each, so call it 12 rows.
341 GLuint urb_entry_size
;
345 struct brw_clip_prog_data
{
346 GLuint curb_read_length
; /* user planes? */
348 GLuint urb_read_length
;
352 struct brw_ff_gs_prog_data
{
353 GLuint urb_read_length
;
357 * Gen6 transform feedback: Amount by which the streaming vertex buffer
358 * indices should be incremented each time the GS is invoked.
360 unsigned svbi_postincrement_value
;
363 /** Number of texture sampler units */
364 #define BRW_MAX_TEX_UNIT 32
366 /** Max number of UBOs in a shader */
367 #define BRW_MAX_UBO 14
369 /** Max number of SSBOs in a shader */
370 #define BRW_MAX_SSBO 12
372 /** Max number of atomic counter buffer objects in a shader */
373 #define BRW_MAX_ABO 16
375 /** Max number of image uniforms in a shader */
376 #define BRW_MAX_IMAGES 32
378 /** Maximum number of actual buffers used for stream output */
379 #define BRW_MAX_SOL_BUFFERS 4
381 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
382 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
387 2 + /* shader time, pull constants */ \
388 1 /* cs num work groups */)
391 struct brw_context
*brw
;
393 struct brw_cache_item
**items
;
395 GLuint size
, n_items
;
397 uint32_t next_offset
;
402 /* Considered adding a member to this struct to document which flags
403 * an update might raise so that ordering of the state atoms can be
404 * checked or derived at runtime. Dropped the idea in favor of having
405 * a debug mode where the state is monitored for flags which are
406 * raised that have already been tested against.
408 struct brw_tracked_state
{
409 struct brw_state_flags dirty
;
410 void (*emit
)( struct brw_context
*brw
);
413 enum shader_time_shader_type
{
424 struct brw_vertex_buffer
{
425 /** Buffer object containing the uploaded vertex data */
429 /** Byte stride between elements in the uploaded array */
433 struct brw_vertex_element
{
434 const struct gl_vertex_array
*glarray
;
438 /** Offset of the first element within the buffer object */
442 struct brw_query_object
{
443 struct gl_query_object Base
;
445 /** Last query BO associated with this query. */
448 /** Last index in bo with query data for this object. */
451 /** True if we know the batch has been flushed since we ended the query. */
461 struct intel_batchbuffer
{
462 /** Current batchbuffer being queued up. */
464 /** Last BO submitted to the hardware. Used for glFinish(). */
465 drm_intel_bo
*last_bo
;
468 uint16_t emit
, total
;
470 uint16_t reserved_space
;
474 #define BATCH_SZ (8192*sizeof(uint32_t))
476 uint32_t state_batch_offset
;
477 enum brw_gpu_ring ring
;
478 bool needs_sol_reset
;
479 bool state_base_address_emitted
;
486 /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */
487 struct hash_table
*state_batch_sizes
;
490 #define BRW_MAX_XFB_STREAMS 4
492 struct brw_transform_feedback_object
{
493 struct gl_transform_feedback_object base
;
495 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
496 drm_intel_bo
*offset_bo
;
498 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
501 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
502 GLenum primitive_mode
;
505 * The maximum number of vertices that we can write without overflowing
506 * any of the buffers currently being used for transform feedback.
511 * Count of primitives generated during this transform feedback operation.
514 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
515 drm_intel_bo
*prim_count_bo
;
516 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
520 * Number of vertices written between last Begin/EndTransformFeedback().
522 * Used to implement DrawTransformFeedback().
524 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
525 bool vertices_written_valid
;
529 * Data shared between each programmable stage in the pipeline (vs, gs, and
532 struct brw_stage_state
534 gl_shader_stage stage
;
535 struct brw_stage_prog_data
*prog_data
;
538 * Optional scratch buffer used to store spilled register values and
539 * variably-indexed GRF arrays.
541 * The contents of this buffer are short-lived so the same memory can be
542 * re-used at will for multiple shader programs (executed by the same fixed
543 * function). However reusing a scratch BO for which shader invocations
544 * are still in flight with a per-thread scratch slot size other than the
545 * original can cause threads with different scratch slot size and FFTID
546 * (which may be executed in parallel depending on the shader stage and
547 * hardware generation) to map to an overlapping region of the scratch
548 * space, which can potentially lead to mutual scratch space corruption.
549 * For that reason if you borrow this scratch buffer you should only be
550 * using the slot size given by the \c per_thread_scratch member below,
551 * unless you're taking additional measures to synchronize thread execution
552 * across slot size changes.
554 drm_intel_bo
*scratch_bo
;
557 * Scratch slot size allocated for each thread in the buffer object given
560 uint32_t per_thread_scratch
;
562 /** Offset in the program cache to the program */
563 uint32_t prog_offset
;
565 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
566 uint32_t state_offset
;
568 uint32_t push_const_offset
; /* Offset in the batchbuffer */
569 int push_const_size
; /* in 256-bit register increments */
571 /* Binding table: pointers to SURFACE_STATE entries. */
572 uint32_t bind_bo_offset
;
573 uint32_t surf_offset
[BRW_MAX_SURFACES
];
575 /** SAMPLER_STATE count and table offset */
576 uint32_t sampler_count
;
577 uint32_t sampler_offset
;
580 enum brw_predicate_state
{
581 /* The first two states are used if we can determine whether to draw
582 * without having to look at the values in the query object buffer. This
583 * will happen if there is no conditional render in progress, if the query
584 * object is already completed or if something else has already added
585 * samples to the preliminary result such as via a BLT command.
587 BRW_PREDICATE_STATE_RENDER
,
588 BRW_PREDICATE_STATE_DONT_RENDER
,
589 /* In this case whether to draw or not depends on the result of an
590 * MI_PREDICATE command so the predicate enable bit needs to be checked.
592 BRW_PREDICATE_STATE_USE_BIT
597 struct gen_l3_config
;
599 enum brw_query_kind
{
604 struct brw_perf_query_info
606 enum brw_query_kind kind
;
609 struct brw_perf_query_counter
*counters
;
614 uint64_t oa_metrics_set_id
;
617 /* For indexing into the accumulator[] ... */
619 int gpu_clock_offset
;
626 * brw_context is derived from gl_context.
630 struct gl_context ctx
; /**< base class, must be first field */
634 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
635 struct gl_renderbuffer
*rb
,
636 uint32_t flags
, unsigned unit
,
637 uint32_t surf_index
);
638 void (*emit_null_surface_state
)(struct brw_context
*brw
,
642 uint32_t *out_offset
);
645 * Send the appropriate state packets to configure depth, stencil, and
646 * HiZ buffers (i965+ only)
648 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
649 struct intel_mipmap_tree
*depth_mt
,
650 uint32_t depth_offset
,
651 uint32_t depthbuffer_format
,
652 uint32_t depth_surface_type
,
653 struct intel_mipmap_tree
*stencil_mt
,
654 bool hiz
, bool separate_stencil
,
655 uint32_t width
, uint32_t height
,
656 uint32_t tile_x
, uint32_t tile_y
);
662 drm_intel_context
*hw_ctx
;
664 /** BO for post-sync nonzero writes for gen6 workaround. */
665 drm_intel_bo
*workaround_bo
;
666 uint8_t pipe_controls_since_last_cs_stall
;
669 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
670 * and would need flushing before being used from another cache domain that
671 * isn't coherent with it (i.e. the sampler).
673 struct set
*render_cache
;
676 * Number of resets observed in the system at context creation.
678 * This is tracked in the context so that we can determine that another
679 * reset has occurred.
681 uint32_t reset_count
;
683 struct intel_batchbuffer batch
;
688 uint32_t next_offset
;
692 * Set if rendering has occurred to the drawable's front buffer.
694 * This is used in the DRI2 case to detect that glFlush should also copy
695 * the contents of the fake front buffer to the real front buffer.
697 bool front_buffer_dirty
;
699 /** Framerate throttling: @{ */
700 drm_intel_bo
*throttle_batch
[2];
702 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
703 * frame of rendering to complete. This gives a very precise cap to the
704 * latency between input and output such that rendering never gets more
705 * than a frame behind the user. (With the caveat that we technically are
706 * not using the SwapBuffers itself as a barrier but the first batch
707 * submitted afterwards, which may be immediately prior to the next
710 bool need_swap_throttle
;
712 /** General throttling, not caught by throttling between SwapBuffers */
713 bool need_flush_throttle
;
723 bool always_flush_batch
;
724 bool always_flush_cache
;
725 bool disable_throttling
;
727 bool dual_color_blend_by_location
;
729 driOptionCache optionCache
;
732 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
734 GLenum reduced_primitive
;
737 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
738 * variable is set, this is the flag indicating to do expensive work that
739 * might lead to a perf_debug() call.
743 uint64_t max_gtt_map_object_size
;
755 bool has_separate_stencil
;
756 bool must_use_separate_stencil
;
759 bool has_surface_tile_offset
;
761 bool has_negative_rhw_bug
;
765 bool use_resource_streamer
;
768 * Some versions of Gen hardware don't do centroid interpolation correctly
769 * on unlit pixels, causing incorrect values for derivatives near triangle
770 * edges. Enabling this flag causes the fragment shader to use
771 * non-centroid interpolation for unlit pixels, at the expense of two extra
772 * fragment shader instructions.
774 bool needs_unlit_centroid_workaround
;
776 struct isl_device isl_dev
;
778 struct blorp_context blorp
;
782 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
785 enum brw_pipeline last_pipeline
;
787 struct brw_cache cache
;
789 /** IDs for meta stencil blit shader programs. */
790 struct gl_shader_program
*meta_stencil_blit_programs
[2];
792 /* Whether a meta-operation is in progress. */
793 bool meta_in_progress
;
795 /* Whether the last depth/stencil packets were both NULL. */
796 bool no_depth_or_stencil
;
798 /* The last PMA stall bits programmed. */
799 uint32_t pma_stall_bits
;
803 /** The value of gl_BaseVertex for the current _mesa_prim. */
806 /** The value of gl_BaseInstance for the current _mesa_prim. */
811 * Buffer and offset used for GL_ARB_shader_draw_parameters
812 * (for now, only gl_BaseVertex).
814 drm_intel_bo
*draw_params_bo
;
815 uint32_t draw_params_offset
;
818 * The value of gl_DrawID for the current _mesa_prim. This always comes
819 * in from it's own vertex buffer since it's not part of the indirect
823 drm_intel_bo
*draw_id_bo
;
824 uint32_t draw_id_offset
;
829 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
830 * an indirect call, and num_work_groups_offset is valid. Otherwise,
831 * num_work_groups is set based on glDispatchCompute.
833 drm_intel_bo
*num_work_groups_bo
;
834 GLintptr num_work_groups_offset
;
835 const GLuint
*num_work_groups
;
839 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
840 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
842 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
846 /* Summary of size and varying of active arrays, so we can check
847 * for changes to this state:
849 bool index_bounds_valid
;
850 unsigned int min_index
, max_index
;
852 /* Offset from start of vertex buffer so we can avoid redefining
853 * the same VB packed over and over again.
855 unsigned int start_vertex_bias
;
858 * Certain vertex attribute formats aren't natively handled by the
859 * hardware and require special VS code to fix up their values.
861 * These bitfields indicate which workarounds are needed.
863 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
868 * Index buffer for this draw_prims call.
870 * Updates are signaled by BRW_NEW_INDICES.
872 const struct _mesa_index_buffer
*ib
;
874 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
879 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
880 * avoid re-uploading the IB packet over and over if we're actually
881 * referencing the same index buffer.
883 unsigned int start_vertex_offset
;
886 /* Active vertex program:
888 const struct gl_program
*vertex_program
;
889 const struct gl_program
*geometry_program
;
890 const struct gl_program
*tess_ctrl_program
;
891 const struct gl_program
*tess_eval_program
;
892 const struct gl_program
*fragment_program
;
893 const struct gl_program
*compute_program
;
896 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
897 * that we don't have to reemit that state every time we change FBOs.
901 /* BRW_NEW_URB_ALLOCATIONS:
904 GLuint vsize
; /* vertex size plus header in urb registers */
905 GLuint gsize
; /* GS output size in urb registers */
906 GLuint hsize
; /* Tessellation control output size in urb registers */
907 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
908 GLuint csize
; /* constant buffer size in urb registers */
909 GLuint sfsize
; /* setup data size in urb registers */
913 GLuint nr_vs_entries
;
914 GLuint nr_hs_entries
;
915 GLuint nr_ds_entries
;
916 GLuint nr_gs_entries
;
917 GLuint nr_clip_entries
;
918 GLuint nr_sf_entries
;
919 GLuint nr_cs_entries
;
929 * URB size in the current configuration. The units this is expressed
930 * in are somewhat inconsistent, see gen_device_info::urb::size.
932 * FINISHME: Represent the URB size consistently in KB on all platforms.
936 /* True if the most recently sent _3DSTATE_URB message allocated
937 * URB space for the GS.
941 /* True if the most recently sent _3DSTATE_URB message allocated
942 * URB space for the HS and DS.
948 /* BRW_NEW_CURBE_OFFSETS:
951 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
952 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
960 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
961 * for upload to the CURBE.
963 drm_intel_bo
*curbe_bo
;
964 /** Offset within curbe_bo of space for current curbe entry */
969 * Layout of vertex data exiting the geometry portion of the pipleine.
970 * This comes from the last enabled shader stage (GS, DS, or VS).
972 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
974 struct brw_vue_map vue_map_geom_out
;
977 struct brw_stage_state base
;
981 struct brw_stage_state base
;
984 * True if the 3DSTATE_HS command most recently emitted to the 3D
985 * pipeline enabled the HS; false otherwise.
991 struct brw_stage_state base
;
994 * True if the 3DSTATE_DS command most recently emitted to the 3D
995 * pipeline enabled the DS; false otherwise.
1001 struct brw_stage_state base
;
1004 * True if the 3DSTATE_GS command most recently emitted to the 3D
1005 * pipeline enabled the GS; false otherwise.
1011 struct brw_ff_gs_prog_data
*prog_data
;
1014 /** Offset in the program cache to the CLIP program pre-gen6 */
1015 uint32_t prog_offset
;
1016 uint32_t state_offset
;
1018 uint32_t bind_bo_offset
;
1020 * Surface offsets for the binding table. We only need surfaces to
1021 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1022 * need in this case.
1024 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1028 struct brw_clip_prog_data
*prog_data
;
1030 /** Offset in the program cache to the CLIP program pre-gen6 */
1031 uint32_t prog_offset
;
1033 /* Offset in the batch to the CLIP state on pre-gen6. */
1034 uint32_t state_offset
;
1036 /* As of gen6, this is the offset in the batch to the CLIP VP,
1042 * The number of viewports to use. If gl_ViewportIndex is written,
1043 * we can have up to ctx->Const.MaxViewports viewports. If not,
1044 * the viewport index is always 0, so we can only emit one.
1046 uint8_t viewport_count
;
1051 struct brw_sf_prog_data
*prog_data
;
1053 /** Offset in the program cache to the CLIP program pre-gen6 */
1054 uint32_t prog_offset
;
1055 uint32_t state_offset
;
1057 bool viewport_transform_enable
;
1061 struct brw_stage_state base
;
1066 * Buffer object used in place of multisampled null render targets on
1067 * Gen6. See brw_emit_null_surface_state().
1069 drm_intel_bo
*multisampled_null_render_target_bo
;
1070 uint32_t fast_clear_op
;
1076 struct brw_stage_state base
;
1080 uint32_t state_offset
;
1081 uint32_t blend_state_offset
;
1082 uint32_t depth_stencil_state_offset
;
1087 struct brw_query_object
*obj
;
1092 enum brw_predicate_state state
;
1097 /* Variables referenced in the XML meta data for OA performance
1098 * counters, e.g in the normalization equations.
1100 * All uint64_t for consistent operand types in generated code
1103 uint64_t timestamp_frequency
; /** $GpuTimestampFrequency */
1104 uint64_t n_eus
; /** $EuCoresTotalCount */
1105 uint64_t n_eu_slices
; /** $EuSlicesTotalCount */
1106 uint64_t subslice_mask
; /** $SubsliceMask */
1107 uint64_t gt_min_freq
; /** $GpuMinFrequency */
1108 uint64_t gt_max_freq
; /** $GpuMaxFrequency */
1111 /* OA metric sets, indexed by GUID, as know by Mesa at build time,
1112 * to cross-reference with the GUIDs of configs advertised by the
1115 struct hash_table
*oa_metrics_table
;
1117 struct brw_perf_query_info
*queries
;
1120 /* The i915 perf stream we open to setup + enable the OA counters */
1123 /* An i915 perf stream fd gives exclusive access to the OA unit that will
1124 * report counter snapshots for a specific counter set/profile in a
1125 * specific layout/format so we can only start OA queries that are
1126 * compatible with the currently open fd...
1128 int current_oa_metrics_set_id
;
1129 int current_oa_format
;
1131 /* List of buffers containing OA reports */
1132 struct exec_list sample_buffers
;
1134 /* Cached list of empty sample buffers */
1135 struct exec_list free_sample_buffers
;
1137 int n_active_oa_queries
;
1138 int n_active_pipeline_stats_queries
;
1140 /* The number of queries depending on running OA counters which
1141 * extends beyond brw_end_perf_query() since we need to wait until
1142 * the last MI_RPC command has parsed by the GPU.
1144 * Accurate accounting is important here as emitting an
1145 * MI_REPORT_PERF_COUNT command while the OA unit is disabled will
1146 * effectively hang the gpu.
1150 /* To help catch an spurious problem with the hardware or perf
1151 * forwarding samples, we emit each MI_REPORT_PERF_COUNT command
1152 * with a unique ID that we can explicitly check for...
1154 int next_query_start_report_id
;
1157 * An array of queries whose results haven't yet been assembled
1158 * based on the data in buffer objects.
1160 * These may be active, or have already ended. However, the
1161 * results have not been requested.
1163 struct brw_perf_query_object
**unaccumulated
;
1164 int unaccumulated_elements
;
1165 int unaccumulated_array_size
;
1167 /* The total number of query objects so we can relinquish
1168 * our exclusive access to perf if the application deletes
1169 * all of its objects. (NB: We only disable perf while
1170 * there are no active queries)
1172 int n_query_instances
;
1175 int num_atoms
[BRW_NUM_PIPELINES
];
1176 const struct brw_tracked_state render_atoms
[76];
1177 const struct brw_tracked_state compute_atoms
[11];
1179 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1180 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1182 /* PrimitiveRestart */
1185 bool enable_cut_index
;
1188 /** Computed depth/stencil/hiz state from the current attached
1189 * renderbuffers, valid only during the drawing state upload loop after
1190 * brw_workaround_depthstencil_alignment().
1193 struct intel_mipmap_tree
*depth_mt
;
1194 struct intel_mipmap_tree
*stencil_mt
;
1196 /* Inter-tile (page-aligned) byte offsets. */
1197 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1198 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1199 uint32_t tile_x
, tile_y
;
1202 uint32_t num_instances
;
1207 const struct gen_l3_config
*config
;
1214 enum shader_time_shader_type
*types
;
1215 struct shader_times
*cumulative
;
1221 struct brw_fast_clear_state
*fast_clear_state
;
1223 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1224 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1225 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1227 * This is needed in case the same underlying buffer is also configured
1228 * to be sampled but with a format that the sampling engine can't treat
1229 * compressed or fast cleared.
1231 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1233 __DRIcontext
*driContext
;
1234 struct intel_screen
*screen
;
1238 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1240 /*======================================================================
1243 extern const char *const brw_vendor_string
;
1246 brw_get_renderer_string(const struct intel_screen
*screen
);
1249 DRI_CONF_BO_REUSE_DISABLED
,
1250 DRI_CONF_BO_REUSE_ALL
1253 void intel_update_renderbuffers(__DRIcontext
*context
,
1254 __DRIdrawable
*drawable
);
1255 void intel_prepare_render(struct brw_context
*brw
);
1257 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1258 __DRIdrawable
*drawable
);
1260 GLboolean
brwCreateContext(gl_api api
,
1261 const struct gl_config
*mesaVis
,
1262 __DRIcontext
*driContextPriv
,
1263 unsigned major_version
,
1264 unsigned minor_version
,
1268 void *sharedContextPrivate
);
1270 /*======================================================================
1274 brw_meta_resolve_color(struct brw_context
*brw
,
1275 struct intel_mipmap_tree
*mt
);
1277 /*======================================================================
1280 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1281 GLbitfield clear_mask
);
1283 /* brw_object_purgeable.c */
1284 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1286 /*======================================================================
1289 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1290 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1291 void brw_emit_query_begin(struct brw_context
*brw
);
1292 void brw_emit_query_end(struct brw_context
*brw
);
1293 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1294 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1295 uint64_t brw_timebase_scale(struct brw_context
*brw
, uint64_t gpu_timestamp
);
1296 uint64_t brw_raw_timestamp_delta(struct brw_context
*brw
,
1297 uint64_t time0
, uint64_t time1
);
1299 /** gen6_queryobj.c */
1300 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1301 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1302 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1304 /** hsw_queryobj.c */
1305 void hsw_overflow_result_to_gpr0(struct brw_context
*brw
,
1306 struct brw_query_object
*query
,
1308 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1310 /** brw_conditional_render.c */
1311 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1312 bool brw_check_conditional_render(struct brw_context
*brw
);
1314 /** intel_batchbuffer.c */
1315 void brw_load_register_mem(struct brw_context
*brw
,
1318 uint32_t read_domains
, uint32_t write_domain
,
1320 void brw_load_register_mem64(struct brw_context
*brw
,
1323 uint32_t read_domains
, uint32_t write_domain
,
1325 void brw_store_register_mem32(struct brw_context
*brw
,
1326 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1327 void brw_store_register_mem64(struct brw_context
*brw
,
1328 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1329 void brw_load_register_imm32(struct brw_context
*brw
,
1330 uint32_t reg
, uint32_t imm
);
1331 void brw_load_register_imm64(struct brw_context
*brw
,
1332 uint32_t reg
, uint64_t imm
);
1333 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1335 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1337 void brw_store_data_imm32(struct brw_context
*brw
, drm_intel_bo
*bo
,
1338 uint32_t offset
, uint32_t imm
);
1339 void brw_store_data_imm64(struct brw_context
*brw
, drm_intel_bo
*bo
,
1340 uint32_t offset
, uint64_t imm
);
1342 /*======================================================================
1343 * intel_tex_validate.c
1345 void brw_validate_textures( struct brw_context
*brw
);
1348 /*======================================================================
1352 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1355 perf_debug(" %s %d->%d\n", name
, a
, b
);
1361 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1363 void brw_get_scratch_bo(struct brw_context
*brw
,
1364 drm_intel_bo
**scratch_bo
, int size
);
1365 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1366 struct brw_stage_state
*stage_state
,
1367 unsigned per_thread_size
,
1368 unsigned thread_count
);
1369 void brw_init_shader_time(struct brw_context
*brw
);
1370 int brw_get_shader_time_index(struct brw_context
*brw
,
1371 struct gl_program
*prog
,
1372 enum shader_time_shader_type type
,
1374 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1375 void brw_destroy_shader_time(struct brw_context
*brw
);
1379 void brw_upload_urb_fence(struct brw_context
*brw
);
1383 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1386 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1388 /* brw_draw_upload.c */
1389 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1390 const struct gl_vertex_array
*glarray
);
1392 static inline unsigned
1393 brw_get_index_type(GLenum type
)
1395 assert((type
== GL_UNSIGNED_BYTE
)
1396 || (type
== GL_UNSIGNED_SHORT
)
1397 || (type
== GL_UNSIGNED_INT
));
1399 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1400 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1401 * to map to scale factors of 0, 1, and 2, respectively. These scale
1402 * factors are then left-shfited by 8 to be in the correct position in the
1403 * CMD_INDEX_BUFFER packet.
1405 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1406 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1407 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1409 return (type
- 0x1401) << 7;
1412 void brw_prepare_vertices(struct brw_context
*brw
);
1414 /* brw_wm_surface_state.c */
1415 void brw_init_surface_formats(struct brw_context
*brw
);
1416 void brw_create_constant_surface(struct brw_context
*brw
,
1420 uint32_t *out_offset
);
1421 void brw_create_buffer_surface(struct brw_context
*brw
,
1425 uint32_t *out_offset
);
1426 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1428 uint32_t *surf_offset
);
1430 brw_update_sol_surface(struct brw_context
*brw
,
1431 struct gl_buffer_object
*buffer_obj
,
1432 uint32_t *out_offset
, unsigned num_vector_components
,
1433 unsigned stride_dwords
, unsigned offset_dwords
);
1434 void brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1435 struct brw_stage_state
*stage_state
,
1436 struct brw_stage_prog_data
*prog_data
);
1437 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1438 const struct gl_program
*prog
,
1439 struct brw_stage_state
*stage_state
,
1440 struct brw_stage_prog_data
*prog_data
);
1441 void brw_upload_image_surfaces(struct brw_context
*brw
,
1442 const struct gl_program
*prog
,
1443 struct brw_stage_state
*stage_state
,
1444 struct brw_stage_prog_data
*prog_data
);
1446 /* brw_surface_formats.c */
1447 bool brw_render_target_supported(struct brw_context
*brw
,
1448 struct gl_renderbuffer
*rb
);
1449 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1451 /* brw_performance_query.c */
1452 void brw_init_performance_queries(struct brw_context
*brw
);
1454 /* intel_buffer_objects.c */
1455 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1456 const char *bo_name
);
1457 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1458 const char *bo_name
);
1460 /* intel_extensions.c */
1461 extern void intelInitExtensions(struct gl_context
*ctx
);
1464 extern int intel_translate_shadow_compare_func(GLenum func
);
1465 extern int intel_translate_compare_func(GLenum func
);
1466 extern int intel_translate_stencil_op(GLenum op
);
1467 extern int intel_translate_logic_op(GLenum opcode
);
1470 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1473 struct gl_transform_feedback_object
*
1474 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1476 brw_delete_transform_feedback(struct gl_context
*ctx
,
1477 struct gl_transform_feedback_object
*obj
);
1479 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1480 struct gl_transform_feedback_object
*obj
);
1482 brw_end_transform_feedback(struct gl_context
*ctx
,
1483 struct gl_transform_feedback_object
*obj
);
1485 brw_pause_transform_feedback(struct gl_context
*ctx
,
1486 struct gl_transform_feedback_object
*obj
);
1488 brw_resume_transform_feedback(struct gl_context
*ctx
,
1489 struct gl_transform_feedback_object
*obj
);
1491 brw_save_primitives_written_counters(struct brw_context
*brw
,
1492 struct brw_transform_feedback_object
*obj
);
1494 brw_compute_xfb_vertices_written(struct brw_context
*brw
,
1495 struct brw_transform_feedback_object
*obj
);
1497 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1498 struct gl_transform_feedback_object
*obj
,
1501 /* gen7_sol_state.c */
1503 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1504 struct gl_transform_feedback_object
*obj
);
1506 gen7_end_transform_feedback(struct gl_context
*ctx
,
1507 struct gl_transform_feedback_object
*obj
);
1509 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1510 struct gl_transform_feedback_object
*obj
);
1512 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1513 struct gl_transform_feedback_object
*obj
);
1517 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1518 struct gl_transform_feedback_object
*obj
);
1520 hsw_end_transform_feedback(struct gl_context
*ctx
,
1521 struct gl_transform_feedback_object
*obj
);
1523 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1524 struct gl_transform_feedback_object
*obj
);
1526 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1527 struct gl_transform_feedback_object
*obj
);
1529 /* brw_blorp_blit.cpp */
1531 brw_blorp_framebuffer(struct brw_context
*brw
,
1532 struct gl_framebuffer
*readFb
,
1533 struct gl_framebuffer
*drawFb
,
1534 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1535 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1536 GLbitfield mask
, GLenum filter
);
1539 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1540 struct gl_renderbuffer
*src_rb
,
1541 struct gl_texture_image
*dst_image
,
1543 int srcX0
, int srcY0
,
1544 int dstX0
, int dstY0
,
1545 int width
, int height
);
1547 /* gen6_multisample_state.c */
1549 gen6_determine_sample_mask(struct brw_context
*brw
);
1552 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1553 unsigned num_samples
);
1555 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1557 gen6_get_sample_position(struct gl_context
*ctx
,
1558 struct gl_framebuffer
*fb
,
1562 gen6_set_sample_maps(struct gl_context
*ctx
);
1564 /* gen8_multisample_state.c */
1565 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1566 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1570 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1571 unsigned hs_size
, unsigned ds_size
,
1572 unsigned gs_size
, unsigned fs_size
);
1575 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1576 bool gs_present
, unsigned gs_size
);
1578 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1579 bool gs_present
, bool tess_present
);
1583 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1585 brw_check_for_reset(struct brw_context
*brw
);
1589 brw_init_compute_functions(struct dd_function_table
*functions
);
1591 /*======================================================================
1592 * Inline conversion functions. These are better-typed than the
1593 * macros used previously:
1595 static inline struct brw_context
*
1596 brw_context( struct gl_context
*ctx
)
1598 return (struct brw_context
*)ctx
;
1601 static inline struct brw_program
*
1602 brw_program(struct gl_program
*p
)
1604 return (struct brw_program
*) p
;
1607 static inline const struct brw_program
*
1608 brw_program_const(const struct gl_program
*p
)
1610 return (const struct brw_program
*) p
;
1613 static inline uint32_t
1614 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1615 uint32_t prog_offset
)
1617 if (brw
->gen
>= 5) {
1618 /* Using state base address. */
1622 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1626 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1628 return brw
->cache
.bo
->offset64
+ prog_offset
;
1632 brw_depth_writes_enabled(const struct brw_context
*brw
)
1634 const struct gl_context
*ctx
= &brw
->ctx
;
1636 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1637 * because it would just overwrite the existing depth value with itself.
1639 * These bonus depth writes not only use bandwidth, but they also can
1640 * prevent early depth processing. For example, if the pixel shader
1641 * discards, the hardware must invoke the to determine whether or not
1642 * to do the depth write. If writes are disabled, we may still be able
1643 * to do the depth test before the shader, and skip the shader execution.
1645 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1646 * a programming note saying to disable depth writes for EQUAL.
1648 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1652 brw_emit_depthbuffer(struct brw_context
*brw
);
1655 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1656 struct intel_mipmap_tree
*depth_mt
,
1657 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1658 uint32_t depth_surface_type
,
1659 struct intel_mipmap_tree
*stencil_mt
,
1660 bool hiz
, bool separate_stencil
,
1661 uint32_t width
, uint32_t height
,
1662 uint32_t tile_x
, uint32_t tile_y
);
1665 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1666 struct intel_mipmap_tree
*depth_mt
,
1667 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1668 uint32_t depth_surface_type
,
1669 struct intel_mipmap_tree
*stencil_mt
,
1670 bool hiz
, bool separate_stencil
,
1671 uint32_t width
, uint32_t height
,
1672 uint32_t tile_x
, uint32_t tile_y
);
1675 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1676 struct intel_mipmap_tree
*depth_mt
,
1677 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1678 uint32_t depth_surface_type
,
1679 struct intel_mipmap_tree
*stencil_mt
,
1680 bool hiz
, bool separate_stencil
,
1681 uint32_t width
, uint32_t height
,
1682 uint32_t tile_x
, uint32_t tile_y
);
1684 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1685 struct intel_mipmap_tree
*depth_mt
,
1686 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1687 uint32_t depth_surface_type
,
1688 struct intel_mipmap_tree
*stencil_mt
,
1689 bool hiz
, bool separate_stencil
,
1690 uint32_t width
, uint32_t height
,
1691 uint32_t tile_x
, uint32_t tile_y
);
1693 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1694 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
);
1696 uint32_t get_hw_prim_for_gl_prim(int mode
);
1699 gen6_upload_push_constants(struct brw_context
*brw
,
1700 const struct gl_program
*prog
,
1701 const struct brw_stage_prog_data
*prog_data
,
1702 struct brw_stage_state
*stage_state
,
1703 enum aub_state_struct_type type
);
1706 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1707 const struct intel_mipmap_tree
*mt
);
1709 /* brw_pipe_control.c */
1710 int brw_init_pipe_control(struct brw_context
*brw
,
1711 const struct gen_device_info
*info
);
1712 void brw_fini_pipe_control(struct brw_context
*brw
);
1714 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1715 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1716 drm_intel_bo
*bo
, uint32_t offset
,
1717 uint32_t imm_lower
, uint32_t imm_upper
);
1718 void brw_emit_mi_flush(struct brw_context
*brw
);
1719 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1720 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1721 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1722 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1724 /* brw_queryformat.c */
1725 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1726 GLenum internalFormat
, GLenum pname
,