2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
43 * URB - uniform resource buffer. A mid-sized buffer which is
44 * partitioned between the fixed function units and used for passing
45 * values (vertices, primitives, constants) between them.
47 * CURBE - constant URB entry. An urb region (entry) used to hold
48 * constant values which the fixed function units can be instructed to
49 * preload into the GRF when spawning a thread.
51 * VUE - vertex URB entry. An urb entry holding a vertex and usually
52 * a vertex header. The header contains control information and
53 * things like primitive type, Begin/end flags and clip codes.
55 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
56 * unit holding rasterization and interpolation parameters.
58 * GRF - general register file. One of several register files
59 * addressable by programmed threads. The inputs (r0, payload, curbe,
60 * urb) of the thread are preloaded to this area before the thread is
61 * spawned. The registers are individually 8 dwords wide and suitable
62 * for general usage. Registers holding thread input values are not
63 * special and may be overwritten.
65 * MRF - message register file. Threads communicate (and terminate)
66 * by sending messages. Message parameters are placed in contiguous
67 * MRF registers. All program output is via these messages. URB
68 * entries are populated by sending a message to the shared URB
69 * function containing the new data, together with a control word,
70 * often an unmodified copy of R0.
72 * R0 - GRF register 0. Typically holds control information used when
73 * sending messages to other threads.
75 * EU or GEN4 EU: The name of the programmable subsystem of the
76 * i965 hardware. Threads are executed by the EU, the registers
77 * described above are part of the EU architecture.
79 * Fixed function units:
81 * CS - Command streamer. Notional first unit, little software
82 * interaction. Holds the URB entries used for constant data, ie the
85 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
86 * this unit is responsible for pulling vertices out of vertex buffers
87 * in vram and injecting them into the processing pipe as VUEs. If
88 * enabled, it first passes them to a VS thread which is a good place
89 * for the driver to implement any active vertex shader.
91 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
92 * enabled, incoming strips etc are passed to GS threads in individual
93 * line/triangle/point units. The GS thread may perform arbitary
94 * computation and emit whatever primtives with whatever vertices it
95 * chooses. This makes GS an excellent place to implement GL's
96 * unfilled polygon modes, though of course it is capable of much
97 * more. Additionally, GS is used to translate away primitives not
98 * handled by latter units, including Quads and Lineloops.
100 * CS - Clipper. Mesa's clipping algorithms are imported to run on
101 * this unit. The fixed function part performs cliptesting against
102 * the 6 fixed clipplanes and makes descisions on whether or not the
103 * incoming primitive needs to be passed to a thread for clipping.
104 * User clip planes are handled via cooperation with the VS thread.
106 * SF - Strips Fans or Setup: Triangles are prepared for
107 * rasterization. Interpolation coefficients are calculated.
108 * Flatshading and two-side lighting usually performed here.
110 * WM - Windower. Interpolation of vertex attributes performed here.
111 * Fragment shader implemented here. SIMD aspects of EU taken full
112 * advantage of, as pixels are processed in blocks of 16.
114 * CC - Color Calculator. No EU threads associated with this unit.
115 * Handles blending and (presumably) depth and stencil testing.
119 #define BRW_MAX_CURBE (32*16)
122 struct brw_instruction
;
123 struct brw_vs_prog_key
;
124 struct brw_wm_prog_key
;
125 struct brw_wm_prog_data
;
129 BRW_STATE_FRAGMENT_PROGRAM
,
130 BRW_STATE_VERTEX_PROGRAM
,
131 BRW_STATE_INPUT_DIMENSIONS
,
132 BRW_STATE_CURBE_OFFSETS
,
133 BRW_STATE_REDUCED_PRIMITIVE
,
136 BRW_STATE_WM_INPUT_DIMENSIONS
,
139 BRW_STATE_VS_BINDING_TABLE
,
140 BRW_STATE_GS_BINDING_TABLE
,
141 BRW_STATE_PS_BINDING_TABLE
,
145 BRW_STATE_NR_WM_SURFACES
,
146 BRW_STATE_NR_VS_SURFACES
,
147 BRW_STATE_INDEX_BUFFER
,
148 BRW_STATE_VS_CONSTBUF
,
149 BRW_STATE_PROGRAM_CACHE
,
150 BRW_STATE_STATE_BASE_ADDRESS
,
151 BRW_STATE_SOL_INDICES
,
154 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
155 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
156 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
157 #define BRW_NEW_INPUT_DIMENSIONS (1 << BRW_STATE_INPUT_DIMENSIONS)
158 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
159 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
160 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
161 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
162 #define BRW_NEW_WM_INPUT_DIMENSIONS (1 << BRW_STATE_WM_INPUT_DIMENSIONS)
163 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
164 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
165 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
166 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
167 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
168 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
169 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
171 * Used for any batch entry with a relocated pointer that will be used
172 * by any 3D rendering.
174 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
175 /** \see brw.state.depth_region */
176 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
177 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
178 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
179 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
180 #define BRW_NEW_SOL_INDICES (1 << BRW_STATE_SOL_INDICES)
182 struct brw_state_flags
{
183 /** State update flags signalled by mesa internals */
186 * State update flags signalled as the result of brw_tracked_state updates
189 /** State update flags signalled by brw_state_cache.c searches */
193 enum state_struct_type
{
194 AUB_TRACE_VS_STATE
= 1,
195 AUB_TRACE_GS_STATE
= 2,
196 AUB_TRACE_CLIP_STATE
= 3,
197 AUB_TRACE_SF_STATE
= 4,
198 AUB_TRACE_WM_STATE
= 5,
199 AUB_TRACE_CC_STATE
= 6,
200 AUB_TRACE_CLIP_VP_STATE
= 7,
201 AUB_TRACE_SF_VP_STATE
= 8,
202 AUB_TRACE_CC_VP_STATE
= 0x9,
203 AUB_TRACE_SAMPLER_STATE
= 0xa,
204 AUB_TRACE_KERNEL_INSTRUCTIONS
= 0xb,
205 AUB_TRACE_SCRATCH_SPACE
= 0xc,
206 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= 0xd,
208 AUB_TRACE_SCISSOR_STATE
= 0x15,
209 AUB_TRACE_BLEND_STATE
= 0x16,
210 AUB_TRACE_DEPTH_STENCIL_STATE
= 0x17,
212 /* Not written to .aub files the same way the structures above are. */
213 AUB_TRACE_NO_TYPE
= 0x100,
214 AUB_TRACE_BINDING_TABLE
= 0x101,
215 AUB_TRACE_SURFACE_STATE
= 0x102,
216 AUB_TRACE_VS_CONSTANTS
= 0x103,
217 AUB_TRACE_WM_CONSTANTS
= 0x104,
220 /** Subclass of Mesa vertex program */
221 struct brw_vertex_program
{
222 struct gl_vertex_program program
;
224 bool use_const_buffer
;
228 /** Subclass of Mesa fragment program */
229 struct brw_fragment_program
{
230 struct gl_fragment_program program
;
231 GLuint id
; /**< serial no. to identify frag progs, never re-used */
235 struct gl_shader base
;
237 /** Shader IR transformed for native compile, at link time. */
238 struct exec_list
*ir
;
241 struct brw_shader_program
{
242 struct gl_shader_program base
;
245 enum param_conversion
{
253 /* Data about a particular attempt to compile a program. Note that
254 * there can be many of these, each in a different GL state
255 * corresponding to a different brw_wm_prog_key struct, with different
258 struct brw_wm_prog_data
{
259 GLuint curb_read_length
;
260 GLuint urb_read_length
;
262 GLuint first_curbe_grf
;
263 GLuint first_curbe_grf_16
;
265 GLuint reg_blocks_16
;
266 GLuint total_scratch
;
268 GLuint nr_params
; /**< number of float params/constants */
269 GLuint nr_pull_params
;
272 uint32_t prog_offset_16
;
275 * Mask of which interpolation modes are required by the fragment shader.
276 * Used in hardware setup on gen6+.
278 uint32_t barycentric_interp_modes
;
280 /* Pointer to tracked values (only valid once
281 * _mesa_load_state_parameters has been called at runtime).
283 const float *param
[MAX_UNIFORMS
* 4]; /* should be: BRW_MAX_CURBE */
284 enum param_conversion param_convert
[MAX_UNIFORMS
* 4];
285 const float *pull_param
[MAX_UNIFORMS
* 4];
286 enum param_conversion pull_param_convert
[MAX_UNIFORMS
* 4];
290 * Enum representing the i965-specific vertex results that don't correspond
291 * exactly to any element of gl_vert_result. The values of this enum are
292 * assigned such that they don't conflict with gl_vert_result.
296 BRW_VERT_RESULT_NDC
= VERT_RESULT_MAX
,
297 BRW_VERT_RESULT_HPOS_DUPLICATE
,
304 * Data structure recording the relationship between the gl_vert_result enum
305 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
306 * single octaword within the VUE (128 bits).
308 * Note that each BRW register contains 256 bits (2 octawords), so when
309 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
310 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
311 * in a vertex shader), each register corresponds to a single VUE slot, since
312 * it contains data for two separate vertices.
316 * Map from gl_vert_result value to VUE slot. For gl_vert_results that are
317 * not stored in a slot (because they are not written, or because
318 * additional processing is applied before storing them in the VUE), the
321 int vert_result_to_slot
[BRW_VERT_RESULT_MAX
];
324 * Map from VUE slot to gl_vert_result value. For slots that do not
325 * directly correspond to a gl_vert_result, the value comes from
328 * For slots that are not in use, the value is BRW_VERT_RESULT_MAX (this
329 * simplifies code that uses the value stored in slot_to_vert_result to
330 * create a bit mask).
332 int slot_to_vert_result
[BRW_VERT_RESULT_MAX
];
335 * Total number of VUE slots in use
341 * Convert a VUE slot number into a byte offset within the VUE.
343 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
349 * Convert a vert_result into a byte offset within the VUE.
351 static inline GLuint
brw_vert_result_to_offset(struct brw_vue_map
*vue_map
,
354 return brw_vue_slot_to_offset(vue_map
->vert_result_to_slot
[vert_result
]);
358 struct brw_sf_prog_data
{
359 GLuint urb_read_length
;
362 /* Each vertex may have upto 12 attributes, 4 components each,
363 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
366 * Actually we use 4 for each, so call it 12 rows.
368 GLuint urb_entry_size
;
371 struct brw_clip_prog_data
{
372 GLuint curb_read_length
; /* user planes? */
374 GLuint urb_read_length
;
378 struct brw_gs_prog_data
{
379 GLuint urb_read_length
;
383 * Gen6 transform feedback: Amount by which the streaming vertex buffer
384 * indices should be incremented each time the GS is invoked.
386 unsigned svbi_postincrement_value
;
389 struct brw_vs_prog_data
{
390 struct brw_vue_map vue_map
;
392 GLuint curb_read_length
;
393 GLuint urb_read_length
;
395 GLbitfield64 outputs_written
;
396 GLuint nr_params
; /**< number of float params/constants */
397 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
398 GLuint total_scratch
;
400 GLbitfield64 inputs_read
;
402 /* Used for calculating urb partitions:
404 GLuint urb_entry_size
;
406 const float *param
[MAX_UNIFORMS
* 4]; /* should be: BRW_MAX_CURBE */
407 const float *pull_param
[MAX_UNIFORMS
* 4];
409 bool uses_new_param_layout
;
415 /* Size == 0 if output either not written, or always [0,0,0,1]
417 struct brw_vs_ouput_sizes
{
418 GLubyte output_size
[VERT_RESULT_MAX
];
422 /** Number of texture sampler units */
423 #define BRW_MAX_TEX_UNIT 16
425 /** Max number of render targets in a shader */
426 #define BRW_MAX_DRAW_BUFFERS 8
429 * Max number of binding table entries used for stream output.
431 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
432 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
434 * On Gen6, the size of transform feedback data is limited not by the number
435 * of components but by the number of binding table entries we set aside. We
436 * use one binding table entry for a float, one entry for a vector, and one
437 * entry per matrix column. Since the only way we can communicate our
438 * transform feedback capabilities to the client is via
439 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
440 * worst case, in which all the varyings are floats, so we use up one binding
441 * table entry per component. Therefore we need to set aside at least 64
442 * binding table entries for use by transform feedback.
444 * Note: since we don't currently pack varyings, it is currently impossible
445 * for the client to actually use up all of these binding table entries--if
446 * all of their varyings were floats, they would run out of varying slots and
447 * fail to link. But that's a bug, so it seems prudent to go ahead and
448 * allocate the number of binding table entries we will need once the bug is
451 #define BRW_MAX_SOL_BINDINGS 64
453 /** Maximum number of actual buffers used for stream output */
454 #define BRW_MAX_SOL_BUFFERS 4
457 * Helpers to create Surface Binding Table indexes for draw buffers,
458 * textures, and constant buffers.
460 * Shader threads access surfaces via numeric handles, rather than directly
461 * using pointers. The binding table maps these numeric handles to the
462 * address of the actual buffer.
464 * For example, a shader might ask to sample from "surface 7." In this case,
465 * bind[7] would contain a pointer to a texture.
467 * Although the hardware supports separate binding tables per pipeline stage
468 * (VS, HS, DS, GS, PS), we currently share a single binding table for all of
469 * them. This is purely for convenience.
471 * Currently our binding tables are (arbitrarily) programmed as follows:
473 * +-------------------------------+
474 * | 0 | Draw buffer 0 | .
476 * | : | : | > Only relevant to the WM.
477 * | 7 | Draw buffer 7 | /
478 * |-----|-------------------------| `
479 * | 8 | VS Pull Constant Buffer |
480 * | 9 | WM Pull Constant Buffer |
481 * |-----|-------------------------|
485 * | 25 | Texture 15 |
486 * +-----|-------------------------+
487 * | 26 | SOL Binding 0 |
490 * | 89 | SOL Binding 63 |
491 * +-------------------------------+
493 * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be
494 * the identity function or things will break. We do want to keep draw buffers
495 * first so we can use headerless render target writes for RT 0.
497 #define SURF_INDEX_DRAW(d) (d)
498 #define SURF_INDEX_VERT_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 0)
499 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
500 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
501 #define SURF_INDEX_SOL_BINDING(t) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + (t))
503 /** Maximum size of the binding table. */
504 #define BRW_MAX_SURFACES SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
508 BRW_DEPTH_STENCIL_STATE
,
509 BRW_COLOR_CALC_STATE
,
517 BRW_SF_UNIT
, /* scissor state on gen6 */
529 struct brw_cache_item
{
531 * Effectively part of the key, cache_id identifies what kind of state
532 * buffer is involved, and also which brw->state.dirty.cache flag should
533 * be set when this cache item is chosen.
535 enum brw_cache_id cache_id
;
536 /** 32-bit hash of the key data */
538 GLuint key_size
; /* for variable-sized keys */
545 struct brw_cache_item
*next
;
551 struct brw_context
*brw
;
553 struct brw_cache_item
**items
;
555 GLuint size
, n_items
;
557 uint32_t next_offset
;
562 /* Considered adding a member to this struct to document which flags
563 * an update might raise so that ordering of the state atoms can be
564 * checked or derived at runtime. Dropped the idea in favor of having
565 * a debug mode where the state is monitored for flags which are
566 * raised that have already been tested against.
568 struct brw_tracked_state
{
569 struct brw_state_flags dirty
;
570 void (*emit
)( struct brw_context
*brw
);
573 /* Flags for brw->state.cache.
575 #define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE)
576 #define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
577 #define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
578 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
579 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
580 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
581 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
582 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
583 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
584 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
585 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
586 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
587 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
588 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
589 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
590 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
591 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
592 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
594 struct brw_cached_batch_item
{
595 struct header
*header
;
597 struct brw_cached_batch_item
*next
;
602 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
603 * be easier if C allowed arrays of packed elements?
605 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
607 struct brw_vertex_buffer
{
608 /** Buffer object containing the uploaded vertex data */
611 /** Byte stride between elements in the uploaded array */
614 struct brw_vertex_element
{
615 const struct gl_client_array
*glarray
;
619 /** The corresponding Mesa vertex attribute */
620 gl_vert_attrib attrib
;
621 /** Size of a complete element */
623 /** Offset of the first element within the buffer object */
629 struct brw_vertex_info
{
630 GLuint sizes
[ATTRIB_BIT_DWORDS
* 2]; /* sizes:2[VERT_ATTRIB_MAX] */
633 struct brw_query_object
{
634 struct gl_query_object Base
;
636 /** Last query BO associated with this query. */
638 /** First index in bo with query data for this object. */
640 /** Last index in bo with query data for this object. */
646 * brw_context is derived from intel_context.
650 struct intel_context intel
; /**< base class, must be first field */
651 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
653 bool emit_state_always
;
654 bool has_surface_tile_offset
;
656 bool has_negative_rhw_bug
;
657 bool has_aa_line_parameters
;
662 struct brw_state_flags dirty
;
665 struct brw_cache cache
;
666 struct brw_cached_batch_item
*cached_batch_items
;
669 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
670 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
675 } current_buffers
[VERT_ATTRIB_MAX
];
677 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
679 GLuint nr_buffers
, nr_current_buffers
;
681 /* Summary of size and varying of active arrays, so we can check
682 * for changes to this state:
684 struct brw_vertex_info info
;
685 unsigned int min_index
, max_index
;
687 /* Offset from start of vertex buffer so we can avoid redefining
688 * the same VB packed over and over again.
690 unsigned int start_vertex_bias
;
695 * Index buffer for this draw_prims call.
697 * Updates are signaled by BRW_NEW_INDICES.
699 const struct _mesa_index_buffer
*ib
;
701 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
705 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
706 * avoid re-uploading the IB packet over and over if we're actually
707 * referencing the same index buffer.
709 unsigned int start_vertex_offset
;
712 /* Active vertex program:
714 const struct gl_vertex_program
*vertex_program
;
715 const struct gl_fragment_program
*fragment_program
;
717 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
718 uint32_t CMD_VF_STATISTICS
;
719 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
720 uint32_t CMD_PIPELINE_SELECT
;
723 * Platform specific constants containing the maximum number of threads
724 * for each pipeline stage.
730 /* BRW_NEW_URB_ALLOCATIONS:
733 GLuint vsize
; /* vertex size plus header in urb registers */
734 GLuint csize
; /* constant buffer size in urb registers */
735 GLuint sfsize
; /* setup data size in urb registers */
739 GLuint max_vs_entries
; /* Maximum number of VS entries */
740 GLuint max_gs_entries
; /* Maximum number of GS entries */
742 GLuint nr_vs_entries
;
743 GLuint nr_gs_entries
;
744 GLuint nr_clip_entries
;
745 GLuint nr_sf_entries
;
746 GLuint nr_cs_entries
;
749 * The length of each URB entry owned by the VS (or GS), as
750 * a number of 1024-bit (128-byte) rows. Should be >= 1.
752 * gen7: Same meaning, but in 512-bit (64-byte) rows.
762 GLuint size
; /* Hardware URB size, in KB. */
764 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
765 * URB space for the GS.
767 bool gen6_gs_previously_active
;
771 /* BRW_NEW_CURBE_OFFSETS:
774 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
775 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
782 drm_intel_bo
*curbe_bo
;
783 /** Offset within curbe_bo of space for current curbe entry */
785 /** Offset within curbe_bo of space for next curbe entry */
786 GLuint curbe_next_offset
;
789 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
790 * in brw_curbe.c with the same set of constant data to be uploaded,
791 * so we'd rather not upload new constants in that case (it can cause
792 * a pipeline bubble since only up to 4 can be pipelined at a time).
796 * Allocation for where to calculate the next set of CURBEs.
797 * It's a hot enough path that malloc/free of that data matters.
804 /** Binding table of pointers to surf_bo entries */
806 uint32_t surf_offset
[BRW_MAX_SURFACES
];
809 /** SAMPLER_STATE count and offset */
816 struct brw_vs_prog_data
*prog_data
;
817 int8_t *constant_map
; /* variable array following prog_data */
819 drm_intel_bo
*scratch_bo
;
820 drm_intel_bo
*const_bo
;
821 /** Offset in the program cache to the VS program */
822 uint32_t prog_offset
;
823 uint32_t state_offset
;
825 uint32_t push_const_offset
; /* Offset in the batchbuffer */
826 int push_const_size
; /* in 256-bit register increments */
828 /** @{ register allocator */
830 struct ra_regs
*regs
;
833 * Array of the ra classes for the unaligned contiguous register
839 * Mapping for register-allocated objects in *regs to the first
840 * GRF for that object.
842 uint8_t *ra_reg_to_grf
;
847 struct brw_gs_prog_data
*prog_data
;
850 /** Offset in the program cache to the CLIP program pre-gen6 */
851 uint32_t prog_offset
;
852 uint32_t state_offset
;
856 struct brw_clip_prog_data
*prog_data
;
858 /** Offset in the program cache to the CLIP program pre-gen6 */
859 uint32_t prog_offset
;
861 /* Offset in the batch to the CLIP state on pre-gen6. */
862 uint32_t state_offset
;
864 /* As of gen6, this is the offset in the batch to the CLIP VP,
872 struct brw_sf_prog_data
*prog_data
;
874 /** Offset in the program cache to the CLIP program pre-gen6 */
875 uint32_t prog_offset
;
876 uint32_t state_offset
;
881 struct brw_wm_prog_data
*prog_data
;
882 struct brw_wm_compile
*compile_data
;
884 /** Input sizes, calculated from active vertex program.
885 * One bit per fragment program input attribute.
887 GLbitfield input_size_masks
[4];
889 /** offsets in the batch to sampler default colors (texture border color)
891 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
895 drm_intel_bo
*scratch_bo
;
897 /** Offset in the program cache to the WM program */
898 uint32_t prog_offset
;
900 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
902 drm_intel_bo
*const_bo
; /* pull constant buffer. */
904 * This is offset in the batch to the push constants on gen6.
906 * Pre-gen6, push constants live in the CURBE.
908 uint32_t push_const_offset
;
910 /** @{ register allocator */
912 struct ra_regs
*regs
;
914 /** Array of the ra classes for the unaligned contiguous
915 * register block sizes used.
920 * Mapping for register-allocated objects in *regs to the first
921 * GRF for that object.
923 uint8_t *ra_reg_to_grf
;
926 * ra class for the aligned pairs we use for PLN, which doesn't
927 * appear in *classes.
929 int aligned_pairs_class
;
936 uint32_t state_offset
;
937 uint32_t blend_state_offset
;
938 uint32_t depth_stencil_state_offset
;
943 struct brw_query_object
*obj
;
948 /* Used to give every program string a unique id
953 const struct brw_tracked_state
**atoms
;
955 /* If (INTEL_DEBUG & DEBUG_BATCH) */
959 enum state_struct_type type
;
961 int state_batch_count
;
964 * \brief State needed to execute HiZ ops.
966 * \see gen6_hiz_init()
967 * \see gen6_hiz_exec()
969 struct brw_hiz_state
{
970 /** \brief VBO for rectangle primitive.
972 * Rather than using glGenBuffers(), we allocate the VBO directly
975 drm_intel_bo
*vertex_bo
;
978 struct brw_sol_state
{
979 uint32_t svbi_0_starting_index
;
980 uint32_t svbi_0_max_index
;
981 uint32_t offset_0_batch_start
;
982 uint32_t primitives_generated
;
983 uint32_t primitives_written
;
986 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
987 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
992 #define BRW_PACKCOLOR8888(r,g,b,a) ((r<<24) | (g<<16) | (b<<8) | a)
994 struct brw_instruction_info
{
1000 extern const struct brw_instruction_info brw_opcodes
[128];
1002 /*======================================================================
1005 void brwInitVtbl( struct brw_context
*brw
);
1007 /*======================================================================
1010 bool brwCreateContext(int api
,
1011 const struct gl_config
*mesaVis
,
1012 __DRIcontext
*driContextPriv
,
1013 void *sharedContextPrivate
);
1015 /*======================================================================
1018 void brw_init_queryobj_functions(struct dd_function_table
*functions
);
1019 void brw_prepare_query_begin(struct brw_context
*brw
);
1020 void brw_emit_query_begin(struct brw_context
*brw
);
1021 void brw_emit_query_end(struct brw_context
*brw
);
1023 /*======================================================================
1026 void brw_debug_batch(struct intel_context
*intel
);
1028 /*======================================================================
1031 void brw_validate_textures( struct brw_context
*brw
);
1034 /*======================================================================
1037 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1039 int brw_get_scratch_size(int size
);
1040 void brw_get_scratch_bo(struct intel_context
*intel
,
1041 drm_intel_bo
**scratch_bo
, int size
);
1046 void brw_upload_urb_fence(struct brw_context
*brw
);
1050 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1053 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1056 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1058 /* brw_wm_surface_state.c */
1059 void brw_init_surface_formats(struct brw_context
*brw
);
1061 brw_update_sol_surface(struct brw_context
*brw
,
1062 struct gl_buffer_object
*buffer_obj
,
1063 uint32_t *out_offset
, unsigned num_vector_components
,
1064 unsigned stride_dwords
, unsigned offset_dwords
);
1066 /* gen6_clip_state.c */
1068 brw_fprog_uses_noperspective(const struct gl_fragment_program
*fprog
);
1072 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1073 struct gl_transform_feedback_object
*obj
);
1075 brw_end_transform_feedback(struct gl_context
*ctx
,
1076 struct gl_transform_feedback_object
*obj
);
1078 /* gen7_sol_state.c */
1080 gen7_end_transform_feedback(struct gl_context
*ctx
,
1081 struct gl_transform_feedback_object
*obj
);
1085 /*======================================================================
1086 * Inline conversion functions. These are better-typed than the
1087 * macros used previously:
1089 static INLINE
struct brw_context
*
1090 brw_context( struct gl_context
*ctx
)
1092 return (struct brw_context
*)ctx
;
1095 static INLINE
struct brw_vertex_program
*
1096 brw_vertex_program(struct gl_vertex_program
*p
)
1098 return (struct brw_vertex_program
*) p
;
1101 static INLINE
const struct brw_vertex_program
*
1102 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1104 return (const struct brw_vertex_program
*) p
;
1107 static INLINE
struct brw_fragment_program
*
1108 brw_fragment_program(struct gl_fragment_program
*p
)
1110 return (struct brw_fragment_program
*) p
;
1113 static INLINE
const struct brw_fragment_program
*
1114 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1116 return (const struct brw_fragment_program
*) p
;
1120 float convert_param(enum param_conversion conversion
, const float *param
)
1128 switch (conversion
) {
1129 case PARAM_NO_CONVERT
:
1131 case PARAM_CONVERT_F2I
:
1134 case PARAM_CONVERT_F2U
:
1137 case PARAM_CONVERT_F2B
:
1143 case PARAM_CONVERT_ZERO
:
1151 * Pre-gen6, the register file of the EUs was shared between threads,
1152 * and each thread used some subset allocated on a 16-register block
1153 * granularity. The unit states wanted these block counts.
1156 brw_register_blocks(int reg_count
)
1158 return ALIGN(reg_count
, 16) / 16 - 1;
1161 static inline uint32_t
1162 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1163 uint32_t prog_offset
)
1165 struct intel_context
*intel
= &brw
->intel
;
1167 if (intel
->gen
>= 5) {
1168 /* Using state base address. */
1172 drm_intel_bo_emit_reloc(intel
->batch
.bo
,
1176 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1178 return brw
->cache
.bo
->offset
+ prog_offset
;
1181 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);