i965: Allocate register sets at screen creation, not context creation.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_context.h
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
35
36 #include <stdbool.h>
37 #include <string.h>
38 #include "main/imports.h"
39 #include "main/macros.h"
40 #include "main/mm.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43
44 #ifdef __cplusplus
45 extern "C" {
46 /* Evil hack for using libdrm in a c++ compiler. */
47 #define virtual virt
48 #endif
49
50 #include <drm.h>
51 #include <intel_bufmgr.h>
52 #include <i915_drm.h>
53 #ifdef __cplusplus
54 #undef virtual
55 }
56 #endif
57
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
64 #include "intel_resolve_map.h"
65
66 /* Glossary:
67 *
68 * URB - uniform resource buffer. A mid-sized buffer which is
69 * partitioned between the fixed function units and used for passing
70 * values (vertices, primitives, constants) between them.
71 *
72 * CURBE - constant URB entry. An urb region (entry) used to hold
73 * constant values which the fixed function units can be instructed to
74 * preload into the GRF when spawning a thread.
75 *
76 * VUE - vertex URB entry. An urb entry holding a vertex and usually
77 * a vertex header. The header contains control information and
78 * things like primitive type, Begin/end flags and clip codes.
79 *
80 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
81 * unit holding rasterization and interpolation parameters.
82 *
83 * GRF - general register file. One of several register files
84 * addressable by programmed threads. The inputs (r0, payload, curbe,
85 * urb) of the thread are preloaded to this area before the thread is
86 * spawned. The registers are individually 8 dwords wide and suitable
87 * for general usage. Registers holding thread input values are not
88 * special and may be overwritten.
89 *
90 * MRF - message register file. Threads communicate (and terminate)
91 * by sending messages. Message parameters are placed in contiguous
92 * MRF registers. All program output is via these messages. URB
93 * entries are populated by sending a message to the shared URB
94 * function containing the new data, together with a control word,
95 * often an unmodified copy of R0.
96 *
97 * R0 - GRF register 0. Typically holds control information used when
98 * sending messages to other threads.
99 *
100 * EU or GEN4 EU: The name of the programmable subsystem of the
101 * i965 hardware. Threads are executed by the EU, the registers
102 * described above are part of the EU architecture.
103 *
104 * Fixed function units:
105 *
106 * CS - Command streamer. Notional first unit, little software
107 * interaction. Holds the URB entries used for constant data, ie the
108 * CURBEs.
109 *
110 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
111 * this unit is responsible for pulling vertices out of vertex buffers
112 * in vram and injecting them into the processing pipe as VUEs. If
113 * enabled, it first passes them to a VS thread which is a good place
114 * for the driver to implement any active vertex shader.
115 *
116 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
117 * enabled, incoming strips etc are passed to GS threads in individual
118 * line/triangle/point units. The GS thread may perform arbitary
119 * computation and emit whatever primtives with whatever vertices it
120 * chooses. This makes GS an excellent place to implement GL's
121 * unfilled polygon modes, though of course it is capable of much
122 * more. Additionally, GS is used to translate away primitives not
123 * handled by latter units, including Quads and Lineloops.
124 *
125 * CS - Clipper. Mesa's clipping algorithms are imported to run on
126 * this unit. The fixed function part performs cliptesting against
127 * the 6 fixed clipplanes and makes descisions on whether or not the
128 * incoming primitive needs to be passed to a thread for clipping.
129 * User clip planes are handled via cooperation with the VS thread.
130 *
131 * SF - Strips Fans or Setup: Triangles are prepared for
132 * rasterization. Interpolation coefficients are calculated.
133 * Flatshading and two-side lighting usually performed here.
134 *
135 * WM - Windower. Interpolation of vertex attributes performed here.
136 * Fragment shader implemented here. SIMD aspects of EU taken full
137 * advantage of, as pixels are processed in blocks of 16.
138 *
139 * CC - Color Calculator. No EU threads associated with this unit.
140 * Handles blending and (presumably) depth and stencil testing.
141 */
142
143 #define BRW_MAX_CURBE (32*16)
144
145 struct brw_context;
146 struct brw_instruction;
147 struct brw_vs_prog_key;
148 struct brw_vec4_prog_key;
149 struct brw_wm_prog_key;
150 struct brw_wm_prog_data;
151
152 enum brw_state_id {
153 BRW_STATE_URB_FENCE,
154 BRW_STATE_FRAGMENT_PROGRAM,
155 BRW_STATE_GEOMETRY_PROGRAM,
156 BRW_STATE_VERTEX_PROGRAM,
157 BRW_STATE_CURBE_OFFSETS,
158 BRW_STATE_REDUCED_PRIMITIVE,
159 BRW_STATE_PRIMITIVE,
160 BRW_STATE_CONTEXT,
161 BRW_STATE_PSP,
162 BRW_STATE_SURFACES,
163 BRW_STATE_VS_BINDING_TABLE,
164 BRW_STATE_GS_BINDING_TABLE,
165 BRW_STATE_PS_BINDING_TABLE,
166 BRW_STATE_INDICES,
167 BRW_STATE_VERTICES,
168 BRW_STATE_BATCH,
169 BRW_STATE_INDEX_BUFFER,
170 BRW_STATE_VS_CONSTBUF,
171 BRW_STATE_GS_CONSTBUF,
172 BRW_STATE_PROGRAM_CACHE,
173 BRW_STATE_STATE_BASE_ADDRESS,
174 BRW_STATE_VUE_MAP_VS,
175 BRW_STATE_VUE_MAP_GEOM_OUT,
176 BRW_STATE_TRANSFORM_FEEDBACK,
177 BRW_STATE_RASTERIZER_DISCARD,
178 BRW_STATE_STATS_WM,
179 BRW_STATE_UNIFORM_BUFFER,
180 BRW_STATE_ATOMIC_BUFFER,
181 BRW_STATE_META_IN_PROGRESS,
182 BRW_STATE_INTERPOLATION_MAP,
183 BRW_STATE_PUSH_CONSTANT_ALLOCATION,
184 BRW_NUM_STATE_BITS
185 };
186
187 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
188 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
189 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
190 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
191 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
192 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
193 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
194 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
195 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
196 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
197 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
198 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
199 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
200 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
201 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
202 /**
203 * Used for any batch entry with a relocated pointer that will be used
204 * by any 3D rendering.
205 */
206 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
207 /** \see brw.state.depth_region */
208 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
209 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
210 #define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
211 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
212 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
213 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
214 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
215 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
216 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
217 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
218 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
219 #define BRW_NEW_ATOMIC_BUFFER (1 << BRW_STATE_ATOMIC_BUFFER)
220 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
221 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
222 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
223
224 struct brw_state_flags {
225 /** State update flags signalled by mesa internals */
226 GLuint mesa;
227 /**
228 * State update flags signalled as the result of brw_tracked_state updates
229 */
230 GLuint brw;
231 /** State update flags signalled by brw_state_cache.c searches */
232 GLuint cache;
233 };
234
235 #define AUB_TRACE_TYPE_MASK 0x0000ff00
236 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
237 #define AUB_TRACE_TYPE_BATCH (1 << 8)
238 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
239 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
240 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
241 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
242 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
243 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
244 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
245 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
246 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
247 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
248
249 /**
250 * state_struct_type enum values are encoded with the top 16 bits representing
251 * the type to be delivered to the .aub file, and the bottom 16 bits
252 * representing the subtype. This macro performs the encoding.
253 */
254 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
255
256 enum state_struct_type {
257 AUB_TRACE_VS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 1),
258 AUB_TRACE_GS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 2),
259 AUB_TRACE_CLIP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 3),
260 AUB_TRACE_SF_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 4),
261 AUB_TRACE_WM_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 5),
262 AUB_TRACE_CC_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 6),
263 AUB_TRACE_CLIP_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 7),
264 AUB_TRACE_SF_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 8),
265 AUB_TRACE_CC_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x9),
266 AUB_TRACE_SAMPLER_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xa),
267 AUB_TRACE_KERNEL_INSTRUCTIONS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xb),
268 AUB_TRACE_SCRATCH_SPACE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xc),
269 AUB_TRACE_SAMPLER_DEFAULT_COLOR = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xd),
270
271 AUB_TRACE_SCISSOR_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x15),
272 AUB_TRACE_BLEND_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x16),
273 AUB_TRACE_DEPTH_STENCIL_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x17),
274
275 AUB_TRACE_VERTEX_BUFFER = ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER, 0),
276 AUB_TRACE_BINDING_TABLE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x100),
277 AUB_TRACE_SURFACE_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x200),
278 AUB_TRACE_VS_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 0),
279 AUB_TRACE_WM_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 1),
280 };
281
282 /**
283 * Decode a state_struct_type value to determine the type that should be
284 * stored in the .aub file.
285 */
286 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type)
287 {
288 return (ss_type & 0xFFFF0000) >> 16;
289 }
290
291 /**
292 * Decode a state_struct_type value to determine the subtype that should be
293 * stored in the .aub file.
294 */
295 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type)
296 {
297 return ss_type & 0xFFFF;
298 }
299
300 /** Subclass of Mesa vertex program */
301 struct brw_vertex_program {
302 struct gl_vertex_program program;
303 GLuint id;
304 };
305
306
307 /** Subclass of Mesa geometry program */
308 struct brw_geometry_program {
309 struct gl_geometry_program program;
310 unsigned id; /**< serial no. to identify geom progs, never re-used */
311 };
312
313
314 /** Subclass of Mesa fragment program */
315 struct brw_fragment_program {
316 struct gl_fragment_program program;
317 GLuint id; /**< serial no. to identify frag progs, never re-used */
318 };
319
320
321 /** Subclass of Mesa compute program */
322 struct brw_compute_program {
323 struct gl_compute_program program;
324 unsigned id; /**< serial no. to identify compute progs, never re-used */
325 };
326
327
328 struct brw_shader {
329 struct gl_shader base;
330
331 bool compiled_once;
332 };
333
334 /* Note: If adding fields that need anything besides a normal memcmp() for
335 * comparing them, be sure to go fix brw_stage_prog_data_compare().
336 */
337 struct brw_stage_prog_data {
338 struct {
339 /** size of our binding table. */
340 uint32_t size_bytes;
341
342 /** @{
343 * surface indices for the various groups of surfaces
344 */
345 uint32_t pull_constants_start;
346 uint32_t texture_start;
347 uint32_t gather_texture_start;
348 uint32_t ubo_start;
349 uint32_t abo_start;
350 uint32_t shader_time_start;
351 /** @} */
352 } binding_table;
353
354 GLuint nr_params; /**< number of float params/constants */
355 GLuint nr_pull_params;
356
357 /* Pointers to tracked values (only valid once
358 * _mesa_load_state_parameters has been called at runtime).
359 *
360 * These must be the last fields of the struct (see
361 * brw_stage_prog_data_compare()).
362 */
363 const float **param;
364 const float **pull_param;
365 };
366
367 /* Data about a particular attempt to compile a program. Note that
368 * there can be many of these, each in a different GL state
369 * corresponding to a different brw_wm_prog_key struct, with different
370 * compiled programs.
371 *
372 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
373 * struct!
374 */
375 struct brw_wm_prog_data {
376 struct brw_stage_prog_data base;
377
378 GLuint curb_read_length;
379 GLuint num_varying_inputs;
380
381 GLuint first_curbe_grf;
382 GLuint first_curbe_grf_16;
383 GLuint reg_blocks;
384 GLuint reg_blocks_16;
385 GLuint total_scratch;
386
387 struct {
388 /** @{
389 * surface indices the WM-specific surfaces
390 */
391 uint32_t render_target_start;
392 /** @} */
393 } binding_table;
394
395 bool dual_src_blend;
396 bool uses_pos_offset;
397 bool uses_omask;
398 uint32_t prog_offset_16;
399
400 /**
401 * Mask of which interpolation modes are required by the fragment shader.
402 * Used in hardware setup on gen6+.
403 */
404 uint32_t barycentric_interp_modes;
405
406 /**
407 * Map from gl_varying_slot to the position within the FS setup data
408 * payload where the varying's attribute vertex deltas should be delivered.
409 * For varying slots that are not used by the FS, the value is -1.
410 */
411 int urb_setup[VARYING_SLOT_MAX];
412 };
413
414 /**
415 * Enum representing the i965-specific vertex results that don't correspond
416 * exactly to any element of gl_varying_slot. The values of this enum are
417 * assigned such that they don't conflict with gl_varying_slot.
418 */
419 typedef enum
420 {
421 BRW_VARYING_SLOT_NDC = VARYING_SLOT_MAX,
422 BRW_VARYING_SLOT_PAD,
423 /**
424 * Technically this is not a varying but just a placeholder that
425 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
426 * builtin variable to be compiled correctly. see compile_sf_prog() for
427 * more info.
428 */
429 BRW_VARYING_SLOT_PNTC,
430 BRW_VARYING_SLOT_COUNT
431 } brw_varying_slot;
432
433
434 /**
435 * Data structure recording the relationship between the gl_varying_slot enum
436 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
437 * single octaword within the VUE (128 bits).
438 *
439 * Note that each BRW register contains 256 bits (2 octawords), so when
440 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
441 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
442 * in a vertex shader), each register corresponds to a single VUE slot, since
443 * it contains data for two separate vertices.
444 */
445 struct brw_vue_map {
446 /**
447 * Bitfield representing all varying slots that are (a) stored in this VUE
448 * map, and (b) actually written by the shader. Does not include any of
449 * the additional varying slots defined in brw_varying_slot.
450 */
451 GLbitfield64 slots_valid;
452
453 /**
454 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
455 * not stored in a slot (because they are not written, or because
456 * additional processing is applied before storing them in the VUE), the
457 * value is -1.
458 */
459 signed char varying_to_slot[BRW_VARYING_SLOT_COUNT];
460
461 /**
462 * Map from VUE slot to gl_varying_slot value. For slots that do not
463 * directly correspond to a gl_varying_slot, the value comes from
464 * brw_varying_slot.
465 *
466 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
467 * simplifies code that uses the value stored in slot_to_varying to
468 * create a bit mask).
469 */
470 signed char slot_to_varying[BRW_VARYING_SLOT_COUNT];
471
472 /**
473 * Total number of VUE slots in use
474 */
475 int num_slots;
476 };
477
478 /**
479 * Convert a VUE slot number into a byte offset within the VUE.
480 */
481 static inline GLuint brw_vue_slot_to_offset(GLuint slot)
482 {
483 return 16*slot;
484 }
485
486 /**
487 * Convert a vertex output (brw_varying_slot) into a byte offset within the
488 * VUE.
489 */
490 static inline GLuint brw_varying_to_offset(struct brw_vue_map *vue_map,
491 GLuint varying)
492 {
493 return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
494 }
495
496 void brw_compute_vue_map(struct brw_context *brw, struct brw_vue_map *vue_map,
497 GLbitfield64 slots_valid);
498
499
500 /**
501 * Bitmask indicating which fragment shader inputs represent varyings (and
502 * hence have to be delivered to the fragment shader by the SF/SBE stage).
503 */
504 #define BRW_FS_VARYING_INPUT_MASK \
505 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
506 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
507
508
509 /*
510 * Mapping of VUE map slots to interpolation modes.
511 */
512 struct interpolation_mode_map {
513 unsigned char mode[BRW_VARYING_SLOT_COUNT];
514 };
515
516 static inline bool brw_any_flat_varyings(struct interpolation_mode_map *map)
517 {
518 for (int i = 0; i < BRW_VARYING_SLOT_COUNT; i++)
519 if (map->mode[i] == INTERP_QUALIFIER_FLAT)
520 return true;
521
522 return false;
523 }
524
525 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map *map)
526 {
527 for (int i = 0; i < BRW_VARYING_SLOT_COUNT; i++)
528 if (map->mode[i] == INTERP_QUALIFIER_NOPERSPECTIVE)
529 return true;
530
531 return false;
532 }
533
534
535 struct brw_sf_prog_data {
536 GLuint urb_read_length;
537 GLuint total_grf;
538
539 /* Each vertex may have upto 12 attributes, 4 components each,
540 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
541 * rows.
542 *
543 * Actually we use 4 for each, so call it 12 rows.
544 */
545 GLuint urb_entry_size;
546 };
547
548
549 /**
550 * We always program SF to start reading at an offset of 1 (2 varying slots)
551 * from the start of the vertex URB entry. This causes it to skip:
552 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
553 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
554 */
555 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
556
557
558 struct brw_clip_prog_data {
559 GLuint curb_read_length; /* user planes? */
560 GLuint clip_mode;
561 GLuint urb_read_length;
562 GLuint total_grf;
563 };
564
565 struct brw_ff_gs_prog_data {
566 GLuint urb_read_length;
567 GLuint total_grf;
568
569 /**
570 * Gen6 transform feedback: Amount by which the streaming vertex buffer
571 * indices should be incremented each time the GS is invoked.
572 */
573 unsigned svbi_postincrement_value;
574 };
575
576
577 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
578 * this struct!
579 */
580 struct brw_vec4_prog_data {
581 struct brw_stage_prog_data base;
582 struct brw_vue_map vue_map;
583
584 /**
585 * Register where the thread expects to find input data from the URB
586 * (typically uniforms, followed by per-vertex inputs).
587 */
588 unsigned dispatch_grf_start_reg;
589
590 GLuint curb_read_length;
591 GLuint urb_read_length;
592 GLuint total_grf;
593 GLuint total_scratch;
594
595 /* Used for calculating urb partitions. In the VS, this is the size of the
596 * URB entry used for both input and output to the thread. In the GS, this
597 * is the size of the URB entry used for output.
598 */
599 GLuint urb_entry_size;
600 };
601
602
603 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
604 * struct!
605 */
606 struct brw_vs_prog_data {
607 struct brw_vec4_prog_data base;
608
609 GLbitfield64 inputs_read;
610
611 bool uses_vertexid;
612 };
613
614
615 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
616 * this struct!
617 */
618 struct brw_gs_prog_data
619 {
620 struct brw_vec4_prog_data base;
621
622 /**
623 * Size of an output vertex, measured in HWORDS (32 bytes).
624 */
625 unsigned output_vertex_size_hwords;
626
627 unsigned output_topology;
628
629 /**
630 * Size of the control data (cut bits or StreamID bits), in hwords (32
631 * bytes). 0 if there is no control data.
632 */
633 unsigned control_data_header_size_hwords;
634
635 /**
636 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
637 * if the control data is StreamID bits, or
638 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
639 * Ignored if control_data_header_size is 0.
640 */
641 unsigned control_data_format;
642
643 bool include_primitive_id;
644
645 int invocations;
646
647 /**
648 * True if the thread should be dispatched in DUAL_INSTANCE mode, false if
649 * it should be dispatched in DUAL_OBJECT mode.
650 */
651 bool dual_instanced_dispatch;
652 };
653
654 /** Number of texture sampler units */
655 #define BRW_MAX_TEX_UNIT 32
656
657 /** Max number of render targets in a shader */
658 #define BRW_MAX_DRAW_BUFFERS 8
659
660 /** Max number of atomic counter buffer objects in a shader */
661 #define BRW_MAX_ABO 16
662
663 /**
664 * Max number of binding table entries used for stream output.
665 *
666 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
667 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
668 *
669 * On Gen6, the size of transform feedback data is limited not by the number
670 * of components but by the number of binding table entries we set aside. We
671 * use one binding table entry for a float, one entry for a vector, and one
672 * entry per matrix column. Since the only way we can communicate our
673 * transform feedback capabilities to the client is via
674 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
675 * worst case, in which all the varyings are floats, so we use up one binding
676 * table entry per component. Therefore we need to set aside at least 64
677 * binding table entries for use by transform feedback.
678 *
679 * Note: since we don't currently pack varyings, it is currently impossible
680 * for the client to actually use up all of these binding table entries--if
681 * all of their varyings were floats, they would run out of varying slots and
682 * fail to link. But that's a bug, so it seems prudent to go ahead and
683 * allocate the number of binding table entries we will need once the bug is
684 * fixed.
685 */
686 #define BRW_MAX_SOL_BINDINGS 64
687
688 /** Maximum number of actual buffers used for stream output */
689 #define BRW_MAX_SOL_BUFFERS 4
690
691 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
692 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
693 12 + /* ubo */ \
694 BRW_MAX_ABO + \
695 2 /* shader time, pull constants */)
696
697 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
698 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
699
700 /**
701 * Stride in bytes between shader_time entries.
702 *
703 * We separate entries by a cacheline to reduce traffic between EUs writing to
704 * different entries.
705 */
706 #define SHADER_TIME_STRIDE 64
707
708 enum brw_cache_id {
709 BRW_CC_VP,
710 BRW_CC_UNIT,
711 BRW_WM_PROG,
712 BRW_BLORP_BLIT_PROG,
713 BRW_BLORP_CONST_COLOR_PROG,
714 BRW_SAMPLER,
715 BRW_WM_UNIT,
716 BRW_SF_PROG,
717 BRW_SF_VP,
718 BRW_SF_UNIT, /* scissor state on gen6 */
719 BRW_VS_UNIT,
720 BRW_VS_PROG,
721 BRW_FF_GS_UNIT,
722 BRW_FF_GS_PROG,
723 BRW_GS_PROG,
724 BRW_CLIP_VP,
725 BRW_CLIP_UNIT,
726 BRW_CLIP_PROG,
727
728 BRW_MAX_CACHE
729 };
730
731 struct brw_cache_item {
732 /**
733 * Effectively part of the key, cache_id identifies what kind of state
734 * buffer is involved, and also which brw->state.dirty.cache flag should
735 * be set when this cache item is chosen.
736 */
737 enum brw_cache_id cache_id;
738 /** 32-bit hash of the key data */
739 GLuint hash;
740 GLuint key_size; /* for variable-sized keys */
741 GLuint aux_size;
742 const void *key;
743
744 uint32_t offset;
745 uint32_t size;
746
747 struct brw_cache_item *next;
748 };
749
750
751 typedef bool (*cache_aux_compare_func)(const void *a, const void *b);
752 typedef void (*cache_aux_free_func)(const void *aux);
753
754 struct brw_cache {
755 struct brw_context *brw;
756
757 struct brw_cache_item **items;
758 drm_intel_bo *bo;
759 GLuint size, n_items;
760
761 uint32_t next_offset;
762 bool bo_used_by_gpu;
763
764 /**
765 * Optional functions used in determining whether the prog_data for a new
766 * cache item matches an existing cache item (in case there's relevant data
767 * outside of the prog_data). If NULL, a plain memcmp is done.
768 */
769 cache_aux_compare_func aux_compare[BRW_MAX_CACHE];
770 /** Optional functions for freeing other pointers attached to a prog_data. */
771 cache_aux_free_func aux_free[BRW_MAX_CACHE];
772 };
773
774
775 /* Considered adding a member to this struct to document which flags
776 * an update might raise so that ordering of the state atoms can be
777 * checked or derived at runtime. Dropped the idea in favor of having
778 * a debug mode where the state is monitored for flags which are
779 * raised that have already been tested against.
780 */
781 struct brw_tracked_state {
782 struct brw_state_flags dirty;
783 void (*emit)( struct brw_context *brw );
784 };
785
786 enum shader_time_shader_type {
787 ST_NONE,
788 ST_VS,
789 ST_VS_WRITTEN,
790 ST_VS_RESET,
791 ST_GS,
792 ST_GS_WRITTEN,
793 ST_GS_RESET,
794 ST_FS8,
795 ST_FS8_WRITTEN,
796 ST_FS8_RESET,
797 ST_FS16,
798 ST_FS16_WRITTEN,
799 ST_FS16_RESET,
800 };
801
802 /* Flags for brw->state.cache.
803 */
804 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
805 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
806 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
807 #define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
808 #define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
809 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
810 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
811 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
812 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
813 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
814 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
815 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
816 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
817 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
818 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
819 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
820 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
821 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
822
823 struct brw_cached_batch_item {
824 struct header *header;
825 GLuint sz;
826 struct brw_cached_batch_item *next;
827 };
828
829 struct brw_vertex_buffer {
830 /** Buffer object containing the uploaded vertex data */
831 drm_intel_bo *bo;
832 uint32_t offset;
833 /** Byte stride between elements in the uploaded array */
834 GLuint stride;
835 GLuint step_rate;
836 };
837 struct brw_vertex_element {
838 const struct gl_client_array *glarray;
839
840 int buffer;
841
842 /** The corresponding Mesa vertex attribute */
843 gl_vert_attrib attrib;
844 /** Offset of the first element within the buffer object */
845 unsigned int offset;
846 };
847
848 struct brw_query_object {
849 struct gl_query_object Base;
850
851 /** Last query BO associated with this query. */
852 drm_intel_bo *bo;
853
854 /** Last index in bo with query data for this object. */
855 int last_index;
856 };
857
858 struct intel_sync_object {
859 struct gl_sync_object Base;
860
861 /** Batch associated with this sync object */
862 drm_intel_bo *bo;
863 };
864
865 enum brw_gpu_ring {
866 UNKNOWN_RING,
867 RENDER_RING,
868 BLT_RING,
869 };
870
871 struct intel_batchbuffer {
872 /** Current batchbuffer being queued up. */
873 drm_intel_bo *bo;
874 /** Last BO submitted to the hardware. Used for glFinish(). */
875 drm_intel_bo *last_bo;
876 /** BO for post-sync nonzero writes for gen6 workaround. */
877 drm_intel_bo *workaround_bo;
878 bool need_workaround_flush;
879
880 struct cached_batch_item *cached_items;
881
882 uint16_t emit, total;
883 uint16_t used, reserved_space;
884 uint32_t *map;
885 uint32_t *cpu_map;
886 #define BATCH_SZ (8192*sizeof(uint32_t))
887
888 uint32_t state_batch_offset;
889 enum brw_gpu_ring ring;
890 bool needs_sol_reset;
891
892 struct {
893 uint16_t used;
894 int reloc_count;
895 } saved;
896 };
897
898 #define BRW_MAX_XFB_STREAMS 4
899
900 struct brw_transform_feedback_object {
901 struct gl_transform_feedback_object base;
902
903 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
904 drm_intel_bo *offset_bo;
905
906 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
907 bool zero_offsets;
908
909 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
910 GLenum primitive_mode;
911
912 /**
913 * Count of primitives generated during this transform feedback operation.
914 * @{
915 */
916 uint64_t prims_generated[BRW_MAX_XFB_STREAMS];
917 drm_intel_bo *prim_count_bo;
918 unsigned prim_count_buffer_index; /**< in number of uint64_t units */
919 /** @} */
920
921 /**
922 * Number of vertices written between last Begin/EndTransformFeedback().
923 *
924 * Used to implement DrawTransformFeedback().
925 */
926 uint64_t vertices_written[BRW_MAX_XFB_STREAMS];
927 bool vertices_written_valid;
928 };
929
930 /**
931 * Data shared between each programmable stage in the pipeline (vs, gs, and
932 * wm).
933 */
934 struct brw_stage_state
935 {
936 struct brw_stage_prog_data *prog_data;
937
938 /**
939 * Optional scratch buffer used to store spilled register values and
940 * variably-indexed GRF arrays.
941 */
942 drm_intel_bo *scratch_bo;
943
944 /** Pull constant buffer */
945 drm_intel_bo *const_bo;
946
947 /** Offset in the program cache to the program */
948 uint32_t prog_offset;
949
950 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
951 uint32_t state_offset;
952
953 uint32_t push_const_offset; /* Offset in the batchbuffer */
954 int push_const_size; /* in 256-bit register increments */
955
956 /* Binding table: pointers to SURFACE_STATE entries. */
957 uint32_t bind_bo_offset;
958 uint32_t surf_offset[BRW_MAX_SURFACES];
959
960 /** SAMPLER_STATE count and table offset */
961 uint32_t sampler_count;
962 uint32_t sampler_offset;
963
964 /** Offsets in the batch to sampler default colors (texture border color) */
965 uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
966 };
967
968
969 /**
970 * brw_context is derived from gl_context.
971 */
972 struct brw_context
973 {
974 struct gl_context ctx; /**< base class, must be first field */
975
976 struct
977 {
978 void (*update_texture_surface)(struct gl_context *ctx,
979 unsigned unit,
980 uint32_t *surf_offset,
981 bool for_gather);
982 void (*update_renderbuffer_surface)(struct brw_context *brw,
983 struct gl_renderbuffer *rb,
984 bool layered,
985 unsigned unit);
986 void (*update_null_renderbuffer_surface)(struct brw_context *brw,
987 unsigned unit);
988
989 void (*create_raw_surface)(struct brw_context *brw,
990 drm_intel_bo *bo,
991 uint32_t offset,
992 uint32_t size,
993 uint32_t *out_offset,
994 bool rw);
995 void (*emit_buffer_surface_state)(struct brw_context *brw,
996 uint32_t *out_offset,
997 drm_intel_bo *bo,
998 unsigned buffer_offset,
999 unsigned surface_format,
1000 unsigned buffer_size,
1001 unsigned pitch,
1002 unsigned mocs,
1003 bool rw);
1004
1005 /** Upload a SAMPLER_STATE table. */
1006 void (*upload_sampler_state_table)(struct brw_context *brw,
1007 struct gl_program *prog,
1008 uint32_t sampler_count,
1009 uint32_t *sst_offset,
1010 uint32_t *sdc_offset);
1011
1012 /**
1013 * Send the appropriate state packets to configure depth, stencil, and
1014 * HiZ buffers (i965+ only)
1015 */
1016 void (*emit_depth_stencil_hiz)(struct brw_context *brw,
1017 struct intel_mipmap_tree *depth_mt,
1018 uint32_t depth_offset,
1019 uint32_t depthbuffer_format,
1020 uint32_t depth_surface_type,
1021 struct intel_mipmap_tree *stencil_mt,
1022 bool hiz, bool separate_stencil,
1023 uint32_t width, uint32_t height,
1024 uint32_t tile_x, uint32_t tile_y);
1025
1026 } vtbl;
1027
1028 dri_bufmgr *bufmgr;
1029
1030 drm_intel_context *hw_ctx;
1031
1032 /**
1033 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
1034 * and would need flushing before being used from another cache domain that
1035 * isn't coherent with it (i.e. the sampler).
1036 */
1037 struct set *render_cache;
1038
1039 /**
1040 * Number of resets observed in the system at context creation.
1041 *
1042 * This is tracked in the context so that we can determine that another
1043 * reset has occured.
1044 */
1045 uint32_t reset_count;
1046
1047 struct intel_batchbuffer batch;
1048 bool no_batch_wrap;
1049
1050 struct {
1051 drm_intel_bo *bo;
1052 GLuint offset;
1053 uint32_t buffer_len;
1054 uint32_t buffer_offset;
1055 char buffer[4096];
1056 } upload;
1057
1058 /**
1059 * Set if rendering has occured to the drawable's front buffer.
1060 *
1061 * This is used in the DRI2 case to detect that glFlush should also copy
1062 * the contents of the fake front buffer to the real front buffer.
1063 */
1064 bool front_buffer_dirty;
1065
1066 /** Framerate throttling: @{ */
1067 drm_intel_bo *first_post_swapbuffers_batch;
1068 bool need_throttle;
1069 /** @} */
1070
1071 GLuint stats_wm;
1072
1073 /**
1074 * drirc options:
1075 * @{
1076 */
1077 bool no_rast;
1078 bool always_flush_batch;
1079 bool always_flush_cache;
1080 bool disable_throttling;
1081 bool precompile;
1082 bool disable_derivative_optimization;
1083
1084 driOptionCache optionCache;
1085 /** @} */
1086
1087 GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1088
1089 GLenum reduced_primitive;
1090
1091 /**
1092 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1093 * variable is set, this is the flag indicating to do expensive work that
1094 * might lead to a perf_debug() call.
1095 */
1096 bool perf_debug;
1097
1098 uint32_t max_gtt_map_object_size;
1099
1100 int gen;
1101 int gt;
1102
1103 bool is_g4x;
1104 bool is_baytrail;
1105 bool is_haswell;
1106
1107 bool has_hiz;
1108 bool has_separate_stencil;
1109 bool must_use_separate_stencil;
1110 bool has_llc;
1111 bool has_swizzling;
1112 bool has_surface_tile_offset;
1113 bool has_compr4;
1114 bool has_negative_rhw_bug;
1115 bool has_pln;
1116
1117 /**
1118 * Some versions of Gen hardware don't do centroid interpolation correctly
1119 * on unlit pixels, causing incorrect values for derivatives near triangle
1120 * edges. Enabling this flag causes the fragment shader to use
1121 * non-centroid interpolation for unlit pixels, at the expense of two extra
1122 * fragment shader instructions.
1123 */
1124 bool needs_unlit_centroid_workaround;
1125
1126 GLuint NewGLState;
1127 struct {
1128 struct brw_state_flags dirty;
1129 } state;
1130
1131 struct brw_cache cache;
1132 struct brw_cached_batch_item *cached_batch_items;
1133
1134 /* Whether a meta-operation is in progress. */
1135 bool meta_in_progress;
1136
1137 struct {
1138 struct brw_vertex_element inputs[VERT_ATTRIB_MAX];
1139 struct brw_vertex_buffer buffers[VERT_ATTRIB_MAX];
1140
1141 struct brw_vertex_element *enabled[VERT_ATTRIB_MAX];
1142 GLuint nr_enabled;
1143 GLuint nr_buffers;
1144
1145 /* Summary of size and varying of active arrays, so we can check
1146 * for changes to this state:
1147 */
1148 unsigned int min_index, max_index;
1149
1150 /* Offset from start of vertex buffer so we can avoid redefining
1151 * the same VB packed over and over again.
1152 */
1153 unsigned int start_vertex_bias;
1154 } vb;
1155
1156 struct {
1157 /**
1158 * Index buffer for this draw_prims call.
1159 *
1160 * Updates are signaled by BRW_NEW_INDICES.
1161 */
1162 const struct _mesa_index_buffer *ib;
1163
1164 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1165 drm_intel_bo *bo;
1166 GLuint type;
1167
1168 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1169 * avoid re-uploading the IB packet over and over if we're actually
1170 * referencing the same index buffer.
1171 */
1172 unsigned int start_vertex_offset;
1173 } ib;
1174
1175 /* Active vertex program:
1176 */
1177 const struct gl_vertex_program *vertex_program;
1178 const struct gl_geometry_program *geometry_program;
1179 const struct gl_fragment_program *fragment_program;
1180
1181 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
1182 uint32_t CMD_VF_STATISTICS;
1183 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
1184 uint32_t CMD_PIPELINE_SELECT;
1185
1186 /**
1187 * Platform specific constants containing the maximum number of threads
1188 * for each pipeline stage.
1189 */
1190 int max_vs_threads;
1191 int max_gs_threads;
1192 int max_wm_threads;
1193
1194 /* BRW_NEW_URB_ALLOCATIONS:
1195 */
1196 struct {
1197 GLuint vsize; /* vertex size plus header in urb registers */
1198 GLuint csize; /* constant buffer size in urb registers */
1199 GLuint sfsize; /* setup data size in urb registers */
1200
1201 bool constrained;
1202
1203 GLuint min_vs_entries; /* Minimum number of VS entries */
1204 GLuint max_vs_entries; /* Maximum number of VS entries */
1205 GLuint max_gs_entries; /* Maximum number of GS entries */
1206
1207 GLuint nr_vs_entries;
1208 GLuint nr_gs_entries;
1209 GLuint nr_clip_entries;
1210 GLuint nr_sf_entries;
1211 GLuint nr_cs_entries;
1212
1213 GLuint vs_start;
1214 GLuint gs_start;
1215 GLuint clip_start;
1216 GLuint sf_start;
1217 GLuint cs_start;
1218 GLuint size; /* Hardware URB size, in KB. */
1219
1220 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1221 * URB space for the GS.
1222 */
1223 bool gen6_gs_previously_active;
1224 } urb;
1225
1226
1227 /* BRW_NEW_CURBE_OFFSETS:
1228 */
1229 struct {
1230 GLuint wm_start; /**< pos of first wm const in CURBE buffer */
1231 GLuint wm_size; /**< number of float[4] consts, multiple of 16 */
1232 GLuint clip_start;
1233 GLuint clip_size;
1234 GLuint vs_start;
1235 GLuint vs_size;
1236 GLuint total_size;
1237
1238 drm_intel_bo *curbe_bo;
1239 /** Offset within curbe_bo of space for current curbe entry */
1240 GLuint curbe_offset;
1241 /** Offset within curbe_bo of space for next curbe entry */
1242 GLuint curbe_next_offset;
1243
1244 /**
1245 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
1246 * in brw_curbe.c with the same set of constant data to be uploaded,
1247 * so we'd rather not upload new constants in that case (it can cause
1248 * a pipeline bubble since only up to 4 can be pipelined at a time).
1249 */
1250 GLfloat *last_buf;
1251 /**
1252 * Allocation for where to calculate the next set of CURBEs.
1253 * It's a hot enough path that malloc/free of that data matters.
1254 */
1255 GLfloat *next_buf;
1256 GLuint last_bufsz;
1257 } curbe;
1258
1259 /**
1260 * Layout of vertex data exiting the vertex shader.
1261 *
1262 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1263 */
1264 struct brw_vue_map vue_map_vs;
1265
1266 /**
1267 * Layout of vertex data exiting the geometry portion of the pipleine.
1268 * This comes from the geometry shader if one exists, otherwise from the
1269 * vertex shader.
1270 *
1271 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1272 */
1273 struct brw_vue_map vue_map_geom_out;
1274
1275 struct {
1276 struct brw_stage_state base;
1277 struct brw_vs_prog_data *prog_data;
1278 } vs;
1279
1280 struct {
1281 struct brw_stage_state base;
1282 struct brw_gs_prog_data *prog_data;
1283
1284 /**
1285 * True if the 3DSTATE_GS command most recently emitted to the 3D
1286 * pipeline enabled the GS; false otherwise.
1287 */
1288 bool enabled;
1289 } gs;
1290
1291 struct {
1292 struct brw_ff_gs_prog_data *prog_data;
1293
1294 bool prog_active;
1295 /** Offset in the program cache to the CLIP program pre-gen6 */
1296 uint32_t prog_offset;
1297 uint32_t state_offset;
1298
1299 uint32_t bind_bo_offset;
1300 uint32_t surf_offset[BRW_MAX_GEN6_GS_SURFACES];
1301 } ff_gs;
1302
1303 struct {
1304 struct brw_clip_prog_data *prog_data;
1305
1306 /** Offset in the program cache to the CLIP program pre-gen6 */
1307 uint32_t prog_offset;
1308
1309 /* Offset in the batch to the CLIP state on pre-gen6. */
1310 uint32_t state_offset;
1311
1312 /* As of gen6, this is the offset in the batch to the CLIP VP,
1313 * instead of vp_bo.
1314 */
1315 uint32_t vp_offset;
1316 } clip;
1317
1318
1319 struct {
1320 struct brw_sf_prog_data *prog_data;
1321
1322 /** Offset in the program cache to the CLIP program pre-gen6 */
1323 uint32_t prog_offset;
1324 uint32_t state_offset;
1325 uint32_t vp_offset;
1326 } sf;
1327
1328 struct {
1329 struct brw_stage_state base;
1330 struct brw_wm_prog_data *prog_data;
1331
1332 GLuint render_surf;
1333
1334 /**
1335 * Buffer object used in place of multisampled null render targets on
1336 * Gen6. See brw_update_null_renderbuffer_surface().
1337 */
1338 drm_intel_bo *multisampled_null_render_target_bo;
1339 } wm;
1340
1341
1342 struct {
1343 uint32_t state_offset;
1344 uint32_t blend_state_offset;
1345 uint32_t depth_stencil_state_offset;
1346 uint32_t vp_offset;
1347 } cc;
1348
1349 struct {
1350 struct brw_query_object *obj;
1351 bool begin_emitted;
1352 } query;
1353
1354 struct {
1355 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1356 const int *statistics_registers;
1357
1358 /** The number of active monitors using OA counters. */
1359 unsigned oa_users;
1360
1361 /**
1362 * A buffer object storing OA counter snapshots taken at the start and
1363 * end of each batch (creating "bookends" around the batch).
1364 */
1365 drm_intel_bo *bookend_bo;
1366
1367 /** The number of snapshots written to bookend_bo. */
1368 int bookend_snapshots;
1369
1370 /**
1371 * An array of monitors whose results haven't yet been assembled based on
1372 * the data in buffer objects.
1373 *
1374 * These may be active, or have already ended. However, the results
1375 * have not been requested.
1376 */
1377 struct brw_perf_monitor_object **unresolved;
1378 int unresolved_elements;
1379 int unresolved_array_size;
1380
1381 /**
1382 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1383 * the counter which MI_REPORT_PERF_COUNT stores there.
1384 */
1385 const int *oa_snapshot_layout;
1386
1387 /** Number of 32-bit entries in a hardware counter snapshot. */
1388 int entries_per_oa_snapshot;
1389 } perfmon;
1390
1391 int num_atoms;
1392 const struct brw_tracked_state **atoms;
1393
1394 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1395 struct {
1396 uint32_t offset;
1397 uint32_t size;
1398 enum state_struct_type type;
1399 } *state_batch_list;
1400 int state_batch_count;
1401
1402 uint32_t render_target_format[MESA_FORMAT_COUNT];
1403 bool format_supported_as_render_target[MESA_FORMAT_COUNT];
1404
1405 /* Interpolation modes, one byte per vue slot.
1406 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1407 */
1408 struct interpolation_mode_map interpolation_mode;
1409
1410 /* PrimitiveRestart */
1411 struct {
1412 bool in_progress;
1413 bool enable_cut_index;
1414 } prim_restart;
1415
1416 /** Computed depth/stencil/hiz state from the current attached
1417 * renderbuffers, valid only during the drawing state upload loop after
1418 * brw_workaround_depthstencil_alignment().
1419 */
1420 struct {
1421 struct intel_mipmap_tree *depth_mt;
1422 struct intel_mipmap_tree *stencil_mt;
1423
1424 /* Inter-tile (page-aligned) byte offsets. */
1425 uint32_t depth_offset, hiz_offset, stencil_offset;
1426 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1427 uint32_t tile_x, tile_y;
1428 } depthstencil;
1429
1430 uint32_t num_instances;
1431 int basevertex;
1432
1433 struct {
1434 drm_intel_bo *bo;
1435 struct gl_shader_program **shader_programs;
1436 struct gl_program **programs;
1437 enum shader_time_shader_type *types;
1438 uint64_t *cumulative;
1439 int num_entries;
1440 int max_entries;
1441 double report_time;
1442 } shader_time;
1443
1444 __DRIcontext *driContext;
1445 struct intel_screen *intelScreen;
1446 };
1447
1448 static inline bool
1449 is_power_of_two(uint32_t value)
1450 {
1451 return (value & (value - 1)) == 0;
1452 }
1453
1454 /*======================================================================
1455 * brw_vtbl.c
1456 */
1457 void brwInitVtbl( struct brw_context *brw );
1458
1459 /* brw_clear.c */
1460 extern void intelInitClearFuncs(struct dd_function_table *functions);
1461
1462 /*======================================================================
1463 * brw_context.c
1464 */
1465 extern const char *const brw_vendor_string;
1466
1467 extern const char *brw_get_renderer_string(unsigned deviceID);
1468
1469 extern void intelFinish(struct gl_context * ctx);
1470
1471 enum {
1472 DRI_CONF_BO_REUSE_DISABLED,
1473 DRI_CONF_BO_REUSE_ALL
1474 };
1475
1476 void intel_update_renderbuffers(__DRIcontext *context,
1477 __DRIdrawable *drawable);
1478 void intel_prepare_render(struct brw_context *brw);
1479
1480 void intel_resolve_for_dri2_flush(struct brw_context *brw,
1481 __DRIdrawable *drawable);
1482
1483 GLboolean brwCreateContext(gl_api api,
1484 const struct gl_config *mesaVis,
1485 __DRIcontext *driContextPriv,
1486 unsigned major_version,
1487 unsigned minor_version,
1488 uint32_t flags,
1489 bool notify_reset,
1490 unsigned *error,
1491 void *sharedContextPrivate);
1492
1493 /*======================================================================
1494 * brw_misc_state.c
1495 */
1496 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree *depth_mt,
1497 uint32_t depth_level,
1498 uint32_t depth_layer,
1499 struct intel_mipmap_tree *stencil_mt,
1500 uint32_t *out_tile_mask_x,
1501 uint32_t *out_tile_mask_y);
1502 void brw_workaround_depthstencil_alignment(struct brw_context *brw,
1503 GLbitfield clear_mask);
1504
1505 /* brw_object_purgeable.c */
1506 void brw_init_object_purgeable_functions(struct dd_function_table *functions);
1507
1508 /*======================================================================
1509 * brw_queryobj.c
1510 */
1511 void brw_init_common_queryobj_functions(struct dd_function_table *functions);
1512 void gen4_init_queryobj_functions(struct dd_function_table *functions);
1513 void brw_emit_query_begin(struct brw_context *brw);
1514 void brw_emit_query_end(struct brw_context *brw);
1515
1516 /** gen6_queryobj.c */
1517 void gen6_init_queryobj_functions(struct dd_function_table *functions);
1518 void brw_write_timestamp(struct brw_context *brw, drm_intel_bo *bo, int idx);
1519 void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *bo, int idx);
1520 void brw_store_register_mem64(struct brw_context *brw,
1521 drm_intel_bo *bo, uint32_t reg, int idx);
1522
1523 /** intel_batchbuffer.c */
1524 void brw_load_register_mem(struct brw_context *brw,
1525 uint32_t reg,
1526 drm_intel_bo *bo,
1527 uint32_t read_domains, uint32_t write_domain,
1528 uint32_t offset);
1529
1530 /*======================================================================
1531 * brw_state_dump.c
1532 */
1533 void brw_debug_batch(struct brw_context *brw);
1534 void brw_annotate_aub(struct brw_context *brw);
1535
1536 /*======================================================================
1537 * brw_tex.c
1538 */
1539 void brw_validate_textures( struct brw_context *brw );
1540
1541
1542 /*======================================================================
1543 * brw_program.c
1544 */
1545 void brwInitFragProgFuncs( struct dd_function_table *functions );
1546
1547 int brw_get_scratch_size(int size);
1548 void brw_get_scratch_bo(struct brw_context *brw,
1549 drm_intel_bo **scratch_bo, int size);
1550 void brw_init_shader_time(struct brw_context *brw);
1551 int brw_get_shader_time_index(struct brw_context *brw,
1552 struct gl_shader_program *shader_prog,
1553 struct gl_program *prog,
1554 enum shader_time_shader_type type);
1555 void brw_collect_and_report_shader_time(struct brw_context *brw);
1556 void brw_destroy_shader_time(struct brw_context *brw);
1557
1558 /* brw_urb.c
1559 */
1560 void brw_upload_urb_fence(struct brw_context *brw);
1561
1562 /* brw_curbe.c
1563 */
1564 void brw_upload_cs_urb_state(struct brw_context *brw);
1565
1566 /* brw_fs_reg_allocate.cpp
1567 */
1568 void brw_fs_alloc_reg_sets(struct intel_screen *screen);
1569
1570 /* brw_vec4_reg_allocate.cpp */
1571 void brw_vec4_alloc_reg_set(struct intel_screen *screen);
1572
1573 /* brw_disasm.c */
1574 int brw_disasm (FILE *file, struct brw_instruction *inst, int gen);
1575
1576 /* brw_vs.c */
1577 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx);
1578
1579 /* brw_draw_upload.c */
1580 unsigned brw_get_vertex_surface_type(struct brw_context *brw,
1581 const struct gl_client_array *glarray);
1582 unsigned brw_get_index_type(GLenum type);
1583 void brw_prepare_vertices(struct brw_context *brw);
1584
1585 /* brw_wm_surface_state.c */
1586 void brw_init_surface_formats(struct brw_context *brw);
1587 void brw_create_constant_surface(struct brw_context *brw,
1588 drm_intel_bo *bo,
1589 uint32_t offset,
1590 uint32_t size,
1591 uint32_t *out_offset,
1592 bool dword_pitch);
1593 void brw_update_buffer_texture_surface(struct gl_context *ctx,
1594 unsigned unit,
1595 uint32_t *surf_offset);
1596 void
1597 brw_update_sol_surface(struct brw_context *brw,
1598 struct gl_buffer_object *buffer_obj,
1599 uint32_t *out_offset, unsigned num_vector_components,
1600 unsigned stride_dwords, unsigned offset_dwords);
1601 void brw_upload_ubo_surfaces(struct brw_context *brw,
1602 struct gl_shader *shader,
1603 struct brw_stage_state *stage_state,
1604 struct brw_stage_prog_data *prog_data);
1605 void brw_upload_abo_surfaces(struct brw_context *brw,
1606 struct gl_shader_program *prog,
1607 struct brw_stage_state *stage_state,
1608 struct brw_stage_prog_data *prog_data);
1609
1610 /* brw_surface_formats.c */
1611 bool brw_is_hiz_depth_format(struct brw_context *ctx, mesa_format format);
1612 bool brw_render_target_supported(struct brw_context *brw,
1613 struct gl_renderbuffer *rb);
1614 uint32_t brw_depth_format(struct brw_context *brw, mesa_format format);
1615
1616 /* brw_performance_monitor.c */
1617 void brw_init_performance_monitors(struct brw_context *brw);
1618 void brw_dump_perf_monitors(struct brw_context *brw);
1619 void brw_perf_monitor_new_batch(struct brw_context *brw);
1620 void brw_perf_monitor_finish_batch(struct brw_context *brw);
1621
1622 /* intel_buffer_objects.c */
1623 int brw_bo_map(struct brw_context *brw, drm_intel_bo *bo, int write_enable,
1624 const char *bo_name);
1625 int brw_bo_map_gtt(struct brw_context *brw, drm_intel_bo *bo,
1626 const char *bo_name);
1627
1628 /* intel_extensions.c */
1629 extern void intelInitExtensions(struct gl_context *ctx);
1630
1631 /* intel_state.c */
1632 extern int intel_translate_shadow_compare_func(GLenum func);
1633 extern int intel_translate_compare_func(GLenum func);
1634 extern int intel_translate_stencil_op(GLenum op);
1635 extern int intel_translate_logic_op(GLenum opcode);
1636
1637 /* intel_syncobj.c */
1638 void intel_init_syncobj_functions(struct dd_function_table *functions);
1639
1640 /* gen6_sol.c */
1641 struct gl_transform_feedback_object *
1642 brw_new_transform_feedback(struct gl_context *ctx, GLuint name);
1643 void
1644 brw_delete_transform_feedback(struct gl_context *ctx,
1645 struct gl_transform_feedback_object *obj);
1646 void
1647 brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1648 struct gl_transform_feedback_object *obj);
1649 void
1650 brw_end_transform_feedback(struct gl_context *ctx,
1651 struct gl_transform_feedback_object *obj);
1652 GLsizei
1653 brw_get_transform_feedback_vertex_count(struct gl_context *ctx,
1654 struct gl_transform_feedback_object *obj,
1655 GLuint stream);
1656
1657 /* gen7_sol_state.c */
1658 void
1659 gen7_begin_transform_feedback(struct gl_context *ctx, GLenum mode,
1660 struct gl_transform_feedback_object *obj);
1661 void
1662 gen7_end_transform_feedback(struct gl_context *ctx,
1663 struct gl_transform_feedback_object *obj);
1664 void
1665 gen7_pause_transform_feedback(struct gl_context *ctx,
1666 struct gl_transform_feedback_object *obj);
1667 void
1668 gen7_resume_transform_feedback(struct gl_context *ctx,
1669 struct gl_transform_feedback_object *obj);
1670
1671 /* brw_blorp_blit.cpp */
1672 GLbitfield
1673 brw_blorp_framebuffer(struct brw_context *brw,
1674 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
1675 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
1676 GLbitfield mask, GLenum filter);
1677
1678 bool
1679 brw_blorp_copytexsubimage(struct brw_context *brw,
1680 struct gl_renderbuffer *src_rb,
1681 struct gl_texture_image *dst_image,
1682 int slice,
1683 int srcX0, int srcY0,
1684 int dstX0, int dstY0,
1685 int width, int height);
1686
1687 /* gen6_multisample_state.c */
1688 unsigned
1689 gen6_determine_sample_mask(struct brw_context *brw);
1690
1691 void
1692 gen6_emit_3dstate_multisample(struct brw_context *brw,
1693 unsigned num_samples);
1694 void
1695 gen6_emit_3dstate_sample_mask(struct brw_context *brw, unsigned mask);
1696 void
1697 gen6_get_sample_position(struct gl_context *ctx,
1698 struct gl_framebuffer *fb,
1699 GLuint index,
1700 GLfloat *result);
1701
1702 /* gen8_multisample_state.c */
1703 void gen8_emit_3dstate_multisample(struct brw_context *brw, unsigned num_samp);
1704 void gen8_emit_3dstate_sample_pattern(struct brw_context *brw);
1705
1706 /* gen7_urb.c */
1707 void
1708 gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
1709 unsigned gs_size, unsigned fs_size);
1710
1711 void
1712 gen7_emit_urb_state(struct brw_context *brw,
1713 unsigned nr_vs_entries, unsigned vs_size,
1714 unsigned vs_start, unsigned nr_gs_entries,
1715 unsigned gs_size, unsigned gs_start);
1716
1717
1718 /* brw_reset.c */
1719 extern GLenum
1720 brw_get_graphics_reset_status(struct gl_context *ctx);
1721
1722 /*======================================================================
1723 * Inline conversion functions. These are better-typed than the
1724 * macros used previously:
1725 */
1726 static inline struct brw_context *
1727 brw_context( struct gl_context *ctx )
1728 {
1729 return (struct brw_context *)ctx;
1730 }
1731
1732 static inline struct brw_vertex_program *
1733 brw_vertex_program(struct gl_vertex_program *p)
1734 {
1735 return (struct brw_vertex_program *) p;
1736 }
1737
1738 static inline const struct brw_vertex_program *
1739 brw_vertex_program_const(const struct gl_vertex_program *p)
1740 {
1741 return (const struct brw_vertex_program *) p;
1742 }
1743
1744 static inline struct brw_geometry_program *
1745 brw_geometry_program(struct gl_geometry_program *p)
1746 {
1747 return (struct brw_geometry_program *) p;
1748 }
1749
1750 static inline struct brw_fragment_program *
1751 brw_fragment_program(struct gl_fragment_program *p)
1752 {
1753 return (struct brw_fragment_program *) p;
1754 }
1755
1756 static inline const struct brw_fragment_program *
1757 brw_fragment_program_const(const struct gl_fragment_program *p)
1758 {
1759 return (const struct brw_fragment_program *) p;
1760 }
1761
1762 /**
1763 * Pre-gen6, the register file of the EUs was shared between threads,
1764 * and each thread used some subset allocated on a 16-register block
1765 * granularity. The unit states wanted these block counts.
1766 */
1767 static inline int
1768 brw_register_blocks(int reg_count)
1769 {
1770 return ALIGN(reg_count, 16) / 16 - 1;
1771 }
1772
1773 static inline uint32_t
1774 brw_program_reloc(struct brw_context *brw, uint32_t state_offset,
1775 uint32_t prog_offset)
1776 {
1777 if (brw->gen >= 5) {
1778 /* Using state base address. */
1779 return prog_offset;
1780 }
1781
1782 drm_intel_bo_emit_reloc(brw->batch.bo,
1783 state_offset,
1784 brw->cache.bo,
1785 prog_offset,
1786 I915_GEM_DOMAIN_INSTRUCTION, 0);
1787
1788 return brw->cache.bo->offset64 + prog_offset;
1789 }
1790
1791 bool brw_do_cubemap_normalize(struct exec_list *instructions);
1792 bool brw_lower_texture_gradients(struct brw_context *brw,
1793 struct exec_list *instructions);
1794 bool brw_do_lower_unnormalized_offset(struct exec_list *instructions);
1795
1796 struct opcode_desc {
1797 char *name;
1798 int nsrc;
1799 int ndst;
1800 };
1801
1802 extern const struct opcode_desc opcode_descs[128];
1803 extern const char * const conditional_modifier[16];
1804
1805 void
1806 brw_emit_depthbuffer(struct brw_context *brw);
1807
1808 void
1809 brw_emit_depth_stencil_hiz(struct brw_context *brw,
1810 struct intel_mipmap_tree *depth_mt,
1811 uint32_t depth_offset, uint32_t depthbuffer_format,
1812 uint32_t depth_surface_type,
1813 struct intel_mipmap_tree *stencil_mt,
1814 bool hiz, bool separate_stencil,
1815 uint32_t width, uint32_t height,
1816 uint32_t tile_x, uint32_t tile_y);
1817
1818 void
1819 gen7_emit_depth_stencil_hiz(struct brw_context *brw,
1820 struct intel_mipmap_tree *depth_mt,
1821 uint32_t depth_offset, uint32_t depthbuffer_format,
1822 uint32_t depth_surface_type,
1823 struct intel_mipmap_tree *stencil_mt,
1824 bool hiz, bool separate_stencil,
1825 uint32_t width, uint32_t height,
1826 uint32_t tile_x, uint32_t tile_y);
1827 void
1828 gen8_emit_depth_stencil_hiz(struct brw_context *brw,
1829 struct intel_mipmap_tree *depth_mt,
1830 uint32_t depth_offset, uint32_t depthbuffer_format,
1831 uint32_t depth_surface_type,
1832 struct intel_mipmap_tree *stencil_mt,
1833 bool hiz, bool separate_stencil,
1834 uint32_t width, uint32_t height,
1835 uint32_t tile_x, uint32_t tile_y);
1836
1837 void gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
1838 unsigned int level, unsigned int layer, enum gen6_hiz_op op);
1839
1840 extern const GLuint prim_to_hw_prim[GL_TRIANGLE_STRIP_ADJACENCY+1];
1841
1842 void
1843 brw_setup_vec4_key_clip_info(struct brw_context *brw,
1844 struct brw_vec4_prog_key *key,
1845 bool program_uses_clip_distance);
1846
1847 void
1848 gen6_upload_vec4_push_constants(struct brw_context *brw,
1849 const struct gl_program *prog,
1850 const struct brw_vec4_prog_data *prog_data,
1851 struct brw_stage_state *stage_state,
1852 enum state_struct_type type);
1853
1854 /* ================================================================
1855 * From linux kernel i386 header files, copes with odd sizes better
1856 * than COPY_DWORDS would:
1857 * XXX Put this in src/mesa/main/imports.h ???
1858 */
1859 #if defined(i386) || defined(__i386__)
1860 static inline void * __memcpy(void * to, const void * from, size_t n)
1861 {
1862 int d0, d1, d2;
1863 __asm__ __volatile__(
1864 "rep ; movsl\n\t"
1865 "testb $2,%b4\n\t"
1866 "je 1f\n\t"
1867 "movsw\n"
1868 "1:\ttestb $1,%b4\n\t"
1869 "je 2f\n\t"
1870 "movsb\n"
1871 "2:"
1872 : "=&c" (d0), "=&D" (d1), "=&S" (d2)
1873 :"0" (n/4), "q" (n),"1" ((long) to),"2" ((long) from)
1874 : "memory");
1875 return (to);
1876 }
1877 #else
1878 #define __memcpy(a,b,c) memcpy(a,b,c)
1879 #endif
1880
1881 #ifdef __cplusplus
1882 }
1883 #endif
1884
1885 #endif