2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
46 /* Evil hack for using libdrm in a c++ compiler. */
51 #include <intel_bufmgr.h>
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
67 * URB - uniform resource buffer. A mid-sized buffer which is
68 * partitioned between the fixed function units and used for passing
69 * values (vertices, primitives, constants) between them.
71 * CURBE - constant URB entry. An urb region (entry) used to hold
72 * constant values which the fixed function units can be instructed to
73 * preload into the GRF when spawning a thread.
75 * VUE - vertex URB entry. An urb entry holding a vertex and usually
76 * a vertex header. The header contains control information and
77 * things like primitive type, Begin/end flags and clip codes.
79 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
80 * unit holding rasterization and interpolation parameters.
82 * GRF - general register file. One of several register files
83 * addressable by programmed threads. The inputs (r0, payload, curbe,
84 * urb) of the thread are preloaded to this area before the thread is
85 * spawned. The registers are individually 8 dwords wide and suitable
86 * for general usage. Registers holding thread input values are not
87 * special and may be overwritten.
89 * MRF - message register file. Threads communicate (and terminate)
90 * by sending messages. Message parameters are placed in contiguous
91 * MRF registers. All program output is via these messages. URB
92 * entries are populated by sending a message to the shared URB
93 * function containing the new data, together with a control word,
94 * often an unmodified copy of R0.
96 * R0 - GRF register 0. Typically holds control information used when
97 * sending messages to other threads.
99 * EU or GEN4 EU: The name of the programmable subsystem of the
100 * i965 hardware. Threads are executed by the EU, the registers
101 * described above are part of the EU architecture.
103 * Fixed function units:
105 * CS - Command streamer. Notional first unit, little software
106 * interaction. Holds the URB entries used for constant data, ie the
109 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
110 * this unit is responsible for pulling vertices out of vertex buffers
111 * in vram and injecting them into the processing pipe as VUEs. If
112 * enabled, it first passes them to a VS thread which is a good place
113 * for the driver to implement any active vertex shader.
115 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
116 * enabled, incoming strips etc are passed to GS threads in individual
117 * line/triangle/point units. The GS thread may perform arbitary
118 * computation and emit whatever primtives with whatever vertices it
119 * chooses. This makes GS an excellent place to implement GL's
120 * unfilled polygon modes, though of course it is capable of much
121 * more. Additionally, GS is used to translate away primitives not
122 * handled by latter units, including Quads and Lineloops.
124 * CS - Clipper. Mesa's clipping algorithms are imported to run on
125 * this unit. The fixed function part performs cliptesting against
126 * the 6 fixed clipplanes and makes descisions on whether or not the
127 * incoming primitive needs to be passed to a thread for clipping.
128 * User clip planes are handled via cooperation with the VS thread.
130 * SF - Strips Fans or Setup: Triangles are prepared for
131 * rasterization. Interpolation coefficients are calculated.
132 * Flatshading and two-side lighting usually performed here.
134 * WM - Windower. Interpolation of vertex attributes performed here.
135 * Fragment shader implemented here. SIMD aspects of EU taken full
136 * advantage of, as pixels are processed in blocks of 16.
138 * CC - Color Calculator. No EU threads associated with this unit.
139 * Handles blending and (presumably) depth and stencil testing.
142 #define INTEL_WRITE_PART 0x1
143 #define INTEL_WRITE_FULL 0x2
144 #define INTEL_READ 0x4
146 #define BRW_MAX_CURBE (32*16)
149 struct brw_instruction
;
150 struct brw_vs_prog_key
;
151 struct brw_vec4_prog_key
;
152 struct brw_wm_prog_key
;
153 struct brw_wm_prog_data
;
157 BRW_STATE_FRAGMENT_PROGRAM
,
158 BRW_STATE_GEOMETRY_PROGRAM
,
159 BRW_STATE_VERTEX_PROGRAM
,
160 BRW_STATE_CURBE_OFFSETS
,
161 BRW_STATE_REDUCED_PRIMITIVE
,
166 BRW_STATE_VS_BINDING_TABLE
,
167 BRW_STATE_GS_BINDING_TABLE
,
168 BRW_STATE_PS_BINDING_TABLE
,
172 BRW_STATE_INDEX_BUFFER
,
173 BRW_STATE_VS_CONSTBUF
,
174 BRW_STATE_GS_CONSTBUF
,
175 BRW_STATE_PROGRAM_CACHE
,
176 BRW_STATE_STATE_BASE_ADDRESS
,
177 BRW_STATE_VUE_MAP_VS
,
178 BRW_STATE_VUE_MAP_GEOM_OUT
,
179 BRW_STATE_TRANSFORM_FEEDBACK
,
180 BRW_STATE_RASTERIZER_DISCARD
,
182 BRW_STATE_UNIFORM_BUFFER
,
183 BRW_STATE_ATOMIC_BUFFER
,
184 BRW_STATE_META_IN_PROGRESS
,
185 BRW_STATE_INTERPOLATION_MAP
,
186 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
190 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
191 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
192 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
193 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
194 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
195 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
196 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
197 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
198 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
199 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
200 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
201 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
202 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
203 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
204 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
206 * Used for any batch entry with a relocated pointer that will be used
207 * by any 3D rendering.
209 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
210 /** \see brw.state.depth_region */
211 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
212 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
213 #define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
214 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
215 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
216 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
217 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
218 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
219 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
220 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
221 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
222 #define BRW_NEW_ATOMIC_BUFFER (1 << BRW_STATE_ATOMIC_BUFFER)
223 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
224 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
225 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
227 struct brw_state_flags
{
228 /** State update flags signalled by mesa internals */
231 * State update flags signalled as the result of brw_tracked_state updates
234 /** State update flags signalled by brw_state_cache.c searches */
238 #define AUB_TRACE_TYPE_MASK 0x0000ff00
239 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
240 #define AUB_TRACE_TYPE_BATCH (1 << 8)
241 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
242 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
243 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
244 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
245 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
246 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
247 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
248 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
249 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
250 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
253 * state_struct_type enum values are encoded with the top 16 bits representing
254 * the type to be delivered to the .aub file, and the bottom 16 bits
255 * representing the subtype. This macro performs the encoding.
257 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
259 enum state_struct_type
{
260 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
261 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
262 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
263 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
264 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
265 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
266 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
267 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
268 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
269 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
270 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
271 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
272 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
274 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
275 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
276 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
278 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
279 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
280 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
281 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
282 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
286 * Decode a state_struct_type value to determine the type that should be
287 * stored in the .aub file.
289 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
291 return (ss_type
& 0xFFFF0000) >> 16;
295 * Decode a state_struct_type value to determine the subtype that should be
296 * stored in the .aub file.
298 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
300 return ss_type
& 0xFFFF;
303 /** Subclass of Mesa vertex program */
304 struct brw_vertex_program
{
305 struct gl_vertex_program program
;
310 /** Subclass of Mesa geometry program */
311 struct brw_geometry_program
{
312 struct gl_geometry_program program
;
313 unsigned id
; /**< serial no. to identify geom progs, never re-used */
317 /** Subclass of Mesa fragment program */
318 struct brw_fragment_program
{
319 struct gl_fragment_program program
;
320 GLuint id
; /**< serial no. to identify frag progs, never re-used */
324 struct gl_shader base
;
328 /** Shader IR transformed for native compile, at link time. */
329 struct exec_list
*ir
;
332 /* Note: If adding fields that need anything besides a normal memcmp() for
333 * comparing them, be sure to go fix the the stage-specific
334 * prog_data_compare().
336 struct brw_stage_prog_data
{
338 /** size of our binding table. */
342 * surface indices for the various groups of surfaces
344 uint32_t pull_constants_start
;
345 uint32_t texture_start
;
346 uint32_t gather_texture_start
;
349 uint32_t shader_time_start
;
354 /* Data about a particular attempt to compile a program. Note that
355 * there can be many of these, each in a different GL state
356 * corresponding to a different brw_wm_prog_key struct, with different
359 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
362 struct brw_wm_prog_data
{
363 struct brw_stage_prog_data base
;
365 GLuint curb_read_length
;
366 GLuint num_varying_inputs
;
368 GLuint first_curbe_grf
;
369 GLuint first_curbe_grf_16
;
371 GLuint reg_blocks_16
;
372 GLuint total_scratch
;
376 * surface indices the WM-specific surfaces
378 uint32_t render_target_start
;
382 GLuint nr_params
; /**< number of float params/constants */
383 GLuint nr_pull_params
;
385 bool uses_pos_offset
;
387 uint32_t prog_offset_16
;
390 * Mask of which interpolation modes are required by the fragment shader.
391 * Used in hardware setup on gen6+.
393 uint32_t barycentric_interp_modes
;
396 * Map from gl_varying_slot to the position within the FS setup data
397 * payload where the varying's attribute vertex deltas should be delivered.
398 * For varying slots that are not used by the FS, the value is -1.
400 int urb_setup
[VARYING_SLOT_MAX
];
402 /* Pointers to tracked values (only valid once
403 * _mesa_load_state_parameters has been called at runtime).
405 * These must be the last fields of the struct (see
406 * brw_wm_prog_data_compare()).
409 const float **pull_param
;
413 * Enum representing the i965-specific vertex results that don't correspond
414 * exactly to any element of gl_varying_slot. The values of this enum are
415 * assigned such that they don't conflict with gl_varying_slot.
419 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
420 BRW_VARYING_SLOT_PAD
,
422 * Technically this is not a varying but just a placeholder that
423 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
424 * builtin variable to be compiled correctly. see compile_sf_prog() for
427 BRW_VARYING_SLOT_PNTC
,
428 BRW_VARYING_SLOT_COUNT
433 * Data structure recording the relationship between the gl_varying_slot enum
434 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
435 * single octaword within the VUE (128 bits).
437 * Note that each BRW register contains 256 bits (2 octawords), so when
438 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
439 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
440 * in a vertex shader), each register corresponds to a single VUE slot, since
441 * it contains data for two separate vertices.
445 * Bitfield representing all varying slots that are (a) stored in this VUE
446 * map, and (b) actually written by the shader. Does not include any of
447 * the additional varying slots defined in brw_varying_slot.
449 GLbitfield64 slots_valid
;
452 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
453 * not stored in a slot (because they are not written, or because
454 * additional processing is applied before storing them in the VUE), the
457 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
460 * Map from VUE slot to gl_varying_slot value. For slots that do not
461 * directly correspond to a gl_varying_slot, the value comes from
464 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
465 * simplifies code that uses the value stored in slot_to_varying to
466 * create a bit mask).
468 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
471 * Total number of VUE slots in use
477 * Convert a VUE slot number into a byte offset within the VUE.
479 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
485 * Convert a vertex output (brw_varying_slot) into a byte offset within the
488 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
491 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
494 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
495 GLbitfield64 slots_valid
);
499 * Bitmask indicating which fragment shader inputs represent varyings (and
500 * hence have to be delivered to the fragment shader by the SF/SBE stage).
502 #define BRW_FS_VARYING_INPUT_MASK \
503 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
504 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
508 * Mapping of VUE map slots to interpolation modes.
510 struct interpolation_mode_map
{
511 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
514 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
516 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
517 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
523 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
525 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
526 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
533 struct brw_sf_prog_data
{
534 GLuint urb_read_length
;
537 /* Each vertex may have upto 12 attributes, 4 components each,
538 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
541 * Actually we use 4 for each, so call it 12 rows.
543 GLuint urb_entry_size
;
548 * We always program SF to start reading at an offset of 1 (2 varying slots)
549 * from the start of the vertex URB entry. This causes it to skip:
550 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
551 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
553 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
556 struct brw_clip_prog_data
{
557 GLuint curb_read_length
; /* user planes? */
559 GLuint urb_read_length
;
563 struct brw_ff_gs_prog_data
{
564 GLuint urb_read_length
;
568 * Gen6 transform feedback: Amount by which the streaming vertex buffer
569 * indices should be incremented each time the GS is invoked.
571 unsigned svbi_postincrement_value
;
575 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
578 struct brw_vec4_prog_data
{
579 struct brw_stage_prog_data base
;
580 struct brw_vue_map vue_map
;
583 * Register where the thread expects to find input data from the URB
584 * (typically uniforms, followed by per-vertex inputs).
586 unsigned dispatch_grf_start_reg
;
588 GLuint curb_read_length
;
589 GLuint urb_read_length
;
591 GLuint nr_params
; /**< number of float params/constants */
592 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
593 GLuint total_scratch
;
595 /* Used for calculating urb partitions. In the VS, this is the size of the
596 * URB entry used for both input and output to the thread. In the GS, this
597 * is the size of the URB entry used for output.
599 GLuint urb_entry_size
;
601 /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
603 const float **pull_param
;
607 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
610 struct brw_vs_prog_data
{
611 struct brw_vec4_prog_data base
;
613 GLbitfield64 inputs_read
;
619 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
622 struct brw_gs_prog_data
624 struct brw_vec4_prog_data base
;
627 * Size of an output vertex, measured in HWORDS (32 bytes).
629 unsigned output_vertex_size_hwords
;
631 unsigned output_topology
;
634 * Size of the control data (cut bits or StreamID bits), in hwords (32
635 * bytes). 0 if there is no control data.
637 unsigned control_data_header_size_hwords
;
640 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
641 * if the control data is StreamID bits, or
642 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
643 * Ignored if control_data_header_size is 0.
645 unsigned control_data_format
;
647 bool include_primitive_id
;
650 * True if the thread should be dispatched in DUAL_INSTANCE mode, false if
651 * it should be dispatched in DUAL_OBJECT mode.
653 bool dual_instanced_dispatch
;
656 /** Number of texture sampler units */
657 #define BRW_MAX_TEX_UNIT 16
659 /** Max number of render targets in a shader */
660 #define BRW_MAX_DRAW_BUFFERS 8
662 /** Max number of atomic counter buffer objects in a shader */
663 #define BRW_MAX_ABO 16
666 * Max number of binding table entries used for stream output.
668 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
669 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
671 * On Gen6, the size of transform feedback data is limited not by the number
672 * of components but by the number of binding table entries we set aside. We
673 * use one binding table entry for a float, one entry for a vector, and one
674 * entry per matrix column. Since the only way we can communicate our
675 * transform feedback capabilities to the client is via
676 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
677 * worst case, in which all the varyings are floats, so we use up one binding
678 * table entry per component. Therefore we need to set aside at least 64
679 * binding table entries for use by transform feedback.
681 * Note: since we don't currently pack varyings, it is currently impossible
682 * for the client to actually use up all of these binding table entries--if
683 * all of their varyings were floats, they would run out of varying slots and
684 * fail to link. But that's a bug, so it seems prudent to go ahead and
685 * allocate the number of binding table entries we will need once the bug is
688 #define BRW_MAX_SOL_BINDINGS 64
690 /** Maximum number of actual buffers used for stream output */
691 #define BRW_MAX_SOL_BUFFERS 4
693 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
694 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
697 2 /* shader time, pull constants */)
699 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
700 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
703 * Stride in bytes between shader_time entries.
705 * We separate entries by a cacheline to reduce traffic between EUs writing to
708 #define SHADER_TIME_STRIDE 64
715 BRW_BLORP_CONST_COLOR_PROG
,
720 BRW_SF_UNIT
, /* scissor state on gen6 */
733 struct brw_cache_item
{
735 * Effectively part of the key, cache_id identifies what kind of state
736 * buffer is involved, and also which brw->state.dirty.cache flag should
737 * be set when this cache item is chosen.
739 enum brw_cache_id cache_id
;
740 /** 32-bit hash of the key data */
742 GLuint key_size
; /* for variable-sized keys */
749 struct brw_cache_item
*next
;
753 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
754 typedef void (*cache_aux_free_func
)(const void *aux
);
757 struct brw_context
*brw
;
759 struct brw_cache_item
**items
;
761 GLuint size
, n_items
;
763 uint32_t next_offset
;
767 * Optional functions used in determining whether the prog_data for a new
768 * cache item matches an existing cache item (in case there's relevant data
769 * outside of the prog_data). If NULL, a plain memcmp is done.
771 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
772 /** Optional functions for freeing other pointers attached to a prog_data. */
773 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
777 /* Considered adding a member to this struct to document which flags
778 * an update might raise so that ordering of the state atoms can be
779 * checked or derived at runtime. Dropped the idea in favor of having
780 * a debug mode where the state is monitored for flags which are
781 * raised that have already been tested against.
783 struct brw_tracked_state
{
784 struct brw_state_flags dirty
;
785 void (*emit
)( struct brw_context
*brw
);
788 enum shader_time_shader_type
{
801 /* Flags for brw->state.cache.
803 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
804 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
805 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
806 #define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
807 #define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
808 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
809 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
810 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
811 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
812 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
813 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
814 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
815 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
816 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
817 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
818 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
819 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
820 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
822 struct brw_cached_batch_item
{
823 struct header
*header
;
825 struct brw_cached_batch_item
*next
;
828 struct brw_vertex_buffer
{
829 /** Buffer object containing the uploaded vertex data */
832 /** Byte stride between elements in the uploaded array */
836 struct brw_vertex_element
{
837 const struct gl_client_array
*glarray
;
841 /** The corresponding Mesa vertex attribute */
842 gl_vert_attrib attrib
;
843 /** Offset of the first element within the buffer object */
847 struct brw_query_object
{
848 struct gl_query_object Base
;
850 /** Last query BO associated with this query. */
853 /** Last index in bo with query data for this object. */
857 struct intel_sync_object
{
858 struct gl_sync_object Base
;
860 /** Batch associated with this sync object */
870 struct intel_batchbuffer
{
871 /** Current batchbuffer being queued up. */
873 /** Last BO submitted to the hardware. Used for glFinish(). */
874 drm_intel_bo
*last_bo
;
875 /** BO for post-sync nonzero writes for gen6 workaround. */
876 drm_intel_bo
*workaround_bo
;
877 bool need_workaround_flush
;
879 struct cached_batch_item
*cached_items
;
881 uint16_t emit
, total
;
882 uint16_t used
, reserved_space
;
885 #define BATCH_SZ (8192*sizeof(uint32_t))
887 uint32_t state_batch_offset
;
888 enum brw_gpu_ring ring
;
889 bool needs_sol_reset
;
897 #define BRW_MAX_XFB_STREAMS 4
899 struct brw_transform_feedback_object
{
900 struct gl_transform_feedback_object base
;
902 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
903 drm_intel_bo
*offset_bo
;
905 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
906 GLenum primitive_mode
;
909 * Count of primitives generated during this transform feedback operation.
912 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
913 drm_intel_bo
*prim_count_bo
;
914 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
918 * Number of vertices written between last Begin/EndTransformFeedback().
920 * Used to implement DrawTransformFeedback().
922 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
923 bool vertices_written_valid
;
927 * Data shared between each programmable stage in the pipeline (vs, gs, and
930 struct brw_stage_state
932 struct brw_stage_prog_data
*prog_data
;
935 * Optional scratch buffer used to store spilled register values and
936 * variably-indexed GRF arrays.
938 drm_intel_bo
*scratch_bo
;
940 /** Pull constant buffer */
941 drm_intel_bo
*const_bo
;
943 /** Offset in the program cache to the program */
944 uint32_t prog_offset
;
946 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
947 uint32_t state_offset
;
949 uint32_t push_const_offset
; /* Offset in the batchbuffer */
950 int push_const_size
; /* in 256-bit register increments */
952 /* Binding table: pointers to SURFACE_STATE entries. */
953 uint32_t bind_bo_offset
;
954 uint32_t surf_offset
[BRW_MAX_SURFACES
];
956 /** SAMPLER_STATE count and table offset */
957 uint32_t sampler_count
;
958 uint32_t sampler_offset
;
960 /** Offsets in the batch to sampler default colors (texture border color) */
961 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
966 * brw_context is derived from gl_context.
970 struct gl_context ctx
; /**< base class, must be first field */
974 void (*update_texture_surface
)(struct gl_context
*ctx
,
976 uint32_t *surf_offset
,
978 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
979 struct gl_renderbuffer
*rb
,
982 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
985 void (*create_raw_surface
)(struct brw_context
*brw
,
989 uint32_t *out_offset
,
991 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
992 uint32_t *out_offset
,
994 unsigned buffer_offset
,
995 unsigned surface_format
,
996 unsigned buffer_size
,
1001 /** Upload a SAMPLER_STATE table. */
1002 void (*upload_sampler_state_table
)(struct brw_context
*brw
,
1003 struct gl_program
*prog
,
1004 uint32_t sampler_count
,
1005 uint32_t *sst_offset
,
1006 uint32_t *sdc_offset
);
1009 * Send the appropriate state packets to configure depth, stencil, and
1010 * HiZ buffers (i965+ only)
1012 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
1013 struct intel_mipmap_tree
*depth_mt
,
1014 uint32_t depth_offset
,
1015 uint32_t depthbuffer_format
,
1016 uint32_t depth_surface_type
,
1017 struct intel_mipmap_tree
*stencil_mt
,
1018 bool hiz
, bool separate_stencil
,
1019 uint32_t width
, uint32_t height
,
1020 uint32_t tile_x
, uint32_t tile_y
);
1026 drm_intel_context
*hw_ctx
;
1029 * Number of resets observed in the system at context creation.
1031 * This is tracked in the context so that we can determine that another
1032 * reset has occured.
1034 uint32_t reset_count
;
1036 struct intel_batchbuffer batch
;
1042 uint32_t buffer_len
;
1043 uint32_t buffer_offset
;
1048 * Set if rendering has occured to the drawable's front buffer.
1050 * This is used in the DRI2 case to detect that glFlush should also copy
1051 * the contents of the fake front buffer to the real front buffer.
1053 bool front_buffer_dirty
;
1056 * Track whether front-buffer rendering is currently enabled
1058 * A separate flag is used to track this in order to support MRT more
1061 bool is_front_buffer_rendering
;
1064 * Track whether front-buffer is the current read target.
1066 * This is closely associated with is_front_buffer_rendering, but may
1067 * be set separately. The DRI2 fake front buffer must be referenced
1070 bool is_front_buffer_reading
;
1072 /** Framerate throttling: @{ */
1073 drm_intel_bo
*first_post_swapbuffers_batch
;
1084 bool always_flush_batch
;
1085 bool always_flush_cache
;
1086 bool disable_throttling
;
1088 bool disable_derivative_optimization
;
1090 driOptionCache optionCache
;
1093 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1095 GLenum reduced_primitive
;
1098 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1099 * variable is set, this is the flag indicating to do expensive work that
1100 * might lead to a perf_debug() call.
1104 uint32_t max_gtt_map_object_size
;
1114 bool has_separate_stencil
;
1115 bool must_use_separate_stencil
;
1118 bool has_surface_tile_offset
;
1120 bool has_negative_rhw_bug
;
1124 * Some versions of Gen hardware don't do centroid interpolation correctly
1125 * on unlit pixels, causing incorrect values for derivatives near triangle
1126 * edges. Enabling this flag causes the fragment shader to use
1127 * non-centroid interpolation for unlit pixels, at the expense of two extra
1128 * fragment shader instructions.
1130 bool needs_unlit_centroid_workaround
;
1134 struct brw_state_flags dirty
;
1137 struct brw_cache cache
;
1138 struct brw_cached_batch_item
*cached_batch_items
;
1140 /* Whether a meta-operation is in progress. */
1141 bool meta_in_progress
;
1144 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1145 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1147 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1151 /* Summary of size and varying of active arrays, so we can check
1152 * for changes to this state:
1154 unsigned int min_index
, max_index
;
1156 /* Offset from start of vertex buffer so we can avoid redefining
1157 * the same VB packed over and over again.
1159 unsigned int start_vertex_bias
;
1164 * Index buffer for this draw_prims call.
1166 * Updates are signaled by BRW_NEW_INDICES.
1168 const struct _mesa_index_buffer
*ib
;
1170 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1174 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1175 * avoid re-uploading the IB packet over and over if we're actually
1176 * referencing the same index buffer.
1178 unsigned int start_vertex_offset
;
1181 /* Active vertex program:
1183 const struct gl_vertex_program
*vertex_program
;
1184 const struct gl_geometry_program
*geometry_program
;
1185 const struct gl_fragment_program
*fragment_program
;
1187 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
1188 uint32_t CMD_VF_STATISTICS
;
1189 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
1190 uint32_t CMD_PIPELINE_SELECT
;
1193 * Platform specific constants containing the maximum number of threads
1194 * for each pipeline stage.
1200 /* BRW_NEW_URB_ALLOCATIONS:
1203 GLuint vsize
; /* vertex size plus header in urb registers */
1204 GLuint csize
; /* constant buffer size in urb registers */
1205 GLuint sfsize
; /* setup data size in urb registers */
1209 GLuint min_vs_entries
; /* Minimum number of VS entries */
1210 GLuint max_vs_entries
; /* Maximum number of VS entries */
1211 GLuint max_gs_entries
; /* Maximum number of GS entries */
1213 GLuint nr_vs_entries
;
1214 GLuint nr_gs_entries
;
1215 GLuint nr_clip_entries
;
1216 GLuint nr_sf_entries
;
1217 GLuint nr_cs_entries
;
1224 GLuint size
; /* Hardware URB size, in KB. */
1226 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1227 * URB space for the GS.
1229 bool gen6_gs_previously_active
;
1233 /* BRW_NEW_CURBE_OFFSETS:
1236 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1237 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1244 drm_intel_bo
*curbe_bo
;
1245 /** Offset within curbe_bo of space for current curbe entry */
1246 GLuint curbe_offset
;
1247 /** Offset within curbe_bo of space for next curbe entry */
1248 GLuint curbe_next_offset
;
1251 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
1252 * in brw_curbe.c with the same set of constant data to be uploaded,
1253 * so we'd rather not upload new constants in that case (it can cause
1254 * a pipeline bubble since only up to 4 can be pipelined at a time).
1258 * Allocation for where to calculate the next set of CURBEs.
1259 * It's a hot enough path that malloc/free of that data matters.
1266 * Layout of vertex data exiting the vertex shader.
1268 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1270 struct brw_vue_map vue_map_vs
;
1273 * Layout of vertex data exiting the geometry portion of the pipleine.
1274 * This comes from the geometry shader if one exists, otherwise from the
1277 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1279 struct brw_vue_map vue_map_geom_out
;
1282 * Data structures used by all vec4 program compiles (not specific to any
1283 * particular program).
1286 struct ra_regs
*regs
;
1289 * Array of the ra classes for the unaligned contiguous register
1295 * Mapping for register-allocated objects in *regs to the first
1296 * GRF for that object.
1298 uint8_t *ra_reg_to_grf
;
1302 struct brw_stage_state base
;
1303 struct brw_vs_prog_data
*prog_data
;
1307 struct brw_stage_state base
;
1308 struct brw_gs_prog_data
*prog_data
;
1311 * True if the 3DSTATE_GS command most recently emitted to the 3D
1312 * pipeline enabled the GS; false otherwise.
1318 struct brw_ff_gs_prog_data
*prog_data
;
1321 /** Offset in the program cache to the CLIP program pre-gen6 */
1322 uint32_t prog_offset
;
1323 uint32_t state_offset
;
1325 uint32_t bind_bo_offset
;
1326 uint32_t surf_offset
[BRW_MAX_GEN6_GS_SURFACES
];
1330 struct brw_clip_prog_data
*prog_data
;
1332 /** Offset in the program cache to the CLIP program pre-gen6 */
1333 uint32_t prog_offset
;
1335 /* Offset in the batch to the CLIP state on pre-gen6. */
1336 uint32_t state_offset
;
1338 /* As of gen6, this is the offset in the batch to the CLIP VP,
1346 struct brw_sf_prog_data
*prog_data
;
1348 /** Offset in the program cache to the CLIP program pre-gen6 */
1349 uint32_t prog_offset
;
1350 uint32_t state_offset
;
1355 struct brw_stage_state base
;
1356 struct brw_wm_prog_data
*prog_data
;
1361 * Buffer object used in place of multisampled null render targets on
1362 * Gen6. See brw_update_null_renderbuffer_surface().
1364 drm_intel_bo
*multisampled_null_render_target_bo
;
1367 struct ra_regs
*regs
;
1370 * Array of the ra classes for the unaligned contiguous register
1371 * block sizes used, indexed by register size.
1376 * Mapping for register-allocated objects in *regs to the first
1377 * GRF for that object.
1379 uint8_t *ra_reg_to_grf
;
1382 * ra class for the aligned pairs we use for PLN, which doesn't
1383 * appear in *classes.
1385 int aligned_pairs_class
;
1391 uint32_t state_offset
;
1392 uint32_t blend_state_offset
;
1393 uint32_t depth_stencil_state_offset
;
1398 struct brw_query_object
*obj
;
1403 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1404 const int *statistics_registers
;
1406 /** The number of active monitors using OA counters. */
1410 * A buffer object storing OA counter snapshots taken at the start and
1411 * end of each batch (creating "bookends" around the batch).
1413 drm_intel_bo
*bookend_bo
;
1415 /** The number of snapshots written to bookend_bo. */
1416 int bookend_snapshots
;
1419 * An array of monitors whose results haven't yet been assembled based on
1420 * the data in buffer objects.
1422 * These may be active, or have already ended. However, the results
1423 * have not been requested.
1425 struct brw_perf_monitor_object
**unresolved
;
1426 int unresolved_elements
;
1427 int unresolved_array_size
;
1430 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1431 * the counter which MI_REPORT_PERF_COUNT stores there.
1433 const int *oa_snapshot_layout
;
1435 /** Number of 32-bit entries in a hardware counter snapshot. */
1436 int entries_per_oa_snapshot
;
1440 const struct brw_tracked_state
**atoms
;
1442 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1446 enum state_struct_type type
;
1447 } *state_batch_list
;
1448 int state_batch_count
;
1450 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1451 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1453 /* Interpolation modes, one byte per vue slot.
1454 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1456 struct interpolation_mode_map interpolation_mode
;
1458 /* PrimitiveRestart */
1461 bool enable_cut_index
;
1464 /** Computed depth/stencil/hiz state from the current attached
1465 * renderbuffers, valid only during the drawing state upload loop after
1466 * brw_workaround_depthstencil_alignment().
1469 struct intel_mipmap_tree
*depth_mt
;
1470 struct intel_mipmap_tree
*stencil_mt
;
1472 /* Inter-tile (page-aligned) byte offsets. */
1473 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1474 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1475 uint32_t tile_x
, tile_y
;
1478 uint32_t num_instances
;
1483 struct gl_shader_program
**shader_programs
;
1484 struct gl_program
**programs
;
1485 enum shader_time_shader_type
*types
;
1486 uint64_t *cumulative
;
1492 __DRIcontext
*driContext
;
1493 struct intel_screen
*intelScreen
;
1497 is_power_of_two(uint32_t value
)
1499 return (value
& (value
- 1)) == 0;
1502 /*======================================================================
1505 void brwInitVtbl( struct brw_context
*brw
);
1508 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1510 /*======================================================================
1513 extern const char *const brw_vendor_string
;
1515 extern const char *brw_get_renderer_string(unsigned deviceID
);
1517 extern void intelFinish(struct gl_context
* ctx
);
1520 DRI_CONF_BO_REUSE_DISABLED
,
1521 DRI_CONF_BO_REUSE_ALL
1524 void intel_update_renderbuffers(__DRIcontext
*context
,
1525 __DRIdrawable
*drawable
);
1526 void intel_prepare_render(struct brw_context
*brw
);
1528 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1529 __DRIdrawable
*drawable
);
1531 GLboolean
brwCreateContext(gl_api api
,
1532 const struct gl_config
*mesaVis
,
1533 __DRIcontext
*driContextPriv
,
1534 unsigned major_version
,
1535 unsigned minor_version
,
1539 void *sharedContextPrivate
);
1541 /*======================================================================
1544 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1545 uint32_t depth_level
,
1546 uint32_t depth_layer
,
1547 struct intel_mipmap_tree
*stencil_mt
,
1548 uint32_t *out_tile_mask_x
,
1549 uint32_t *out_tile_mask_y
);
1550 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1551 GLbitfield clear_mask
);
1553 /* brw_object_purgeable.c */
1554 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1556 /*======================================================================
1559 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1560 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1561 void brw_emit_query_begin(struct brw_context
*brw
);
1562 void brw_emit_query_end(struct brw_context
*brw
);
1564 /** gen6_queryobj.c */
1565 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1566 void brw_store_register_mem64(struct brw_context
*brw
,
1567 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1569 /*======================================================================
1572 void brw_debug_batch(struct brw_context
*brw
);
1573 void brw_annotate_aub(struct brw_context
*brw
);
1575 /*======================================================================
1578 void brw_validate_textures( struct brw_context
*brw
);
1581 /*======================================================================
1584 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1586 int brw_get_scratch_size(int size
);
1587 void brw_get_scratch_bo(struct brw_context
*brw
,
1588 drm_intel_bo
**scratch_bo
, int size
);
1589 void brw_init_shader_time(struct brw_context
*brw
);
1590 int brw_get_shader_time_index(struct brw_context
*brw
,
1591 struct gl_shader_program
*shader_prog
,
1592 struct gl_program
*prog
,
1593 enum shader_time_shader_type type
);
1594 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1595 void brw_destroy_shader_time(struct brw_context
*brw
);
1599 void brw_upload_urb_fence(struct brw_context
*brw
);
1603 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1605 /* brw_fs_reg_allocate.cpp
1607 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1609 /* brw_vec4_reg_allocate.cpp */
1610 void brw_vec4_alloc_reg_set(struct brw_context
*brw
);
1613 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1616 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1618 /* brw_draw_upload.c */
1619 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1620 const struct gl_client_array
*glarray
);
1621 unsigned brw_get_index_type(GLenum type
);
1623 /* brw_wm_surface_state.c */
1624 void brw_init_surface_formats(struct brw_context
*brw
);
1625 void brw_create_constant_surface(struct brw_context
*brw
,
1629 uint32_t *out_offset
,
1631 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1633 uint32_t *surf_offset
);
1635 brw_update_sol_surface(struct brw_context
*brw
,
1636 struct gl_buffer_object
*buffer_obj
,
1637 uint32_t *out_offset
, unsigned num_vector_components
,
1638 unsigned stride_dwords
, unsigned offset_dwords
);
1639 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1640 struct gl_shader
*shader
,
1641 struct brw_stage_state
*stage_state
,
1642 struct brw_stage_prog_data
*prog_data
);
1643 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1644 struct gl_shader_program
*prog
,
1645 struct brw_stage_state
*stage_state
,
1646 struct brw_stage_prog_data
*prog_data
);
1648 /* brw_surface_formats.c */
1649 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, gl_format format
);
1650 bool brw_render_target_supported(struct brw_context
*brw
,
1651 struct gl_renderbuffer
*rb
);
1653 /* brw_performance_monitor.c */
1654 void brw_init_performance_monitors(struct brw_context
*brw
);
1655 void brw_dump_perf_monitors(struct brw_context
*brw
);
1656 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1657 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1659 /* intel_extensions.c */
1660 extern void intelInitExtensions(struct gl_context
*ctx
);
1663 extern int intel_translate_shadow_compare_func(GLenum func
);
1664 extern int intel_translate_compare_func(GLenum func
);
1665 extern int intel_translate_stencil_op(GLenum op
);
1666 extern int intel_translate_logic_op(GLenum opcode
);
1668 /* intel_syncobj.c */
1669 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1672 struct gl_transform_feedback_object
*
1673 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1675 brw_delete_transform_feedback(struct gl_context
*ctx
,
1676 struct gl_transform_feedback_object
*obj
);
1678 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1679 struct gl_transform_feedback_object
*obj
);
1681 brw_end_transform_feedback(struct gl_context
*ctx
,
1682 struct gl_transform_feedback_object
*obj
);
1684 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1685 struct gl_transform_feedback_object
*obj
,
1688 /* gen7_sol_state.c */
1690 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1691 struct gl_transform_feedback_object
*obj
);
1693 gen7_end_transform_feedback(struct gl_context
*ctx
,
1694 struct gl_transform_feedback_object
*obj
);
1696 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1697 struct gl_transform_feedback_object
*obj
);
1699 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1700 struct gl_transform_feedback_object
*obj
);
1702 /* brw_blorp_blit.cpp */
1704 brw_blorp_framebuffer(struct brw_context
*brw
,
1705 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1706 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1707 GLbitfield mask
, GLenum filter
);
1710 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1711 struct gl_renderbuffer
*src_rb
,
1712 struct gl_texture_image
*dst_image
,
1714 int srcX0
, int srcY0
,
1715 int dstX0
, int dstY0
,
1716 int width
, int height
);
1718 /* gen6_multisample_state.c */
1720 gen6_determine_sample_mask(struct brw_context
*brw
);
1723 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1724 unsigned num_samples
);
1726 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1728 gen6_get_sample_position(struct gl_context
*ctx
,
1729 struct gl_framebuffer
*fb
,
1735 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1736 unsigned gs_size
, unsigned fs_size
);
1739 gen7_emit_urb_state(struct brw_context
*brw
,
1740 unsigned nr_vs_entries
, unsigned vs_size
,
1741 unsigned vs_start
, unsigned nr_gs_entries
,
1742 unsigned gs_size
, unsigned gs_start
);
1747 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1749 /*======================================================================
1750 * Inline conversion functions. These are better-typed than the
1751 * macros used previously:
1753 static inline struct brw_context
*
1754 brw_context( struct gl_context
*ctx
)
1756 return (struct brw_context
*)ctx
;
1759 static inline struct brw_vertex_program
*
1760 brw_vertex_program(struct gl_vertex_program
*p
)
1762 return (struct brw_vertex_program
*) p
;
1765 static inline const struct brw_vertex_program
*
1766 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1768 return (const struct brw_vertex_program
*) p
;
1771 static inline struct brw_geometry_program
*
1772 brw_geometry_program(struct gl_geometry_program
*p
)
1774 return (struct brw_geometry_program
*) p
;
1777 static inline struct brw_fragment_program
*
1778 brw_fragment_program(struct gl_fragment_program
*p
)
1780 return (struct brw_fragment_program
*) p
;
1783 static inline const struct brw_fragment_program
*
1784 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1786 return (const struct brw_fragment_program
*) p
;
1790 * Pre-gen6, the register file of the EUs was shared between threads,
1791 * and each thread used some subset allocated on a 16-register block
1792 * granularity. The unit states wanted these block counts.
1795 brw_register_blocks(int reg_count
)
1797 return ALIGN(reg_count
, 16) / 16 - 1;
1800 static inline uint32_t
1801 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1802 uint32_t prog_offset
)
1804 if (brw
->gen
>= 5) {
1805 /* Using state base address. */
1809 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1813 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1815 return brw
->cache
.bo
->offset
+ prog_offset
;
1818 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1819 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1820 struct exec_list
*instructions
);
1821 bool brw_do_lower_offset_arrays(struct exec_list
*instructions
);
1822 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1824 struct opcode_desc
{
1830 extern const struct opcode_desc opcode_descs
[128];
1831 extern const char * const conditional_modifier
[16];
1832 extern const char * const reg_encoding
[8];
1835 brw_emit_depthbuffer(struct brw_context
*brw
);
1838 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1839 struct intel_mipmap_tree
*depth_mt
,
1840 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1841 uint32_t depth_surface_type
,
1842 struct intel_mipmap_tree
*stencil_mt
,
1843 bool hiz
, bool separate_stencil
,
1844 uint32_t width
, uint32_t height
,
1845 uint32_t tile_x
, uint32_t tile_y
);
1848 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1849 struct intel_mipmap_tree
*depth_mt
,
1850 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1851 uint32_t depth_surface_type
,
1852 struct intel_mipmap_tree
*stencil_mt
,
1853 bool hiz
, bool separate_stencil
,
1854 uint32_t width
, uint32_t height
,
1855 uint32_t tile_x
, uint32_t tile_y
);
1857 extern const GLuint prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1];
1860 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1861 struct brw_vec4_prog_key
*key
,
1862 bool program_uses_clip_distance
);
1865 gen6_upload_vec4_push_constants(struct brw_context
*brw
,
1866 const struct gl_program
*prog
,
1867 const struct brw_vec4_prog_data
*prog_data
,
1868 struct brw_stage_state
*stage_state
,
1869 enum state_struct_type type
);
1871 /* ================================================================
1872 * From linux kernel i386 header files, copes with odd sizes better
1873 * than COPY_DWORDS would:
1874 * XXX Put this in src/mesa/main/imports.h ???
1876 #if defined(i386) || defined(__i386__)
1877 static inline void * __memcpy(void * to
, const void * from
, size_t n
)
1880 __asm__
__volatile__(
1885 "1:\ttestb $1,%b4\n\t"
1889 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1890 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1895 #define __memcpy(a,b,c) memcpy(a,b,c)