2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vec4_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
154 BRW_STATE_FRAGMENT_PROGRAM
,
155 BRW_STATE_GEOMETRY_PROGRAM
,
156 BRW_STATE_VERTEX_PROGRAM
,
157 BRW_STATE_CURBE_OFFSETS
,
158 BRW_STATE_REDUCED_PRIMITIVE
,
163 BRW_STATE_VS_BINDING_TABLE
,
164 BRW_STATE_GS_BINDING_TABLE
,
165 BRW_STATE_PS_BINDING_TABLE
,
169 BRW_STATE_INDEX_BUFFER
,
170 BRW_STATE_VS_CONSTBUF
,
171 BRW_STATE_GS_CONSTBUF
,
172 BRW_STATE_PROGRAM_CACHE
,
173 BRW_STATE_STATE_BASE_ADDRESS
,
174 BRW_STATE_VUE_MAP_VS
,
175 BRW_STATE_VUE_MAP_GEOM_OUT
,
176 BRW_STATE_TRANSFORM_FEEDBACK
,
177 BRW_STATE_RASTERIZER_DISCARD
,
179 BRW_STATE_UNIFORM_BUFFER
,
180 BRW_STATE_ATOMIC_BUFFER
,
181 BRW_STATE_META_IN_PROGRESS
,
182 BRW_STATE_INTERPOLATION_MAP
,
183 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
184 BRW_STATE_NUM_SAMPLES
,
188 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
189 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
190 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
191 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
192 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
193 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
194 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
195 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
196 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
197 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
198 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
199 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
200 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
201 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
202 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
204 * Used for any batch entry with a relocated pointer that will be used
205 * by any 3D rendering.
207 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
208 /** \see brw.state.depth_region */
209 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
210 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
211 #define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
212 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
213 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
214 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
215 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
216 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
217 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
218 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
219 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
220 #define BRW_NEW_ATOMIC_BUFFER (1 << BRW_STATE_ATOMIC_BUFFER)
221 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
222 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
223 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
224 #define BRW_NEW_NUM_SAMPLES (1 << BRW_STATE_NUM_SAMPLES)
226 struct brw_state_flags
{
227 /** State update flags signalled by mesa internals */
230 * State update flags signalled as the result of brw_tracked_state updates
234 * State update flags that used to be signalled by brw_state_cache.c
237 * Now almost all of that state is just streamed out on demand, but the
238 * flags for those state blobs updating have stayed in the same bitfield.
239 * brw_state_cache.c still flags CACHE_NEW_*_PROG.
246 * Set one of the bits in a field of brw_state_flags.
248 #define SET_DIRTY_BIT(FIELD, FLAG) brw->state.dirty.FIELD |= (FLAG)
251 /** Subclass of Mesa vertex program */
252 struct brw_vertex_program
{
253 struct gl_vertex_program program
;
258 /** Subclass of Mesa geometry program */
259 struct brw_geometry_program
{
260 struct gl_geometry_program program
;
261 unsigned id
; /**< serial no. to identify geom progs, never re-used */
265 /** Subclass of Mesa fragment program */
266 struct brw_fragment_program
{
267 struct gl_fragment_program program
;
268 GLuint id
; /**< serial no. to identify frag progs, never re-used */
272 /** Subclass of Mesa compute program */
273 struct brw_compute_program
{
274 struct gl_compute_program program
;
275 unsigned id
; /**< serial no. to identify compute progs, never re-used */
280 struct gl_shader base
;
285 /* Note: If adding fields that need anything besides a normal memcmp() for
286 * comparing them, be sure to go fix brw_stage_prog_data_compare().
288 struct brw_stage_prog_data
{
290 /** size of our binding table. */
294 * surface indices for the various groups of surfaces
296 uint32_t pull_constants_start
;
297 uint32_t texture_start
;
298 uint32_t gather_texture_start
;
301 uint32_t shader_time_start
;
305 GLuint nr_params
; /**< number of float params/constants */
306 GLuint nr_pull_params
;
309 * Register where the thread expects to find input data from the URB
310 * (typically uniforms, followed by vertex or fragment attributes).
312 unsigned dispatch_grf_start_reg
;
314 /* Pointers to tracked values (only valid once
315 * _mesa_load_state_parameters has been called at runtime).
317 * These must be the last fields of the struct (see
318 * brw_stage_prog_data_compare()).
320 const gl_constant_value
**param
;
321 const gl_constant_value
**pull_param
;
324 /* Data about a particular attempt to compile a program. Note that
325 * there can be many of these, each in a different GL state
326 * corresponding to a different brw_wm_prog_key struct, with different
329 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
332 struct brw_wm_prog_data
{
333 struct brw_stage_prog_data base
;
335 GLuint curb_read_length
;
336 GLuint num_varying_inputs
;
338 GLuint dispatch_grf_start_reg_16
;
340 GLuint reg_blocks_16
;
341 GLuint total_scratch
;
345 * surface indices the WM-specific surfaces
347 uint32_t render_target_start
;
353 bool uses_pos_offset
;
355 uint32_t prog_offset_16
;
358 * Mask of which interpolation modes are required by the fragment shader.
359 * Used in hardware setup on gen6+.
361 uint32_t barycentric_interp_modes
;
364 * Map from gl_varying_slot to the position within the FS setup data
365 * payload where the varying's attribute vertex deltas should be delivered.
366 * For varying slots that are not used by the FS, the value is -1.
368 int urb_setup
[VARYING_SLOT_MAX
];
372 * Enum representing the i965-specific vertex results that don't correspond
373 * exactly to any element of gl_varying_slot. The values of this enum are
374 * assigned such that they don't conflict with gl_varying_slot.
378 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
379 BRW_VARYING_SLOT_PAD
,
381 * Technically this is not a varying but just a placeholder that
382 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
383 * builtin variable to be compiled correctly. see compile_sf_prog() for
386 BRW_VARYING_SLOT_PNTC
,
387 BRW_VARYING_SLOT_COUNT
392 * Data structure recording the relationship between the gl_varying_slot enum
393 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
394 * single octaword within the VUE (128 bits).
396 * Note that each BRW register contains 256 bits (2 octawords), so when
397 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
398 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
399 * in a vertex shader), each register corresponds to a single VUE slot, since
400 * it contains data for two separate vertices.
404 * Bitfield representing all varying slots that are (a) stored in this VUE
405 * map, and (b) actually written by the shader. Does not include any of
406 * the additional varying slots defined in brw_varying_slot.
408 GLbitfield64 slots_valid
;
411 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
412 * not stored in a slot (because they are not written, or because
413 * additional processing is applied before storing them in the VUE), the
416 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
419 * Map from VUE slot to gl_varying_slot value. For slots that do not
420 * directly correspond to a gl_varying_slot, the value comes from
423 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
424 * simplifies code that uses the value stored in slot_to_varying to
425 * create a bit mask).
427 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
430 * Total number of VUE slots in use
436 * Convert a VUE slot number into a byte offset within the VUE.
438 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
444 * Convert a vertex output (brw_varying_slot) into a byte offset within the
447 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
450 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
453 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
454 GLbitfield64 slots_valid
);
458 * Bitmask indicating which fragment shader inputs represent varyings (and
459 * hence have to be delivered to the fragment shader by the SF/SBE stage).
461 #define BRW_FS_VARYING_INPUT_MASK \
462 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
463 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
467 * Mapping of VUE map slots to interpolation modes.
469 struct interpolation_mode_map
{
470 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
473 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
475 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
476 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
482 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
484 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
485 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
492 struct brw_sf_prog_data
{
493 GLuint urb_read_length
;
496 /* Each vertex may have upto 12 attributes, 4 components each,
497 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
500 * Actually we use 4 for each, so call it 12 rows.
502 GLuint urb_entry_size
;
507 * We always program SF to start reading at an offset of 1 (2 varying slots)
508 * from the start of the vertex URB entry. This causes it to skip:
509 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
510 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
512 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
515 struct brw_clip_prog_data
{
516 GLuint curb_read_length
; /* user planes? */
518 GLuint urb_read_length
;
522 struct brw_ff_gs_prog_data
{
523 GLuint urb_read_length
;
527 * Gen6 transform feedback: Amount by which the streaming vertex buffer
528 * indices should be incremented each time the GS is invoked.
530 unsigned svbi_postincrement_value
;
534 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
537 struct brw_vec4_prog_data
{
538 struct brw_stage_prog_data base
;
539 struct brw_vue_map vue_map
;
541 GLuint curb_read_length
;
542 GLuint urb_read_length
;
544 GLuint total_scratch
;
546 /* Used for calculating urb partitions. In the VS, this is the size of the
547 * URB entry used for both input and output to the thread. In the GS, this
548 * is the size of the URB entry used for output.
550 GLuint urb_entry_size
;
554 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
557 struct brw_vs_prog_data
{
558 struct brw_vec4_prog_data base
;
560 GLbitfield64 inputs_read
;
566 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
569 struct brw_gs_prog_data
571 struct brw_vec4_prog_data base
;
574 * Size of an output vertex, measured in HWORDS (32 bytes).
576 unsigned output_vertex_size_hwords
;
578 unsigned output_topology
;
581 * Size of the control data (cut bits or StreamID bits), in hwords (32
582 * bytes). 0 if there is no control data.
584 unsigned control_data_header_size_hwords
;
587 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
588 * if the control data is StreamID bits, or
589 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
590 * Ignored if control_data_header_size is 0.
592 unsigned control_data_format
;
594 bool include_primitive_id
;
599 * True if the thread should be dispatched in DUAL_INSTANCE mode, false if
600 * it should be dispatched in DUAL_OBJECT mode.
602 bool dual_instanced_dispatch
;
605 /** Number of texture sampler units */
606 #define BRW_MAX_TEX_UNIT 32
608 /** Max number of render targets in a shader */
609 #define BRW_MAX_DRAW_BUFFERS 8
611 /** Max number of atomic counter buffer objects in a shader */
612 #define BRW_MAX_ABO 16
615 * Max number of binding table entries used for stream output.
617 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
618 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
620 * On Gen6, the size of transform feedback data is limited not by the number
621 * of components but by the number of binding table entries we set aside. We
622 * use one binding table entry for a float, one entry for a vector, and one
623 * entry per matrix column. Since the only way we can communicate our
624 * transform feedback capabilities to the client is via
625 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
626 * worst case, in which all the varyings are floats, so we use up one binding
627 * table entry per component. Therefore we need to set aside at least 64
628 * binding table entries for use by transform feedback.
630 * Note: since we don't currently pack varyings, it is currently impossible
631 * for the client to actually use up all of these binding table entries--if
632 * all of their varyings were floats, they would run out of varying slots and
633 * fail to link. But that's a bug, so it seems prudent to go ahead and
634 * allocate the number of binding table entries we will need once the bug is
637 #define BRW_MAX_SOL_BINDINGS 64
639 /** Maximum number of actual buffers used for stream output */
640 #define BRW_MAX_SOL_BUFFERS 4
642 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
643 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
646 2 /* shader time, pull constants */)
648 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
649 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
652 * Stride in bytes between shader_time entries.
654 * We separate entries by a cacheline to reduce traffic between EUs writing to
657 #define SHADER_TIME_STRIDE 64
664 BRW_BLORP_CONST_COLOR_PROG
,
669 BRW_SF_UNIT
, /* scissor state on gen6 */
682 struct brw_cache_item
{
684 * Effectively part of the key, cache_id identifies what kind of state
685 * buffer is involved, and also which brw->state.dirty.cache flag should
686 * be set when this cache item is chosen.
688 enum brw_cache_id cache_id
;
689 /** 32-bit hash of the key data */
691 GLuint key_size
; /* for variable-sized keys */
698 struct brw_cache_item
*next
;
702 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
703 typedef void (*cache_aux_free_func
)(const void *aux
);
706 struct brw_context
*brw
;
708 struct brw_cache_item
**items
;
710 GLuint size
, n_items
;
712 uint32_t next_offset
;
716 * Optional functions used in determining whether the prog_data for a new
717 * cache item matches an existing cache item (in case there's relevant data
718 * outside of the prog_data). If NULL, a plain memcmp is done.
720 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
721 /** Optional functions for freeing other pointers attached to a prog_data. */
722 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
726 /* Considered adding a member to this struct to document which flags
727 * an update might raise so that ordering of the state atoms can be
728 * checked or derived at runtime. Dropped the idea in favor of having
729 * a debug mode where the state is monitored for flags which are
730 * raised that have already been tested against.
732 struct brw_tracked_state
{
733 struct brw_state_flags dirty
;
734 void (*emit
)( struct brw_context
*brw
);
737 enum shader_time_shader_type
{
753 /* Flags for brw->state.cache.
755 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
756 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
757 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
758 #define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
759 #define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
760 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
761 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
762 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
763 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
764 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
765 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
766 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
767 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
768 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
769 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
770 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
771 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
772 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
774 struct brw_vertex_buffer
{
775 /** Buffer object containing the uploaded vertex data */
778 /** Byte stride between elements in the uploaded array */
782 struct brw_vertex_element
{
783 const struct gl_client_array
*glarray
;
787 /** Offset of the first element within the buffer object */
791 struct brw_query_object
{
792 struct gl_query_object Base
;
794 /** Last query BO associated with this query. */
797 /** Last index in bo with query data for this object. */
801 struct intel_sync_object
{
802 struct gl_sync_object Base
;
804 /** Batch associated with this sync object */
814 struct intel_batchbuffer
{
815 /** Current batchbuffer being queued up. */
817 /** Last BO submitted to the hardware. Used for glFinish(). */
818 drm_intel_bo
*last_bo
;
819 /** BO for post-sync nonzero writes for gen6 workaround. */
820 drm_intel_bo
*workaround_bo
;
821 bool need_workaround_flush
;
823 uint16_t emit
, total
;
824 uint16_t used
, reserved_space
;
827 #define BATCH_SZ (8192*sizeof(uint32_t))
829 uint32_t state_batch_offset
;
830 enum brw_gpu_ring ring
;
831 bool needs_sol_reset
;
839 #define BRW_MAX_XFB_STREAMS 4
841 struct brw_transform_feedback_object
{
842 struct gl_transform_feedback_object base
;
844 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
845 drm_intel_bo
*offset_bo
;
847 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
850 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
851 GLenum primitive_mode
;
854 * Count of primitives generated during this transform feedback operation.
857 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
858 drm_intel_bo
*prim_count_bo
;
859 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
863 * Number of vertices written between last Begin/EndTransformFeedback().
865 * Used to implement DrawTransformFeedback().
867 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
868 bool vertices_written_valid
;
872 * Data shared between each programmable stage in the pipeline (vs, gs, and
875 struct brw_stage_state
877 gl_shader_stage stage
;
878 struct brw_stage_prog_data
*prog_data
;
881 * Optional scratch buffer used to store spilled register values and
882 * variably-indexed GRF arrays.
884 drm_intel_bo
*scratch_bo
;
886 /** Offset in the program cache to the program */
887 uint32_t prog_offset
;
889 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
890 uint32_t state_offset
;
892 uint32_t push_const_offset
; /* Offset in the batchbuffer */
893 int push_const_size
; /* in 256-bit register increments */
895 /* Binding table: pointers to SURFACE_STATE entries. */
896 uint32_t bind_bo_offset
;
897 uint32_t surf_offset
[BRW_MAX_SURFACES
];
899 /** SAMPLER_STATE count and table offset */
900 uint32_t sampler_count
;
901 uint32_t sampler_offset
;
906 * brw_context is derived from gl_context.
910 struct gl_context ctx
; /**< base class, must be first field */
914 void (*update_texture_surface
)(struct gl_context
*ctx
,
916 uint32_t *surf_offset
,
918 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
919 struct gl_renderbuffer
*rb
,
922 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
925 void (*create_raw_surface
)(struct brw_context
*brw
,
929 uint32_t *out_offset
,
931 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
932 uint32_t *out_offset
,
934 unsigned buffer_offset
,
935 unsigned surface_format
,
936 unsigned buffer_size
,
942 * Send the appropriate state packets to configure depth, stencil, and
943 * HiZ buffers (i965+ only)
945 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
946 struct intel_mipmap_tree
*depth_mt
,
947 uint32_t depth_offset
,
948 uint32_t depthbuffer_format
,
949 uint32_t depth_surface_type
,
950 struct intel_mipmap_tree
*stencil_mt
,
951 bool hiz
, bool separate_stencil
,
952 uint32_t width
, uint32_t height
,
953 uint32_t tile_x
, uint32_t tile_y
);
959 drm_intel_context
*hw_ctx
;
962 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
963 * and would need flushing before being used from another cache domain that
964 * isn't coherent with it (i.e. the sampler).
966 struct set
*render_cache
;
969 * Number of resets observed in the system at context creation.
971 * This is tracked in the context so that we can determine that another
974 uint32_t reset_count
;
976 struct intel_batchbuffer batch
;
981 uint32_t next_offset
;
985 * Set if rendering has occured to the drawable's front buffer.
987 * This is used in the DRI2 case to detect that glFlush should also copy
988 * the contents of the fake front buffer to the real front buffer.
990 bool front_buffer_dirty
;
992 /** Framerate throttling: @{ */
993 drm_intel_bo
*first_post_swapbuffers_batch
;
1004 bool always_flush_batch
;
1005 bool always_flush_cache
;
1006 bool disable_throttling
;
1008 bool disable_derivative_optimization
;
1010 driOptionCache optionCache
;
1013 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1015 GLenum reduced_primitive
;
1018 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1019 * variable is set, this is the flag indicating to do expensive work that
1020 * might lead to a perf_debug() call.
1024 uint32_t max_gtt_map_object_size
;
1035 bool has_separate_stencil
;
1036 bool must_use_separate_stencil
;
1039 bool has_surface_tile_offset
;
1041 bool has_negative_rhw_bug
;
1047 * Some versions of Gen hardware don't do centroid interpolation correctly
1048 * on unlit pixels, causing incorrect values for derivatives near triangle
1049 * edges. Enabling this flag causes the fragment shader to use
1050 * non-centroid interpolation for unlit pixels, at the expense of two extra
1051 * fragment shader instructions.
1053 bool needs_unlit_centroid_workaround
;
1057 struct brw_state_flags dirty
;
1060 struct brw_cache cache
;
1062 /** IDs for meta stencil blit shader programs. */
1063 unsigned meta_stencil_blit_programs
[2];
1065 /* Whether a meta-operation is in progress. */
1066 bool meta_in_progress
;
1068 /* Whether the last depth/stencil packets were both NULL. */
1069 bool no_depth_or_stencil
;
1072 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1073 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1075 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1079 /* Summary of size and varying of active arrays, so we can check
1080 * for changes to this state:
1082 unsigned int min_index
, max_index
;
1084 /* Offset from start of vertex buffer so we can avoid redefining
1085 * the same VB packed over and over again.
1087 unsigned int start_vertex_bias
;
1092 * Index buffer for this draw_prims call.
1094 * Updates are signaled by BRW_NEW_INDICES.
1096 const struct _mesa_index_buffer
*ib
;
1098 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1102 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1103 * avoid re-uploading the IB packet over and over if we're actually
1104 * referencing the same index buffer.
1106 unsigned int start_vertex_offset
;
1109 /* Active vertex program:
1111 const struct gl_vertex_program
*vertex_program
;
1112 const struct gl_geometry_program
*geometry_program
;
1113 const struct gl_fragment_program
*fragment_program
;
1116 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1117 * that we don't have to reemit that state every time we change FBOs.
1122 * Platform specific constants containing the maximum number of threads
1123 * for each pipeline stage.
1129 /* BRW_NEW_URB_ALLOCATIONS:
1132 GLuint vsize
; /* vertex size plus header in urb registers */
1133 GLuint csize
; /* constant buffer size in urb registers */
1134 GLuint sfsize
; /* setup data size in urb registers */
1138 GLuint min_vs_entries
; /* Minimum number of VS entries */
1139 GLuint max_vs_entries
; /* Maximum number of VS entries */
1140 GLuint max_gs_entries
; /* Maximum number of GS entries */
1142 GLuint nr_vs_entries
;
1143 GLuint nr_gs_entries
;
1144 GLuint nr_clip_entries
;
1145 GLuint nr_sf_entries
;
1146 GLuint nr_cs_entries
;
1153 GLuint size
; /* Hardware URB size, in KB. */
1155 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1156 * URB space for the GS.
1158 bool gen6_gs_previously_active
;
1162 /* BRW_NEW_CURBE_OFFSETS:
1165 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1166 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1174 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1175 * for upload to the CURBE.
1177 drm_intel_bo
*curbe_bo
;
1178 /** Offset within curbe_bo of space for current curbe entry */
1179 GLuint curbe_offset
;
1183 * Layout of vertex data exiting the vertex shader.
1185 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1187 struct brw_vue_map vue_map_vs
;
1190 * Layout of vertex data exiting the geometry portion of the pipleine.
1191 * This comes from the geometry shader if one exists, otherwise from the
1194 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1196 struct brw_vue_map vue_map_geom_out
;
1199 struct brw_stage_state base
;
1200 struct brw_vs_prog_data
*prog_data
;
1204 struct brw_stage_state base
;
1205 struct brw_gs_prog_data
*prog_data
;
1208 * True if the 3DSTATE_GS command most recently emitted to the 3D
1209 * pipeline enabled the GS; false otherwise.
1215 struct brw_ff_gs_prog_data
*prog_data
;
1218 /** Offset in the program cache to the CLIP program pre-gen6 */
1219 uint32_t prog_offset
;
1220 uint32_t state_offset
;
1222 uint32_t bind_bo_offset
;
1223 uint32_t surf_offset
[BRW_MAX_GEN6_GS_SURFACES
];
1227 struct brw_clip_prog_data
*prog_data
;
1229 /** Offset in the program cache to the CLIP program pre-gen6 */
1230 uint32_t prog_offset
;
1232 /* Offset in the batch to the CLIP state on pre-gen6. */
1233 uint32_t state_offset
;
1235 /* As of gen6, this is the offset in the batch to the CLIP VP,
1243 struct brw_sf_prog_data
*prog_data
;
1245 /** Offset in the program cache to the CLIP program pre-gen6 */
1246 uint32_t prog_offset
;
1247 uint32_t state_offset
;
1249 bool viewport_transform_enable
;
1253 struct brw_stage_state base
;
1254 struct brw_wm_prog_data
*prog_data
;
1259 * Buffer object used in place of multisampled null render targets on
1260 * Gen6. See brw_update_null_renderbuffer_surface().
1262 drm_intel_bo
*multisampled_null_render_target_bo
;
1263 uint32_t fast_clear_op
;
1268 uint32_t state_offset
;
1269 uint32_t blend_state_offset
;
1270 uint32_t depth_stencil_state_offset
;
1275 struct brw_query_object
*obj
;
1280 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1281 const int *statistics_registers
;
1283 /** The number of active monitors using OA counters. */
1287 * A buffer object storing OA counter snapshots taken at the start and
1288 * end of each batch (creating "bookends" around the batch).
1290 drm_intel_bo
*bookend_bo
;
1292 /** The number of snapshots written to bookend_bo. */
1293 int bookend_snapshots
;
1296 * An array of monitors whose results haven't yet been assembled based on
1297 * the data in buffer objects.
1299 * These may be active, or have already ended. However, the results
1300 * have not been requested.
1302 struct brw_perf_monitor_object
**unresolved
;
1303 int unresolved_elements
;
1304 int unresolved_array_size
;
1307 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1308 * the counter which MI_REPORT_PERF_COUNT stores there.
1310 const int *oa_snapshot_layout
;
1312 /** Number of 32-bit entries in a hardware counter snapshot. */
1313 int entries_per_oa_snapshot
;
1317 const struct brw_tracked_state
**atoms
;
1319 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1323 enum aub_state_struct_type type
;
1324 } *state_batch_list
;
1325 int state_batch_count
;
1327 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1328 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1330 /* Interpolation modes, one byte per vue slot.
1331 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1333 struct interpolation_mode_map interpolation_mode
;
1335 /* PrimitiveRestart */
1338 bool enable_cut_index
;
1341 /** Computed depth/stencil/hiz state from the current attached
1342 * renderbuffers, valid only during the drawing state upload loop after
1343 * brw_workaround_depthstencil_alignment().
1346 struct intel_mipmap_tree
*depth_mt
;
1347 struct intel_mipmap_tree
*stencil_mt
;
1349 /* Inter-tile (page-aligned) byte offsets. */
1350 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1351 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1352 uint32_t tile_x
, tile_y
;
1355 uint32_t num_instances
;
1360 struct gl_shader_program
**shader_programs
;
1361 struct gl_program
**programs
;
1362 enum shader_time_shader_type
*types
;
1363 uint64_t *cumulative
;
1369 struct brw_fast_clear_state
*fast_clear_state
;
1371 __DRIcontext
*driContext
;
1372 struct intel_screen
*intelScreen
;
1375 /*======================================================================
1378 void brwInitVtbl( struct brw_context
*brw
);
1381 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1383 /*======================================================================
1386 extern const char *const brw_vendor_string
;
1388 extern const char *brw_get_renderer_string(unsigned deviceID
);
1391 DRI_CONF_BO_REUSE_DISABLED
,
1392 DRI_CONF_BO_REUSE_ALL
1395 void intel_update_renderbuffers(__DRIcontext
*context
,
1396 __DRIdrawable
*drawable
);
1397 void intel_prepare_render(struct brw_context
*brw
);
1399 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1400 __DRIdrawable
*drawable
);
1402 GLboolean
brwCreateContext(gl_api api
,
1403 const struct gl_config
*mesaVis
,
1404 __DRIcontext
*driContextPriv
,
1405 unsigned major_version
,
1406 unsigned minor_version
,
1410 void *sharedContextPrivate
);
1412 /*======================================================================
1415 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1416 struct intel_mipmap_tree
*mt
,
1417 unsigned level
, unsigned layer
, bool flat
);
1419 void brw_meta_updownsample(struct brw_context
*brw
,
1420 struct intel_mipmap_tree
*src
,
1421 struct intel_mipmap_tree
*dst
);
1423 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1424 GLfloat srcX0
, GLfloat srcY0
,
1425 GLfloat srcX1
, GLfloat srcY1
,
1426 GLfloat dstX0
, GLfloat dstY0
,
1427 GLfloat dstX1
, GLfloat dstY1
);
1429 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1430 struct intel_mipmap_tree
*src
,
1431 struct intel_mipmap_tree
*dst
);
1433 bool brw_meta_fast_clear(struct brw_context
*brw
,
1434 struct gl_framebuffer
*fb
,
1436 bool partial_clear
);
1439 brw_meta_resolve_color(struct brw_context
*brw
,
1440 struct intel_mipmap_tree
*mt
);
1442 brw_meta_fast_clear_free(struct brw_context
*brw
);
1445 /*======================================================================
1448 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1449 uint32_t depth_level
,
1450 uint32_t depth_layer
,
1451 struct intel_mipmap_tree
*stencil_mt
,
1452 uint32_t *out_tile_mask_x
,
1453 uint32_t *out_tile_mask_y
);
1454 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1455 GLbitfield clear_mask
);
1457 /* brw_object_purgeable.c */
1458 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1460 /*======================================================================
1463 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1464 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1465 void brw_emit_query_begin(struct brw_context
*brw
);
1466 void brw_emit_query_end(struct brw_context
*brw
);
1468 /** gen6_queryobj.c */
1469 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1470 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1471 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1472 void brw_store_register_mem64(struct brw_context
*brw
,
1473 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1475 /** intel_batchbuffer.c */
1476 void brw_load_register_mem(struct brw_context
*brw
,
1479 uint32_t read_domains
, uint32_t write_domain
,
1482 /*======================================================================
1485 void brw_debug_batch(struct brw_context
*brw
);
1486 void brw_annotate_aub(struct brw_context
*brw
);
1488 /*======================================================================
1491 void brw_validate_textures( struct brw_context
*brw
);
1494 /*======================================================================
1497 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1499 int brw_get_scratch_size(int size
);
1500 void brw_get_scratch_bo(struct brw_context
*brw
,
1501 drm_intel_bo
**scratch_bo
, int size
);
1502 void brw_init_shader_time(struct brw_context
*brw
);
1503 int brw_get_shader_time_index(struct brw_context
*brw
,
1504 struct gl_shader_program
*shader_prog
,
1505 struct gl_program
*prog
,
1506 enum shader_time_shader_type type
);
1507 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1508 void brw_destroy_shader_time(struct brw_context
*brw
);
1512 void brw_upload_urb_fence(struct brw_context
*brw
);
1516 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1518 /* brw_fs_reg_allocate.cpp
1520 void brw_fs_alloc_reg_sets(struct intel_screen
*screen
);
1522 /* brw_vec4_reg_allocate.cpp */
1523 void brw_vec4_alloc_reg_set(struct intel_screen
*screen
);
1526 int brw_disassemble_inst(FILE *file
, struct brw_context
*brw
,
1527 struct brw_inst
*inst
, bool is_compacted
);
1530 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1532 /* brw_draw_upload.c */
1533 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1534 const struct gl_client_array
*glarray
);
1535 unsigned brw_get_index_type(GLenum type
);
1536 void brw_prepare_vertices(struct brw_context
*brw
);
1538 /* brw_wm_surface_state.c */
1539 void brw_init_surface_formats(struct brw_context
*brw
);
1540 void brw_create_constant_surface(struct brw_context
*brw
,
1544 uint32_t *out_offset
,
1546 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1548 uint32_t *surf_offset
);
1550 brw_update_sol_surface(struct brw_context
*brw
,
1551 struct gl_buffer_object
*buffer_obj
,
1552 uint32_t *out_offset
, unsigned num_vector_components
,
1553 unsigned stride_dwords
, unsigned offset_dwords
);
1554 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1555 struct gl_shader
*shader
,
1556 struct brw_stage_state
*stage_state
,
1557 struct brw_stage_prog_data
*prog_data
);
1558 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1559 struct gl_shader_program
*prog
,
1560 struct brw_stage_state
*stage_state
,
1561 struct brw_stage_prog_data
*prog_data
);
1563 /* brw_surface_formats.c */
1564 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, mesa_format format
);
1565 bool brw_render_target_supported(struct brw_context
*brw
,
1566 struct gl_renderbuffer
*rb
);
1567 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1569 /* brw_performance_monitor.c */
1570 void brw_init_performance_monitors(struct brw_context
*brw
);
1571 void brw_dump_perf_monitors(struct brw_context
*brw
);
1572 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1573 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1575 /* intel_buffer_objects.c */
1576 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1577 const char *bo_name
);
1578 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1579 const char *bo_name
);
1581 /* intel_extensions.c */
1582 extern void intelInitExtensions(struct gl_context
*ctx
);
1585 extern int intel_translate_shadow_compare_func(GLenum func
);
1586 extern int intel_translate_compare_func(GLenum func
);
1587 extern int intel_translate_stencil_op(GLenum op
);
1588 extern int intel_translate_logic_op(GLenum opcode
);
1590 /* intel_syncobj.c */
1591 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1594 struct gl_transform_feedback_object
*
1595 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1597 brw_delete_transform_feedback(struct gl_context
*ctx
,
1598 struct gl_transform_feedback_object
*obj
);
1600 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1601 struct gl_transform_feedback_object
*obj
);
1603 brw_end_transform_feedback(struct gl_context
*ctx
,
1604 struct gl_transform_feedback_object
*obj
);
1606 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1607 struct gl_transform_feedback_object
*obj
,
1610 /* gen7_sol_state.c */
1612 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1613 struct gl_transform_feedback_object
*obj
);
1615 gen7_end_transform_feedback(struct gl_context
*ctx
,
1616 struct gl_transform_feedback_object
*obj
);
1618 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1619 struct gl_transform_feedback_object
*obj
);
1621 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1622 struct gl_transform_feedback_object
*obj
);
1624 /* brw_blorp_blit.cpp */
1626 brw_blorp_framebuffer(struct brw_context
*brw
,
1627 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1628 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1629 GLbitfield mask
, GLenum filter
);
1632 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1633 struct gl_renderbuffer
*src_rb
,
1634 struct gl_texture_image
*dst_image
,
1636 int srcX0
, int srcY0
,
1637 int dstX0
, int dstY0
,
1638 int width
, int height
);
1640 /* gen6_multisample_state.c */
1642 gen6_determine_sample_mask(struct brw_context
*brw
);
1645 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1646 unsigned num_samples
);
1648 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1650 gen6_get_sample_position(struct gl_context
*ctx
,
1651 struct gl_framebuffer
*fb
,
1655 /* gen8_multisample_state.c */
1656 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1657 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1661 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1662 unsigned gs_size
, unsigned fs_size
);
1665 gen7_emit_urb_state(struct brw_context
*brw
,
1666 unsigned nr_vs_entries
, unsigned vs_size
,
1667 unsigned vs_start
, unsigned nr_gs_entries
,
1668 unsigned gs_size
, unsigned gs_start
);
1673 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1675 /*======================================================================
1676 * Inline conversion functions. These are better-typed than the
1677 * macros used previously:
1679 static inline struct brw_context
*
1680 brw_context( struct gl_context
*ctx
)
1682 return (struct brw_context
*)ctx
;
1685 static inline struct brw_vertex_program
*
1686 brw_vertex_program(struct gl_vertex_program
*p
)
1688 return (struct brw_vertex_program
*) p
;
1691 static inline const struct brw_vertex_program
*
1692 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1694 return (const struct brw_vertex_program
*) p
;
1697 static inline struct brw_geometry_program
*
1698 brw_geometry_program(struct gl_geometry_program
*p
)
1700 return (struct brw_geometry_program
*) p
;
1703 static inline struct brw_fragment_program
*
1704 brw_fragment_program(struct gl_fragment_program
*p
)
1706 return (struct brw_fragment_program
*) p
;
1709 static inline const struct brw_fragment_program
*
1710 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1712 return (const struct brw_fragment_program
*) p
;
1716 * Pre-gen6, the register file of the EUs was shared between threads,
1717 * and each thread used some subset allocated on a 16-register block
1718 * granularity. The unit states wanted these block counts.
1721 brw_register_blocks(int reg_count
)
1723 return ALIGN(reg_count
, 16) / 16 - 1;
1726 static inline uint32_t
1727 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1728 uint32_t prog_offset
)
1730 if (brw
->gen
>= 5) {
1731 /* Using state base address. */
1735 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1739 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1741 return brw
->cache
.bo
->offset64
+ prog_offset
;
1744 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1745 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1746 struct exec_list
*instructions
);
1747 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1749 struct opcode_desc
{
1755 extern const struct opcode_desc opcode_descs
[128];
1756 extern const char * const conditional_modifier
[16];
1759 brw_emit_depthbuffer(struct brw_context
*brw
);
1762 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1763 struct intel_mipmap_tree
*depth_mt
,
1764 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1765 uint32_t depth_surface_type
,
1766 struct intel_mipmap_tree
*stencil_mt
,
1767 bool hiz
, bool separate_stencil
,
1768 uint32_t width
, uint32_t height
,
1769 uint32_t tile_x
, uint32_t tile_y
);
1772 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1773 struct intel_mipmap_tree
*depth_mt
,
1774 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1775 uint32_t depth_surface_type
,
1776 struct intel_mipmap_tree
*stencil_mt
,
1777 bool hiz
, bool separate_stencil
,
1778 uint32_t width
, uint32_t height
,
1779 uint32_t tile_x
, uint32_t tile_y
);
1782 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1783 struct intel_mipmap_tree
*depth_mt
,
1784 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1785 uint32_t depth_surface_type
,
1786 struct intel_mipmap_tree
*stencil_mt
,
1787 bool hiz
, bool separate_stencil
,
1788 uint32_t width
, uint32_t height
,
1789 uint32_t tile_x
, uint32_t tile_y
);
1791 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1792 struct intel_mipmap_tree
*depth_mt
,
1793 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1794 uint32_t depth_surface_type
,
1795 struct intel_mipmap_tree
*stencil_mt
,
1796 bool hiz
, bool separate_stencil
,
1797 uint32_t width
, uint32_t height
,
1798 uint32_t tile_x
, uint32_t tile_y
);
1800 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1801 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1803 uint32_t get_hw_prim_for_gl_prim(int mode
);
1806 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1807 struct brw_vec4_prog_key
*key
,
1808 bool program_uses_clip_distance
);
1811 gen6_upload_push_constants(struct brw_context
*brw
,
1812 const struct gl_program
*prog
,
1813 const struct brw_stage_prog_data
*prog_data
,
1814 struct brw_stage_state
*stage_state
,
1815 enum aub_state_struct_type type
);
1817 /* ================================================================
1818 * From linux kernel i386 header files, copes with odd sizes better
1819 * than COPY_DWORDS would:
1820 * XXX Put this in src/mesa/main/imports.h ???
1822 #if defined(i386) || defined(__i386__)
1823 static inline void * __memcpy(void * to
, const void * from
, size_t n
)
1826 __asm__
__volatile__(
1831 "1:\ttestb $1,%b4\n\t"
1835 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1836 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1841 #define __memcpy(a,b,c) memcpy(a,b,c)