2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
46 * URB - uniform resource buffer. A mid-sized buffer which is
47 * partitioned between the fixed function units and used for passing
48 * values (vertices, primitives, constants) between them.
50 * CURBE - constant URB entry. An urb region (entry) used to hold
51 * constant values which the fixed function units can be instructed to
52 * preload into the GRF when spawning a thread.
54 * VUE - vertex URB entry. An urb entry holding a vertex and usually
55 * a vertex header. The header contains control information and
56 * things like primitive type, Begin/end flags and clip codes.
58 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
59 * unit holding rasterization and interpolation parameters.
61 * GRF - general register file. One of several register files
62 * addressable by programmed threads. The inputs (r0, payload, curbe,
63 * urb) of the thread are preloaded to this area before the thread is
64 * spawned. The registers are individually 8 dwords wide and suitable
65 * for general usage. Registers holding thread input values are not
66 * special and may be overwritten.
68 * MRF - message register file. Threads communicate (and terminate)
69 * by sending messages. Message parameters are placed in contiguous
70 * MRF registers. All program output is via these messages. URB
71 * entries are populated by sending a message to the shared URB
72 * function containing the new data, together with a control word,
73 * often an unmodified copy of R0.
75 * R0 - GRF register 0. Typically holds control information used when
76 * sending messages to other threads.
78 * EU or GEN4 EU: The name of the programmable subsystem of the
79 * i965 hardware. Threads are executed by the EU, the registers
80 * described above are part of the EU architecture.
82 * Fixed function units:
84 * CS - Command streamer. Notional first unit, little software
85 * interaction. Holds the URB entries used for constant data, ie the
88 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
89 * this unit is responsible for pulling vertices out of vertex buffers
90 * in vram and injecting them into the processing pipe as VUEs. If
91 * enabled, it first passes them to a VS thread which is a good place
92 * for the driver to implement any active vertex shader.
94 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
95 * enabled, incoming strips etc are passed to GS threads in individual
96 * line/triangle/point units. The GS thread may perform arbitary
97 * computation and emit whatever primtives with whatever vertices it
98 * chooses. This makes GS an excellent place to implement GL's
99 * unfilled polygon modes, though of course it is capable of much
100 * more. Additionally, GS is used to translate away primitives not
101 * handled by latter units, including Quads and Lineloops.
103 * CS - Clipper. Mesa's clipping algorithms are imported to run on
104 * this unit. The fixed function part performs cliptesting against
105 * the 6 fixed clipplanes and makes descisions on whether or not the
106 * incoming primitive needs to be passed to a thread for clipping.
107 * User clip planes are handled via cooperation with the VS thread.
109 * SF - Strips Fans or Setup: Triangles are prepared for
110 * rasterization. Interpolation coefficients are calculated.
111 * Flatshading and two-side lighting usually performed here.
113 * WM - Windower. Interpolation of vertex attributes performed here.
114 * Fragment shader implemented here. SIMD aspects of EU taken full
115 * advantage of, as pixels are processed in blocks of 16.
117 * CC - Color Calculator. No EU threads associated with this unit.
118 * Handles blending and (presumably) depth and stencil testing.
122 #define BRW_MAX_CURBE (32*16)
125 struct brw_instruction
;
126 struct brw_vs_prog_key
;
127 struct brw_wm_prog_key
;
128 struct brw_wm_prog_data
;
132 BRW_STATE_FRAGMENT_PROGRAM
,
133 BRW_STATE_VERTEX_PROGRAM
,
134 BRW_STATE_INPUT_DIMENSIONS
,
135 BRW_STATE_CURBE_OFFSETS
,
136 BRW_STATE_REDUCED_PRIMITIVE
,
139 BRW_STATE_WM_INPUT_DIMENSIONS
,
142 BRW_STATE_VS_BINDING_TABLE
,
143 BRW_STATE_GS_BINDING_TABLE
,
144 BRW_STATE_PS_BINDING_TABLE
,
148 BRW_STATE_NR_WM_SURFACES
,
149 BRW_STATE_NR_VS_SURFACES
,
150 BRW_STATE_INDEX_BUFFER
,
151 BRW_STATE_VS_CONSTBUF
,
152 BRW_STATE_PROGRAM_CACHE
,
153 BRW_STATE_STATE_BASE_ADDRESS
,
154 BRW_STATE_SOL_INDICES
,
157 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
158 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
159 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
160 #define BRW_NEW_INPUT_DIMENSIONS (1 << BRW_STATE_INPUT_DIMENSIONS)
161 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
162 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
163 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
164 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
165 #define BRW_NEW_WM_INPUT_DIMENSIONS (1 << BRW_STATE_WM_INPUT_DIMENSIONS)
166 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
167 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
168 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
169 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
170 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
171 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
172 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
174 * Used for any batch entry with a relocated pointer that will be used
175 * by any 3D rendering.
177 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
178 /** \see brw.state.depth_region */
179 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
180 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
181 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
182 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
183 #define BRW_NEW_SOL_INDICES (1 << BRW_STATE_SOL_INDICES)
185 struct brw_state_flags
{
186 /** State update flags signalled by mesa internals */
189 * State update flags signalled as the result of brw_tracked_state updates
192 /** State update flags signalled by brw_state_cache.c searches */
196 #define AUB_TRACE_TYPE_MASK 0x0000ff00
197 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
198 #define AUB_TRACE_TYPE_BATCH (1 << 8)
199 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
200 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
201 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
202 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
203 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
204 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
205 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
206 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
207 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
208 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
211 * state_struct_type enum values are encoded with the top 16 bits representing
212 * the type to be delivered to the .aub file, and the bottom 16 bits
213 * representing the subtype. This macro performs the encoding.
215 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
217 enum state_struct_type
{
218 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
219 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
220 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
221 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
222 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
223 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
224 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
225 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
226 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
227 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
228 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
229 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
230 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
232 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
233 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
234 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
236 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
237 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
238 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
239 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
240 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
244 * Decode a state_struct_type value to determine the type that should be
245 * stored in the .aub file.
247 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
249 return (ss_type
& 0xFFFF0000) >> 16;
253 * Decode a state_struct_type value to determine the subtype that should be
254 * stored in the .aub file.
256 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
258 return ss_type
& 0xFFFF;
261 /** Subclass of Mesa vertex program */
262 struct brw_vertex_program
{
263 struct gl_vertex_program program
;
265 bool use_const_buffer
;
269 /** Subclass of Mesa fragment program */
270 struct brw_fragment_program
{
271 struct gl_fragment_program program
;
272 GLuint id
; /**< serial no. to identify frag progs, never re-used */
276 struct gl_shader base
;
278 /** Shader IR transformed for native compile, at link time. */
279 struct exec_list
*ir
;
282 struct brw_shader_program
{
283 struct gl_shader_program base
;
286 enum param_conversion
{
294 /* Data about a particular attempt to compile a program. Note that
295 * there can be many of these, each in a different GL state
296 * corresponding to a different brw_wm_prog_key struct, with different
299 struct brw_wm_prog_data
{
300 GLuint curb_read_length
;
301 GLuint urb_read_length
;
303 GLuint first_curbe_grf
;
304 GLuint first_curbe_grf_16
;
306 GLuint reg_blocks_16
;
307 GLuint total_scratch
;
309 GLuint nr_params
; /**< number of float params/constants */
310 GLuint nr_pull_params
;
314 uint32_t prog_offset_16
;
317 * Mask of which interpolation modes are required by the fragment shader.
318 * Used in hardware setup on gen6+.
320 uint32_t barycentric_interp_modes
;
322 /* Pointer to tracked values (only valid once
323 * _mesa_load_state_parameters has been called at runtime).
325 const float *param
[MAX_UNIFORMS
* 4]; /* should be: BRW_MAX_CURBE */
326 enum param_conversion param_convert
[MAX_UNIFORMS
* 4];
327 const float *pull_param
[MAX_UNIFORMS
* 4];
328 enum param_conversion pull_param_convert
[MAX_UNIFORMS
* 4];
332 * Enum representing the i965-specific vertex results that don't correspond
333 * exactly to any element of gl_vert_result. The values of this enum are
334 * assigned such that they don't conflict with gl_vert_result.
338 BRW_VERT_RESULT_NDC
= VERT_RESULT_MAX
,
339 BRW_VERT_RESULT_HPOS_DUPLICATE
,
342 * It's actually not a vert_result but just a _mark_ to let sf aware that
343 * he need do something special to handle gl_PointCoord builtin variable
344 * correctly. see compile_sf_prog() for more info.
346 BRW_VERT_RESULT_PNTC
,
352 * Data structure recording the relationship between the gl_vert_result enum
353 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
354 * single octaword within the VUE (128 bits).
356 * Note that each BRW register contains 256 bits (2 octawords), so when
357 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
358 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
359 * in a vertex shader), each register corresponds to a single VUE slot, since
360 * it contains data for two separate vertices.
364 * Map from gl_vert_result value to VUE slot. For gl_vert_results that are
365 * not stored in a slot (because they are not written, or because
366 * additional processing is applied before storing them in the VUE), the
369 int vert_result_to_slot
[BRW_VERT_RESULT_MAX
];
372 * Map from VUE slot to gl_vert_result value. For slots that do not
373 * directly correspond to a gl_vert_result, the value comes from
376 * For slots that are not in use, the value is BRW_VERT_RESULT_MAX (this
377 * simplifies code that uses the value stored in slot_to_vert_result to
378 * create a bit mask).
380 int slot_to_vert_result
[BRW_VERT_RESULT_MAX
];
383 * Total number of VUE slots in use
389 * Convert a VUE slot number into a byte offset within the VUE.
391 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
397 * Convert a vert_result into a byte offset within the VUE.
399 static inline GLuint
brw_vert_result_to_offset(struct brw_vue_map
*vue_map
,
402 return brw_vue_slot_to_offset(vue_map
->vert_result_to_slot
[vert_result
]);
406 struct brw_sf_prog_data
{
407 GLuint urb_read_length
;
410 /* Each vertex may have upto 12 attributes, 4 components each,
411 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
414 * Actually we use 4 for each, so call it 12 rows.
416 GLuint urb_entry_size
;
419 struct brw_clip_prog_data
{
420 GLuint curb_read_length
; /* user planes? */
422 GLuint urb_read_length
;
426 struct brw_gs_prog_data
{
427 GLuint urb_read_length
;
431 * Gen6 transform feedback: Amount by which the streaming vertex buffer
432 * indices should be incremented each time the GS is invoked.
434 unsigned svbi_postincrement_value
;
437 struct brw_vs_prog_data
{
438 struct brw_vue_map vue_map
;
440 GLuint curb_read_length
;
441 GLuint urb_read_length
;
443 GLbitfield64 outputs_written
;
444 GLuint nr_params
; /**< number of float params/constants */
445 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
446 GLuint total_scratch
;
448 GLbitfield64 inputs_read
;
450 /* Used for calculating urb partitions:
452 GLuint urb_entry_size
;
454 const float *param
[MAX_UNIFORMS
* 4]; /* should be: BRW_MAX_CURBE */
455 const float *pull_param
[MAX_UNIFORMS
* 4];
457 bool uses_new_param_layout
;
465 /* Size == 0 if output either not written, or always [0,0,0,1]
467 struct brw_vs_ouput_sizes
{
468 GLubyte output_size
[VERT_RESULT_MAX
];
472 /** Number of texture sampler units */
473 #define BRW_MAX_TEX_UNIT 16
475 /** Max number of render targets in a shader */
476 #define BRW_MAX_DRAW_BUFFERS 8
479 * Max number of binding table entries used for stream output.
481 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
482 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
484 * On Gen6, the size of transform feedback data is limited not by the number
485 * of components but by the number of binding table entries we set aside. We
486 * use one binding table entry for a float, one entry for a vector, and one
487 * entry per matrix column. Since the only way we can communicate our
488 * transform feedback capabilities to the client is via
489 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
490 * worst case, in which all the varyings are floats, so we use up one binding
491 * table entry per component. Therefore we need to set aside at least 64
492 * binding table entries for use by transform feedback.
494 * Note: since we don't currently pack varyings, it is currently impossible
495 * for the client to actually use up all of these binding table entries--if
496 * all of their varyings were floats, they would run out of varying slots and
497 * fail to link. But that's a bug, so it seems prudent to go ahead and
498 * allocate the number of binding table entries we will need once the bug is
501 #define BRW_MAX_SOL_BINDINGS 64
503 /** Maximum number of actual buffers used for stream output */
504 #define BRW_MAX_SOL_BUFFERS 4
507 * Helpers to create Surface Binding Table indexes for draw buffers,
508 * textures, and constant buffers.
510 * Shader threads access surfaces via numeric handles, rather than directly
511 * using pointers. The binding table maps these numeric handles to the
512 * address of the actual buffer.
514 * For example, a shader might ask to sample from "surface 7." In this case,
515 * bind[7] would contain a pointer to a texture.
517 * Currently, our WM binding tables are (arbitrarily) programmed as follows:
519 * +-------------------------------+
520 * | 0 | Draw buffer 0 |
523 * | 7 | Draw buffer 7 |
524 * |-----|-------------------------|
525 * | 8 | WM Pull Constant Buffer |
526 * |-----|-------------------------|
530 * | 24 | Texture 15 |
531 * +-------------------------------+
533 * Our VS binding tables are programmed as follows:
535 * +-----+-------------------------+
536 * | 0 | VS Pull Constant Buffer |
537 * +-----+-------------------------+
541 * | 16 | Texture 15 |
542 * +-------------------------------+
544 * Our (gen6) GS binding tables are programmed as follows:
546 * +-----+-------------------------+
547 * | 0 | SOL Binding 0 |
550 * | 63 | SOL Binding 63 |
551 * +-----+-------------------------+
553 * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be
554 * the identity function or things will break. We do want to keep draw buffers
555 * first so we can use headerless render target writes for RT 0.
557 #define SURF_INDEX_DRAW(d) (d)
558 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
559 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
561 /** Maximum size of the binding table. */
562 #define BRW_MAX_WM_SURFACES SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT)
564 #define SURF_INDEX_VERT_CONST_BUFFER (0)
565 #define SURF_INDEX_VS_TEXTURE(t) (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t))
566 #define BRW_MAX_VS_SURFACES SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT)
568 #define SURF_INDEX_SOL_BINDING(t) ((t))
569 #define BRW_MAX_GS_SURFACES SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
573 BRW_DEPTH_STENCIL_STATE
,
574 BRW_COLOR_CALC_STATE
,
583 BRW_SF_UNIT
, /* scissor state on gen6 */
595 struct brw_cache_item
{
597 * Effectively part of the key, cache_id identifies what kind of state
598 * buffer is involved, and also which brw->state.dirty.cache flag should
599 * be set when this cache item is chosen.
601 enum brw_cache_id cache_id
;
602 /** 32-bit hash of the key data */
604 GLuint key_size
; /* for variable-sized keys */
611 struct brw_cache_item
*next
;
617 struct brw_context
*brw
;
619 struct brw_cache_item
**items
;
621 GLuint size
, n_items
;
623 uint32_t next_offset
;
628 /* Considered adding a member to this struct to document which flags
629 * an update might raise so that ordering of the state atoms can be
630 * checked or derived at runtime. Dropped the idea in favor of having
631 * a debug mode where the state is monitored for flags which are
632 * raised that have already been tested against.
634 struct brw_tracked_state
{
635 struct brw_state_flags dirty
;
636 void (*emit
)( struct brw_context
*brw
);
639 /* Flags for brw->state.cache.
641 #define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE)
642 #define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
643 #define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
644 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
645 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
646 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
647 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
648 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
649 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
650 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
651 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
652 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
653 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
654 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
655 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
656 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
657 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
658 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
660 struct brw_cached_batch_item
{
661 struct header
*header
;
663 struct brw_cached_batch_item
*next
;
668 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
669 * be easier if C allowed arrays of packed elements?
671 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
673 struct brw_vertex_buffer
{
674 /** Buffer object containing the uploaded vertex data */
677 /** Byte stride between elements in the uploaded array */
681 struct brw_vertex_element
{
682 const struct gl_client_array
*glarray
;
686 /** The corresponding Mesa vertex attribute */
687 gl_vert_attrib attrib
;
688 /** Size of a complete element */
690 /** Offset of the first element within the buffer object */
696 struct brw_vertex_info
{
697 GLuint sizes
[ATTRIB_BIT_DWORDS
* 2]; /* sizes:2[VERT_ATTRIB_MAX] */
700 struct brw_query_object
{
701 struct gl_query_object Base
;
703 /** Last query BO associated with this query. */
705 /** First index in bo with query data for this object. */
707 /** Last index in bo with query data for this object. */
713 * brw_context is derived from intel_context.
717 struct intel_context intel
; /**< base class, must be first field */
718 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
720 bool emit_state_always
;
721 bool has_surface_tile_offset
;
723 bool has_negative_rhw_bug
;
724 bool has_aa_line_parameters
;
729 struct brw_state_flags dirty
;
732 struct brw_cache cache
;
733 struct brw_cached_batch_item
*cached_batch_items
;
736 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
737 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
743 } current_buffers
[VERT_ATTRIB_MAX
];
745 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
747 GLuint nr_buffers
, nr_current_buffers
;
749 /* Summary of size and varying of active arrays, so we can check
750 * for changes to this state:
752 struct brw_vertex_info info
;
753 unsigned int min_index
, max_index
;
755 /* Offset from start of vertex buffer so we can avoid redefining
756 * the same VB packed over and over again.
758 unsigned int start_vertex_bias
;
763 * Index buffer for this draw_prims call.
765 * Updates are signaled by BRW_NEW_INDICES.
767 const struct _mesa_index_buffer
*ib
;
769 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
773 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
774 * avoid re-uploading the IB packet over and over if we're actually
775 * referencing the same index buffer.
777 unsigned int start_vertex_offset
;
780 /* Active vertex program:
782 const struct gl_vertex_program
*vertex_program
;
783 const struct gl_fragment_program
*fragment_program
;
785 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
786 uint32_t CMD_VF_STATISTICS
;
787 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
788 uint32_t CMD_PIPELINE_SELECT
;
791 * Platform specific constants containing the maximum number of threads
792 * for each pipeline stage.
798 /* BRW_NEW_URB_ALLOCATIONS:
801 GLuint vsize
; /* vertex size plus header in urb registers */
802 GLuint csize
; /* constant buffer size in urb registers */
803 GLuint sfsize
; /* setup data size in urb registers */
807 GLuint max_vs_entries
; /* Maximum number of VS entries */
808 GLuint max_gs_entries
; /* Maximum number of GS entries */
810 GLuint nr_vs_entries
;
811 GLuint nr_gs_entries
;
812 GLuint nr_clip_entries
;
813 GLuint nr_sf_entries
;
814 GLuint nr_cs_entries
;
817 * The length of each URB entry owned by the VS (or GS), as
818 * a number of 1024-bit (128-byte) rows. Should be >= 1.
820 * gen7: Same meaning, but in 512-bit (64-byte) rows.
830 GLuint size
; /* Hardware URB size, in KB. */
832 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
833 * URB space for the GS.
835 bool gen6_gs_previously_active
;
839 /* BRW_NEW_CURBE_OFFSETS:
842 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
843 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
850 drm_intel_bo
*curbe_bo
;
851 /** Offset within curbe_bo of space for current curbe entry */
853 /** Offset within curbe_bo of space for next curbe entry */
854 GLuint curbe_next_offset
;
857 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
858 * in brw_curbe.c with the same set of constant data to be uploaded,
859 * so we'd rather not upload new constants in that case (it can cause
860 * a pipeline bubble since only up to 4 can be pipelined at a time).
864 * Allocation for where to calculate the next set of CURBEs.
865 * It's a hot enough path that malloc/free of that data matters.
871 /** SAMPLER_STATE count and offset */
878 struct brw_vs_prog_data
*prog_data
;
879 int8_t *constant_map
; /* variable array following prog_data */
881 drm_intel_bo
*scratch_bo
;
882 drm_intel_bo
*const_bo
;
883 /** Offset in the program cache to the VS program */
884 uint32_t prog_offset
;
885 uint32_t state_offset
;
887 uint32_t push_const_offset
; /* Offset in the batchbuffer */
888 int push_const_size
; /* in 256-bit register increments */
890 /** @{ register allocator */
892 struct ra_regs
*regs
;
895 * Array of the ra classes for the unaligned contiguous register
901 * Mapping for register-allocated objects in *regs to the first
902 * GRF for that object.
904 uint8_t *ra_reg_to_grf
;
907 uint32_t bind_bo_offset
;
908 uint32_t surf_offset
[BRW_MAX_VS_SURFACES
];
912 struct brw_gs_prog_data
*prog_data
;
915 /** Offset in the program cache to the CLIP program pre-gen6 */
916 uint32_t prog_offset
;
917 uint32_t state_offset
;
919 uint32_t bind_bo_offset
;
920 uint32_t surf_offset
[BRW_MAX_GS_SURFACES
];
924 struct brw_clip_prog_data
*prog_data
;
926 /** Offset in the program cache to the CLIP program pre-gen6 */
927 uint32_t prog_offset
;
929 /* Offset in the batch to the CLIP state on pre-gen6. */
930 uint32_t state_offset
;
932 /* As of gen6, this is the offset in the batch to the CLIP VP,
940 struct brw_sf_prog_data
*prog_data
;
942 /** Offset in the program cache to the CLIP program pre-gen6 */
943 uint32_t prog_offset
;
944 uint32_t state_offset
;
949 struct brw_wm_prog_data
*prog_data
;
950 struct brw_wm_compile
*compile_data
;
952 /** Input sizes, calculated from active vertex program.
953 * One bit per fragment program input attribute.
955 GLbitfield input_size_masks
[4];
957 /** offsets in the batch to sampler default colors (texture border color)
959 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
963 drm_intel_bo
*scratch_bo
;
965 /** Offset in the program cache to the WM program */
966 uint32_t prog_offset
;
968 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
970 drm_intel_bo
*const_bo
; /* pull constant buffer. */
972 * This is offset in the batch to the push constants on gen6.
974 * Pre-gen6, push constants live in the CURBE.
976 uint32_t push_const_offset
;
978 /** Binding table of pointers to surf_bo entries */
979 uint32_t bind_bo_offset
;
980 uint32_t surf_offset
[BRW_MAX_WM_SURFACES
];
982 /** @{ register allocator */
984 struct ra_regs
*regs
;
986 /** Array of the ra classes for the unaligned contiguous
987 * register block sizes used.
992 * Mapping for register-allocated objects in *regs to the first
993 * GRF for that object.
995 uint8_t *ra_reg_to_grf
;
998 * ra class for the aligned pairs we use for PLN, which doesn't
999 * appear in *classes.
1001 int aligned_pairs_class
;
1008 uint32_t state_offset
;
1009 uint32_t blend_state_offset
;
1010 uint32_t depth_stencil_state_offset
;
1015 struct brw_query_object
*obj
;
1020 /* Used to give every program string a unique id
1025 const struct brw_tracked_state
**atoms
;
1027 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1031 enum state_struct_type type
;
1032 } *state_batch_list
;
1033 int state_batch_count
;
1035 struct brw_sol_state
{
1036 uint32_t svbi_0_starting_index
;
1037 uint32_t svbi_0_max_index
;
1038 uint32_t offset_0_batch_start
;
1039 uint32_t primitives_generated
;
1040 uint32_t primitives_written
;
1041 bool counting_primitives_generated
;
1042 bool counting_primitives_written
;
1045 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1046 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1048 /* PrimitiveRestart */
1051 bool enable_cut_index
;
1054 uint32_t num_instances
;
1059 #define BRW_PACKCOLOR8888(r,g,b,a) ((r<<24) | (g<<16) | (b<<8) | a)
1061 struct brw_instruction_info
{
1067 extern const struct brw_instruction_info brw_opcodes
[128];
1069 /*======================================================================
1072 void brwInitVtbl( struct brw_context
*brw
);
1074 /*======================================================================
1077 bool brwCreateContext(int api
,
1078 const struct gl_config
*mesaVis
,
1079 __DRIcontext
*driContextPriv
,
1080 void *sharedContextPrivate
);
1082 /*======================================================================
1085 void brw_init_queryobj_functions(struct dd_function_table
*functions
);
1086 void brw_prepare_query_begin(struct brw_context
*brw
);
1087 void brw_emit_query_begin(struct brw_context
*brw
);
1088 void brw_emit_query_end(struct brw_context
*brw
);
1090 /*======================================================================
1093 void brw_debug_batch(struct intel_context
*intel
);
1094 void brw_annotate_aub(struct intel_context
*intel
);
1096 /*======================================================================
1099 void brw_validate_textures( struct brw_context
*brw
);
1102 /*======================================================================
1105 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1107 int brw_get_scratch_size(int size
);
1108 void brw_get_scratch_bo(struct intel_context
*intel
,
1109 drm_intel_bo
**scratch_bo
, int size
);
1114 void brw_upload_urb_fence(struct brw_context
*brw
);
1118 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1121 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1124 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1126 /* brw_wm_surface_state.c */
1127 void brw_init_surface_formats(struct brw_context
*brw
);
1129 brw_update_sol_surface(struct brw_context
*brw
,
1130 struct gl_buffer_object
*buffer_obj
,
1131 uint32_t *out_offset
, unsigned num_vector_components
,
1132 unsigned stride_dwords
, unsigned offset_dwords
);
1136 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1137 struct gl_transform_feedback_object
*obj
);
1139 brw_end_transform_feedback(struct gl_context
*ctx
,
1140 struct gl_transform_feedback_object
*obj
);
1142 /* gen7_sol_state.c */
1144 gen7_end_transform_feedback(struct gl_context
*ctx
,
1145 struct gl_transform_feedback_object
*obj
);
1147 /* brw_blorp_blit.cpp */
1149 brw_blorp_framebuffer(struct intel_context
*intel
,
1150 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1151 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1152 GLbitfield mask
, GLenum filter
);
1154 /* gen6_multisample_state.c */
1156 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1157 unsigned num_samples
);
1159 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
,
1160 unsigned num_samples
, float coverage
,
1161 bool coverage_invert
);
1165 gen7_allocate_push_constants(struct brw_context
*brw
);
1168 gen7_emit_urb_state(struct brw_context
*brw
, GLuint nr_vs_entries
,
1169 GLuint vs_size
, GLuint vs_start
);
1173 /*======================================================================
1174 * Inline conversion functions. These are better-typed than the
1175 * macros used previously:
1177 static INLINE
struct brw_context
*
1178 brw_context( struct gl_context
*ctx
)
1180 return (struct brw_context
*)ctx
;
1183 static INLINE
struct brw_vertex_program
*
1184 brw_vertex_program(struct gl_vertex_program
*p
)
1186 return (struct brw_vertex_program
*) p
;
1189 static INLINE
const struct brw_vertex_program
*
1190 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1192 return (const struct brw_vertex_program
*) p
;
1195 static INLINE
struct brw_fragment_program
*
1196 brw_fragment_program(struct gl_fragment_program
*p
)
1198 return (struct brw_fragment_program
*) p
;
1201 static INLINE
const struct brw_fragment_program
*
1202 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1204 return (const struct brw_fragment_program
*) p
;
1208 float convert_param(enum param_conversion conversion
, const float *param
)
1216 switch (conversion
) {
1217 case PARAM_NO_CONVERT
:
1219 case PARAM_CONVERT_F2I
:
1222 case PARAM_CONVERT_F2U
:
1225 case PARAM_CONVERT_F2B
:
1231 case PARAM_CONVERT_ZERO
:
1239 * Pre-gen6, the register file of the EUs was shared between threads,
1240 * and each thread used some subset allocated on a 16-register block
1241 * granularity. The unit states wanted these block counts.
1244 brw_register_blocks(int reg_count
)
1246 return ALIGN(reg_count
, 16) / 16 - 1;
1249 static inline uint32_t
1250 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1251 uint32_t prog_offset
)
1253 struct intel_context
*intel
= &brw
->intel
;
1255 if (intel
->gen
>= 5) {
1256 /* Using state base address. */
1260 drm_intel_bo_emit_reloc(intel
->batch
.bo
,
1264 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1266 return brw
->cache
.bo
->offset
+ prog_offset
;
1269 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);