2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vue_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
151 struct brw_cs_prog_data
;
155 BRW_COMPUTE_PIPELINE
,
162 BRW_CACHE_BLORP_BLIT_PROG
,
165 BRW_CACHE_FF_GS_PROG
,
174 /* brw_cache_ids must come first - see brw_state_cache.c */
175 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
176 BRW_STATE_FRAGMENT_PROGRAM
,
177 BRW_STATE_GEOMETRY_PROGRAM
,
178 BRW_STATE_VERTEX_PROGRAM
,
179 BRW_STATE_CURBE_OFFSETS
,
180 BRW_STATE_REDUCED_PRIMITIVE
,
185 BRW_STATE_VS_BINDING_TABLE
,
186 BRW_STATE_GS_BINDING_TABLE
,
187 BRW_STATE_PS_BINDING_TABLE
,
191 BRW_STATE_INDEX_BUFFER
,
192 BRW_STATE_VS_CONSTBUF
,
193 BRW_STATE_GS_CONSTBUF
,
194 BRW_STATE_PROGRAM_CACHE
,
195 BRW_STATE_STATE_BASE_ADDRESS
,
196 BRW_STATE_VUE_MAP_VS
,
197 BRW_STATE_VUE_MAP_GEOM_OUT
,
198 BRW_STATE_TRANSFORM_FEEDBACK
,
199 BRW_STATE_RASTERIZER_DISCARD
,
201 BRW_STATE_UNIFORM_BUFFER
,
202 BRW_STATE_ATOMIC_BUFFER
,
203 BRW_STATE_META_IN_PROGRESS
,
204 BRW_STATE_INTERPOLATION_MAP
,
205 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
206 BRW_STATE_NUM_SAMPLES
,
207 BRW_STATE_TEXTURE_BUFFER
,
208 BRW_STATE_GEN4_UNIT_STATE
,
212 BRW_STATE_SAMPLER_STATE_TABLE
,
213 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
214 BRW_STATE_COMPUTE_PROGRAM
,
219 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
221 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
222 * When the currently bound shader program differs from the previous draw
223 * call, these will be flagged. They cover brw->{stage}_program and
224 * ctx->{Stage}Program->_Current.
226 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
227 * driver perspective. Even if the same shader is bound at the API level,
228 * we may need to switch between multiple versions of that shader to handle
229 * changes in non-orthagonal state.
231 * Additionally, multiple shader programs may have identical vertex shaders
232 * (for example), or compile down to the same code in the backend. We combine
233 * those into a single program cache entry.
235 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
236 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
238 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
239 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
240 * use the normal state upload paths), but the cache is still used. To avoid
241 * polluting the brw_state_cache code with special cases, we retain the dirty
242 * bit for now. It should eventually be removed.
244 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
245 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
246 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
247 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
248 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
249 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
250 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
251 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
252 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
253 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
254 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
255 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
256 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
257 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
258 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
259 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
260 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
261 #define BRW_NEW_VS_BINDING_TABLE (1ull << BRW_STATE_VS_BINDING_TABLE)
262 #define BRW_NEW_GS_BINDING_TABLE (1ull << BRW_STATE_GS_BINDING_TABLE)
263 #define BRW_NEW_PS_BINDING_TABLE (1ull << BRW_STATE_PS_BINDING_TABLE)
264 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
265 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
267 * Used for any batch entry with a relocated pointer that will be used
268 * by any 3D rendering.
270 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
271 /** \see brw.state.depth_region */
272 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
273 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
274 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
275 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
276 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
277 #define BRW_NEW_VUE_MAP_VS (1ull << BRW_STATE_VUE_MAP_VS)
278 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
279 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
280 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
281 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
282 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
283 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
284 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
285 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
286 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
287 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
288 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
289 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
290 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
291 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
292 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
293 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
294 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
295 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
297 struct brw_state_flags
{
298 /** State update flags signalled by mesa internals */
301 * State update flags signalled as the result of brw_tracked_state updates
306 /** Subclass of Mesa vertex program */
307 struct brw_vertex_program
{
308 struct gl_vertex_program program
;
313 /** Subclass of Mesa geometry program */
314 struct brw_geometry_program
{
315 struct gl_geometry_program program
;
316 unsigned id
; /**< serial no. to identify geom progs, never re-used */
320 /** Subclass of Mesa fragment program */
321 struct brw_fragment_program
{
322 struct gl_fragment_program program
;
323 GLuint id
; /**< serial no. to identify frag progs, never re-used */
327 /** Subclass of Mesa compute program */
328 struct brw_compute_program
{
329 struct gl_compute_program program
;
330 unsigned id
; /**< serial no. to identify compute progs, never re-used */
335 struct gl_shader base
;
340 /* Note: If adding fields that need anything besides a normal memcmp() for
341 * comparing them, be sure to go fix brw_stage_prog_data_compare().
343 struct brw_stage_prog_data
{
345 /** size of our binding table. */
349 * surface indices for the various groups of surfaces
351 uint32_t pull_constants_start
;
352 uint32_t texture_start
;
353 uint32_t gather_texture_start
;
356 uint32_t image_start
;
357 uint32_t shader_time_start
;
361 GLuint nr_params
; /**< number of float params/constants */
362 GLuint nr_pull_params
;
364 unsigned curb_read_length
;
365 unsigned total_scratch
;
368 * Register where the thread expects to find input data from the URB
369 * (typically uniforms, followed by vertex or fragment attributes).
371 unsigned dispatch_grf_start_reg
;
373 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
375 /* Pointers to tracked values (only valid once
376 * _mesa_load_state_parameters has been called at runtime).
378 * These must be the last fields of the struct (see
379 * brw_stage_prog_data_compare()).
381 const gl_constant_value
**param
;
382 const gl_constant_value
**pull_param
;
385 /* Data about a particular attempt to compile a program. Note that
386 * there can be many of these, each in a different GL state
387 * corresponding to a different brw_wm_prog_key struct, with different
390 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
393 struct brw_wm_prog_data
{
394 struct brw_stage_prog_data base
;
396 GLuint num_varying_inputs
;
398 GLuint dispatch_grf_start_reg_16
;
400 GLuint reg_blocks_16
;
404 * surface indices the WM-specific surfaces
406 uint32_t render_target_start
;
410 uint8_t computed_depth_mode
;
414 bool uses_pos_offset
;
417 uint32_t prog_offset_16
;
420 * Mask of which interpolation modes are required by the fragment shader.
421 * Used in hardware setup on gen6+.
423 uint32_t barycentric_interp_modes
;
426 * Map from gl_varying_slot to the position within the FS setup data
427 * payload where the varying's attribute vertex deltas should be delivered.
428 * For varying slots that are not used by the FS, the value is -1.
430 int urb_setup
[VARYING_SLOT_MAX
];
433 /* Note: brw_cs_prog_data_compare() must be updated when adding fields to this
436 struct brw_cs_prog_data
{
437 struct brw_stage_prog_data base
;
439 GLuint dispatch_grf_start_reg_16
;
440 unsigned local_size
[3];
445 * Enum representing the i965-specific vertex results that don't correspond
446 * exactly to any element of gl_varying_slot. The values of this enum are
447 * assigned such that they don't conflict with gl_varying_slot.
451 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
452 BRW_VARYING_SLOT_PAD
,
454 * Technically this is not a varying but just a placeholder that
455 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
456 * builtin variable to be compiled correctly. see compile_sf_prog() for
459 BRW_VARYING_SLOT_PNTC
,
460 BRW_VARYING_SLOT_COUNT
465 * Data structure recording the relationship between the gl_varying_slot enum
466 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
467 * single octaword within the VUE (128 bits).
469 * Note that each BRW register contains 256 bits (2 octawords), so when
470 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
471 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
472 * in a vertex shader), each register corresponds to a single VUE slot, since
473 * it contains data for two separate vertices.
477 * Bitfield representing all varying slots that are (a) stored in this VUE
478 * map, and (b) actually written by the shader. Does not include any of
479 * the additional varying slots defined in brw_varying_slot.
481 GLbitfield64 slots_valid
;
484 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
485 * not stored in a slot (because they are not written, or because
486 * additional processing is applied before storing them in the VUE), the
489 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
492 * Map from VUE slot to gl_varying_slot value. For slots that do not
493 * directly correspond to a gl_varying_slot, the value comes from
496 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
497 * simplifies code that uses the value stored in slot_to_varying to
498 * create a bit mask).
500 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
503 * Total number of VUE slots in use
509 * Convert a VUE slot number into a byte offset within the VUE.
511 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
517 * Convert a vertex output (brw_varying_slot) into a byte offset within the
520 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
523 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
526 void brw_compute_vue_map(const struct brw_device_info
*devinfo
,
527 struct brw_vue_map
*vue_map
,
528 GLbitfield64 slots_valid
);
532 * Bitmask indicating which fragment shader inputs represent varyings (and
533 * hence have to be delivered to the fragment shader by the SF/SBE stage).
535 #define BRW_FS_VARYING_INPUT_MASK \
536 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
537 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
541 * Mapping of VUE map slots to interpolation modes.
543 struct interpolation_mode_map
{
544 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
547 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
549 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
550 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
556 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
558 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
559 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
566 struct brw_sf_prog_data
{
567 GLuint urb_read_length
;
570 /* Each vertex may have upto 12 attributes, 4 components each,
571 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
574 * Actually we use 4 for each, so call it 12 rows.
576 GLuint urb_entry_size
;
581 * We always program SF to start reading at an offset of 1 (2 varying slots)
582 * from the start of the vertex URB entry. This causes it to skip:
583 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
584 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
586 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
589 struct brw_clip_prog_data
{
590 GLuint curb_read_length
; /* user planes? */
592 GLuint urb_read_length
;
596 struct brw_ff_gs_prog_data
{
597 GLuint urb_read_length
;
601 * Gen6 transform feedback: Amount by which the streaming vertex buffer
602 * indices should be incremented each time the GS is invoked.
604 unsigned svbi_postincrement_value
;
608 /* Note: brw_vue_prog_data_compare() must be updated when adding fields to
611 struct brw_vue_prog_data
{
612 struct brw_stage_prog_data base
;
613 struct brw_vue_map vue_map
;
615 GLuint urb_read_length
;
618 /* Used for calculating urb partitions. In the VS, this is the size of the
619 * URB entry used for both input and output to the thread. In the GS, this
620 * is the size of the URB entry used for output.
622 GLuint urb_entry_size
;
628 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
631 struct brw_vs_prog_data
{
632 struct brw_vue_prog_data base
;
634 GLbitfield64 inputs_read
;
637 bool uses_instanceid
;
640 /** Number of texture sampler units */
641 #define BRW_MAX_TEX_UNIT 32
643 /** Max number of render targets in a shader */
644 #define BRW_MAX_DRAW_BUFFERS 8
646 /** Max number of atomic counter buffer objects in a shader */
647 #define BRW_MAX_ABO 16
649 /** Max number of image uniforms in a shader */
650 #define BRW_MAX_IMAGES 32
653 * Max number of binding table entries used for stream output.
655 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
656 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
658 * On Gen6, the size of transform feedback data is limited not by the number
659 * of components but by the number of binding table entries we set aside. We
660 * use one binding table entry for a float, one entry for a vector, and one
661 * entry per matrix column. Since the only way we can communicate our
662 * transform feedback capabilities to the client is via
663 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
664 * worst case, in which all the varyings are floats, so we use up one binding
665 * table entry per component. Therefore we need to set aside at least 64
666 * binding table entries for use by transform feedback.
668 * Note: since we don't currently pack varyings, it is currently impossible
669 * for the client to actually use up all of these binding table entries--if
670 * all of their varyings were floats, they would run out of varying slots and
671 * fail to link. But that's a bug, so it seems prudent to go ahead and
672 * allocate the number of binding table entries we will need once the bug is
675 #define BRW_MAX_SOL_BINDINGS 64
677 /** Maximum number of actual buffers used for stream output */
678 #define BRW_MAX_SOL_BUFFERS 4
680 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
681 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
685 2 /* shader time, pull constants */)
687 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
689 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
692 struct brw_gs_prog_data
694 struct brw_vue_prog_data base
;
697 * Size of an output vertex, measured in HWORDS (32 bytes).
699 unsigned output_vertex_size_hwords
;
701 unsigned output_topology
;
704 * Size of the control data (cut bits or StreamID bits), in hwords (32
705 * bytes). 0 if there is no control data.
707 unsigned control_data_header_size_hwords
;
710 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
711 * if the control data is StreamID bits, or
712 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
713 * Ignored if control_data_header_size is 0.
715 unsigned control_data_format
;
717 bool include_primitive_id
;
722 * Dispatch mode, can be any of:
723 * GEN7_GS_DISPATCH_MODE_DUAL_OBJECT
724 * GEN7_GS_DISPATCH_MODE_DUAL_INSTANCE
725 * GEN7_GS_DISPATCH_MODE_SINGLE
730 * Gen6 transform feedback enabled flag.
732 bool gen6_xfb_enabled
;
735 * Gen6: Provoking vertex convention for odd-numbered triangles
741 * Gen6: Number of varyings that are output to transform feedback.
743 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
746 * Gen6: Map from the index of a transform feedback binding table entry to the
747 * gl_varying_slot that should be streamed out through that binding table
750 unsigned char transform_feedback_bindings
[BRW_MAX_SOL_BINDINGS
];
753 * Gen6: Map from the index of a transform feedback binding table entry to the
754 * swizzles that should be used when streaming out data through that
755 * binding table entry.
757 unsigned char transform_feedback_swizzles
[BRW_MAX_SOL_BINDINGS
];
761 * Stride in bytes between shader_time entries.
763 * We separate entries by a cacheline to reduce traffic between EUs writing to
766 #define SHADER_TIME_STRIDE 64
768 struct brw_cache_item
{
770 * Effectively part of the key, cache_id identifies what kind of state
771 * buffer is involved, and also which dirty flag should set.
773 enum brw_cache_id cache_id
;
774 /** 32-bit hash of the key data */
776 GLuint key_size
; /* for variable-sized keys */
783 struct brw_cache_item
*next
;
787 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
788 typedef void (*cache_aux_free_func
)(const void *aux
);
791 struct brw_context
*brw
;
793 struct brw_cache_item
**items
;
795 GLuint size
, n_items
;
797 uint32_t next_offset
;
801 * Optional functions used in determining whether the prog_data for a new
802 * cache item matches an existing cache item (in case there's relevant data
803 * outside of the prog_data). If NULL, a plain memcmp is done.
805 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
806 /** Optional functions for freeing other pointers attached to a prog_data. */
807 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
811 /* Considered adding a member to this struct to document which flags
812 * an update might raise so that ordering of the state atoms can be
813 * checked or derived at runtime. Dropped the idea in favor of having
814 * a debug mode where the state is monitored for flags which are
815 * raised that have already been tested against.
817 struct brw_tracked_state
{
818 struct brw_state_flags dirty
;
819 void (*emit
)( struct brw_context
*brw
);
822 enum shader_time_shader_type
{
838 struct brw_vertex_buffer
{
839 /** Buffer object containing the uploaded vertex data */
842 /** Byte stride between elements in the uploaded array */
846 struct brw_vertex_element
{
847 const struct gl_client_array
*glarray
;
851 /** Offset of the first element within the buffer object */
855 struct brw_query_object
{
856 struct gl_query_object Base
;
858 /** Last query BO associated with this query. */
861 /** Last index in bo with query data for this object. */
864 /** True if we know the batch has been flushed since we ended the query. */
868 struct intel_sync_object
{
869 struct gl_sync_object Base
;
871 /** Batch associated with this sync object */
881 struct intel_batchbuffer
{
882 /** Current batchbuffer being queued up. */
884 /** Last BO submitted to the hardware. Used for glFinish(). */
885 drm_intel_bo
*last_bo
;
886 /** BO for post-sync nonzero writes for gen6 workaround. */
887 drm_intel_bo
*workaround_bo
;
889 uint16_t emit
, total
;
890 uint16_t used
, reserved_space
;
893 #define BATCH_SZ (8192*sizeof(uint32_t))
895 uint32_t state_batch_offset
;
896 enum brw_gpu_ring ring
;
897 bool needs_sol_reset
;
899 uint8_t pipe_controls_since_last_cs_stall
;
907 #define BRW_MAX_XFB_STREAMS 4
909 struct brw_transform_feedback_object
{
910 struct gl_transform_feedback_object base
;
912 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
913 drm_intel_bo
*offset_bo
;
915 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
918 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
919 GLenum primitive_mode
;
922 * Count of primitives generated during this transform feedback operation.
925 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
926 drm_intel_bo
*prim_count_bo
;
927 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
931 * Number of vertices written between last Begin/EndTransformFeedback().
933 * Used to implement DrawTransformFeedback().
935 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
936 bool vertices_written_valid
;
940 * Data shared between each programmable stage in the pipeline (vs, gs, and
943 struct brw_stage_state
945 gl_shader_stage stage
;
946 struct brw_stage_prog_data
*prog_data
;
949 * Optional scratch buffer used to store spilled register values and
950 * variably-indexed GRF arrays.
952 drm_intel_bo
*scratch_bo
;
954 /** Offset in the program cache to the program */
955 uint32_t prog_offset
;
957 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
958 uint32_t state_offset
;
960 uint32_t push_const_offset
; /* Offset in the batchbuffer */
961 int push_const_size
; /* in 256-bit register increments */
963 /* Binding table: pointers to SURFACE_STATE entries. */
964 uint32_t bind_bo_offset
;
965 uint32_t surf_offset
[BRW_MAX_SURFACES
];
967 /** SAMPLER_STATE count and table offset */
968 uint32_t sampler_count
;
969 uint32_t sampler_offset
;
974 * brw_context is derived from gl_context.
978 struct gl_context ctx
; /**< base class, must be first field */
982 void (*update_texture_surface
)(struct gl_context
*ctx
,
984 uint32_t *surf_offset
,
986 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
987 struct gl_renderbuffer
*rb
,
988 bool layered
, unsigned unit
,
989 uint32_t surf_index
);
991 void (*emit_texture_surface_state
)(struct brw_context
*brw
,
992 struct intel_mipmap_tree
*mt
,
1000 uint32_t *surf_offset
,
1001 bool rw
, bool for_gather
);
1002 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
1003 uint32_t *out_offset
,
1005 unsigned buffer_offset
,
1006 unsigned surface_format
,
1007 unsigned buffer_size
,
1010 void (*emit_null_surface_state
)(struct brw_context
*brw
,
1014 uint32_t *out_offset
);
1017 * Send the appropriate state packets to configure depth, stencil, and
1018 * HiZ buffers (i965+ only)
1020 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
1021 struct intel_mipmap_tree
*depth_mt
,
1022 uint32_t depth_offset
,
1023 uint32_t depthbuffer_format
,
1024 uint32_t depth_surface_type
,
1025 struct intel_mipmap_tree
*stencil_mt
,
1026 bool hiz
, bool separate_stencil
,
1027 uint32_t width
, uint32_t height
,
1028 uint32_t tile_x
, uint32_t tile_y
);
1034 drm_intel_context
*hw_ctx
;
1037 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
1038 * and would need flushing before being used from another cache domain that
1039 * isn't coherent with it (i.e. the sampler).
1041 struct set
*render_cache
;
1044 * Number of resets observed in the system at context creation.
1046 * This is tracked in the context so that we can determine that another
1047 * reset has occurred.
1049 uint32_t reset_count
;
1051 struct intel_batchbuffer batch
;
1056 uint32_t next_offset
;
1060 * Set if rendering has occurred to the drawable's front buffer.
1062 * This is used in the DRI2 case to detect that glFlush should also copy
1063 * the contents of the fake front buffer to the real front buffer.
1065 bool front_buffer_dirty
;
1067 /** Framerate throttling: @{ */
1068 drm_intel_bo
*throttle_batch
[2];
1070 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
1071 * frame of rendering to complete. This gives a very precise cap to the
1072 * latency between input and output such that rendering never gets more
1073 * than a frame behind the user. (With the caveat that we technically are
1074 * not using the SwapBuffers itself as a barrier but the first batch
1075 * submitted afterwards, which may be immediately prior to the next
1078 bool need_swap_throttle
;
1080 /** General throttling, not caught by throttling between SwapBuffers */
1081 bool need_flush_throttle
;
1091 bool always_flush_batch
;
1092 bool always_flush_cache
;
1093 bool disable_throttling
;
1096 driOptionCache optionCache
;
1099 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1101 GLenum reduced_primitive
;
1104 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1105 * variable is set, this is the flag indicating to do expensive work that
1106 * might lead to a perf_debug() call.
1110 uint32_t max_gtt_map_object_size
;
1121 bool has_separate_stencil
;
1122 bool must_use_separate_stencil
;
1125 bool has_surface_tile_offset
;
1127 bool has_negative_rhw_bug
;
1134 * Some versions of Gen hardware don't do centroid interpolation correctly
1135 * on unlit pixels, causing incorrect values for derivatives near triangle
1136 * edges. Enabling this flag causes the fragment shader to use
1137 * non-centroid interpolation for unlit pixels, at the expense of two extra
1138 * fragment shader instructions.
1140 bool needs_unlit_centroid_workaround
;
1144 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
1147 struct brw_cache cache
;
1149 /** IDs for meta stencil blit shader programs. */
1150 unsigned meta_stencil_blit_programs
[2];
1152 /* Whether a meta-operation is in progress. */
1153 bool meta_in_progress
;
1155 /* Whether the last depth/stencil packets were both NULL. */
1156 bool no_depth_or_stencil
;
1158 /* The last PMA stall bits programmed. */
1159 uint32_t pma_stall_bits
;
1162 /** The value of gl_BaseVertex for the current _mesa_prim. */
1166 * Buffer and offset used for GL_ARB_shader_draw_parameters
1167 * (for now, only gl_BaseVertex).
1169 drm_intel_bo
*draw_params_bo
;
1170 uint32_t draw_params_offset
;
1174 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1175 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1177 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1181 /* Summary of size and varying of active arrays, so we can check
1182 * for changes to this state:
1184 unsigned int min_index
, max_index
;
1186 /* Offset from start of vertex buffer so we can avoid redefining
1187 * the same VB packed over and over again.
1189 unsigned int start_vertex_bias
;
1192 * Certain vertex attribute formats aren't natively handled by the
1193 * hardware and require special VS code to fix up their values.
1195 * These bitfields indicate which workarounds are needed.
1197 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
1202 * Index buffer for this draw_prims call.
1204 * Updates are signaled by BRW_NEW_INDICES.
1206 const struct _mesa_index_buffer
*ib
;
1208 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1212 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1213 * avoid re-uploading the IB packet over and over if we're actually
1214 * referencing the same index buffer.
1216 unsigned int start_vertex_offset
;
1219 /* Active vertex program:
1221 const struct gl_vertex_program
*vertex_program
;
1222 const struct gl_geometry_program
*geometry_program
;
1223 const struct gl_fragment_program
*fragment_program
;
1224 const struct gl_compute_program
*compute_program
;
1227 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1228 * that we don't have to reemit that state every time we change FBOs.
1233 * Platform specific constants containing the maximum number of threads
1234 * for each pipeline stage.
1242 /* BRW_NEW_URB_ALLOCATIONS:
1245 GLuint vsize
; /* vertex size plus header in urb registers */
1246 GLuint gsize
; /* GS output size in urb registers */
1247 GLuint csize
; /* constant buffer size in urb registers */
1248 GLuint sfsize
; /* setup data size in urb registers */
1252 GLuint min_vs_entries
; /* Minimum number of VS entries */
1253 GLuint max_vs_entries
; /* Maximum number of VS entries */
1254 GLuint max_hs_entries
; /* Maximum number of HS entries */
1255 GLuint max_ds_entries
; /* Maximum number of DS entries */
1256 GLuint max_gs_entries
; /* Maximum number of GS entries */
1258 GLuint nr_vs_entries
;
1259 GLuint nr_gs_entries
;
1260 GLuint nr_clip_entries
;
1261 GLuint nr_sf_entries
;
1262 GLuint nr_cs_entries
;
1269 GLuint size
; /* Hardware URB size, in KB. */
1271 /* True if the most recently sent _3DSTATE_URB message allocated
1272 * URB space for the GS.
1278 /* BRW_NEW_CURBE_OFFSETS:
1281 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1282 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1290 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1291 * for upload to the CURBE.
1293 drm_intel_bo
*curbe_bo
;
1294 /** Offset within curbe_bo of space for current curbe entry */
1295 GLuint curbe_offset
;
1299 * Layout of vertex data exiting the vertex shader.
1301 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1303 struct brw_vue_map vue_map_vs
;
1306 * Layout of vertex data exiting the geometry portion of the pipleine.
1307 * This comes from the geometry shader if one exists, otherwise from the
1310 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1312 struct brw_vue_map vue_map_geom_out
;
1315 struct brw_stage_state base
;
1316 struct brw_vs_prog_data
*prog_data
;
1320 struct brw_stage_state base
;
1321 struct brw_gs_prog_data
*prog_data
;
1324 * True if the 3DSTATE_GS command most recently emitted to the 3D
1325 * pipeline enabled the GS; false otherwise.
1331 struct brw_ff_gs_prog_data
*prog_data
;
1334 /** Offset in the program cache to the CLIP program pre-gen6 */
1335 uint32_t prog_offset
;
1336 uint32_t state_offset
;
1338 uint32_t bind_bo_offset
;
1340 * Surface offsets for the binding table. We only need surfaces to
1341 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1342 * need in this case.
1344 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1348 struct brw_clip_prog_data
*prog_data
;
1350 /** Offset in the program cache to the CLIP program pre-gen6 */
1351 uint32_t prog_offset
;
1353 /* Offset in the batch to the CLIP state on pre-gen6. */
1354 uint32_t state_offset
;
1356 /* As of gen6, this is the offset in the batch to the CLIP VP,
1364 struct brw_sf_prog_data
*prog_data
;
1366 /** Offset in the program cache to the CLIP program pre-gen6 */
1367 uint32_t prog_offset
;
1368 uint32_t state_offset
;
1370 bool viewport_transform_enable
;
1374 struct brw_stage_state base
;
1375 struct brw_wm_prog_data
*prog_data
;
1380 * Buffer object used in place of multisampled null render targets on
1381 * Gen6. See brw_emit_null_surface_state().
1383 drm_intel_bo
*multisampled_null_render_target_bo
;
1384 uint32_t fast_clear_op
;
1388 struct brw_stage_state base
;
1389 struct brw_cs_prog_data
*prog_data
;
1393 uint32_t state_offset
;
1394 uint32_t blend_state_offset
;
1395 uint32_t depth_stencil_state_offset
;
1400 struct brw_query_object
*obj
;
1405 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1406 const int *statistics_registers
;
1408 /** The number of active monitors using OA counters. */
1412 * A buffer object storing OA counter snapshots taken at the start and
1413 * end of each batch (creating "bookends" around the batch).
1415 drm_intel_bo
*bookend_bo
;
1417 /** The number of snapshots written to bookend_bo. */
1418 int bookend_snapshots
;
1421 * An array of monitors whose results haven't yet been assembled based on
1422 * the data in buffer objects.
1424 * These may be active, or have already ended. However, the results
1425 * have not been requested.
1427 struct brw_perf_monitor_object
**unresolved
;
1428 int unresolved_elements
;
1429 int unresolved_array_size
;
1432 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1433 * the counter which MI_REPORT_PERF_COUNT stores there.
1435 const int *oa_snapshot_layout
;
1437 /** Number of 32-bit entries in a hardware counter snapshot. */
1438 int entries_per_oa_snapshot
;
1441 int num_atoms
[BRW_NUM_PIPELINES
];
1442 const struct brw_tracked_state render_atoms
[57];
1443 const struct brw_tracked_state compute_atoms
[1];
1445 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1449 enum aub_state_struct_type type
;
1450 } *state_batch_list
;
1451 int state_batch_count
;
1453 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1454 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1456 /* Interpolation modes, one byte per vue slot.
1457 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1459 struct interpolation_mode_map interpolation_mode
;
1461 /* PrimitiveRestart */
1464 bool enable_cut_index
;
1467 /** Computed depth/stencil/hiz state from the current attached
1468 * renderbuffers, valid only during the drawing state upload loop after
1469 * brw_workaround_depthstencil_alignment().
1472 struct intel_mipmap_tree
*depth_mt
;
1473 struct intel_mipmap_tree
*stencil_mt
;
1475 /* Inter-tile (page-aligned) byte offsets. */
1476 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1477 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1478 uint32_t tile_x
, tile_y
;
1481 uint32_t num_instances
;
1488 enum shader_time_shader_type
*types
;
1489 uint64_t *cumulative
;
1495 struct brw_fast_clear_state
*fast_clear_state
;
1497 __DRIcontext
*driContext
;
1498 struct intel_screen
*intelScreen
;
1501 /*======================================================================
1504 void brwInitVtbl( struct brw_context
*brw
);
1507 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1509 /*======================================================================
1512 extern const char *const brw_vendor_string
;
1514 extern const char *brw_get_renderer_string(unsigned deviceID
);
1517 DRI_CONF_BO_REUSE_DISABLED
,
1518 DRI_CONF_BO_REUSE_ALL
1521 void intel_update_renderbuffers(__DRIcontext
*context
,
1522 __DRIdrawable
*drawable
);
1523 void intel_prepare_render(struct brw_context
*brw
);
1525 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1526 __DRIdrawable
*drawable
);
1528 GLboolean
brwCreateContext(gl_api api
,
1529 const struct gl_config
*mesaVis
,
1530 __DRIcontext
*driContextPriv
,
1531 unsigned major_version
,
1532 unsigned minor_version
,
1536 void *sharedContextPrivate
);
1538 /*======================================================================
1541 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1542 struct intel_mipmap_tree
*mt
,
1543 unsigned level
, unsigned layer
, bool flat
);
1545 void brw_meta_updownsample(struct brw_context
*brw
,
1546 struct intel_mipmap_tree
*src
,
1547 struct intel_mipmap_tree
*dst
);
1549 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1550 struct gl_framebuffer
*read_fb
,
1551 struct gl_framebuffer
*draw_fb
,
1552 GLfloat srcX0
, GLfloat srcY0
,
1553 GLfloat srcX1
, GLfloat srcY1
,
1554 GLfloat dstX0
, GLfloat dstY0
,
1555 GLfloat dstX1
, GLfloat dstY1
);
1557 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1558 struct intel_mipmap_tree
*src
,
1559 struct intel_mipmap_tree
*dst
);
1561 bool brw_meta_fast_clear(struct brw_context
*brw
,
1562 struct gl_framebuffer
*fb
,
1564 bool partial_clear
);
1567 brw_meta_resolve_color(struct brw_context
*brw
,
1568 struct intel_mipmap_tree
*mt
);
1570 brw_meta_fast_clear_free(struct brw_context
*brw
);
1573 /*======================================================================
1576 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1577 uint32_t depth_level
,
1578 uint32_t depth_layer
,
1579 struct intel_mipmap_tree
*stencil_mt
,
1580 uint32_t *out_tile_mask_x
,
1581 uint32_t *out_tile_mask_y
);
1582 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1583 GLbitfield clear_mask
);
1585 /* brw_object_purgeable.c */
1586 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1588 /*======================================================================
1591 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1592 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1593 void brw_emit_query_begin(struct brw_context
*brw
);
1594 void brw_emit_query_end(struct brw_context
*brw
);
1596 /** gen6_queryobj.c */
1597 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1598 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1599 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1600 void brw_store_register_mem64(struct brw_context
*brw
,
1601 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1603 /** intel_batchbuffer.c */
1604 void brw_load_register_mem(struct brw_context
*brw
,
1607 uint32_t read_domains
, uint32_t write_domain
,
1610 /*======================================================================
1613 void brw_debug_batch(struct brw_context
*brw
);
1614 void brw_annotate_aub(struct brw_context
*brw
);
1616 /*======================================================================
1619 void brw_validate_textures( struct brw_context
*brw
);
1622 /*======================================================================
1625 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1627 int brw_get_scratch_size(int size
);
1628 void brw_get_scratch_bo(struct brw_context
*brw
,
1629 drm_intel_bo
**scratch_bo
, int size
);
1630 void brw_init_shader_time(struct brw_context
*brw
);
1631 int brw_get_shader_time_index(struct brw_context
*brw
,
1632 struct gl_shader_program
*shader_prog
,
1633 struct gl_program
*prog
,
1634 enum shader_time_shader_type type
);
1635 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1636 void brw_destroy_shader_time(struct brw_context
*brw
);
1640 void brw_upload_urb_fence(struct brw_context
*brw
);
1644 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1646 /* brw_fs_reg_allocate.cpp
1648 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1650 /* brw_vec4_reg_allocate.cpp */
1651 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1654 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1655 struct brw_inst
*inst
, bool is_compacted
);
1658 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1660 /* brw_draw_upload.c */
1661 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1662 const struct gl_client_array
*glarray
);
1664 static inline unsigned
1665 brw_get_index_type(GLenum type
)
1667 assert((type
== GL_UNSIGNED_BYTE
)
1668 || (type
== GL_UNSIGNED_SHORT
)
1669 || (type
== GL_UNSIGNED_INT
));
1671 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1672 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1673 * to map to scale factors of 0, 1, and 2, respectively. These scale
1674 * factors are then left-shfited by 8 to be in the correct position in the
1675 * CMD_INDEX_BUFFER packet.
1677 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1678 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1679 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1681 return (type
- 0x1401) << 7;
1684 void brw_prepare_vertices(struct brw_context
*brw
);
1686 /* brw_wm_surface_state.c */
1687 void brw_init_surface_formats(struct brw_context
*brw
);
1688 void brw_create_constant_surface(struct brw_context
*brw
,
1692 uint32_t *out_offset
,
1694 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1696 uint32_t *surf_offset
);
1698 brw_update_sol_surface(struct brw_context
*brw
,
1699 struct gl_buffer_object
*buffer_obj
,
1700 uint32_t *out_offset
, unsigned num_vector_components
,
1701 unsigned stride_dwords
, unsigned offset_dwords
);
1702 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1703 struct gl_shader
*shader
,
1704 struct brw_stage_state
*stage_state
,
1705 struct brw_stage_prog_data
*prog_data
,
1707 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1708 struct gl_shader_program
*prog
,
1709 struct brw_stage_state
*stage_state
,
1710 struct brw_stage_prog_data
*prog_data
);
1712 /* brw_surface_formats.c */
1713 bool brw_render_target_supported(struct brw_context
*brw
,
1714 struct gl_renderbuffer
*rb
);
1715 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1717 /* brw_performance_monitor.c */
1718 void brw_init_performance_monitors(struct brw_context
*brw
);
1719 void brw_dump_perf_monitors(struct brw_context
*brw
);
1720 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1721 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1723 /* intel_buffer_objects.c */
1724 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1725 const char *bo_name
);
1726 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1727 const char *bo_name
);
1729 /* intel_extensions.c */
1730 extern void intelInitExtensions(struct gl_context
*ctx
);
1733 extern int intel_translate_shadow_compare_func(GLenum func
);
1734 extern int intel_translate_compare_func(GLenum func
);
1735 extern int intel_translate_stencil_op(GLenum op
);
1736 extern int intel_translate_logic_op(GLenum opcode
);
1738 /* intel_syncobj.c */
1739 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1742 struct gl_transform_feedback_object
*
1743 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1745 brw_delete_transform_feedback(struct gl_context
*ctx
,
1746 struct gl_transform_feedback_object
*obj
);
1748 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1749 struct gl_transform_feedback_object
*obj
);
1751 brw_end_transform_feedback(struct gl_context
*ctx
,
1752 struct gl_transform_feedback_object
*obj
);
1754 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1755 struct gl_transform_feedback_object
*obj
,
1758 /* gen7_sol_state.c */
1760 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1761 struct gl_transform_feedback_object
*obj
);
1763 gen7_end_transform_feedback(struct gl_context
*ctx
,
1764 struct gl_transform_feedback_object
*obj
);
1766 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1767 struct gl_transform_feedback_object
*obj
);
1769 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1770 struct gl_transform_feedback_object
*obj
);
1772 /* brw_blorp_blit.cpp */
1774 brw_blorp_framebuffer(struct brw_context
*brw
,
1775 struct gl_framebuffer
*readFb
,
1776 struct gl_framebuffer
*drawFb
,
1777 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1778 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1779 GLbitfield mask
, GLenum filter
);
1782 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1783 struct gl_renderbuffer
*src_rb
,
1784 struct gl_texture_image
*dst_image
,
1786 int srcX0
, int srcY0
,
1787 int dstX0
, int dstY0
,
1788 int width
, int height
);
1790 /* gen6_multisample_state.c */
1792 gen6_determine_sample_mask(struct brw_context
*brw
);
1795 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1796 unsigned num_samples
);
1798 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1800 gen6_get_sample_position(struct gl_context
*ctx
,
1801 struct gl_framebuffer
*fb
,
1805 gen6_set_sample_maps(struct gl_context
*ctx
);
1807 /* gen8_multisample_state.c */
1808 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1809 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1813 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1814 unsigned gs_size
, unsigned fs_size
);
1817 gen7_emit_urb_state(struct brw_context
*brw
,
1818 unsigned nr_vs_entries
, unsigned vs_size
,
1819 unsigned vs_start
, unsigned nr_gs_entries
,
1820 unsigned gs_size
, unsigned gs_start
);
1825 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1827 /*======================================================================
1828 * Inline conversion functions. These are better-typed than the
1829 * macros used previously:
1831 static inline struct brw_context
*
1832 brw_context( struct gl_context
*ctx
)
1834 return (struct brw_context
*)ctx
;
1837 static inline struct brw_vertex_program
*
1838 brw_vertex_program(struct gl_vertex_program
*p
)
1840 return (struct brw_vertex_program
*) p
;
1843 static inline const struct brw_vertex_program
*
1844 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1846 return (const struct brw_vertex_program
*) p
;
1849 static inline struct brw_geometry_program
*
1850 brw_geometry_program(struct gl_geometry_program
*p
)
1852 return (struct brw_geometry_program
*) p
;
1855 static inline struct brw_fragment_program
*
1856 brw_fragment_program(struct gl_fragment_program
*p
)
1858 return (struct brw_fragment_program
*) p
;
1861 static inline const struct brw_fragment_program
*
1862 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1864 return (const struct brw_fragment_program
*) p
;
1868 * Pre-gen6, the register file of the EUs was shared between threads,
1869 * and each thread used some subset allocated on a 16-register block
1870 * granularity. The unit states wanted these block counts.
1873 brw_register_blocks(int reg_count
)
1875 return ALIGN(reg_count
, 16) / 16 - 1;
1878 static inline uint32_t
1879 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1880 uint32_t prog_offset
)
1882 if (brw
->gen
>= 5) {
1883 /* Using state base address. */
1887 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1891 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1893 return brw
->cache
.bo
->offset64
+ prog_offset
;
1896 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1897 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1898 struct exec_list
*instructions
);
1899 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1901 struct opcode_desc
{
1907 extern const struct opcode_desc opcode_descs
[128];
1908 extern const char * const conditional_modifier
[16];
1911 brw_emit_depthbuffer(struct brw_context
*brw
);
1914 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1915 struct intel_mipmap_tree
*depth_mt
,
1916 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1917 uint32_t depth_surface_type
,
1918 struct intel_mipmap_tree
*stencil_mt
,
1919 bool hiz
, bool separate_stencil
,
1920 uint32_t width
, uint32_t height
,
1921 uint32_t tile_x
, uint32_t tile_y
);
1924 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1925 struct intel_mipmap_tree
*depth_mt
,
1926 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1927 uint32_t depth_surface_type
,
1928 struct intel_mipmap_tree
*stencil_mt
,
1929 bool hiz
, bool separate_stencil
,
1930 uint32_t width
, uint32_t height
,
1931 uint32_t tile_x
, uint32_t tile_y
);
1934 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1935 struct intel_mipmap_tree
*depth_mt
,
1936 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1937 uint32_t depth_surface_type
,
1938 struct intel_mipmap_tree
*stencil_mt
,
1939 bool hiz
, bool separate_stencil
,
1940 uint32_t width
, uint32_t height
,
1941 uint32_t tile_x
, uint32_t tile_y
);
1943 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1944 struct intel_mipmap_tree
*depth_mt
,
1945 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1946 uint32_t depth_surface_type
,
1947 struct intel_mipmap_tree
*stencil_mt
,
1948 bool hiz
, bool separate_stencil
,
1949 uint32_t width
, uint32_t height
,
1950 uint32_t tile_x
, uint32_t tile_y
);
1952 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1953 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1955 uint32_t get_hw_prim_for_gl_prim(int mode
);
1958 brw_setup_vue_key_clip_info(struct brw_context
*brw
,
1959 struct brw_vue_prog_key
*key
,
1960 bool program_uses_clip_distance
);
1963 gen6_upload_push_constants(struct brw_context
*brw
,
1964 const struct gl_program
*prog
,
1965 const struct brw_stage_prog_data
*prog_data
,
1966 struct brw_stage_state
*stage_state
,
1967 enum aub_state_struct_type type
);