2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
47 * URB - uniform resource buffer. A mid-sized buffer which is
48 * partitioned between the fixed function units and used for passing
49 * values (vertices, primitives, constants) between them.
51 * CURBE - constant URB entry. An urb region (entry) used to hold
52 * constant values which the fixed function units can be instructed to
53 * preload into the GRF when spawning a thread.
55 * VUE - vertex URB entry. An urb entry holding a vertex and usually
56 * a vertex header. The header contains control information and
57 * things like primitive type, Begin/end flags and clip codes.
59 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
60 * unit holding rasterization and interpolation parameters.
62 * GRF - general register file. One of several register files
63 * addressable by programmed threads. The inputs (r0, payload, curbe,
64 * urb) of the thread are preloaded to this area before the thread is
65 * spawned. The registers are individually 8 dwords wide and suitable
66 * for general usage. Registers holding thread input values are not
67 * special and may be overwritten.
69 * MRF - message register file. Threads communicate (and terminate)
70 * by sending messages. Message parameters are placed in contiguous
71 * MRF registers. All program output is via these messages. URB
72 * entries are populated by sending a message to the shared URB
73 * function containing the new data, together with a control word,
74 * often an unmodified copy of R0.
76 * R0 - GRF register 0. Typically holds control information used when
77 * sending messages to other threads.
79 * EU or GEN4 EU: The name of the programmable subsystem of the
80 * i965 hardware. Threads are executed by the EU, the registers
81 * described above are part of the EU architecture.
83 * Fixed function units:
85 * CS - Command streamer. Notional first unit, little software
86 * interaction. Holds the URB entries used for constant data, ie the
89 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
90 * this unit is responsible for pulling vertices out of vertex buffers
91 * in vram and injecting them into the processing pipe as VUEs. If
92 * enabled, it first passes them to a VS thread which is a good place
93 * for the driver to implement any active vertex shader.
95 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
96 * enabled, incoming strips etc are passed to GS threads in individual
97 * line/triangle/point units. The GS thread may perform arbitary
98 * computation and emit whatever primtives with whatever vertices it
99 * chooses. This makes GS an excellent place to implement GL's
100 * unfilled polygon modes, though of course it is capable of much
101 * more. Additionally, GS is used to translate away primitives not
102 * handled by latter units, including Quads and Lineloops.
104 * CS - Clipper. Mesa's clipping algorithms are imported to run on
105 * this unit. The fixed function part performs cliptesting against
106 * the 6 fixed clipplanes and makes descisions on whether or not the
107 * incoming primitive needs to be passed to a thread for clipping.
108 * User clip planes are handled via cooperation with the VS thread.
110 * SF - Strips Fans or Setup: Triangles are prepared for
111 * rasterization. Interpolation coefficients are calculated.
112 * Flatshading and two-side lighting usually performed here.
114 * WM - Windower. Interpolation of vertex attributes performed here.
115 * Fragment shader implemented here. SIMD aspects of EU taken full
116 * advantage of, as pixels are processed in blocks of 16.
118 * CC - Color Calculator. No EU threads associated with this unit.
119 * Handles blending and (presumably) depth and stencil testing.
123 #define BRW_MAX_CURBE (32*16)
126 struct brw_instruction
;
127 struct brw_vs_prog_key
;
128 struct brw_wm_prog_key
;
129 struct brw_wm_prog_data
;
133 BRW_STATE_FRAGMENT_PROGRAM
,
134 BRW_STATE_VERTEX_PROGRAM
,
135 BRW_STATE_CURBE_OFFSETS
,
136 BRW_STATE_REDUCED_PRIMITIVE
,
141 BRW_STATE_VS_BINDING_TABLE
,
142 BRW_STATE_GS_BINDING_TABLE
,
143 BRW_STATE_PS_BINDING_TABLE
,
147 BRW_STATE_INDEX_BUFFER
,
148 BRW_STATE_VS_CONSTBUF
,
149 BRW_STATE_PROGRAM_CACHE
,
150 BRW_STATE_STATE_BASE_ADDRESS
,
151 BRW_STATE_VUE_MAP_GEOM_OUT
,
152 BRW_STATE_TRANSFORM_FEEDBACK
,
153 BRW_STATE_RASTERIZER_DISCARD
,
155 BRW_STATE_UNIFORM_BUFFER
,
156 BRW_STATE_META_IN_PROGRESS
,
157 BRW_STATE_INTERPOLATION_MAP
,
160 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
161 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
162 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
163 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
164 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
165 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
166 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
167 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
168 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
169 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
170 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
171 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
172 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
173 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
175 * Used for any batch entry with a relocated pointer that will be used
176 * by any 3D rendering.
178 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
179 /** \see brw.state.depth_region */
180 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
181 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
182 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
183 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
184 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
185 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
186 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
187 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
188 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
189 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
190 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
192 struct brw_state_flags
{
193 /** State update flags signalled by mesa internals */
196 * State update flags signalled as the result of brw_tracked_state updates
199 /** State update flags signalled by brw_state_cache.c searches */
203 #define AUB_TRACE_TYPE_MASK 0x0000ff00
204 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
205 #define AUB_TRACE_TYPE_BATCH (1 << 8)
206 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
207 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
208 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
209 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
210 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
211 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
212 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
213 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
214 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
215 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
218 * state_struct_type enum values are encoded with the top 16 bits representing
219 * the type to be delivered to the .aub file, and the bottom 16 bits
220 * representing the subtype. This macro performs the encoding.
222 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
224 enum state_struct_type
{
225 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
226 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
227 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
228 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
229 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
230 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
231 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
232 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
233 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
234 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
235 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
236 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
237 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
239 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
240 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
241 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
243 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
244 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
245 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
246 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
247 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
251 * Decode a state_struct_type value to determine the type that should be
252 * stored in the .aub file.
254 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
256 return (ss_type
& 0xFFFF0000) >> 16;
260 * Decode a state_struct_type value to determine the subtype that should be
261 * stored in the .aub file.
263 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
265 return ss_type
& 0xFFFF;
268 /** Subclass of Mesa vertex program */
269 struct brw_vertex_program
{
270 struct gl_vertex_program program
;
275 /** Subclass of Mesa fragment program */
276 struct brw_fragment_program
{
277 struct gl_fragment_program program
;
278 GLuint id
; /**< serial no. to identify frag progs, never re-used */
282 struct gl_shader base
;
286 /** Shader IR transformed for native compile, at link time. */
287 struct exec_list
*ir
;
290 /* Data about a particular attempt to compile a program. Note that
291 * there can be many of these, each in a different GL state
292 * corresponding to a different brw_wm_prog_key struct, with different
295 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
298 struct brw_wm_prog_data
{
299 GLuint curb_read_length
;
300 GLuint urb_read_length
;
302 GLuint first_curbe_grf
;
303 GLuint first_curbe_grf_16
;
305 GLuint reg_blocks_16
;
306 GLuint total_scratch
;
308 GLuint nr_params
; /**< number of float params/constants */
309 GLuint nr_pull_params
;
312 uint32_t prog_offset_16
;
315 * Mask of which interpolation modes are required by the fragment shader.
316 * Used in hardware setup on gen6+.
318 uint32_t barycentric_interp_modes
;
320 /* Pointers to tracked values (only valid once
321 * _mesa_load_state_parameters has been called at runtime).
323 * These must be the last fields of the struct (see
324 * brw_wm_prog_data_compare()).
327 const float **pull_param
;
331 * Enum representing the i965-specific vertex results that don't correspond
332 * exactly to any element of gl_varying_slot. The values of this enum are
333 * assigned such that they don't conflict with gl_varying_slot.
337 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
338 BRW_VARYING_SLOT_PAD
,
340 * Technically this is not a varying but just a placeholder that
341 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
342 * builtin variable to be compiled correctly. see compile_sf_prog() for
345 BRW_VARYING_SLOT_PNTC
,
346 BRW_VARYING_SLOT_COUNT
351 * Data structure recording the relationship between the gl_varying_slot enum
352 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
353 * single octaword within the VUE (128 bits).
355 * Note that each BRW register contains 256 bits (2 octawords), so when
356 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
357 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
358 * in a vertex shader), each register corresponds to a single VUE slot, since
359 * it contains data for two separate vertices.
363 * Bitfield representing all varying slots that are (a) stored in this VUE
364 * map, and (b) actually written by the shader. Does not include any of
365 * the additional varying slots defined in brw_varying_slot.
367 GLbitfield64 slots_valid
;
370 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
371 * not stored in a slot (because they are not written, or because
372 * additional processing is applied before storing them in the VUE), the
375 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
378 * Map from VUE slot to gl_varying_slot value. For slots that do not
379 * directly correspond to a gl_varying_slot, the value comes from
382 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
383 * simplifies code that uses the value stored in slot_to_varying to
384 * create a bit mask).
386 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
389 * Total number of VUE slots in use
395 * Convert a VUE slot number into a byte offset within the VUE.
397 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
403 * Convert a vertex output (brw_varying_slot) into a byte offset within the
406 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
409 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
412 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
413 GLbitfield64 slots_valid
, bool userclip_active
);
417 * Mapping of VUE map slots to interpolation modes.
419 struct interpolation_mode_map
{
420 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
424 struct brw_sf_prog_data
{
425 GLuint urb_read_length
;
428 /* Each vertex may have upto 12 attributes, 4 components each,
429 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
432 * Actually we use 4 for each, so call it 12 rows.
434 GLuint urb_entry_size
;
437 struct brw_clip_prog_data
{
438 GLuint curb_read_length
; /* user planes? */
440 GLuint urb_read_length
;
444 struct brw_gs_prog_data
{
445 GLuint urb_read_length
;
449 * Gen6 transform feedback: Amount by which the streaming vertex buffer
450 * indices should be incremented each time the GS is invoked.
452 unsigned svbi_postincrement_value
;
456 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
459 struct brw_vec4_prog_data
{
460 struct brw_vue_map vue_map
;
462 GLuint curb_read_length
;
463 GLuint urb_read_length
;
465 GLuint nr_params
; /**< number of float params/constants */
466 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
467 GLuint total_scratch
;
469 /* Used for calculating urb partitions. In the VS, this is the size of the
470 * URB entry used for both input and output to the thread. In the GS, this
471 * is the size of the URB entry used for output.
473 GLuint urb_entry_size
;
477 /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
479 const float **pull_param
;
483 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
486 struct brw_vs_prog_data
{
487 struct brw_vec4_prog_data base
;
489 GLbitfield64 inputs_read
;
494 /** Number of texture sampler units */
495 #define BRW_MAX_TEX_UNIT 16
497 /** Max number of render targets in a shader */
498 #define BRW_MAX_DRAW_BUFFERS 8
501 * Max number of binding table entries used for stream output.
503 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
504 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
506 * On Gen6, the size of transform feedback data is limited not by the number
507 * of components but by the number of binding table entries we set aside. We
508 * use one binding table entry for a float, one entry for a vector, and one
509 * entry per matrix column. Since the only way we can communicate our
510 * transform feedback capabilities to the client is via
511 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
512 * worst case, in which all the varyings are floats, so we use up one binding
513 * table entry per component. Therefore we need to set aside at least 64
514 * binding table entries for use by transform feedback.
516 * Note: since we don't currently pack varyings, it is currently impossible
517 * for the client to actually use up all of these binding table entries--if
518 * all of their varyings were floats, they would run out of varying slots and
519 * fail to link. But that's a bug, so it seems prudent to go ahead and
520 * allocate the number of binding table entries we will need once the bug is
523 #define BRW_MAX_SOL_BINDINGS 64
525 /** Maximum number of actual buffers used for stream output */
526 #define BRW_MAX_SOL_BUFFERS 4
528 #define BRW_MAX_WM_UBOS 12
529 #define BRW_MAX_VS_UBOS 12
532 * Helpers to create Surface Binding Table indexes for draw buffers,
533 * textures, and constant buffers.
535 * Shader threads access surfaces via numeric handles, rather than directly
536 * using pointers. The binding table maps these numeric handles to the
537 * address of the actual buffer.
539 * For example, a shader might ask to sample from "surface 7." In this case,
540 * bind[7] would contain a pointer to a texture.
542 * Currently, our WM binding tables are (arbitrarily) programmed as follows:
544 * +-------------------------------+
545 * | 0 | Draw buffer 0 |
548 * | 7 | Draw buffer 7 |
549 * |-----|-------------------------|
550 * | 8 | WM Pull Constant Buffer |
551 * |-----|-------------------------|
555 * | 24 | Texture 15 |
556 * |-----|-------------------------|
561 * +-------------------------------+
563 * Our VS binding tables are programmed as follows:
565 * +-----+-------------------------+
566 * | 0 | VS Pull Constant Buffer |
567 * +-----+-------------------------+
571 * | 16 | Texture 15 |
572 * +-----+-------------------------+
577 * +-------------------------------+
579 * Our (gen6) GS binding tables are programmed as follows:
581 * +-----+-------------------------+
582 * | 0 | SOL Binding 0 |
585 * | 63 | SOL Binding 63 |
586 * +-----+-------------------------+
588 * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be
589 * the identity function or things will break. We do want to keep draw buffers
590 * first so we can use headerless render target writes for RT 0.
592 #define SURF_INDEX_DRAW(d) (d)
593 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
594 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
595 #define SURF_INDEX_WM_UBO(u) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)
596 #define SURF_INDEX_WM_SHADER_TIME (SURF_INDEX_WM_UBO(12))
597 /** Maximum size of the binding table. */
598 #define BRW_MAX_WM_SURFACES (SURF_INDEX_WM_SHADER_TIME + 1)
600 #define SURF_INDEX_VERT_CONST_BUFFER (0)
601 #define SURF_INDEX_VS_TEXTURE(t) (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t))
602 #define SURF_INDEX_VS_UBO(u) (SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT) + u)
603 #define SURF_INDEX_VS_SHADER_TIME (SURF_INDEX_VS_UBO(12))
604 #define BRW_MAX_VS_SURFACES (SURF_INDEX_VS_SHADER_TIME + 1)
606 #define SURF_INDEX_SOL_BINDING(t) ((t))
607 #define BRW_MAX_GS_SURFACES SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
610 * Stride in bytes between shader_time entries.
612 * We separate entries by a cacheline to reduce traffic between EUs writing to
615 #define SHADER_TIME_STRIDE 64
622 BRW_BLORP_CONST_COLOR_PROG
,
627 BRW_SF_UNIT
, /* scissor state on gen6 */
639 struct brw_cache_item
{
641 * Effectively part of the key, cache_id identifies what kind of state
642 * buffer is involved, and also which brw->state.dirty.cache flag should
643 * be set when this cache item is chosen.
645 enum brw_cache_id cache_id
;
646 /** 32-bit hash of the key data */
648 GLuint key_size
; /* for variable-sized keys */
655 struct brw_cache_item
*next
;
659 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
,
660 int aux_size
, const void *key
);
661 typedef void (*cache_aux_free_func
)(const void *aux
);
664 struct brw_context
*brw
;
666 struct brw_cache_item
**items
;
668 GLuint size
, n_items
;
670 uint32_t next_offset
;
674 * Optional functions used in determining whether the prog_data for a new
675 * cache item matches an existing cache item (in case there's relevant data
676 * outside of the prog_data). If NULL, a plain memcmp is done.
678 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
679 /** Optional functions for freeing other pointers attached to a prog_data. */
680 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
684 /* Considered adding a member to this struct to document which flags
685 * an update might raise so that ordering of the state atoms can be
686 * checked or derived at runtime. Dropped the idea in favor of having
687 * a debug mode where the state is monitored for flags which are
688 * raised that have already been tested against.
690 struct brw_tracked_state
{
691 struct brw_state_flags dirty
;
692 void (*emit
)( struct brw_context
*brw
);
695 enum shader_time_shader_type
{
708 /* Flags for brw->state.cache.
710 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
711 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
712 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
713 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
714 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
715 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
716 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
717 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
718 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
719 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
720 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
721 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
722 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
723 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
724 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
726 struct brw_cached_batch_item
{
727 struct header
*header
;
729 struct brw_cached_batch_item
*next
;
734 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
735 * be easier if C allowed arrays of packed elements?
737 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
739 struct brw_vertex_buffer
{
740 /** Buffer object containing the uploaded vertex data */
743 /** Byte stride between elements in the uploaded array */
747 struct brw_vertex_element
{
748 const struct gl_client_array
*glarray
;
752 /** The corresponding Mesa vertex attribute */
753 gl_vert_attrib attrib
;
754 /** Offset of the first element within the buffer object */
758 struct brw_query_object
{
759 struct gl_query_object Base
;
761 /** Last query BO associated with this query. */
764 /** Last index in bo with query data for this object. */
770 * brw_context is derived from gl_context.
774 struct gl_context ctx
; /**< base class, must be first field */
778 void (*destroy
) (struct brw_context
* brw
);
779 void (*finish_batch
) (struct brw_context
* brw
);
780 void (*new_batch
) (struct brw_context
* brw
);
782 void (*update_texture_surface
)(struct gl_context
*ctx
,
784 uint32_t *binding_table
,
785 unsigned surf_index
);
786 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
787 struct gl_renderbuffer
*rb
,
790 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
792 void (*create_constant_surface
)(struct brw_context
*brw
,
796 uint32_t *out_offset
,
800 * Send the appropriate state packets to configure depth, stencil, and
801 * HiZ buffers (i965+ only)
803 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
804 struct intel_mipmap_tree
*depth_mt
,
805 uint32_t depth_offset
,
806 uint32_t depthbuffer_format
,
807 uint32_t depth_surface_type
,
808 struct intel_mipmap_tree
*stencil_mt
,
809 bool hiz
, bool separate_stencil
,
810 uint32_t width
, uint32_t height
,
811 uint32_t tile_x
, uint32_t tile_y
);
817 drm_intel_context
*hw_ctx
;
819 struct intel_batchbuffer batch
;
826 uint32_t buffer_offset
;
831 * Set if rendering has occured to the drawable's front buffer.
833 * This is used in the DRI2 case to detect that glFlush should also copy
834 * the contents of the fake front buffer to the real front buffer.
836 bool front_buffer_dirty
;
839 * Track whether front-buffer rendering is currently enabled
841 * A separate flag is used to track this in order to support MRT more
844 bool is_front_buffer_rendering
;
847 * Track whether front-buffer is the current read target.
849 * This is closely associated with is_front_buffer_rendering, but may
850 * be set separately. The DRI2 fake front buffer must be referenced
853 bool is_front_buffer_reading
;
855 /** Framerate throttling: @{ */
856 drm_intel_bo
*first_post_swapbuffers_batch
;
867 bool always_flush_batch
;
868 bool always_flush_cache
;
869 bool disable_throttling
;
872 driOptionCache optionCache
;
875 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
877 GLenum reduced_primitive
;
880 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
881 * variable is set, this is the flag indicating to do expensive work that
882 * might lead to a perf_debug() call.
886 uint32_t max_gtt_map_object_size
;
888 bool emit_state_always
;
898 bool has_separate_stencil
;
899 bool must_use_separate_stencil
;
902 bool has_surface_tile_offset
;
904 bool has_negative_rhw_bug
;
905 bool has_aa_line_parameters
;
909 * Some versions of Gen hardware don't do centroid interpolation correctly
910 * on unlit pixels, causing incorrect values for derivatives near triangle
911 * edges. Enabling this flag causes the fragment shader to use
912 * non-centroid interpolation for unlit pixels, at the expense of two extra
913 * fragment shader instructions.
915 bool needs_unlit_centroid_workaround
;
919 struct brw_state_flags dirty
;
922 struct brw_cache cache
;
923 struct brw_cached_batch_item
*cached_batch_items
;
925 /* Whether a meta-operation is in progress. */
926 bool meta_in_progress
;
929 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
930 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
932 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
936 /* Summary of size and varying of active arrays, so we can check
937 * for changes to this state:
939 unsigned int min_index
, max_index
;
941 /* Offset from start of vertex buffer so we can avoid redefining
942 * the same VB packed over and over again.
944 unsigned int start_vertex_bias
;
949 * Index buffer for this draw_prims call.
951 * Updates are signaled by BRW_NEW_INDICES.
953 const struct _mesa_index_buffer
*ib
;
955 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
959 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
960 * avoid re-uploading the IB packet over and over if we're actually
961 * referencing the same index buffer.
963 unsigned int start_vertex_offset
;
966 /* Active vertex program:
968 const struct gl_vertex_program
*vertex_program
;
969 const struct gl_fragment_program
*fragment_program
;
971 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
972 uint32_t CMD_VF_STATISTICS
;
973 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
974 uint32_t CMD_PIPELINE_SELECT
;
977 * Platform specific constants containing the maximum number of threads
978 * for each pipeline stage.
984 /* BRW_NEW_URB_ALLOCATIONS:
987 GLuint vsize
; /* vertex size plus header in urb registers */
988 GLuint csize
; /* constant buffer size in urb registers */
989 GLuint sfsize
; /* setup data size in urb registers */
993 GLuint max_vs_entries
; /* Maximum number of VS entries */
994 GLuint max_gs_entries
; /* Maximum number of GS entries */
996 GLuint nr_vs_entries
;
997 GLuint nr_gs_entries
;
998 GLuint nr_clip_entries
;
999 GLuint nr_sf_entries
;
1000 GLuint nr_cs_entries
;
1007 GLuint size
; /* Hardware URB size, in KB. */
1009 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1010 * URB space for the GS.
1012 bool gen6_gs_previously_active
;
1016 /* BRW_NEW_CURBE_OFFSETS:
1019 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1020 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1027 drm_intel_bo
*curbe_bo
;
1028 /** Offset within curbe_bo of space for current curbe entry */
1029 GLuint curbe_offset
;
1030 /** Offset within curbe_bo of space for next curbe entry */
1031 GLuint curbe_next_offset
;
1034 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
1035 * in brw_curbe.c with the same set of constant data to be uploaded,
1036 * so we'd rather not upload new constants in that case (it can cause
1037 * a pipeline bubble since only up to 4 can be pipelined at a time).
1041 * Allocation for where to calculate the next set of CURBEs.
1042 * It's a hot enough path that malloc/free of that data matters.
1048 /** SAMPLER_STATE count and offset */
1055 * Layout of vertex data exiting the geometry portion of the pipleine.
1056 * This comes from the geometry shader if one exists, otherwise from the
1059 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1061 struct brw_vue_map vue_map_geom_out
;
1064 struct brw_vs_prog_data
*prog_data
;
1066 drm_intel_bo
*scratch_bo
;
1067 drm_intel_bo
*const_bo
;
1068 /** Offset in the program cache to the VS program */
1069 uint32_t prog_offset
;
1070 uint32_t state_offset
;
1072 uint32_t push_const_offset
; /* Offset in the batchbuffer */
1073 int push_const_size
; /* in 256-bit register increments */
1075 /** @{ register allocator */
1077 struct ra_regs
*regs
;
1080 * Array of the ra classes for the unaligned contiguous register
1086 * Mapping for register-allocated objects in *regs to the first
1087 * GRF for that object.
1089 uint8_t *ra_reg_to_grf
;
1092 uint32_t bind_bo_offset
;
1093 uint32_t surf_offset
[BRW_MAX_VS_SURFACES
];
1097 struct brw_gs_prog_data
*prog_data
;
1100 /** Offset in the program cache to the CLIP program pre-gen6 */
1101 uint32_t prog_offset
;
1102 uint32_t state_offset
;
1104 uint32_t bind_bo_offset
;
1105 uint32_t surf_offset
[BRW_MAX_GS_SURFACES
];
1109 struct brw_clip_prog_data
*prog_data
;
1111 /** Offset in the program cache to the CLIP program pre-gen6 */
1112 uint32_t prog_offset
;
1114 /* Offset in the batch to the CLIP state on pre-gen6. */
1115 uint32_t state_offset
;
1117 /* As of gen6, this is the offset in the batch to the CLIP VP,
1125 struct brw_sf_prog_data
*prog_data
;
1127 /** Offset in the program cache to the CLIP program pre-gen6 */
1128 uint32_t prog_offset
;
1129 uint32_t state_offset
;
1134 struct brw_wm_prog_data
*prog_data
;
1136 /** offsets in the batch to sampler default colors (texture border color)
1138 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
1142 drm_intel_bo
*scratch_bo
;
1145 * Buffer object used in place of multisampled null render targets on
1146 * Gen6. See brw_update_null_renderbuffer_surface().
1148 drm_intel_bo
*multisampled_null_render_target_bo
;
1150 /** Offset in the program cache to the WM program */
1151 uint32_t prog_offset
;
1153 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
1155 drm_intel_bo
*const_bo
; /* pull constant buffer. */
1157 * This is offset in the batch to the push constants on gen6.
1159 * Pre-gen6, push constants live in the CURBE.
1161 uint32_t push_const_offset
;
1163 /** Binding table of pointers to surf_bo entries */
1164 uint32_t bind_bo_offset
;
1165 uint32_t surf_offset
[BRW_MAX_WM_SURFACES
];
1168 struct ra_regs
*regs
;
1170 /** Array of the ra classes for the unaligned contiguous
1171 * register block sizes used.
1176 * Mapping for register-allocated objects in *regs to the first
1177 * GRF for that object.
1179 uint8_t *ra_reg_to_grf
;
1182 * ra class for the aligned pairs we use for PLN, which doesn't
1183 * appear in *classes.
1185 int aligned_pairs_class
;
1191 uint32_t state_offset
;
1192 uint32_t blend_state_offset
;
1193 uint32_t depth_stencil_state_offset
;
1198 struct brw_query_object
*obj
;
1203 const struct brw_tracked_state
**atoms
;
1205 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1209 enum state_struct_type type
;
1210 } *state_batch_list
;
1211 int state_batch_count
;
1213 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1214 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1216 /* Interpolation modes, one byte per vue slot.
1217 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1219 struct interpolation_mode_map interpolation_mode
;
1221 /* PrimitiveRestart */
1224 bool enable_cut_index
;
1227 /** Computed depth/stencil/hiz state from the current attached
1228 * renderbuffers, valid only during the drawing state upload loop after
1229 * brw_workaround_depthstencil_alignment().
1232 struct intel_mipmap_tree
*depth_mt
;
1233 struct intel_mipmap_tree
*stencil_mt
;
1235 /* Inter-tile (page-aligned) byte offsets. */
1236 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1237 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1238 uint32_t tile_x
, tile_y
;
1241 uint32_t num_instances
;
1246 struct gl_shader_program
**shader_programs
;
1247 struct gl_program
**programs
;
1248 enum shader_time_shader_type
*types
;
1249 uint64_t *cumulative
;
1255 __DRIcontext
*driContext
;
1256 struct intel_screen
*intelScreen
;
1257 void (*saved_viewport
)(struct gl_context
*ctx
,
1258 GLint x
, GLint y
, GLsizei width
, GLsizei height
);
1261 /*======================================================================
1264 void brwInitVtbl( struct brw_context
*brw
);
1266 /*======================================================================
1269 bool brwCreateContext(int api
,
1270 const struct gl_config
*mesaVis
,
1271 __DRIcontext
*driContextPriv
,
1272 unsigned major_version
,
1273 unsigned minor_version
,
1276 void *sharedContextPrivate
);
1278 /*======================================================================
1281 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1282 uint32_t depth_level
,
1283 uint32_t depth_layer
,
1284 struct intel_mipmap_tree
*stencil_mt
,
1285 uint32_t *out_tile_mask_x
,
1286 uint32_t *out_tile_mask_y
);
1287 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1288 GLbitfield clear_mask
);
1290 /*======================================================================
1293 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1294 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1295 void brw_emit_query_begin(struct brw_context
*brw
);
1296 void brw_emit_query_end(struct brw_context
*brw
);
1298 /** gen6_queryobj.c */
1299 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1301 /*======================================================================
1304 void brw_debug_batch(struct brw_context
*brw
);
1305 void brw_annotate_aub(struct brw_context
*brw
);
1307 /*======================================================================
1310 void brw_validate_textures( struct brw_context
*brw
);
1313 /*======================================================================
1316 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1318 int brw_get_scratch_size(int size
);
1319 void brw_get_scratch_bo(struct brw_context
*brw
,
1320 drm_intel_bo
**scratch_bo
, int size
);
1321 void brw_init_shader_time(struct brw_context
*brw
);
1322 int brw_get_shader_time_index(struct brw_context
*brw
,
1323 struct gl_shader_program
*shader_prog
,
1324 struct gl_program
*prog
,
1325 enum shader_time_shader_type type
);
1326 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1327 void brw_destroy_shader_time(struct brw_context
*brw
);
1331 void brw_upload_urb_fence(struct brw_context
*brw
);
1335 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1337 /* brw_fs_reg_allocate.cpp
1339 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1342 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1345 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1347 /* brw_wm_surface_state.c */
1348 void brw_init_surface_formats(struct brw_context
*brw
);
1350 brw_update_sol_surface(struct brw_context
*brw
,
1351 struct gl_buffer_object
*buffer_obj
,
1352 uint32_t *out_offset
, unsigned num_vector_components
,
1353 unsigned stride_dwords
, unsigned offset_dwords
);
1354 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1355 struct gl_shader
*shader
,
1356 uint32_t *surf_offsets
);
1358 /* brw_surface_formats.c */
1359 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, gl_format format
);
1360 bool brw_render_target_supported(struct brw_context
*brw
,
1361 struct gl_renderbuffer
*rb
);
1365 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1366 struct gl_transform_feedback_object
*obj
);
1368 brw_end_transform_feedback(struct gl_context
*ctx
,
1369 struct gl_transform_feedback_object
*obj
);
1371 /* gen7_sol_state.c */
1373 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1374 struct gl_transform_feedback_object
*obj
);
1376 gen7_end_transform_feedback(struct gl_context
*ctx
,
1377 struct gl_transform_feedback_object
*obj
);
1379 /* brw_blorp_blit.cpp */
1381 brw_blorp_framebuffer(struct brw_context
*brw
,
1382 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1383 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1384 GLbitfield mask
, GLenum filter
);
1387 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1388 struct gl_renderbuffer
*src_rb
,
1389 struct gl_texture_image
*dst_image
,
1391 int srcX0
, int srcY0
,
1392 int dstX0
, int dstY0
,
1393 int width
, int height
);
1395 /* gen6_multisample_state.c */
1397 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1398 unsigned num_samples
);
1400 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
,
1401 unsigned num_samples
, float coverage
,
1402 bool coverage_invert
, unsigned sample_mask
);
1404 gen6_get_sample_position(struct gl_context
*ctx
,
1405 struct gl_framebuffer
*fb
,
1411 gen7_allocate_push_constants(struct brw_context
*brw
);
1414 gen7_emit_urb_state(struct brw_context
*brw
, GLuint nr_vs_entries
,
1415 GLuint vs_size
, GLuint vs_start
);
1419 /*======================================================================
1420 * Inline conversion functions. These are better-typed than the
1421 * macros used previously:
1423 static INLINE
struct brw_context
*
1424 brw_context( struct gl_context
*ctx
)
1426 return (struct brw_context
*)ctx
;
1429 static INLINE
struct brw_vertex_program
*
1430 brw_vertex_program(struct gl_vertex_program
*p
)
1432 return (struct brw_vertex_program
*) p
;
1435 static INLINE
const struct brw_vertex_program
*
1436 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1438 return (const struct brw_vertex_program
*) p
;
1441 static INLINE
struct brw_fragment_program
*
1442 brw_fragment_program(struct gl_fragment_program
*p
)
1444 return (struct brw_fragment_program
*) p
;
1447 static INLINE
const struct brw_fragment_program
*
1448 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1450 return (const struct brw_fragment_program
*) p
;
1454 * Pre-gen6, the register file of the EUs was shared between threads,
1455 * and each thread used some subset allocated on a 16-register block
1456 * granularity. The unit states wanted these block counts.
1459 brw_register_blocks(int reg_count
)
1461 return ALIGN(reg_count
, 16) / 16 - 1;
1464 static inline uint32_t
1465 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1466 uint32_t prog_offset
)
1468 if (brw
->gen
>= 5) {
1469 /* Using state base address. */
1473 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1477 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1479 return brw
->cache
.bo
->offset
+ prog_offset
;
1482 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1483 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1484 struct exec_list
*instructions
);
1486 struct opcode_desc
{
1492 extern const struct opcode_desc opcode_descs
[128];
1495 brw_emit_depthbuffer(struct brw_context
*brw
);
1498 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1499 struct intel_mipmap_tree
*depth_mt
,
1500 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1501 uint32_t depth_surface_type
,
1502 struct intel_mipmap_tree
*stencil_mt
,
1503 bool hiz
, bool separate_stencil
,
1504 uint32_t width
, uint32_t height
,
1505 uint32_t tile_x
, uint32_t tile_y
);
1508 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1509 struct intel_mipmap_tree
*depth_mt
,
1510 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1511 uint32_t depth_surface_type
,
1512 struct intel_mipmap_tree
*stencil_mt
,
1513 bool hiz
, bool separate_stencil
,
1514 uint32_t width
, uint32_t height
,
1515 uint32_t tile_x
, uint32_t tile_y
);