2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
43 * URB - uniform resource buffer. A mid-sized buffer which is
44 * partitioned between the fixed function units and used for passing
45 * values (vertices, primitives, constants) between them.
47 * CURBE - constant URB entry. An urb region (entry) used to hold
48 * constant values which the fixed function units can be instructed to
49 * preload into the GRF when spawning a thread.
51 * VUE - vertex URB entry. An urb entry holding a vertex and usually
52 * a vertex header. The header contains control information and
53 * things like primitive type, Begin/end flags and clip codes.
55 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
56 * unit holding rasterization and interpolation parameters.
58 * GRF - general register file. One of several register files
59 * addressable by programmed threads. The inputs (r0, payload, curbe,
60 * urb) of the thread are preloaded to this area before the thread is
61 * spawned. The registers are individually 8 dwords wide and suitable
62 * for general usage. Registers holding thread input values are not
63 * special and may be overwritten.
65 * MRF - message register file. Threads communicate (and terminate)
66 * by sending messages. Message parameters are placed in contiguous
67 * MRF registers. All program output is via these messages. URB
68 * entries are populated by sending a message to the shared URB
69 * function containing the new data, together with a control word,
70 * often an unmodified copy of R0.
72 * R0 - GRF register 0. Typically holds control information used when
73 * sending messages to other threads.
75 * EU or GEN4 EU: The name of the programmable subsystem of the
76 * i965 hardware. Threads are executed by the EU, the registers
77 * described above are part of the EU architecture.
79 * Fixed function units:
81 * CS - Command streamer. Notional first unit, little software
82 * interaction. Holds the URB entries used for constant data, ie the
85 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
86 * this unit is responsible for pulling vertices out of vertex buffers
87 * in vram and injecting them into the processing pipe as VUEs. If
88 * enabled, it first passes them to a VS thread which is a good place
89 * for the driver to implement any active vertex shader.
91 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
92 * enabled, incoming strips etc are passed to GS threads in individual
93 * line/triangle/point units. The GS thread may perform arbitary
94 * computation and emit whatever primtives with whatever vertices it
95 * chooses. This makes GS an excellent place to implement GL's
96 * unfilled polygon modes, though of course it is capable of much
97 * more. Additionally, GS is used to translate away primitives not
98 * handled by latter units, including Quads and Lineloops.
100 * CS - Clipper. Mesa's clipping algorithms are imported to run on
101 * this unit. The fixed function part performs cliptesting against
102 * the 6 fixed clipplanes and makes descisions on whether or not the
103 * incoming primitive needs to be passed to a thread for clipping.
104 * User clip planes are handled via cooperation with the VS thread.
106 * SF - Strips Fans or Setup: Triangles are prepared for
107 * rasterization. Interpolation coefficients are calculated.
108 * Flatshading and two-side lighting usually performed here.
110 * WM - Windower. Interpolation of vertex attributes performed here.
111 * Fragment shader implemented here. SIMD aspects of EU taken full
112 * advantage of, as pixels are processed in blocks of 16.
114 * CC - Color Calculator. No EU threads associated with this unit.
115 * Handles blending and (presumably) depth and stencil testing.
119 #define BRW_MAX_CURBE (32*16)
125 BRW_STATE_FRAGMENT_PROGRAM
,
126 BRW_STATE_VERTEX_PROGRAM
,
127 BRW_STATE_INPUT_DIMENSIONS
,
128 BRW_STATE_CURBE_OFFSETS
,
129 BRW_STATE_REDUCED_PRIMITIVE
,
132 BRW_STATE_WM_INPUT_DIMENSIONS
,
134 BRW_STATE_WM_SURFACES
,
135 BRW_STATE_VS_BINDING_TABLE
,
136 BRW_STATE_GS_BINDING_TABLE
,
137 BRW_STATE_PS_BINDING_TABLE
,
141 BRW_STATE_NR_WM_SURFACES
,
142 BRW_STATE_NR_VS_SURFACES
,
143 BRW_STATE_INDEX_BUFFER
,
144 BRW_STATE_VS_CONSTBUF
,
145 BRW_STATE_WM_CONSTBUF
,
146 BRW_STATE_PROGRAM_CACHE
,
147 BRW_STATE_STATE_BASE_ADDRESS
,
150 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
151 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
152 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
153 #define BRW_NEW_INPUT_DIMENSIONS (1 << BRW_STATE_INPUT_DIMENSIONS)
154 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
155 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
156 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
157 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
158 #define BRW_NEW_WM_INPUT_DIMENSIONS (1 << BRW_STATE_WM_INPUT_DIMENSIONS)
159 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
160 #define BRW_NEW_WM_SURFACES (1 << BRW_STATE_WM_SURFACES)
161 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
162 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
163 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
164 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
165 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
167 * Used for any batch entry with a relocated pointer that will be used
168 * by any 3D rendering.
170 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
171 /** \see brw.state.depth_region */
172 #define BRW_NEW_NR_WM_SURFACES (1 << BRW_STATE_NR_WM_SURFACES)
173 #define BRW_NEW_NR_VS_SURFACES (1 << BRW_STATE_NR_VS_SURFACES)
174 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
175 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
176 #define BRW_NEW_WM_CONSTBUF (1 << BRW_STATE_WM_CONSTBUF)
177 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
178 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
180 struct brw_state_flags
{
181 /** State update flags signalled by mesa internals */
184 * State update flags signalled as the result of brw_tracked_state updates
187 /** State update flags signalled by brw_state_cache.c searches */
191 enum state_struct_type
{
192 AUB_TRACE_VS_STATE
= 1,
193 AUB_TRACE_GS_STATE
= 2,
194 AUB_TRACE_CLIP_STATE
= 3,
195 AUB_TRACE_SF_STATE
= 4,
196 AUB_TRACE_WM_STATE
= 5,
197 AUB_TRACE_CC_STATE
= 6,
198 AUB_TRACE_CLIP_VP_STATE
= 7,
199 AUB_TRACE_SF_VP_STATE
= 8,
200 AUB_TRACE_CC_VP_STATE
= 0x9,
201 AUB_TRACE_SAMPLER_STATE
= 0xa,
202 AUB_TRACE_KERNEL_INSTRUCTIONS
= 0xb,
203 AUB_TRACE_SCRATCH_SPACE
= 0xc,
204 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= 0xd,
206 AUB_TRACE_SCISSOR_STATE
= 0x15,
207 AUB_TRACE_BLEND_STATE
= 0x16,
208 AUB_TRACE_DEPTH_STENCIL_STATE
= 0x17,
210 /* Not written to .aub files the same way the structures above are. */
211 AUB_TRACE_NO_TYPE
= 0x100,
212 AUB_TRACE_BINDING_TABLE
= 0x101,
213 AUB_TRACE_SURFACE_STATE
= 0x102,
214 AUB_TRACE_VS_CONSTANTS
= 0x103,
215 AUB_TRACE_WM_CONSTANTS
= 0x104,
218 /** Subclass of Mesa vertex program */
219 struct brw_vertex_program
{
220 struct gl_vertex_program program
;
222 GLboolean use_const_buffer
;
226 /** Subclass of Mesa fragment program */
227 struct brw_fragment_program
{
228 struct gl_fragment_program program
;
229 GLuint id
; /**< serial no. to identify frag progs, never re-used */
231 /** for debugging, which texture units are referenced */
232 GLbitfield tex_units_used
;
236 struct gl_shader base
;
238 /** Shader IR transformed for native compile, at link time. */
239 struct exec_list
*ir
;
242 struct brw_shader_program
{
243 struct gl_shader_program base
;
246 enum param_conversion
{
254 /* Data about a particular attempt to compile a program. Note that
255 * there can be many of these, each in a different GL state
256 * corresponding to a different brw_wm_prog_key struct, with different
259 struct brw_wm_prog_data
{
260 GLuint curb_read_length
;
261 GLuint urb_read_length
;
263 GLuint first_curbe_grf
;
264 GLuint first_curbe_grf_16
;
266 GLuint reg_blocks_16
;
267 GLuint total_scratch
;
269 GLuint nr_params
; /**< number of float params/constants */
270 GLuint nr_pull_params
;
273 uint32_t prog_offset_16
;
275 /* Pointer to tracked values (only valid once
276 * _mesa_load_state_parameters has been called at runtime).
278 const float *param
[MAX_UNIFORMS
* 4]; /* should be: BRW_MAX_CURBE */
279 enum param_conversion param_convert
[MAX_UNIFORMS
* 4];
280 const float *pull_param
[MAX_UNIFORMS
* 4];
281 enum param_conversion pull_param_convert
[MAX_UNIFORMS
* 4];
284 struct brw_sf_prog_data
{
285 GLuint urb_read_length
;
288 /* Each vertex may have upto 12 attributes, 4 components each,
289 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
292 * Actually we use 4 for each, so call it 12 rows.
294 GLuint urb_entry_size
;
297 struct brw_clip_prog_data
{
298 GLuint curb_read_length
; /* user planes? */
300 GLuint urb_read_length
;
304 struct brw_gs_prog_data
{
305 GLuint urb_read_length
;
309 struct brw_vs_prog_data
{
310 GLuint curb_read_length
;
311 GLuint urb_read_length
;
313 GLbitfield64 outputs_written
;
314 GLuint nr_params
; /**< number of float params/constants */
318 /* Used for calculating urb partitions:
320 GLuint urb_entry_size
;
322 const float *param
[MAX_UNIFORMS
* 4]; /* should be: BRW_MAX_CURBE */
323 enum param_conversion param_convert
[MAX_UNIFORMS
* 4];
324 const float *pull_param
[MAX_UNIFORMS
* 4];
325 enum param_conversion pull_param_convert
[MAX_UNIFORMS
* 4];
327 bool uses_new_param_layout
;
331 /* Size == 0 if output either not written, or always [0,0,0,1]
333 struct brw_vs_ouput_sizes
{
334 GLubyte output_size
[VERT_RESULT_MAX
];
338 /** Number of texture sampler units */
339 #define BRW_MAX_TEX_UNIT 16
341 /** Max number of render targets in a shader */
342 #define BRW_MAX_DRAW_BUFFERS 8
345 * Size of our surface binding table for the WM.
346 * This contains pointers to the drawing surfaces and current texture
347 * objects and shader constant buffers (+2).
349 #define BRW_WM_MAX_SURF (BRW_MAX_DRAW_BUFFERS + BRW_MAX_TEX_UNIT + 1)
352 * Helpers to convert drawing buffers, textures and constant buffers
353 * to surface binding table indexes, for WM.
355 #define SURF_INDEX_DRAW(d) (d)
356 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS)
357 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 1 + (t))
360 * Size of surface binding table for the VS.
361 * Only one constant buffer for now.
363 #define BRW_VS_MAX_SURF 1
366 * Only a VS constant buffer
368 #define SURF_INDEX_VERT_CONST_BUFFER 0
373 BRW_DEPTH_STENCIL_STATE
,
374 BRW_COLOR_CALC_STATE
,
382 BRW_SF_UNIT
, /* scissor state on gen6 */
394 struct brw_cache_item
{
396 * Effectively part of the key, cache_id identifies what kind of state
397 * buffer is involved, and also which brw->state.dirty.cache flag should
398 * be set when this cache item is chosen.
400 enum brw_cache_id cache_id
;
401 /** 32-bit hash of the key data */
403 GLuint key_size
; /* for variable-sized keys */
410 struct brw_cache_item
*next
;
416 struct brw_context
*brw
;
418 struct brw_cache_item
**items
;
420 GLuint size
, n_items
;
422 uint32_t next_offset
;
427 /* Considered adding a member to this struct to document which flags
428 * an update might raise so that ordering of the state atoms can be
429 * checked or derived at runtime. Dropped the idea in favor of having
430 * a debug mode where the state is monitored for flags which are
431 * raised that have already been tested against.
433 struct brw_tracked_state
{
434 struct brw_state_flags dirty
;
435 void (*prepare
)( struct brw_context
*brw
);
436 void (*emit
)( struct brw_context
*brw
);
439 /* Flags for brw->state.cache.
441 #define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE)
442 #define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
443 #define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
444 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
445 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
446 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
447 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
448 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
449 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
450 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
451 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
452 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
453 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
454 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
455 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
456 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
457 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
458 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
460 struct brw_cached_batch_item
{
461 struct header
*header
;
463 struct brw_cached_batch_item
*next
;
468 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
469 * be easier if C allowed arrays of packed elements?
471 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
473 struct brw_vertex_buffer
{
474 /** Buffer object containing the uploaded vertex data */
477 /** Byte stride between elements in the uploaded array */
480 struct brw_vertex_element
{
481 const struct gl_client_array
*glarray
;
485 /** The corresponding Mesa vertex attribute */
486 gl_vert_attrib attrib
;
487 /** Size of a complete element */
489 /** Offset of the first element within the buffer object */
495 struct brw_vertex_info
{
496 GLuint sizes
[ATTRIB_BIT_DWORDS
* 2]; /* sizes:2[VERT_ATTRIB_MAX] */
499 struct brw_query_object
{
500 struct gl_query_object Base
;
502 /** Last query BO associated with this query. */
504 /** First index in bo with query data for this object. */
506 /** Last index in bo with query data for this object. */
512 * brw_context is derived from intel_context.
516 struct intel_context intel
; /**< base class, must be first field */
519 GLboolean emit_state_always
;
520 GLboolean has_surface_tile_offset
;
521 GLboolean has_compr4
;
522 GLboolean has_negative_rhw_bug
;
523 GLboolean has_aa_line_parameters
;
527 struct brw_state_flags dirty
;
529 * List of buffers accumulated in brw_validate_state to receive
530 * drm_intel_bo_check_aperture treatment before exec, so we can
531 * know if we should flush the batch and try again before
532 * emitting primitives.
534 * This can be a fixed number as we only have a limited number of
535 * objects referenced from the batchbuffer in a primitive emit,
536 * consisting of the vertex buffers, pipelined state pointers,
537 * the CURBE, the depth buffer, and a query BO.
539 drm_intel_bo
*validated_bos
[VERT_ATTRIB_MAX
+ BRW_WM_MAX_SURF
+ 16];
540 unsigned int validated_bo_count
;
543 struct brw_cache cache
;
544 struct brw_cached_batch_item
*cached_batch_items
;
547 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
548 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
553 } current_buffers
[VERT_ATTRIB_MAX
];
555 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
557 GLuint nr_buffers
, nr_current_buffers
;
559 /* Summary of size and varying of active arrays, so we can check
560 * for changes to this state:
562 struct brw_vertex_info info
;
563 unsigned int min_index
, max_index
;
565 /* Offset from start of vertex buffer so we can avoid redefining
566 * the same VB packed over and over again.
568 unsigned int start_vertex_bias
;
573 * Index buffer for this draw_prims call.
575 * Updates are signaled by BRW_NEW_INDICES.
577 const struct _mesa_index_buffer
*ib
;
579 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
583 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
584 * avoid re-uploading the IB packet over and over if we're actually
585 * referencing the same index buffer.
587 unsigned int start_vertex_offset
;
590 /* Active vertex program:
592 const struct gl_vertex_program
*vertex_program
;
593 const struct gl_fragment_program
*fragment_program
;
595 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
596 uint32_t CMD_VF_STATISTICS
;
597 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
598 uint32_t CMD_PIPELINE_SELECT
;
602 /* BRW_NEW_URB_ALLOCATIONS:
605 GLuint vsize
; /* vertex size plus header in urb registers */
606 GLuint csize
; /* constant buffer size in urb registers */
607 GLuint sfsize
; /* setup data size in urb registers */
609 GLboolean constrained
;
611 GLuint max_vs_entries
; /* Maximum number of VS entries */
612 GLuint max_gs_entries
; /* Maximum number of GS entries */
614 GLuint nr_vs_entries
;
615 GLuint nr_gs_entries
;
616 GLuint nr_clip_entries
;
617 GLuint nr_sf_entries
;
618 GLuint nr_cs_entries
;
621 * The length of each URB entry owned by the VS (or GS), as
622 * a number of 1024-bit (128-byte) rows. Should be >= 1.
624 * gen7: Same meaning, but in 512-bit (64-byte) rows.
634 GLuint size
; /* Hardware URB size, in KB. */
638 /* BRW_NEW_CURBE_OFFSETS:
641 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
642 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
649 drm_intel_bo
*curbe_bo
;
650 /** Offset within curbe_bo of space for current curbe entry */
652 /** Offset within curbe_bo of space for next curbe entry */
653 GLuint curbe_next_offset
;
656 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
657 * in brw_curbe.c with the same set of constant data to be uploaded,
658 * so we'd rather not upload new constants in that case (it can cause
659 * a pipeline bubble since only up to 4 can be pipelined at a time).
663 * Allocation for where to calculate the next set of CURBEs.
664 * It's a hot enough path that malloc/free of that data matters.
671 struct brw_vs_prog_data
*prog_data
;
672 int8_t *constant_map
; /* variable array following prog_data */
674 drm_intel_bo
*const_bo
;
675 /** Offset in the program cache to the VS program */
676 uint32_t prog_offset
;
677 uint32_t state_offset
;
679 /** Binding table of pointers to surf_bo entries */
680 uint32_t bind_bo_offset
;
681 uint32_t surf_offset
[BRW_VS_MAX_SURF
];
684 uint32_t push_const_offset
; /* Offset in the batchbuffer */
685 int push_const_size
; /* in 256-bit register increments */
689 struct brw_gs_prog_data
*prog_data
;
691 GLboolean prog_active
;
692 /** Offset in the program cache to the CLIP program pre-gen6 */
693 uint32_t prog_offset
;
694 uint32_t state_offset
;
698 struct brw_clip_prog_data
*prog_data
;
700 /** Offset in the program cache to the CLIP program pre-gen6 */
701 uint32_t prog_offset
;
703 /* Offset in the batch to the CLIP state on pre-gen6. */
704 uint32_t state_offset
;
706 /* As of gen6, this is the offset in the batch to the CLIP VP,
714 struct brw_sf_prog_data
*prog_data
;
716 /** Offset in the program cache to the CLIP program pre-gen6 */
717 uint32_t prog_offset
;
718 uint32_t state_offset
;
723 struct brw_wm_prog_data
*prog_data
;
724 struct brw_wm_compile
*compile_data
;
726 /** Input sizes, calculated from active vertex program.
727 * One bit per fragment program input attribute.
729 GLbitfield input_size_masks
[4];
731 /** offsets in the batch to sampler default colors (texture border color)
733 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
739 drm_intel_bo
*scratch_bo
;
741 GLuint sampler_count
;
742 uint32_t sampler_offset
;
744 /** Offset in the program cache to the WM program */
745 uint32_t prog_offset
;
747 /** Binding table of pointers to surf_bo entries */
748 uint32_t bind_bo_offset
;
749 uint32_t surf_offset
[BRW_WM_MAX_SURF
];
750 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
752 drm_intel_bo
*const_bo
; /* pull constant buffer. */
754 * This is offset in the batch to the push constants on gen6.
756 * Pre-gen6, push constants live in the CURBE.
758 uint32_t push_const_offset
;
760 /** @{ register allocator */
762 struct ra_regs
*regs
;
764 /** Array of the ra classes for the unaligned contiguous
765 * register block sizes used.
770 * Mapping for register-allocated objects in *regs to the first
771 * GRF for that object.
773 uint8_t *ra_reg_to_grf
;
776 * ra class for the aligned pairs we use for PLN, which doesn't
777 * appear in *classes.
779 int aligned_pairs_class
;
786 uint32_t state_offset
;
787 uint32_t blend_state_offset
;
788 uint32_t depth_stencil_state_offset
;
793 struct brw_query_object
*obj
;
798 /* Used to give every program string a unique id
802 int num_prepare_atoms
, num_emit_atoms
;
803 struct brw_tracked_state prepare_atoms
[64], emit_atoms
[64];
805 /* If (INTEL_DEBUG & DEBUG_BATCH) */
809 enum state_struct_type type
;
811 int state_batch_count
;
815 #define BRW_PACKCOLOR8888(r,g,b,a) ((r<<24) | (g<<16) | (b<<8) | a)
817 struct brw_instruction_info
{
823 extern const struct brw_instruction_info brw_opcodes
[128];
825 /*======================================================================
828 void brwInitVtbl( struct brw_context
*brw
);
830 /*======================================================================
833 GLboolean
brwCreateContext( int api
,
834 const struct gl_config
*mesaVis
,
835 __DRIcontext
*driContextPriv
,
836 void *sharedContextPrivate
);
838 /*======================================================================
841 void brw_init_queryobj_functions(struct dd_function_table
*functions
);
842 void brw_prepare_query_begin(struct brw_context
*brw
);
843 void brw_emit_query_begin(struct brw_context
*brw
);
844 void brw_emit_query_end(struct brw_context
*brw
);
846 /*======================================================================
849 void brw_debug_batch(struct intel_context
*intel
);
851 /*======================================================================
854 void brw_validate_textures( struct brw_context
*brw
);
857 /*======================================================================
860 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
865 void brw_upload_urb_fence(struct brw_context
*brw
);
869 void brw_upload_cs_urb_state(struct brw_context
*brw
);
872 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
874 /*======================================================================
875 * Inline conversion functions. These are better-typed than the
876 * macros used previously:
878 static INLINE
struct brw_context
*
879 brw_context( struct gl_context
*ctx
)
881 return (struct brw_context
*)ctx
;
884 static INLINE
struct brw_vertex_program
*
885 brw_vertex_program(struct gl_vertex_program
*p
)
887 return (struct brw_vertex_program
*) p
;
890 static INLINE
const struct brw_vertex_program
*
891 brw_vertex_program_const(const struct gl_vertex_program
*p
)
893 return (const struct brw_vertex_program
*) p
;
896 static INLINE
struct brw_fragment_program
*
897 brw_fragment_program(struct gl_fragment_program
*p
)
899 return (struct brw_fragment_program
*) p
;
902 static INLINE
const struct brw_fragment_program
*
903 brw_fragment_program_const(const struct gl_fragment_program
*p
)
905 return (const struct brw_fragment_program
*) p
;
909 float convert_param(enum param_conversion conversion
, const float *param
)
917 switch (conversion
) {
918 case PARAM_NO_CONVERT
:
920 case PARAM_CONVERT_F2I
:
923 case PARAM_CONVERT_F2U
:
926 case PARAM_CONVERT_F2B
:
932 case PARAM_CONVERT_ZERO
:
940 * Pre-gen6, the register file of the EUs was shared between threads,
941 * and each thread used some subset allocated on a 16-register block
942 * granularity. The unit states wanted these block counts.
945 brw_register_blocks(int reg_count
)
947 return ALIGN(reg_count
, 16) / 16 - 1;
950 static inline uint32_t
951 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
952 uint32_t prog_offset
)
954 struct intel_context
*intel
= &brw
->intel
;
956 if (intel
->gen
>= 5) {
957 /* Using state base address. */
961 drm_intel_bo_emit_reloc(intel
->batch
.bo
,
965 I915_GEM_DOMAIN_INSTRUCTION
, 0);
967 return brw
->cache
.bo
->offset
+ prog_offset
;
970 GLboolean
brw_do_cubemap_normalize(struct exec_list
*instructions
);