2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
47 /* Evil hack for using libdrm in a c++ compiler. */
52 #include <intel_bufmgr.h>
62 #include "intel_debug.h"
63 #include "intel_screen.h"
64 #include "intel_tex_obj.h"
65 #include "intel_resolve_map.h"
69 * URB - uniform resource buffer. A mid-sized buffer which is
70 * partitioned between the fixed function units and used for passing
71 * values (vertices, primitives, constants) between them.
73 * CURBE - constant URB entry. An urb region (entry) used to hold
74 * constant values which the fixed function units can be instructed to
75 * preload into the GRF when spawning a thread.
77 * VUE - vertex URB entry. An urb entry holding a vertex and usually
78 * a vertex header. The header contains control information and
79 * things like primitive type, Begin/end flags and clip codes.
81 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
82 * unit holding rasterization and interpolation parameters.
84 * GRF - general register file. One of several register files
85 * addressable by programmed threads. The inputs (r0, payload, curbe,
86 * urb) of the thread are preloaded to this area before the thread is
87 * spawned. The registers are individually 8 dwords wide and suitable
88 * for general usage. Registers holding thread input values are not
89 * special and may be overwritten.
91 * MRF - message register file. Threads communicate (and terminate)
92 * by sending messages. Message parameters are placed in contiguous
93 * MRF registers. All program output is via these messages. URB
94 * entries are populated by sending a message to the shared URB
95 * function containing the new data, together with a control word,
96 * often an unmodified copy of R0.
98 * R0 - GRF register 0. Typically holds control information used when
99 * sending messages to other threads.
101 * EU or GEN4 EU: The name of the programmable subsystem of the
102 * i965 hardware. Threads are executed by the EU, the registers
103 * described above are part of the EU architecture.
105 * Fixed function units:
107 * CS - Command streamer. Notional first unit, little software
108 * interaction. Holds the URB entries used for constant data, ie the
111 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
112 * this unit is responsible for pulling vertices out of vertex buffers
113 * in vram and injecting them into the processing pipe as VUEs. If
114 * enabled, it first passes them to a VS thread which is a good place
115 * for the driver to implement any active vertex shader.
117 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
118 * enabled, incoming strips etc are passed to GS threads in individual
119 * line/triangle/point units. The GS thread may perform arbitary
120 * computation and emit whatever primtives with whatever vertices it
121 * chooses. This makes GS an excellent place to implement GL's
122 * unfilled polygon modes, though of course it is capable of much
123 * more. Additionally, GS is used to translate away primitives not
124 * handled by latter units, including Quads and Lineloops.
126 * CS - Clipper. Mesa's clipping algorithms are imported to run on
127 * this unit. The fixed function part performs cliptesting against
128 * the 6 fixed clipplanes and makes descisions on whether or not the
129 * incoming primitive needs to be passed to a thread for clipping.
130 * User clip planes are handled via cooperation with the VS thread.
132 * SF - Strips Fans or Setup: Triangles are prepared for
133 * rasterization. Interpolation coefficients are calculated.
134 * Flatshading and two-side lighting usually performed here.
136 * WM - Windower. Interpolation of vertex attributes performed here.
137 * Fragment shader implemented here. SIMD aspects of EU taken full
138 * advantage of, as pixels are processed in blocks of 16.
140 * CC - Color Calculator. No EU threads associated with this unit.
141 * Handles blending and (presumably) depth and stencil testing.
146 struct brw_vs_prog_key
;
147 struct brw_vec4_prog_key
;
148 struct brw_wm_prog_key
;
149 struct brw_wm_prog_data
;
153 BRW_STATE_FRAGMENT_PROGRAM
,
154 BRW_STATE_GEOMETRY_PROGRAM
,
155 BRW_STATE_VERTEX_PROGRAM
,
156 BRW_STATE_CURBE_OFFSETS
,
157 BRW_STATE_REDUCED_PRIMITIVE
,
162 BRW_STATE_VS_BINDING_TABLE
,
163 BRW_STATE_GS_BINDING_TABLE
,
164 BRW_STATE_PS_BINDING_TABLE
,
168 BRW_STATE_INDEX_BUFFER
,
169 BRW_STATE_VS_CONSTBUF
,
170 BRW_STATE_GS_CONSTBUF
,
171 BRW_STATE_PROGRAM_CACHE
,
172 BRW_STATE_STATE_BASE_ADDRESS
,
173 BRW_STATE_VUE_MAP_VS
,
174 BRW_STATE_VUE_MAP_GEOM_OUT
,
175 BRW_STATE_TRANSFORM_FEEDBACK
,
176 BRW_STATE_RASTERIZER_DISCARD
,
178 BRW_STATE_UNIFORM_BUFFER
,
179 BRW_STATE_ATOMIC_BUFFER
,
180 BRW_STATE_META_IN_PROGRESS
,
181 BRW_STATE_INTERPOLATION_MAP
,
182 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
183 BRW_STATE_NUM_SAMPLES
,
187 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
188 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
189 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
190 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
191 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
192 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
193 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
194 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
195 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
196 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
197 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
198 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
199 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
200 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
201 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
203 * Used for any batch entry with a relocated pointer that will be used
204 * by any 3D rendering.
206 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
207 /** \see brw.state.depth_region */
208 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
209 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
210 #define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
211 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
212 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
213 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
214 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
215 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
216 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
217 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
218 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
219 #define BRW_NEW_ATOMIC_BUFFER (1 << BRW_STATE_ATOMIC_BUFFER)
220 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
221 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
222 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
223 #define BRW_NEW_NUM_SAMPLES (1 << BRW_STATE_NUM_SAMPLES)
225 struct brw_state_flags
{
226 /** State update flags signalled by mesa internals */
229 * State update flags signalled as the result of brw_tracked_state updates
233 * State update flags that used to be signalled by brw_state_cache.c
236 * Now almost all of that state is just streamed out on demand, but the
237 * flags for those state blobs updating have stayed in the same bitfield.
238 * brw_state_cache.c still flags CACHE_NEW_*_PROG.
243 /** Subclass of Mesa vertex program */
244 struct brw_vertex_program
{
245 struct gl_vertex_program program
;
250 /** Subclass of Mesa geometry program */
251 struct brw_geometry_program
{
252 struct gl_geometry_program program
;
253 unsigned id
; /**< serial no. to identify geom progs, never re-used */
257 /** Subclass of Mesa fragment program */
258 struct brw_fragment_program
{
259 struct gl_fragment_program program
;
260 GLuint id
; /**< serial no. to identify frag progs, never re-used */
264 /** Subclass of Mesa compute program */
265 struct brw_compute_program
{
266 struct gl_compute_program program
;
267 unsigned id
; /**< serial no. to identify compute progs, never re-used */
272 struct gl_shader base
;
277 /* Note: If adding fields that need anything besides a normal memcmp() for
278 * comparing them, be sure to go fix brw_stage_prog_data_compare().
280 struct brw_stage_prog_data
{
282 /** size of our binding table. */
286 * surface indices for the various groups of surfaces
288 uint32_t pull_constants_start
;
289 uint32_t texture_start
;
290 uint32_t gather_texture_start
;
293 uint32_t shader_time_start
;
297 GLuint nr_params
; /**< number of float params/constants */
298 GLuint nr_pull_params
;
301 * Register where the thread expects to find input data from the URB
302 * (typically uniforms, followed by vertex or fragment attributes).
304 unsigned dispatch_grf_start_reg
;
306 /* Pointers to tracked values (only valid once
307 * _mesa_load_state_parameters has been called at runtime).
309 * These must be the last fields of the struct (see
310 * brw_stage_prog_data_compare()).
313 const float **pull_param
;
316 /* Data about a particular attempt to compile a program. Note that
317 * there can be many of these, each in a different GL state
318 * corresponding to a different brw_wm_prog_key struct, with different
321 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
324 struct brw_wm_prog_data
{
325 struct brw_stage_prog_data base
;
327 GLuint curb_read_length
;
328 GLuint num_varying_inputs
;
330 GLuint dispatch_grf_start_reg_16
;
332 GLuint reg_blocks_16
;
333 GLuint total_scratch
;
337 * surface indices the WM-specific surfaces
339 uint32_t render_target_start
;
344 bool uses_pos_offset
;
346 uint32_t prog_offset_16
;
349 * Mask of which interpolation modes are required by the fragment shader.
350 * Used in hardware setup on gen6+.
352 uint32_t barycentric_interp_modes
;
355 * Map from gl_varying_slot to the position within the FS setup data
356 * payload where the varying's attribute vertex deltas should be delivered.
357 * For varying slots that are not used by the FS, the value is -1.
359 int urb_setup
[VARYING_SLOT_MAX
];
363 * Enum representing the i965-specific vertex results that don't correspond
364 * exactly to any element of gl_varying_slot. The values of this enum are
365 * assigned such that they don't conflict with gl_varying_slot.
369 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
370 BRW_VARYING_SLOT_PAD
,
372 * Technically this is not a varying but just a placeholder that
373 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
374 * builtin variable to be compiled correctly. see compile_sf_prog() for
377 BRW_VARYING_SLOT_PNTC
,
378 BRW_VARYING_SLOT_COUNT
383 * Data structure recording the relationship between the gl_varying_slot enum
384 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
385 * single octaword within the VUE (128 bits).
387 * Note that each BRW register contains 256 bits (2 octawords), so when
388 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
389 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
390 * in a vertex shader), each register corresponds to a single VUE slot, since
391 * it contains data for two separate vertices.
395 * Bitfield representing all varying slots that are (a) stored in this VUE
396 * map, and (b) actually written by the shader. Does not include any of
397 * the additional varying slots defined in brw_varying_slot.
399 GLbitfield64 slots_valid
;
402 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
403 * not stored in a slot (because they are not written, or because
404 * additional processing is applied before storing them in the VUE), the
407 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
410 * Map from VUE slot to gl_varying_slot value. For slots that do not
411 * directly correspond to a gl_varying_slot, the value comes from
414 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
415 * simplifies code that uses the value stored in slot_to_varying to
416 * create a bit mask).
418 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
421 * Total number of VUE slots in use
427 * Convert a VUE slot number into a byte offset within the VUE.
429 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
435 * Convert a vertex output (brw_varying_slot) into a byte offset within the
438 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
441 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
444 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
445 GLbitfield64 slots_valid
);
449 * Bitmask indicating which fragment shader inputs represent varyings (and
450 * hence have to be delivered to the fragment shader by the SF/SBE stage).
452 #define BRW_FS_VARYING_INPUT_MASK \
453 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
454 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
458 * Mapping of VUE map slots to interpolation modes.
460 struct interpolation_mode_map
{
461 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
464 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
466 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
467 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
473 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
475 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
476 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
483 struct brw_sf_prog_data
{
484 GLuint urb_read_length
;
487 /* Each vertex may have upto 12 attributes, 4 components each,
488 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
491 * Actually we use 4 for each, so call it 12 rows.
493 GLuint urb_entry_size
;
498 * We always program SF to start reading at an offset of 1 (2 varying slots)
499 * from the start of the vertex URB entry. This causes it to skip:
500 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
501 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
503 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
506 struct brw_clip_prog_data
{
507 GLuint curb_read_length
; /* user planes? */
509 GLuint urb_read_length
;
513 struct brw_ff_gs_prog_data
{
514 GLuint urb_read_length
;
518 * Gen6 transform feedback: Amount by which the streaming vertex buffer
519 * indices should be incremented each time the GS is invoked.
521 unsigned svbi_postincrement_value
;
525 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
528 struct brw_vec4_prog_data
{
529 struct brw_stage_prog_data base
;
530 struct brw_vue_map vue_map
;
532 GLuint curb_read_length
;
533 GLuint urb_read_length
;
535 GLuint total_scratch
;
537 /* Used for calculating urb partitions. In the VS, this is the size of the
538 * URB entry used for both input and output to the thread. In the GS, this
539 * is the size of the URB entry used for output.
541 GLuint urb_entry_size
;
545 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
548 struct brw_vs_prog_data
{
549 struct brw_vec4_prog_data base
;
551 GLbitfield64 inputs_read
;
557 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
560 struct brw_gs_prog_data
562 struct brw_vec4_prog_data base
;
565 * Size of an output vertex, measured in HWORDS (32 bytes).
567 unsigned output_vertex_size_hwords
;
569 unsigned output_topology
;
572 * Size of the control data (cut bits or StreamID bits), in hwords (32
573 * bytes). 0 if there is no control data.
575 unsigned control_data_header_size_hwords
;
578 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
579 * if the control data is StreamID bits, or
580 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
581 * Ignored if control_data_header_size is 0.
583 unsigned control_data_format
;
585 bool include_primitive_id
;
590 * True if the thread should be dispatched in DUAL_INSTANCE mode, false if
591 * it should be dispatched in DUAL_OBJECT mode.
593 bool dual_instanced_dispatch
;
596 /** Number of texture sampler units */
597 #define BRW_MAX_TEX_UNIT 32
599 /** Max number of render targets in a shader */
600 #define BRW_MAX_DRAW_BUFFERS 8
602 /** Max number of atomic counter buffer objects in a shader */
603 #define BRW_MAX_ABO 16
606 * Max number of binding table entries used for stream output.
608 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
609 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
611 * On Gen6, the size of transform feedback data is limited not by the number
612 * of components but by the number of binding table entries we set aside. We
613 * use one binding table entry for a float, one entry for a vector, and one
614 * entry per matrix column. Since the only way we can communicate our
615 * transform feedback capabilities to the client is via
616 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
617 * worst case, in which all the varyings are floats, so we use up one binding
618 * table entry per component. Therefore we need to set aside at least 64
619 * binding table entries for use by transform feedback.
621 * Note: since we don't currently pack varyings, it is currently impossible
622 * for the client to actually use up all of these binding table entries--if
623 * all of their varyings were floats, they would run out of varying slots and
624 * fail to link. But that's a bug, so it seems prudent to go ahead and
625 * allocate the number of binding table entries we will need once the bug is
628 #define BRW_MAX_SOL_BINDINGS 64
630 /** Maximum number of actual buffers used for stream output */
631 #define BRW_MAX_SOL_BUFFERS 4
633 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
634 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
637 2 /* shader time, pull constants */)
639 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
640 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
643 * Stride in bytes between shader_time entries.
645 * We separate entries by a cacheline to reduce traffic between EUs writing to
648 #define SHADER_TIME_STRIDE 64
655 BRW_BLORP_CONST_COLOR_PROG
,
660 BRW_SF_UNIT
, /* scissor state on gen6 */
673 struct brw_cache_item
{
675 * Effectively part of the key, cache_id identifies what kind of state
676 * buffer is involved, and also which brw->state.dirty.cache flag should
677 * be set when this cache item is chosen.
679 enum brw_cache_id cache_id
;
680 /** 32-bit hash of the key data */
682 GLuint key_size
; /* for variable-sized keys */
689 struct brw_cache_item
*next
;
693 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
);
694 typedef void (*cache_aux_free_func
)(const void *aux
);
697 struct brw_context
*brw
;
699 struct brw_cache_item
**items
;
701 GLuint size
, n_items
;
703 uint32_t next_offset
;
707 * Optional functions used in determining whether the prog_data for a new
708 * cache item matches an existing cache item (in case there's relevant data
709 * outside of the prog_data). If NULL, a plain memcmp is done.
711 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
712 /** Optional functions for freeing other pointers attached to a prog_data. */
713 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
717 /* Considered adding a member to this struct to document which flags
718 * an update might raise so that ordering of the state atoms can be
719 * checked or derived at runtime. Dropped the idea in favor of having
720 * a debug mode where the state is monitored for flags which are
721 * raised that have already been tested against.
723 struct brw_tracked_state
{
724 struct brw_state_flags dirty
;
725 void (*emit
)( struct brw_context
*brw
);
728 enum shader_time_shader_type
{
744 /* Flags for brw->state.cache.
746 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
747 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
748 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
749 #define CACHE_NEW_BLORP_BLIT_PROG (1<<BRW_BLORP_BLIT_PROG)
750 #define CACHE_NEW_BLORP_CONST_COLOR_PROG (1<<BRW_BLORP_CONST_COLOR_PROG)
751 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
752 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
753 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
754 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
755 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
756 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
757 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
758 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
759 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
760 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
761 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
762 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
763 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
765 struct brw_vertex_buffer
{
766 /** Buffer object containing the uploaded vertex data */
769 /** Byte stride between elements in the uploaded array */
773 struct brw_vertex_element
{
774 const struct gl_client_array
*glarray
;
778 /** Offset of the first element within the buffer object */
782 struct brw_query_object
{
783 struct gl_query_object Base
;
785 /** Last query BO associated with this query. */
788 /** Last index in bo with query data for this object. */
792 struct intel_sync_object
{
793 struct gl_sync_object Base
;
795 /** Batch associated with this sync object */
805 struct intel_batchbuffer
{
806 /** Current batchbuffer being queued up. */
808 /** Last BO submitted to the hardware. Used for glFinish(). */
809 drm_intel_bo
*last_bo
;
810 /** BO for post-sync nonzero writes for gen6 workaround. */
811 drm_intel_bo
*workaround_bo
;
812 bool need_workaround_flush
;
814 uint16_t emit
, total
;
815 uint16_t used
, reserved_space
;
818 #define BATCH_SZ (8192*sizeof(uint32_t))
820 uint32_t state_batch_offset
;
821 enum brw_gpu_ring ring
;
822 bool needs_sol_reset
;
830 #define BRW_MAX_XFB_STREAMS 4
832 struct brw_transform_feedback_object
{
833 struct gl_transform_feedback_object base
;
835 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
836 drm_intel_bo
*offset_bo
;
838 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
841 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
842 GLenum primitive_mode
;
845 * Count of primitives generated during this transform feedback operation.
848 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
849 drm_intel_bo
*prim_count_bo
;
850 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
854 * Number of vertices written between last Begin/EndTransformFeedback().
856 * Used to implement DrawTransformFeedback().
858 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
859 bool vertices_written_valid
;
863 * Data shared between each programmable stage in the pipeline (vs, gs, and
866 struct brw_stage_state
868 gl_shader_stage stage
;
869 struct brw_stage_prog_data
*prog_data
;
872 * Optional scratch buffer used to store spilled register values and
873 * variably-indexed GRF arrays.
875 drm_intel_bo
*scratch_bo
;
877 /** Offset in the program cache to the program */
878 uint32_t prog_offset
;
880 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
881 uint32_t state_offset
;
883 uint32_t push_const_offset
; /* Offset in the batchbuffer */
884 int push_const_size
; /* in 256-bit register increments */
886 /* Binding table: pointers to SURFACE_STATE entries. */
887 uint32_t bind_bo_offset
;
888 uint32_t surf_offset
[BRW_MAX_SURFACES
];
890 /** SAMPLER_STATE count and table offset */
891 uint32_t sampler_count
;
892 uint32_t sampler_offset
;
897 * brw_context is derived from gl_context.
901 struct gl_context ctx
; /**< base class, must be first field */
905 void (*update_texture_surface
)(struct gl_context
*ctx
,
907 uint32_t *surf_offset
,
909 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
910 struct gl_renderbuffer
*rb
,
913 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
916 void (*create_raw_surface
)(struct brw_context
*brw
,
920 uint32_t *out_offset
,
922 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
923 uint32_t *out_offset
,
925 unsigned buffer_offset
,
926 unsigned surface_format
,
927 unsigned buffer_size
,
932 /** Upload a SAMPLER_STATE table. */
933 void (*upload_sampler_state_table
)(struct brw_context
*brw
,
934 struct gl_program
*prog
,
935 struct brw_stage_state
*stage_state
);
938 * Send the appropriate state packets to configure depth, stencil, and
939 * HiZ buffers (i965+ only)
941 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
942 struct intel_mipmap_tree
*depth_mt
,
943 uint32_t depth_offset
,
944 uint32_t depthbuffer_format
,
945 uint32_t depth_surface_type
,
946 struct intel_mipmap_tree
*stencil_mt
,
947 bool hiz
, bool separate_stencil
,
948 uint32_t width
, uint32_t height
,
949 uint32_t tile_x
, uint32_t tile_y
);
955 drm_intel_context
*hw_ctx
;
958 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
959 * and would need flushing before being used from another cache domain that
960 * isn't coherent with it (i.e. the sampler).
962 struct set
*render_cache
;
965 * Number of resets observed in the system at context creation.
967 * This is tracked in the context so that we can determine that another
970 uint32_t reset_count
;
972 struct intel_batchbuffer batch
;
977 uint32_t next_offset
;
981 * Set if rendering has occured to the drawable's front buffer.
983 * This is used in the DRI2 case to detect that glFlush should also copy
984 * the contents of the fake front buffer to the real front buffer.
986 bool front_buffer_dirty
;
988 /** Framerate throttling: @{ */
989 drm_intel_bo
*first_post_swapbuffers_batch
;
1000 bool always_flush_batch
;
1001 bool always_flush_cache
;
1002 bool disable_throttling
;
1004 bool disable_derivative_optimization
;
1006 driOptionCache optionCache
;
1009 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1011 GLenum reduced_primitive
;
1014 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1015 * variable is set, this is the flag indicating to do expensive work that
1016 * might lead to a perf_debug() call.
1020 uint32_t max_gtt_map_object_size
;
1031 bool has_separate_stencil
;
1032 bool must_use_separate_stencil
;
1035 bool has_surface_tile_offset
;
1037 bool has_negative_rhw_bug
;
1041 * Some versions of Gen hardware don't do centroid interpolation correctly
1042 * on unlit pixels, causing incorrect values for derivatives near triangle
1043 * edges. Enabling this flag causes the fragment shader to use
1044 * non-centroid interpolation for unlit pixels, at the expense of two extra
1045 * fragment shader instructions.
1047 bool needs_unlit_centroid_workaround
;
1051 struct brw_state_flags dirty
;
1054 struct brw_cache cache
;
1056 /** IDs for meta stencil blit shader programs. */
1057 unsigned meta_stencil_blit_programs
[2];
1059 /* Whether a meta-operation is in progress. */
1060 bool meta_in_progress
;
1062 /* Whether the last depth/stencil packets were both NULL. */
1063 bool no_depth_or_stencil
;
1066 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1067 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1069 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1073 /* Summary of size and varying of active arrays, so we can check
1074 * for changes to this state:
1076 unsigned int min_index
, max_index
;
1078 /* Offset from start of vertex buffer so we can avoid redefining
1079 * the same VB packed over and over again.
1081 unsigned int start_vertex_bias
;
1086 * Index buffer for this draw_prims call.
1088 * Updates are signaled by BRW_NEW_INDICES.
1090 const struct _mesa_index_buffer
*ib
;
1092 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1096 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1097 * avoid re-uploading the IB packet over and over if we're actually
1098 * referencing the same index buffer.
1100 unsigned int start_vertex_offset
;
1103 /* Active vertex program:
1105 const struct gl_vertex_program
*vertex_program
;
1106 const struct gl_geometry_program
*geometry_program
;
1107 const struct gl_fragment_program
*fragment_program
;
1110 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1111 * that we don't have to reemit that state every time we change FBOs.
1116 * Platform specific constants containing the maximum number of threads
1117 * for each pipeline stage.
1123 /* BRW_NEW_URB_ALLOCATIONS:
1126 GLuint vsize
; /* vertex size plus header in urb registers */
1127 GLuint csize
; /* constant buffer size in urb registers */
1128 GLuint sfsize
; /* setup data size in urb registers */
1132 GLuint min_vs_entries
; /* Minimum number of VS entries */
1133 GLuint max_vs_entries
; /* Maximum number of VS entries */
1134 GLuint max_gs_entries
; /* Maximum number of GS entries */
1136 GLuint nr_vs_entries
;
1137 GLuint nr_gs_entries
;
1138 GLuint nr_clip_entries
;
1139 GLuint nr_sf_entries
;
1140 GLuint nr_cs_entries
;
1147 GLuint size
; /* Hardware URB size, in KB. */
1149 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1150 * URB space for the GS.
1152 bool gen6_gs_previously_active
;
1156 /* BRW_NEW_CURBE_OFFSETS:
1159 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1160 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1168 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1169 * for upload to the CURBE.
1171 drm_intel_bo
*curbe_bo
;
1172 /** Offset within curbe_bo of space for current curbe entry */
1173 GLuint curbe_offset
;
1177 * Layout of vertex data exiting the vertex shader.
1179 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1181 struct brw_vue_map vue_map_vs
;
1184 * Layout of vertex data exiting the geometry portion of the pipleine.
1185 * This comes from the geometry shader if one exists, otherwise from the
1188 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1190 struct brw_vue_map vue_map_geom_out
;
1193 struct brw_stage_state base
;
1194 struct brw_vs_prog_data
*prog_data
;
1198 struct brw_stage_state base
;
1199 struct brw_gs_prog_data
*prog_data
;
1202 * True if the 3DSTATE_GS command most recently emitted to the 3D
1203 * pipeline enabled the GS; false otherwise.
1209 struct brw_ff_gs_prog_data
*prog_data
;
1212 /** Offset in the program cache to the CLIP program pre-gen6 */
1213 uint32_t prog_offset
;
1214 uint32_t state_offset
;
1216 uint32_t bind_bo_offset
;
1217 uint32_t surf_offset
[BRW_MAX_GEN6_GS_SURFACES
];
1221 struct brw_clip_prog_data
*prog_data
;
1223 /** Offset in the program cache to the CLIP program pre-gen6 */
1224 uint32_t prog_offset
;
1226 /* Offset in the batch to the CLIP state on pre-gen6. */
1227 uint32_t state_offset
;
1229 /* As of gen6, this is the offset in the batch to the CLIP VP,
1237 struct brw_sf_prog_data
*prog_data
;
1239 /** Offset in the program cache to the CLIP program pre-gen6 */
1240 uint32_t prog_offset
;
1241 uint32_t state_offset
;
1246 struct brw_stage_state base
;
1247 struct brw_wm_prog_data
*prog_data
;
1252 * Buffer object used in place of multisampled null render targets on
1253 * Gen6. See brw_update_null_renderbuffer_surface().
1255 drm_intel_bo
*multisampled_null_render_target_bo
;
1260 uint32_t state_offset
;
1261 uint32_t blend_state_offset
;
1262 uint32_t depth_stencil_state_offset
;
1267 struct brw_query_object
*obj
;
1272 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1273 const int *statistics_registers
;
1275 /** The number of active monitors using OA counters. */
1279 * A buffer object storing OA counter snapshots taken at the start and
1280 * end of each batch (creating "bookends" around the batch).
1282 drm_intel_bo
*bookend_bo
;
1284 /** The number of snapshots written to bookend_bo. */
1285 int bookend_snapshots
;
1288 * An array of monitors whose results haven't yet been assembled based on
1289 * the data in buffer objects.
1291 * These may be active, or have already ended. However, the results
1292 * have not been requested.
1294 struct brw_perf_monitor_object
**unresolved
;
1295 int unresolved_elements
;
1296 int unresolved_array_size
;
1299 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1300 * the counter which MI_REPORT_PERF_COUNT stores there.
1302 const int *oa_snapshot_layout
;
1304 /** Number of 32-bit entries in a hardware counter snapshot. */
1305 int entries_per_oa_snapshot
;
1309 const struct brw_tracked_state
**atoms
;
1311 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1315 enum aub_state_struct_type type
;
1316 } *state_batch_list
;
1317 int state_batch_count
;
1319 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1320 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1322 /* Interpolation modes, one byte per vue slot.
1323 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1325 struct interpolation_mode_map interpolation_mode
;
1327 /* PrimitiveRestart */
1330 bool enable_cut_index
;
1333 /** Computed depth/stencil/hiz state from the current attached
1334 * renderbuffers, valid only during the drawing state upload loop after
1335 * brw_workaround_depthstencil_alignment().
1338 struct intel_mipmap_tree
*depth_mt
;
1339 struct intel_mipmap_tree
*stencil_mt
;
1341 /* Inter-tile (page-aligned) byte offsets. */
1342 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1343 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1344 uint32_t tile_x
, tile_y
;
1347 uint32_t num_instances
;
1352 struct gl_shader_program
**shader_programs
;
1353 struct gl_program
**programs
;
1354 enum shader_time_shader_type
*types
;
1355 uint64_t *cumulative
;
1361 __DRIcontext
*driContext
;
1362 struct intel_screen
*intelScreen
;
1365 /*======================================================================
1368 void brwInitVtbl( struct brw_context
*brw
);
1371 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1373 /*======================================================================
1376 extern const char *const brw_vendor_string
;
1378 extern const char *brw_get_renderer_string(unsigned deviceID
);
1380 extern void intelFinish(struct gl_context
* ctx
);
1383 DRI_CONF_BO_REUSE_DISABLED
,
1384 DRI_CONF_BO_REUSE_ALL
1387 void intel_update_renderbuffers(__DRIcontext
*context
,
1388 __DRIdrawable
*drawable
);
1389 void intel_prepare_render(struct brw_context
*brw
);
1391 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1392 __DRIdrawable
*drawable
);
1394 GLboolean
brwCreateContext(gl_api api
,
1395 const struct gl_config
*mesaVis
,
1396 __DRIcontext
*driContextPriv
,
1397 unsigned major_version
,
1398 unsigned minor_version
,
1402 void *sharedContextPrivate
);
1404 /*======================================================================
1407 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1408 struct intel_mipmap_tree
*mt
,
1409 unsigned level
, unsigned layer
, bool flat
);
1411 void brw_meta_updownsample(struct brw_context
*brw
,
1412 struct intel_mipmap_tree
*src
,
1413 struct intel_mipmap_tree
*dst
);
1415 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1416 GLfloat srcX0
, GLfloat srcY0
,
1417 GLfloat srcX1
, GLfloat srcY1
,
1418 GLfloat dstX0
, GLfloat dstY0
,
1419 GLfloat dstX1
, GLfloat dstY1
);
1421 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1422 struct intel_mipmap_tree
*src
,
1423 struct intel_mipmap_tree
*dst
);
1424 /*======================================================================
1427 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1428 uint32_t depth_level
,
1429 uint32_t depth_layer
,
1430 struct intel_mipmap_tree
*stencil_mt
,
1431 uint32_t *out_tile_mask_x
,
1432 uint32_t *out_tile_mask_y
);
1433 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1434 GLbitfield clear_mask
);
1436 /* brw_object_purgeable.c */
1437 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1439 /*======================================================================
1442 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1443 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1444 void brw_emit_query_begin(struct brw_context
*brw
);
1445 void brw_emit_query_end(struct brw_context
*brw
);
1447 /** gen6_queryobj.c */
1448 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1449 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1450 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1451 void brw_store_register_mem64(struct brw_context
*brw
,
1452 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1454 /** intel_batchbuffer.c */
1455 void brw_load_register_mem(struct brw_context
*brw
,
1458 uint32_t read_domains
, uint32_t write_domain
,
1461 /*======================================================================
1464 void brw_debug_batch(struct brw_context
*brw
);
1465 void brw_annotate_aub(struct brw_context
*brw
);
1467 /*======================================================================
1470 void brw_validate_textures( struct brw_context
*brw
);
1473 /*======================================================================
1476 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1478 int brw_get_scratch_size(int size
);
1479 void brw_get_scratch_bo(struct brw_context
*brw
,
1480 drm_intel_bo
**scratch_bo
, int size
);
1481 void brw_init_shader_time(struct brw_context
*brw
);
1482 int brw_get_shader_time_index(struct brw_context
*brw
,
1483 struct gl_shader_program
*shader_prog
,
1484 struct gl_program
*prog
,
1485 enum shader_time_shader_type type
);
1486 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1487 void brw_destroy_shader_time(struct brw_context
*brw
);
1491 void brw_upload_urb_fence(struct brw_context
*brw
);
1495 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1497 /* brw_fs_reg_allocate.cpp
1499 void brw_fs_alloc_reg_sets(struct intel_screen
*screen
);
1501 /* brw_vec4_reg_allocate.cpp */
1502 void brw_vec4_alloc_reg_set(struct intel_screen
*screen
);
1505 int brw_disassemble_inst(FILE *file
, struct brw_context
*brw
,
1506 struct brw_inst
*inst
, bool is_compacted
);
1509 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1511 /* brw_draw_upload.c */
1512 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1513 const struct gl_client_array
*glarray
);
1514 unsigned brw_get_index_type(GLenum type
);
1515 void brw_prepare_vertices(struct brw_context
*brw
);
1517 /* brw_wm_surface_state.c */
1518 void brw_init_surface_formats(struct brw_context
*brw
);
1519 void brw_create_constant_surface(struct brw_context
*brw
,
1523 uint32_t *out_offset
,
1525 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1527 uint32_t *surf_offset
);
1529 brw_update_sol_surface(struct brw_context
*brw
,
1530 struct gl_buffer_object
*buffer_obj
,
1531 uint32_t *out_offset
, unsigned num_vector_components
,
1532 unsigned stride_dwords
, unsigned offset_dwords
);
1533 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1534 struct gl_shader
*shader
,
1535 struct brw_stage_state
*stage_state
,
1536 struct brw_stage_prog_data
*prog_data
);
1537 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1538 struct gl_shader_program
*prog
,
1539 struct brw_stage_state
*stage_state
,
1540 struct brw_stage_prog_data
*prog_data
);
1542 /* brw_surface_formats.c */
1543 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, mesa_format format
);
1544 bool brw_render_target_supported(struct brw_context
*brw
,
1545 struct gl_renderbuffer
*rb
);
1546 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1548 /* brw_performance_monitor.c */
1549 void brw_init_performance_monitors(struct brw_context
*brw
);
1550 void brw_dump_perf_monitors(struct brw_context
*brw
);
1551 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1552 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1554 /* intel_buffer_objects.c */
1555 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1556 const char *bo_name
);
1557 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1558 const char *bo_name
);
1560 /* intel_extensions.c */
1561 extern void intelInitExtensions(struct gl_context
*ctx
);
1564 extern int intel_translate_shadow_compare_func(GLenum func
);
1565 extern int intel_translate_compare_func(GLenum func
);
1566 extern int intel_translate_stencil_op(GLenum op
);
1567 extern int intel_translate_logic_op(GLenum opcode
);
1569 /* intel_syncobj.c */
1570 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1573 struct gl_transform_feedback_object
*
1574 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1576 brw_delete_transform_feedback(struct gl_context
*ctx
,
1577 struct gl_transform_feedback_object
*obj
);
1579 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1580 struct gl_transform_feedback_object
*obj
);
1582 brw_end_transform_feedback(struct gl_context
*ctx
,
1583 struct gl_transform_feedback_object
*obj
);
1585 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1586 struct gl_transform_feedback_object
*obj
,
1589 /* gen7_sol_state.c */
1591 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1592 struct gl_transform_feedback_object
*obj
);
1594 gen7_end_transform_feedback(struct gl_context
*ctx
,
1595 struct gl_transform_feedback_object
*obj
);
1597 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1598 struct gl_transform_feedback_object
*obj
);
1600 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1601 struct gl_transform_feedback_object
*obj
);
1603 /* brw_blorp_blit.cpp */
1605 brw_blorp_framebuffer(struct brw_context
*brw
,
1606 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1607 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1608 GLbitfield mask
, GLenum filter
);
1611 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1612 struct gl_renderbuffer
*src_rb
,
1613 struct gl_texture_image
*dst_image
,
1615 int srcX0
, int srcY0
,
1616 int dstX0
, int dstY0
,
1617 int width
, int height
);
1619 /* gen6_multisample_state.c */
1621 gen6_determine_sample_mask(struct brw_context
*brw
);
1624 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1625 unsigned num_samples
);
1627 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1629 gen6_get_sample_position(struct gl_context
*ctx
,
1630 struct gl_framebuffer
*fb
,
1634 /* gen8_multisample_state.c */
1635 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1636 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1640 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1641 unsigned gs_size
, unsigned fs_size
);
1644 gen7_emit_urb_state(struct brw_context
*brw
,
1645 unsigned nr_vs_entries
, unsigned vs_size
,
1646 unsigned vs_start
, unsigned nr_gs_entries
,
1647 unsigned gs_size
, unsigned gs_start
);
1652 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1654 /*======================================================================
1655 * Inline conversion functions. These are better-typed than the
1656 * macros used previously:
1658 static inline struct brw_context
*
1659 brw_context( struct gl_context
*ctx
)
1661 return (struct brw_context
*)ctx
;
1664 static inline struct brw_vertex_program
*
1665 brw_vertex_program(struct gl_vertex_program
*p
)
1667 return (struct brw_vertex_program
*) p
;
1670 static inline const struct brw_vertex_program
*
1671 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1673 return (const struct brw_vertex_program
*) p
;
1676 static inline struct brw_geometry_program
*
1677 brw_geometry_program(struct gl_geometry_program
*p
)
1679 return (struct brw_geometry_program
*) p
;
1682 static inline struct brw_fragment_program
*
1683 brw_fragment_program(struct gl_fragment_program
*p
)
1685 return (struct brw_fragment_program
*) p
;
1688 static inline const struct brw_fragment_program
*
1689 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1691 return (const struct brw_fragment_program
*) p
;
1695 * Pre-gen6, the register file of the EUs was shared between threads,
1696 * and each thread used some subset allocated on a 16-register block
1697 * granularity. The unit states wanted these block counts.
1700 brw_register_blocks(int reg_count
)
1702 return ALIGN(reg_count
, 16) / 16 - 1;
1705 static inline uint32_t
1706 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1707 uint32_t prog_offset
)
1709 if (brw
->gen
>= 5) {
1710 /* Using state base address. */
1714 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1718 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1720 return brw
->cache
.bo
->offset64
+ prog_offset
;
1723 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1724 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1725 struct exec_list
*instructions
);
1726 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1728 struct opcode_desc
{
1734 extern const struct opcode_desc opcode_descs
[128];
1735 extern const char * const conditional_modifier
[16];
1738 brw_emit_depthbuffer(struct brw_context
*brw
);
1741 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1742 struct intel_mipmap_tree
*depth_mt
,
1743 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1744 uint32_t depth_surface_type
,
1745 struct intel_mipmap_tree
*stencil_mt
,
1746 bool hiz
, bool separate_stencil
,
1747 uint32_t width
, uint32_t height
,
1748 uint32_t tile_x
, uint32_t tile_y
);
1751 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1752 struct intel_mipmap_tree
*depth_mt
,
1753 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1754 uint32_t depth_surface_type
,
1755 struct intel_mipmap_tree
*stencil_mt
,
1756 bool hiz
, bool separate_stencil
,
1757 uint32_t width
, uint32_t height
,
1758 uint32_t tile_x
, uint32_t tile_y
);
1760 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1761 struct intel_mipmap_tree
*depth_mt
,
1762 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1763 uint32_t depth_surface_type
,
1764 struct intel_mipmap_tree
*stencil_mt
,
1765 bool hiz
, bool separate_stencil
,
1766 uint32_t width
, uint32_t height
,
1767 uint32_t tile_x
, uint32_t tile_y
);
1769 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1770 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1772 extern const GLuint prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1];
1775 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1776 struct brw_vec4_prog_key
*key
,
1777 bool program_uses_clip_distance
);
1780 gen6_upload_push_constants(struct brw_context
*brw
,
1781 const struct gl_program
*prog
,
1782 const struct brw_stage_prog_data
*prog_data
,
1783 struct brw_stage_state
*stage_state
,
1784 enum aub_state_struct_type type
);
1786 /* ================================================================
1787 * From linux kernel i386 header files, copes with odd sizes better
1788 * than COPY_DWORDS would:
1789 * XXX Put this in src/mesa/main/imports.h ???
1791 #if defined(i386) || defined(__i386__)
1792 static inline void * __memcpy(void * to
, const void * from
, size_t n
)
1795 __asm__
__volatile__(
1800 "1:\ttestb $1,%b4\n\t"
1804 : "=&c" (d0
), "=&D" (d1
), "=&S" (d2
)
1805 :"0" (n
/4), "q" (n
),"1" ((long) to
),"2" ((long) from
)
1810 #define __memcpy(a,b,c) memcpy(a,b,c)