2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
47 * URB - uniform resource buffer. A mid-sized buffer which is
48 * partitioned between the fixed function units and used for passing
49 * values (vertices, primitives, constants) between them.
51 * CURBE - constant URB entry. An urb region (entry) used to hold
52 * constant values which the fixed function units can be instructed to
53 * preload into the GRF when spawning a thread.
55 * VUE - vertex URB entry. An urb entry holding a vertex and usually
56 * a vertex header. The header contains control information and
57 * things like primitive type, Begin/end flags and clip codes.
59 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
60 * unit holding rasterization and interpolation parameters.
62 * GRF - general register file. One of several register files
63 * addressable by programmed threads. The inputs (r0, payload, curbe,
64 * urb) of the thread are preloaded to this area before the thread is
65 * spawned. The registers are individually 8 dwords wide and suitable
66 * for general usage. Registers holding thread input values are not
67 * special and may be overwritten.
69 * MRF - message register file. Threads communicate (and terminate)
70 * by sending messages. Message parameters are placed in contiguous
71 * MRF registers. All program output is via these messages. URB
72 * entries are populated by sending a message to the shared URB
73 * function containing the new data, together with a control word,
74 * often an unmodified copy of R0.
76 * R0 - GRF register 0. Typically holds control information used when
77 * sending messages to other threads.
79 * EU or GEN4 EU: The name of the programmable subsystem of the
80 * i965 hardware. Threads are executed by the EU, the registers
81 * described above are part of the EU architecture.
83 * Fixed function units:
85 * CS - Command streamer. Notional first unit, little software
86 * interaction. Holds the URB entries used for constant data, ie the
89 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
90 * this unit is responsible for pulling vertices out of vertex buffers
91 * in vram and injecting them into the processing pipe as VUEs. If
92 * enabled, it first passes them to a VS thread which is a good place
93 * for the driver to implement any active vertex shader.
95 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
96 * enabled, incoming strips etc are passed to GS threads in individual
97 * line/triangle/point units. The GS thread may perform arbitary
98 * computation and emit whatever primtives with whatever vertices it
99 * chooses. This makes GS an excellent place to implement GL's
100 * unfilled polygon modes, though of course it is capable of much
101 * more. Additionally, GS is used to translate away primitives not
102 * handled by latter units, including Quads and Lineloops.
104 * CS - Clipper. Mesa's clipping algorithms are imported to run on
105 * this unit. The fixed function part performs cliptesting against
106 * the 6 fixed clipplanes and makes descisions on whether or not the
107 * incoming primitive needs to be passed to a thread for clipping.
108 * User clip planes are handled via cooperation with the VS thread.
110 * SF - Strips Fans or Setup: Triangles are prepared for
111 * rasterization. Interpolation coefficients are calculated.
112 * Flatshading and two-side lighting usually performed here.
114 * WM - Windower. Interpolation of vertex attributes performed here.
115 * Fragment shader implemented here. SIMD aspects of EU taken full
116 * advantage of, as pixels are processed in blocks of 16.
118 * CC - Color Calculator. No EU threads associated with this unit.
119 * Handles blending and (presumably) depth and stencil testing.
123 #define BRW_MAX_CURBE (32*16)
126 struct brw_instruction
;
127 struct brw_vs_prog_key
;
128 struct brw_vec4_prog_key
;
129 struct brw_wm_prog_key
;
130 struct brw_wm_prog_data
;
134 BRW_STATE_FRAGMENT_PROGRAM
,
135 BRW_STATE_GEOMETRY_PROGRAM
,
136 BRW_STATE_VERTEX_PROGRAM
,
137 BRW_STATE_CURBE_OFFSETS
,
138 BRW_STATE_REDUCED_PRIMITIVE
,
143 BRW_STATE_VS_BINDING_TABLE
,
144 BRW_STATE_GS_BINDING_TABLE
,
145 BRW_STATE_PS_BINDING_TABLE
,
149 BRW_STATE_INDEX_BUFFER
,
150 BRW_STATE_VS_CONSTBUF
,
151 BRW_STATE_PROGRAM_CACHE
,
152 BRW_STATE_STATE_BASE_ADDRESS
,
153 BRW_STATE_VUE_MAP_VS
,
154 BRW_STATE_VUE_MAP_GEOM_OUT
,
155 BRW_STATE_TRANSFORM_FEEDBACK
,
156 BRW_STATE_RASTERIZER_DISCARD
,
158 BRW_STATE_UNIFORM_BUFFER
,
159 BRW_STATE_META_IN_PROGRESS
,
160 BRW_STATE_INTERPOLATION_MAP
,
164 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
165 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
166 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
167 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
168 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
169 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
170 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
171 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
172 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
173 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
174 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
175 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
176 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
177 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
178 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
180 * Used for any batch entry with a relocated pointer that will be used
181 * by any 3D rendering.
183 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
184 /** \see brw.state.depth_region */
185 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
186 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
187 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
188 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
189 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
190 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
191 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
192 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
193 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
194 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
195 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
196 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
198 struct brw_state_flags
{
199 /** State update flags signalled by mesa internals */
202 * State update flags signalled as the result of brw_tracked_state updates
205 /** State update flags signalled by brw_state_cache.c searches */
209 #define AUB_TRACE_TYPE_MASK 0x0000ff00
210 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
211 #define AUB_TRACE_TYPE_BATCH (1 << 8)
212 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
213 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
214 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
215 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
216 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
217 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
218 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
219 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
220 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
221 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
224 * state_struct_type enum values are encoded with the top 16 bits representing
225 * the type to be delivered to the .aub file, and the bottom 16 bits
226 * representing the subtype. This macro performs the encoding.
228 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
230 enum state_struct_type
{
231 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
232 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
233 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
234 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
235 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
236 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
237 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
238 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
239 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
240 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
241 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
242 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
243 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
245 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
246 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
247 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
249 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
250 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
251 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
252 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
253 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
257 * Decode a state_struct_type value to determine the type that should be
258 * stored in the .aub file.
260 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
262 return (ss_type
& 0xFFFF0000) >> 16;
266 * Decode a state_struct_type value to determine the subtype that should be
267 * stored in the .aub file.
269 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
271 return ss_type
& 0xFFFF;
274 /** Subclass of Mesa vertex program */
275 struct brw_vertex_program
{
276 struct gl_vertex_program program
;
281 /** Subclass of Mesa geometry program */
282 struct brw_geometry_program
{
283 struct gl_geometry_program program
;
284 unsigned id
; /**< serial no. to identify geom progs, never re-used */
288 /** Subclass of Mesa fragment program */
289 struct brw_fragment_program
{
290 struct gl_fragment_program program
;
291 GLuint id
; /**< serial no. to identify frag progs, never re-used */
295 struct gl_shader base
;
299 /** Shader IR transformed for native compile, at link time. */
300 struct exec_list
*ir
;
303 /* Data about a particular attempt to compile a program. Note that
304 * there can be many of these, each in a different GL state
305 * corresponding to a different brw_wm_prog_key struct, with different
308 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
311 struct brw_wm_prog_data
{
312 GLuint curb_read_length
;
313 GLuint urb_read_length
;
315 GLuint first_curbe_grf
;
316 GLuint first_curbe_grf_16
;
318 GLuint reg_blocks_16
;
319 GLuint total_scratch
;
321 unsigned binding_table_size
;
323 GLuint nr_params
; /**< number of float params/constants */
324 GLuint nr_pull_params
;
327 uint32_t prog_offset_16
;
330 * Mask of which interpolation modes are required by the fragment shader.
331 * Used in hardware setup on gen6+.
333 uint32_t barycentric_interp_modes
;
335 /* Pointers to tracked values (only valid once
336 * _mesa_load_state_parameters has been called at runtime).
338 * These must be the last fields of the struct (see
339 * brw_wm_prog_data_compare()).
342 const float **pull_param
;
346 * Enum representing the i965-specific vertex results that don't correspond
347 * exactly to any element of gl_varying_slot. The values of this enum are
348 * assigned such that they don't conflict with gl_varying_slot.
352 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
353 BRW_VARYING_SLOT_PAD
,
355 * Technically this is not a varying but just a placeholder that
356 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
357 * builtin variable to be compiled correctly. see compile_sf_prog() for
360 BRW_VARYING_SLOT_PNTC
,
361 BRW_VARYING_SLOT_COUNT
366 * Data structure recording the relationship between the gl_varying_slot enum
367 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
368 * single octaword within the VUE (128 bits).
370 * Note that each BRW register contains 256 bits (2 octawords), so when
371 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
372 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
373 * in a vertex shader), each register corresponds to a single VUE slot, since
374 * it contains data for two separate vertices.
378 * Bitfield representing all varying slots that are (a) stored in this VUE
379 * map, and (b) actually written by the shader. Does not include any of
380 * the additional varying slots defined in brw_varying_slot.
382 GLbitfield64 slots_valid
;
385 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
386 * not stored in a slot (because they are not written, or because
387 * additional processing is applied before storing them in the VUE), the
390 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
393 * Map from VUE slot to gl_varying_slot value. For slots that do not
394 * directly correspond to a gl_varying_slot, the value comes from
397 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
398 * simplifies code that uses the value stored in slot_to_varying to
399 * create a bit mask).
401 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
404 * Total number of VUE slots in use
410 * Convert a VUE slot number into a byte offset within the VUE.
412 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
418 * Convert a vertex output (brw_varying_slot) into a byte offset within the
421 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
424 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
427 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
428 GLbitfield64 slots_valid
, bool userclip_active
);
432 * Mapping of VUE map slots to interpolation modes.
434 struct interpolation_mode_map
{
435 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
438 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
440 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
441 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
447 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
449 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
450 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
457 struct brw_sf_prog_data
{
458 GLuint urb_read_length
;
461 /* Each vertex may have upto 12 attributes, 4 components each,
462 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
465 * Actually we use 4 for each, so call it 12 rows.
467 GLuint urb_entry_size
;
470 struct brw_clip_prog_data
{
471 GLuint curb_read_length
; /* user planes? */
473 GLuint urb_read_length
;
477 struct brw_ff_gs_prog_data
{
478 GLuint urb_read_length
;
482 * Gen6 transform feedback: Amount by which the streaming vertex buffer
483 * indices should be incremented each time the GS is invoked.
485 unsigned svbi_postincrement_value
;
489 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
492 struct brw_vec4_prog_data
{
493 struct brw_vue_map vue_map
;
496 * Register where the thread expects to find input data from the URB
497 * (typically uniforms, followed by per-vertex inputs).
499 unsigned dispatch_grf_start_reg
;
501 GLuint curb_read_length
;
502 GLuint urb_read_length
;
504 GLuint nr_params
; /**< number of float params/constants */
505 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
506 GLuint total_scratch
;
508 /* Used for calculating urb partitions. In the VS, this is the size of the
509 * URB entry used for both input and output to the thread. In the GS, this
510 * is the size of the URB entry used for output.
512 GLuint urb_entry_size
;
514 unsigned binding_table_size
;
516 /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
518 const float **pull_param
;
522 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
525 struct brw_vs_prog_data
{
526 struct brw_vec4_prog_data base
;
528 GLbitfield64 inputs_read
;
534 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
537 struct brw_gs_prog_data
539 struct brw_vec4_prog_data base
;
542 * Size of an output vertex, measured in HWORDS (32 bytes).
544 unsigned output_vertex_size_hwords
;
546 unsigned output_topology
;
549 /** Number of texture sampler units */
550 #define BRW_MAX_TEX_UNIT 16
552 /** Max number of render targets in a shader */
553 #define BRW_MAX_DRAW_BUFFERS 8
556 * Max number of binding table entries used for stream output.
558 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
559 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
561 * On Gen6, the size of transform feedback data is limited not by the number
562 * of components but by the number of binding table entries we set aside. We
563 * use one binding table entry for a float, one entry for a vector, and one
564 * entry per matrix column. Since the only way we can communicate our
565 * transform feedback capabilities to the client is via
566 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
567 * worst case, in which all the varyings are floats, so we use up one binding
568 * table entry per component. Therefore we need to set aside at least 64
569 * binding table entries for use by transform feedback.
571 * Note: since we don't currently pack varyings, it is currently impossible
572 * for the client to actually use up all of these binding table entries--if
573 * all of their varyings were floats, they would run out of varying slots and
574 * fail to link. But that's a bug, so it seems prudent to go ahead and
575 * allocate the number of binding table entries we will need once the bug is
578 #define BRW_MAX_SOL_BINDINGS 64
580 /** Maximum number of actual buffers used for stream output */
581 #define BRW_MAX_SOL_BUFFERS 4
583 #define BRW_MAX_WM_UBOS 12
584 #define BRW_MAX_VS_UBOS 12
587 * Helpers to create Surface Binding Table indexes for draw buffers,
588 * textures, and constant buffers.
590 * Shader threads access surfaces via numeric handles, rather than directly
591 * using pointers. The binding table maps these numeric handles to the
592 * address of the actual buffer.
594 * For example, a shader might ask to sample from "surface 7." In this case,
595 * bind[7] would contain a pointer to a texture.
597 * Currently, our WM binding tables are (arbitrarily) programmed as follows:
599 * +-------------------------------+
600 * | 0 | Draw buffer 0 |
603 * | 7 | Draw buffer 7 |
604 * |-----|-------------------------|
605 * | 8 | WM Pull Constant Buffer |
606 * |-----|-------------------------|
610 * | 24 | Texture 15 |
611 * |-----|-------------------------|
616 * +-------------------------------+
618 * Our VS (and Gen7 GS) binding tables are programmed as follows:
620 * +-----+-------------------------+
621 * | 0 | Pull Constant Buffer |
622 * +-----+-------------------------+
626 * | 16 | Texture 15 |
627 * +-----+-------------------------+
632 * +-------------------------------+
634 * Our (gen6) GS binding tables are programmed as follows:
636 * +-----+-------------------------+
637 * | 0 | SOL Binding 0 |
640 * | 63 | SOL Binding 63 |
641 * +-----+-------------------------+
643 #define SURF_INDEX_DRAW(d) (d)
644 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
645 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
646 #define SURF_INDEX_WM_UBO(u) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)
647 #define SURF_INDEX_WM_SHADER_TIME (SURF_INDEX_WM_UBO(12))
648 /** Maximum size of the binding table. */
649 #define BRW_MAX_WM_SURFACES (SURF_INDEX_WM_SHADER_TIME + 1)
651 #define SURF_INDEX_VEC4_CONST_BUFFER (0)
652 #define SURF_INDEX_VEC4_TEXTURE(t) (SURF_INDEX_VEC4_CONST_BUFFER + 1 + (t))
653 #define SURF_INDEX_VEC4_UBO(u) (SURF_INDEX_VEC4_TEXTURE(BRW_MAX_TEX_UNIT) + u)
654 #define SURF_INDEX_VEC4_SHADER_TIME (SURF_INDEX_VEC4_UBO(12))
655 #define BRW_MAX_VEC4_SURFACES (SURF_INDEX_VEC4_SHADER_TIME + 1)
657 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
658 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
661 * Stride in bytes between shader_time entries.
663 * We separate entries by a cacheline to reduce traffic between EUs writing to
666 #define SHADER_TIME_STRIDE 64
673 BRW_BLORP_CONST_COLOR_PROG
,
678 BRW_SF_UNIT
, /* scissor state on gen6 */
690 struct brw_cache_item
{
692 * Effectively part of the key, cache_id identifies what kind of state
693 * buffer is involved, and also which brw->state.dirty.cache flag should
694 * be set when this cache item is chosen.
696 enum brw_cache_id cache_id
;
697 /** 32-bit hash of the key data */
699 GLuint key_size
; /* for variable-sized keys */
706 struct brw_cache_item
*next
;
710 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
,
711 int aux_size
, const void *key
);
712 typedef void (*cache_aux_free_func
)(const void *aux
);
715 struct brw_context
*brw
;
717 struct brw_cache_item
**items
;
719 GLuint size
, n_items
;
721 uint32_t next_offset
;
725 * Optional functions used in determining whether the prog_data for a new
726 * cache item matches an existing cache item (in case there's relevant data
727 * outside of the prog_data). If NULL, a plain memcmp is done.
729 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
730 /** Optional functions for freeing other pointers attached to a prog_data. */
731 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
735 /* Considered adding a member to this struct to document which flags
736 * an update might raise so that ordering of the state atoms can be
737 * checked or derived at runtime. Dropped the idea in favor of having
738 * a debug mode where the state is monitored for flags which are
739 * raised that have already been tested against.
741 struct brw_tracked_state
{
742 struct brw_state_flags dirty
;
743 void (*emit
)( struct brw_context
*brw
);
746 enum shader_time_shader_type
{
759 /* Flags for brw->state.cache.
761 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
762 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
763 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
764 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
765 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
766 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
767 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
768 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
769 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
770 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
771 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
772 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
773 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
774 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
775 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
777 struct brw_cached_batch_item
{
778 struct header
*header
;
780 struct brw_cached_batch_item
*next
;
785 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
786 * be easier if C allowed arrays of packed elements?
788 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
790 struct brw_vertex_buffer
{
791 /** Buffer object containing the uploaded vertex data */
794 /** Byte stride between elements in the uploaded array */
798 struct brw_vertex_element
{
799 const struct gl_client_array
*glarray
;
803 /** The corresponding Mesa vertex attribute */
804 gl_vert_attrib attrib
;
805 /** Offset of the first element within the buffer object */
809 struct brw_query_object
{
810 struct gl_query_object Base
;
812 /** Last query BO associated with this query. */
815 /** Last index in bo with query data for this object. */
821 * Data shared between brw_context::vs and brw_context::gs
823 struct brw_stage_state
825 drm_intel_bo
*scratch_bo
;
826 drm_intel_bo
*const_bo
;
827 /** Offset in the program cache to the program */
828 uint32_t prog_offset
;
829 uint32_t state_offset
;
831 uint32_t push_const_offset
; /* Offset in the batchbuffer */
832 int push_const_size
; /* in 256-bit register increments */
834 uint32_t bind_bo_offset
;
835 uint32_t surf_offset
[BRW_MAX_VEC4_SURFACES
];
837 /** SAMPLER_STATE count and table offset */
838 uint32_t sampler_count
;
839 uint32_t sampler_offset
;
841 /** Offsets in the batch to sampler default colors (texture border color) */
842 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
847 * brw_context is derived from gl_context.
851 struct gl_context ctx
; /**< base class, must be first field */
855 void (*destroy
) (struct brw_context
* brw
);
856 void (*finish_batch
) (struct brw_context
* brw
);
857 void (*new_batch
) (struct brw_context
* brw
);
859 void (*update_texture_surface
)(struct gl_context
*ctx
,
861 uint32_t *binding_table
,
862 unsigned surf_index
);
863 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
864 struct gl_renderbuffer
*rb
,
867 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
869 void (*create_constant_surface
)(struct brw_context
*brw
,
873 uint32_t *out_offset
,
876 /** Upload a SAMPLER_STATE table. */
877 void (*upload_sampler_state_table
)(struct brw_context
*brw
,
878 struct gl_program
*prog
,
879 uint32_t sampler_count
,
880 uint32_t *sst_offset
,
881 uint32_t *sdc_offset
);
884 * Send the appropriate state packets to configure depth, stencil, and
885 * HiZ buffers (i965+ only)
887 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
888 struct intel_mipmap_tree
*depth_mt
,
889 uint32_t depth_offset
,
890 uint32_t depthbuffer_format
,
891 uint32_t depth_surface_type
,
892 struct intel_mipmap_tree
*stencil_mt
,
893 bool hiz
, bool separate_stencil
,
894 uint32_t width
, uint32_t height
,
895 uint32_t tile_x
, uint32_t tile_y
);
901 drm_intel_context
*hw_ctx
;
903 struct intel_batchbuffer batch
;
910 uint32_t buffer_offset
;
915 * Set if rendering has occured to the drawable's front buffer.
917 * This is used in the DRI2 case to detect that glFlush should also copy
918 * the contents of the fake front buffer to the real front buffer.
920 bool front_buffer_dirty
;
923 * Track whether front-buffer rendering is currently enabled
925 * A separate flag is used to track this in order to support MRT more
928 bool is_front_buffer_rendering
;
931 * Track whether front-buffer is the current read target.
933 * This is closely associated with is_front_buffer_rendering, but may
934 * be set separately. The DRI2 fake front buffer must be referenced
937 bool is_front_buffer_reading
;
939 /** Framerate throttling: @{ */
940 drm_intel_bo
*first_post_swapbuffers_batch
;
951 bool always_flush_batch
;
952 bool always_flush_cache
;
953 bool disable_throttling
;
956 driOptionCache optionCache
;
959 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
961 GLenum reduced_primitive
;
964 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
965 * variable is set, this is the flag indicating to do expensive work that
966 * might lead to a perf_debug() call.
970 uint32_t max_gtt_map_object_size
;
972 bool emit_state_always
;
982 bool has_separate_stencil
;
983 bool must_use_separate_stencil
;
986 bool has_surface_tile_offset
;
988 bool has_negative_rhw_bug
;
989 bool has_aa_line_parameters
;
993 * Some versions of Gen hardware don't do centroid interpolation correctly
994 * on unlit pixels, causing incorrect values for derivatives near triangle
995 * edges. Enabling this flag causes the fragment shader to use
996 * non-centroid interpolation for unlit pixels, at the expense of two extra
997 * fragment shader instructions.
999 bool needs_unlit_centroid_workaround
;
1003 struct brw_state_flags dirty
;
1006 struct brw_cache cache
;
1007 struct brw_cached_batch_item
*cached_batch_items
;
1009 /* Whether a meta-operation is in progress. */
1010 bool meta_in_progress
;
1013 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1014 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1016 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1020 /* Summary of size and varying of active arrays, so we can check
1021 * for changes to this state:
1023 unsigned int min_index
, max_index
;
1025 /* Offset from start of vertex buffer so we can avoid redefining
1026 * the same VB packed over and over again.
1028 unsigned int start_vertex_bias
;
1033 * Index buffer for this draw_prims call.
1035 * Updates are signaled by BRW_NEW_INDICES.
1037 const struct _mesa_index_buffer
*ib
;
1039 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1043 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1044 * avoid re-uploading the IB packet over and over if we're actually
1045 * referencing the same index buffer.
1047 unsigned int start_vertex_offset
;
1050 /* Active vertex program:
1052 const struct gl_vertex_program
*vertex_program
;
1053 const struct gl_geometry_program
*geometry_program
;
1054 const struct gl_fragment_program
*fragment_program
;
1056 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
1057 uint32_t CMD_VF_STATISTICS
;
1058 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
1059 uint32_t CMD_PIPELINE_SELECT
;
1062 * Platform specific constants containing the maximum number of threads
1063 * for each pipeline stage.
1069 /* BRW_NEW_URB_ALLOCATIONS:
1072 GLuint vsize
; /* vertex size plus header in urb registers */
1073 GLuint csize
; /* constant buffer size in urb registers */
1074 GLuint sfsize
; /* setup data size in urb registers */
1078 GLuint max_vs_entries
; /* Maximum number of VS entries */
1079 GLuint max_gs_entries
; /* Maximum number of GS entries */
1081 GLuint nr_vs_entries
;
1082 GLuint nr_gs_entries
;
1083 GLuint nr_clip_entries
;
1084 GLuint nr_sf_entries
;
1085 GLuint nr_cs_entries
;
1092 GLuint size
; /* Hardware URB size, in KB. */
1094 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1095 * URB space for the GS.
1097 bool gen6_gs_previously_active
;
1101 /* BRW_NEW_CURBE_OFFSETS:
1104 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1105 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1112 drm_intel_bo
*curbe_bo
;
1113 /** Offset within curbe_bo of space for current curbe entry */
1114 GLuint curbe_offset
;
1115 /** Offset within curbe_bo of space for next curbe entry */
1116 GLuint curbe_next_offset
;
1119 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
1120 * in brw_curbe.c with the same set of constant data to be uploaded,
1121 * so we'd rather not upload new constants in that case (it can cause
1122 * a pipeline bubble since only up to 4 can be pipelined at a time).
1126 * Allocation for where to calculate the next set of CURBEs.
1127 * It's a hot enough path that malloc/free of that data matters.
1134 * Layout of vertex data exiting the vertex shader.
1136 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1138 struct brw_vue_map vue_map_vs
;
1141 * Layout of vertex data exiting the geometry portion of the pipleine.
1142 * This comes from the geometry shader if one exists, otherwise from the
1145 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1147 struct brw_vue_map vue_map_geom_out
;
1150 * Data structures used by all vec4 program compiles (not specific to any
1151 * particular program).
1154 struct ra_regs
*regs
;
1157 * Array of the ra classes for the unaligned contiguous register
1163 * Mapping for register-allocated objects in *regs to the first
1164 * GRF for that object.
1166 uint8_t *ra_reg_to_grf
;
1170 struct brw_stage_state base
;
1171 struct brw_vs_prog_data
*prog_data
;
1175 struct brw_stage_state base
;
1176 struct brw_gs_prog_data
*prog_data
;
1180 struct brw_ff_gs_prog_data
*prog_data
;
1183 /** Offset in the program cache to the CLIP program pre-gen6 */
1184 uint32_t prog_offset
;
1185 uint32_t state_offset
;
1187 uint32_t bind_bo_offset
;
1188 uint32_t surf_offset
[BRW_MAX_GEN6_GS_SURFACES
];
1192 struct brw_clip_prog_data
*prog_data
;
1194 /** Offset in the program cache to the CLIP program pre-gen6 */
1195 uint32_t prog_offset
;
1197 /* Offset in the batch to the CLIP state on pre-gen6. */
1198 uint32_t state_offset
;
1200 /* As of gen6, this is the offset in the batch to the CLIP VP,
1208 struct brw_sf_prog_data
*prog_data
;
1210 /** Offset in the program cache to the CLIP program pre-gen6 */
1211 uint32_t prog_offset
;
1212 uint32_t state_offset
;
1217 struct brw_wm_prog_data
*prog_data
;
1221 drm_intel_bo
*scratch_bo
;
1224 * Buffer object used in place of multisampled null render targets on
1225 * Gen6. See brw_update_null_renderbuffer_surface().
1227 drm_intel_bo
*multisampled_null_render_target_bo
;
1229 /** Offset in the program cache to the WM program */
1230 uint32_t prog_offset
;
1232 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
1234 drm_intel_bo
*const_bo
; /* pull constant buffer. */
1236 * This is offset in the batch to the push constants on gen6.
1238 * Pre-gen6, push constants live in the CURBE.
1240 uint32_t push_const_offset
;
1242 /** Binding table of pointers to surf_bo entries */
1243 uint32_t bind_bo_offset
;
1244 uint32_t surf_offset
[BRW_MAX_WM_SURFACES
];
1246 /** SAMPLER_STATE count and table offset */
1247 uint32_t sampler_count
;
1248 uint32_t sampler_offset
;
1250 /** Offsets in the batch to sampler default colors (texture border color)
1252 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
1255 struct ra_regs
*regs
;
1257 /** Array of the ra classes for the unaligned contiguous
1258 * register block sizes used.
1263 * Mapping for register-allocated objects in *regs to the first
1264 * GRF for that object.
1266 uint8_t *ra_reg_to_grf
;
1269 * ra class for the aligned pairs we use for PLN, which doesn't
1270 * appear in *classes.
1272 int aligned_pairs_class
;
1278 uint32_t state_offset
;
1279 uint32_t blend_state_offset
;
1280 uint32_t depth_stencil_state_offset
;
1285 struct brw_query_object
*obj
;
1290 const struct brw_tracked_state
**atoms
;
1292 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1296 enum state_struct_type type
;
1297 } *state_batch_list
;
1298 int state_batch_count
;
1300 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1301 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1303 /* Interpolation modes, one byte per vue slot.
1304 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1306 struct interpolation_mode_map interpolation_mode
;
1308 /* PrimitiveRestart */
1311 bool enable_cut_index
;
1314 /** Computed depth/stencil/hiz state from the current attached
1315 * renderbuffers, valid only during the drawing state upload loop after
1316 * brw_workaround_depthstencil_alignment().
1319 struct intel_mipmap_tree
*depth_mt
;
1320 struct intel_mipmap_tree
*stencil_mt
;
1322 /* Inter-tile (page-aligned) byte offsets. */
1323 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1324 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1325 uint32_t tile_x
, tile_y
;
1328 uint32_t num_instances
;
1333 struct gl_shader_program
**shader_programs
;
1334 struct gl_program
**programs
;
1335 enum shader_time_shader_type
*types
;
1336 uint64_t *cumulative
;
1342 __DRIcontext
*driContext
;
1343 struct intel_screen
*intelScreen
;
1344 void (*saved_viewport
)(struct gl_context
*ctx
,
1345 GLint x
, GLint y
, GLsizei width
, GLsizei height
);
1348 /*======================================================================
1351 void brwInitVtbl( struct brw_context
*brw
);
1353 /*======================================================================
1356 bool brwCreateContext(int api
,
1357 const struct gl_config
*mesaVis
,
1358 __DRIcontext
*driContextPriv
,
1359 unsigned major_version
,
1360 unsigned minor_version
,
1363 void *sharedContextPrivate
);
1365 /*======================================================================
1368 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1369 uint32_t depth_level
,
1370 uint32_t depth_layer
,
1371 struct intel_mipmap_tree
*stencil_mt
,
1372 uint32_t *out_tile_mask_x
,
1373 uint32_t *out_tile_mask_y
);
1374 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1375 GLbitfield clear_mask
);
1377 /* brw_object_purgeable.c */
1378 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1380 /*======================================================================
1383 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1384 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1385 void brw_emit_query_begin(struct brw_context
*brw
);
1386 void brw_emit_query_end(struct brw_context
*brw
);
1388 /** gen6_queryobj.c */
1389 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1391 /*======================================================================
1394 void brw_debug_batch(struct brw_context
*brw
);
1395 void brw_annotate_aub(struct brw_context
*brw
);
1397 /*======================================================================
1400 void brw_validate_textures( struct brw_context
*brw
);
1403 /*======================================================================
1406 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1408 int brw_get_scratch_size(int size
);
1409 void brw_get_scratch_bo(struct brw_context
*brw
,
1410 drm_intel_bo
**scratch_bo
, int size
);
1411 void brw_init_shader_time(struct brw_context
*brw
);
1412 int brw_get_shader_time_index(struct brw_context
*brw
,
1413 struct gl_shader_program
*shader_prog
,
1414 struct gl_program
*prog
,
1415 enum shader_time_shader_type type
);
1416 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1417 void brw_destroy_shader_time(struct brw_context
*brw
);
1421 void brw_upload_urb_fence(struct brw_context
*brw
);
1425 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1427 /* brw_fs_reg_allocate.cpp
1429 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1431 /* brw_vec4_reg_allocate.cpp */
1432 void brw_vec4_alloc_reg_set(struct brw_context
*brw
);
1435 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1438 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1440 /* brw_draw_upload.c */
1441 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1442 const struct gl_client_array
*glarray
);
1443 unsigned brw_get_index_type(GLenum type
);
1445 /* brw_wm_surface_state.c */
1446 void brw_init_surface_formats(struct brw_context
*brw
);
1448 brw_update_sol_surface(struct brw_context
*brw
,
1449 struct gl_buffer_object
*buffer_obj
,
1450 uint32_t *out_offset
, unsigned num_vector_components
,
1451 unsigned stride_dwords
, unsigned offset_dwords
);
1452 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1453 struct gl_shader
*shader
,
1454 uint32_t *surf_offsets
);
1456 /* brw_surface_formats.c */
1457 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, gl_format format
);
1458 bool brw_render_target_supported(struct brw_context
*brw
,
1459 struct gl_renderbuffer
*rb
);
1463 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1464 struct gl_transform_feedback_object
*obj
);
1466 brw_end_transform_feedback(struct gl_context
*ctx
,
1467 struct gl_transform_feedback_object
*obj
);
1469 /* gen7_sol_state.c */
1471 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1472 struct gl_transform_feedback_object
*obj
);
1474 gen7_end_transform_feedback(struct gl_context
*ctx
,
1475 struct gl_transform_feedback_object
*obj
);
1477 /* brw_blorp_blit.cpp */
1479 brw_blorp_framebuffer(struct brw_context
*brw
,
1480 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1481 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1482 GLbitfield mask
, GLenum filter
);
1485 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1486 struct gl_renderbuffer
*src_rb
,
1487 struct gl_texture_image
*dst_image
,
1489 int srcX0
, int srcY0
,
1490 int dstX0
, int dstY0
,
1491 int width
, int height
);
1493 /* gen6_multisample_state.c */
1495 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1496 unsigned num_samples
);
1498 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
,
1499 unsigned num_samples
, float coverage
,
1500 bool coverage_invert
, unsigned sample_mask
);
1502 gen6_get_sample_position(struct gl_context
*ctx
,
1503 struct gl_framebuffer
*fb
,
1509 gen7_allocate_push_constants(struct brw_context
*brw
);
1512 gen7_emit_urb_state(struct brw_context
*brw
, GLuint nr_vs_entries
,
1513 GLuint vs_size
, GLuint vs_start
);
1517 /*======================================================================
1518 * Inline conversion functions. These are better-typed than the
1519 * macros used previously:
1521 static INLINE
struct brw_context
*
1522 brw_context( struct gl_context
*ctx
)
1524 return (struct brw_context
*)ctx
;
1527 static INLINE
struct brw_vertex_program
*
1528 brw_vertex_program(struct gl_vertex_program
*p
)
1530 return (struct brw_vertex_program
*) p
;
1533 static INLINE
const struct brw_vertex_program
*
1534 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1536 return (const struct brw_vertex_program
*) p
;
1539 static INLINE
struct brw_fragment_program
*
1540 brw_fragment_program(struct gl_fragment_program
*p
)
1542 return (struct brw_fragment_program
*) p
;
1545 static INLINE
const struct brw_fragment_program
*
1546 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1548 return (const struct brw_fragment_program
*) p
;
1552 * Pre-gen6, the register file of the EUs was shared between threads,
1553 * and each thread used some subset allocated on a 16-register block
1554 * granularity. The unit states wanted these block counts.
1557 brw_register_blocks(int reg_count
)
1559 return ALIGN(reg_count
, 16) / 16 - 1;
1562 static inline uint32_t
1563 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1564 uint32_t prog_offset
)
1566 if (brw
->gen
>= 5) {
1567 /* Using state base address. */
1571 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1575 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1577 return brw
->cache
.bo
->offset
+ prog_offset
;
1580 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1581 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1582 struct exec_list
*instructions
);
1584 struct opcode_desc
{
1590 extern const struct opcode_desc opcode_descs
[128];
1593 brw_emit_depthbuffer(struct brw_context
*brw
);
1596 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1597 struct intel_mipmap_tree
*depth_mt
,
1598 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1599 uint32_t depth_surface_type
,
1600 struct intel_mipmap_tree
*stencil_mt
,
1601 bool hiz
, bool separate_stencil
,
1602 uint32_t width
, uint32_t height
,
1603 uint32_t tile_x
, uint32_t tile_y
);
1606 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1607 struct intel_mipmap_tree
*depth_mt
,
1608 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1609 uint32_t depth_surface_type
,
1610 struct intel_mipmap_tree
*stencil_mt
,
1611 bool hiz
, bool separate_stencil
,
1612 uint32_t width
, uint32_t height
,
1613 uint32_t tile_x
, uint32_t tile_y
);
1615 extern const GLuint prim_to_hw_prim
[GL_POLYGON
+1];
1618 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1619 struct brw_vec4_prog_key
*key
,
1620 bool program_uses_clip_distance
);