2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
47 * URB - uniform resource buffer. A mid-sized buffer which is
48 * partitioned between the fixed function units and used for passing
49 * values (vertices, primitives, constants) between them.
51 * CURBE - constant URB entry. An urb region (entry) used to hold
52 * constant values which the fixed function units can be instructed to
53 * preload into the GRF when spawning a thread.
55 * VUE - vertex URB entry. An urb entry holding a vertex and usually
56 * a vertex header. The header contains control information and
57 * things like primitive type, Begin/end flags and clip codes.
59 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
60 * unit holding rasterization and interpolation parameters.
62 * GRF - general register file. One of several register files
63 * addressable by programmed threads. The inputs (r0, payload, curbe,
64 * urb) of the thread are preloaded to this area before the thread is
65 * spawned. The registers are individually 8 dwords wide and suitable
66 * for general usage. Registers holding thread input values are not
67 * special and may be overwritten.
69 * MRF - message register file. Threads communicate (and terminate)
70 * by sending messages. Message parameters are placed in contiguous
71 * MRF registers. All program output is via these messages. URB
72 * entries are populated by sending a message to the shared URB
73 * function containing the new data, together with a control word,
74 * often an unmodified copy of R0.
76 * R0 - GRF register 0. Typically holds control information used when
77 * sending messages to other threads.
79 * EU or GEN4 EU: The name of the programmable subsystem of the
80 * i965 hardware. Threads are executed by the EU, the registers
81 * described above are part of the EU architecture.
83 * Fixed function units:
85 * CS - Command streamer. Notional first unit, little software
86 * interaction. Holds the URB entries used for constant data, ie the
89 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
90 * this unit is responsible for pulling vertices out of vertex buffers
91 * in vram and injecting them into the processing pipe as VUEs. If
92 * enabled, it first passes them to a VS thread which is a good place
93 * for the driver to implement any active vertex shader.
95 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
96 * enabled, incoming strips etc are passed to GS threads in individual
97 * line/triangle/point units. The GS thread may perform arbitary
98 * computation and emit whatever primtives with whatever vertices it
99 * chooses. This makes GS an excellent place to implement GL's
100 * unfilled polygon modes, though of course it is capable of much
101 * more. Additionally, GS is used to translate away primitives not
102 * handled by latter units, including Quads and Lineloops.
104 * CS - Clipper. Mesa's clipping algorithms are imported to run on
105 * this unit. The fixed function part performs cliptesting against
106 * the 6 fixed clipplanes and makes descisions on whether or not the
107 * incoming primitive needs to be passed to a thread for clipping.
108 * User clip planes are handled via cooperation with the VS thread.
110 * SF - Strips Fans or Setup: Triangles are prepared for
111 * rasterization. Interpolation coefficients are calculated.
112 * Flatshading and two-side lighting usually performed here.
114 * WM - Windower. Interpolation of vertex attributes performed here.
115 * Fragment shader implemented here. SIMD aspects of EU taken full
116 * advantage of, as pixels are processed in blocks of 16.
118 * CC - Color Calculator. No EU threads associated with this unit.
119 * Handles blending and (presumably) depth and stencil testing.
123 #define BRW_MAX_CURBE (32*16)
126 struct brw_instruction
;
127 struct brw_vs_prog_key
;
128 struct brw_wm_prog_key
;
129 struct brw_wm_prog_data
;
133 BRW_STATE_FRAGMENT_PROGRAM
,
134 BRW_STATE_VERTEX_PROGRAM
,
135 BRW_STATE_CURBE_OFFSETS
,
136 BRW_STATE_REDUCED_PRIMITIVE
,
141 BRW_STATE_VS_BINDING_TABLE
,
142 BRW_STATE_GS_BINDING_TABLE
,
143 BRW_STATE_PS_BINDING_TABLE
,
147 BRW_STATE_INDEX_BUFFER
,
148 BRW_STATE_VS_CONSTBUF
,
149 BRW_STATE_PROGRAM_CACHE
,
150 BRW_STATE_STATE_BASE_ADDRESS
,
151 BRW_STATE_SOL_INDICES
,
152 BRW_STATE_VUE_MAP_GEOM_OUT
,
153 BRW_STATE_TRANSFORM_FEEDBACK
,
156 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
157 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
158 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
159 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
160 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
161 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
162 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
163 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
164 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
165 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
166 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
167 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
168 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
169 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
171 * Used for any batch entry with a relocated pointer that will be used
172 * by any 3D rendering.
174 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
175 /** \see brw.state.depth_region */
176 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
177 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
178 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
179 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
180 #define BRW_NEW_SOL_INDICES (1 << BRW_STATE_SOL_INDICES)
181 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
182 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
184 struct brw_state_flags
{
185 /** State update flags signalled by mesa internals */
188 * State update flags signalled as the result of brw_tracked_state updates
191 /** State update flags signalled by brw_state_cache.c searches */
195 #define AUB_TRACE_TYPE_MASK 0x0000ff00
196 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
197 #define AUB_TRACE_TYPE_BATCH (1 << 8)
198 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
199 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
200 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
201 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
202 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
203 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
204 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
205 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
206 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
207 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
210 * state_struct_type enum values are encoded with the top 16 bits representing
211 * the type to be delivered to the .aub file, and the bottom 16 bits
212 * representing the subtype. This macro performs the encoding.
214 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
216 enum state_struct_type
{
217 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
218 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
219 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
220 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
221 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
222 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
223 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
224 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
225 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
226 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
227 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
228 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
229 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
231 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
232 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
233 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
235 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
236 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
237 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
238 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
239 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
243 * Decode a state_struct_type value to determine the type that should be
244 * stored in the .aub file.
246 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
248 return (ss_type
& 0xFFFF0000) >> 16;
252 * Decode a state_struct_type value to determine the subtype that should be
253 * stored in the .aub file.
255 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
257 return ss_type
& 0xFFFF;
260 /** Subclass of Mesa vertex program */
261 struct brw_vertex_program
{
262 struct gl_vertex_program program
;
267 /** Subclass of Mesa fragment program */
268 struct brw_fragment_program
{
269 struct gl_fragment_program program
;
270 GLuint id
; /**< serial no. to identify frag progs, never re-used */
274 struct gl_shader base
;
278 /** Shader IR transformed for native compile, at link time. */
279 struct exec_list
*ir
;
282 /* Data about a particular attempt to compile a program. Note that
283 * there can be many of these, each in a different GL state
284 * corresponding to a different brw_wm_prog_key struct, with different
287 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
290 struct brw_wm_prog_data
{
291 GLuint curb_read_length
;
292 GLuint urb_read_length
;
294 GLuint first_curbe_grf
;
295 GLuint first_curbe_grf_16
;
297 GLuint reg_blocks_16
;
298 GLuint total_scratch
;
300 GLuint nr_params
; /**< number of float params/constants */
301 GLuint nr_pull_params
;
304 uint32_t prog_offset_16
;
307 * Mask of which interpolation modes are required by the fragment shader.
308 * Used in hardware setup on gen6+.
310 uint32_t barycentric_interp_modes
;
312 /* Pointers to tracked values (only valid once
313 * _mesa_load_state_parameters has been called at runtime).
315 * These must be the last fields of the struct (see
316 * brw_wm_prog_data_compare()).
319 const float **pull_param
;
323 * Enum representing the i965-specific vertex results that don't correspond
324 * exactly to any element of gl_varying_slot. The values of this enum are
325 * assigned such that they don't conflict with gl_varying_slot.
329 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
330 BRW_VARYING_SLOT_POS_DUPLICATE
,
331 BRW_VARYING_SLOT_PAD
,
333 * Technically this is not a varying but just a placeholder that
334 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
335 * builtin variable to be compiled correctly. see compile_sf_prog() for
338 BRW_VARYING_SLOT_PNTC
,
339 BRW_VARYING_SLOT_COUNT
344 * Data structure recording the relationship between the gl_varying_slot enum
345 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
346 * single octaword within the VUE (128 bits).
348 * Note that each BRW register contains 256 bits (2 octawords), so when
349 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
350 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
351 * in a vertex shader), each register corresponds to a single VUE slot, since
352 * it contains data for two separate vertices.
356 * Bitfield representing all varying slots that are (a) stored in this VUE
357 * map, and (b) actually written by the shader. Does not include any of
358 * the additional varying slots defined in brw_varying_slot.
360 GLbitfield64 slots_valid
;
363 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
364 * not stored in a slot (because they are not written, or because
365 * additional processing is applied before storing them in the VUE), the
368 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
371 * Map from VUE slot to gl_varying_slot value. For slots that do not
372 * directly correspond to a gl_varying_slot, the value comes from
375 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
376 * simplifies code that uses the value stored in slot_to_varying to
377 * create a bit mask).
379 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
382 * Total number of VUE slots in use
388 * Convert a VUE slot number into a byte offset within the VUE.
390 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
396 * Convert a vertex output (brw_varying_slot) into a byte offset within the
399 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
402 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
405 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
406 GLbitfield64 slots_valid
, bool userclip_active
);
409 struct brw_sf_prog_data
{
410 GLuint urb_read_length
;
413 /* Each vertex may have upto 12 attributes, 4 components each,
414 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
417 * Actually we use 4 for each, so call it 12 rows.
419 GLuint urb_entry_size
;
422 struct brw_clip_prog_data
{
423 GLuint curb_read_length
; /* user planes? */
425 GLuint urb_read_length
;
429 struct brw_gs_prog_data
{
430 GLuint urb_read_length
;
434 * Gen6 transform feedback: Amount by which the streaming vertex buffer
435 * indices should be incremented each time the GS is invoked.
437 unsigned svbi_postincrement_value
;
441 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
444 struct brw_vec4_prog_data
{
445 struct brw_vue_map vue_map
;
447 GLuint curb_read_length
;
448 GLuint urb_read_length
;
450 GLuint nr_params
; /**< number of float params/constants */
451 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
452 GLuint total_scratch
;
454 /* Used for calculating urb partitions. In the VS, this is the size of the
455 * URB entry used for both input and output to the thread. In the GS, this
456 * is the size of the URB entry used for output.
458 GLuint urb_entry_size
;
462 /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
464 const float **pull_param
;
468 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
471 struct brw_vs_prog_data
{
472 struct brw_vec4_prog_data base
;
474 GLbitfield64 inputs_read
;
479 /** Number of texture sampler units */
480 #define BRW_MAX_TEX_UNIT 16
482 /** Max number of render targets in a shader */
483 #define BRW_MAX_DRAW_BUFFERS 8
486 * Max number of binding table entries used for stream output.
488 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
489 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
491 * On Gen6, the size of transform feedback data is limited not by the number
492 * of components but by the number of binding table entries we set aside. We
493 * use one binding table entry for a float, one entry for a vector, and one
494 * entry per matrix column. Since the only way we can communicate our
495 * transform feedback capabilities to the client is via
496 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
497 * worst case, in which all the varyings are floats, so we use up one binding
498 * table entry per component. Therefore we need to set aside at least 64
499 * binding table entries for use by transform feedback.
501 * Note: since we don't currently pack varyings, it is currently impossible
502 * for the client to actually use up all of these binding table entries--if
503 * all of their varyings were floats, they would run out of varying slots and
504 * fail to link. But that's a bug, so it seems prudent to go ahead and
505 * allocate the number of binding table entries we will need once the bug is
508 #define BRW_MAX_SOL_BINDINGS 64
510 /** Maximum number of actual buffers used for stream output */
511 #define BRW_MAX_SOL_BUFFERS 4
513 #define BRW_MAX_WM_UBOS 12
514 #define BRW_MAX_VS_UBOS 12
517 * Helpers to create Surface Binding Table indexes for draw buffers,
518 * textures, and constant buffers.
520 * Shader threads access surfaces via numeric handles, rather than directly
521 * using pointers. The binding table maps these numeric handles to the
522 * address of the actual buffer.
524 * For example, a shader might ask to sample from "surface 7." In this case,
525 * bind[7] would contain a pointer to a texture.
527 * Currently, our WM binding tables are (arbitrarily) programmed as follows:
529 * +-------------------------------+
530 * | 0 | Draw buffer 0 |
533 * | 7 | Draw buffer 7 |
534 * |-----|-------------------------|
535 * | 8 | WM Pull Constant Buffer |
536 * |-----|-------------------------|
540 * | 24 | Texture 15 |
541 * |-----|-------------------------|
546 * +-------------------------------+
548 * Our VS binding tables are programmed as follows:
550 * +-----+-------------------------+
551 * | 0 | VS Pull Constant Buffer |
552 * +-----+-------------------------+
556 * | 16 | Texture 15 |
557 * +-----+-------------------------+
562 * +-------------------------------+
564 * Our (gen6) GS binding tables are programmed as follows:
566 * +-----+-------------------------+
567 * | 0 | SOL Binding 0 |
570 * | 63 | SOL Binding 63 |
571 * +-----+-------------------------+
573 * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be
574 * the identity function or things will break. We do want to keep draw buffers
575 * first so we can use headerless render target writes for RT 0.
577 #define SURF_INDEX_DRAW(d) (d)
578 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
579 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
580 #define SURF_INDEX_WM_UBO(u) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)
581 #define SURF_INDEX_WM_SHADER_TIME (SURF_INDEX_WM_UBO(12))
582 /** Maximum size of the binding table. */
583 #define BRW_MAX_WM_SURFACES (SURF_INDEX_WM_SHADER_TIME + 1)
585 #define SURF_INDEX_VERT_CONST_BUFFER (0)
586 #define SURF_INDEX_VS_TEXTURE(t) (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t))
587 #define SURF_INDEX_VS_UBO(u) (SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT) + u)
588 #define SURF_INDEX_VS_SHADER_TIME (SURF_INDEX_VS_UBO(12))
589 #define BRW_MAX_VS_SURFACES (SURF_INDEX_VS_SHADER_TIME + 1)
591 #define SURF_INDEX_SOL_BINDING(t) ((t))
592 #define BRW_MAX_GS_SURFACES SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
595 * Stride in bytes between shader_time entries.
597 * We separate entries by a cacheline to reduce traffic between EUs writing to
600 #define SHADER_TIME_STRIDE 64
604 BRW_DEPTH_STENCIL_STATE
,
605 BRW_COLOR_CALC_STATE
,
614 BRW_SF_UNIT
, /* scissor state on gen6 */
626 struct brw_cache_item
{
628 * Effectively part of the key, cache_id identifies what kind of state
629 * buffer is involved, and also which brw->state.dirty.cache flag should
630 * be set when this cache item is chosen.
632 enum brw_cache_id cache_id
;
633 /** 32-bit hash of the key data */
635 GLuint key_size
; /* for variable-sized keys */
642 struct brw_cache_item
*next
;
646 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
,
647 int aux_size
, const void *key
);
648 typedef void (*cache_aux_free_func
)(const void *aux
);
651 struct brw_context
*brw
;
653 struct brw_cache_item
**items
;
655 GLuint size
, n_items
;
657 uint32_t next_offset
;
661 * Optional functions used in determining whether the prog_data for a new
662 * cache item matches an existing cache item (in case there's relevant data
663 * outside of the prog_data). If NULL, a plain memcmp is done.
665 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
666 /** Optional functions for freeing other pointers attached to a prog_data. */
667 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
671 /* Considered adding a member to this struct to document which flags
672 * an update might raise so that ordering of the state atoms can be
673 * checked or derived at runtime. Dropped the idea in favor of having
674 * a debug mode where the state is monitored for flags which are
675 * raised that have already been tested against.
677 struct brw_tracked_state
{
678 struct brw_state_flags dirty
;
679 void (*emit
)( struct brw_context
*brw
);
682 enum shader_time_shader_type
{
695 /* Flags for brw->state.cache.
697 #define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE)
698 #define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
699 #define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
700 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
701 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
702 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
703 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
704 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
705 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
706 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
707 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
708 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
709 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
710 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
711 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
712 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
713 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
714 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
716 struct brw_cached_batch_item
{
717 struct header
*header
;
719 struct brw_cached_batch_item
*next
;
724 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
725 * be easier if C allowed arrays of packed elements?
727 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
729 struct brw_vertex_buffer
{
730 /** Buffer object containing the uploaded vertex data */
733 /** Byte stride between elements in the uploaded array */
737 struct brw_vertex_element
{
738 const struct gl_client_array
*glarray
;
742 /** The corresponding Mesa vertex attribute */
743 gl_vert_attrib attrib
;
744 /** Offset of the first element within the buffer object */
748 struct brw_query_object
{
749 struct gl_query_object Base
;
751 /** Last query BO associated with this query. */
754 /** Last index in bo with query data for this object. */
760 * brw_context is derived from intel_context.
764 struct intel_context intel
; /**< base class, must be first field */
765 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
767 bool emit_state_always
;
768 bool has_surface_tile_offset
;
770 bool has_negative_rhw_bug
;
771 bool has_aa_line_parameters
;
776 * Some versions of Gen hardware don't do centroid interpolation correctly
777 * on unlit pixels, causing incorrect values for derivatives near triangle
778 * edges. Enabling this flag causes the fragment shader to use
779 * non-centroid interpolation for unlit pixels, at the expense of two extra
780 * fragment shader instructions.
782 bool needs_unlit_centroid_workaround
;
785 struct brw_state_flags dirty
;
788 struct brw_cache cache
;
789 struct brw_cached_batch_item
*cached_batch_items
;
792 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
793 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
795 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
799 /* Summary of size and varying of active arrays, so we can check
800 * for changes to this state:
802 unsigned int min_index
, max_index
;
804 /* Offset from start of vertex buffer so we can avoid redefining
805 * the same VB packed over and over again.
807 unsigned int start_vertex_bias
;
812 * Index buffer for this draw_prims call.
814 * Updates are signaled by BRW_NEW_INDICES.
816 const struct _mesa_index_buffer
*ib
;
818 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
822 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
823 * avoid re-uploading the IB packet over and over if we're actually
824 * referencing the same index buffer.
826 unsigned int start_vertex_offset
;
829 /* Active vertex program:
831 const struct gl_vertex_program
*vertex_program
;
832 const struct gl_fragment_program
*fragment_program
;
834 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
835 uint32_t CMD_VF_STATISTICS
;
836 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
837 uint32_t CMD_PIPELINE_SELECT
;
840 * Platform specific constants containing the maximum number of threads
841 * for each pipeline stage.
847 /* BRW_NEW_URB_ALLOCATIONS:
850 GLuint vsize
; /* vertex size plus header in urb registers */
851 GLuint csize
; /* constant buffer size in urb registers */
852 GLuint sfsize
; /* setup data size in urb registers */
856 GLuint max_vs_entries
; /* Maximum number of VS entries */
857 GLuint max_gs_entries
; /* Maximum number of GS entries */
859 GLuint nr_vs_entries
;
860 GLuint nr_gs_entries
;
861 GLuint nr_clip_entries
;
862 GLuint nr_sf_entries
;
863 GLuint nr_cs_entries
;
870 GLuint size
; /* Hardware URB size, in KB. */
872 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
873 * URB space for the GS.
875 bool gen6_gs_previously_active
;
879 /* BRW_NEW_CURBE_OFFSETS:
882 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
883 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
890 drm_intel_bo
*curbe_bo
;
891 /** Offset within curbe_bo of space for current curbe entry */
893 /** Offset within curbe_bo of space for next curbe entry */
894 GLuint curbe_next_offset
;
897 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
898 * in brw_curbe.c with the same set of constant data to be uploaded,
899 * so we'd rather not upload new constants in that case (it can cause
900 * a pipeline bubble since only up to 4 can be pipelined at a time).
904 * Allocation for where to calculate the next set of CURBEs.
905 * It's a hot enough path that malloc/free of that data matters.
911 /** SAMPLER_STATE count and offset */
918 * Layout of vertex data exiting the geometry portion of the pipleine.
919 * This comes from the geometry shader if one exists, otherwise from the
922 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
924 struct brw_vue_map vue_map_geom_out
;
927 struct brw_vs_prog_data
*prog_data
;
929 drm_intel_bo
*scratch_bo
;
930 drm_intel_bo
*const_bo
;
931 /** Offset in the program cache to the VS program */
932 uint32_t prog_offset
;
933 uint32_t state_offset
;
935 uint32_t push_const_offset
; /* Offset in the batchbuffer */
936 int push_const_size
; /* in 256-bit register increments */
938 /** @{ register allocator */
940 struct ra_regs
*regs
;
943 * Array of the ra classes for the unaligned contiguous register
949 * Mapping for register-allocated objects in *regs to the first
950 * GRF for that object.
952 uint8_t *ra_reg_to_grf
;
955 uint32_t bind_bo_offset
;
956 uint32_t surf_offset
[BRW_MAX_VS_SURFACES
];
960 struct brw_gs_prog_data
*prog_data
;
963 /** Offset in the program cache to the CLIP program pre-gen6 */
964 uint32_t prog_offset
;
965 uint32_t state_offset
;
967 uint32_t bind_bo_offset
;
968 uint32_t surf_offset
[BRW_MAX_GS_SURFACES
];
972 struct brw_clip_prog_data
*prog_data
;
974 /** Offset in the program cache to the CLIP program pre-gen6 */
975 uint32_t prog_offset
;
977 /* Offset in the batch to the CLIP state on pre-gen6. */
978 uint32_t state_offset
;
980 /* As of gen6, this is the offset in the batch to the CLIP VP,
988 struct brw_sf_prog_data
*prog_data
;
990 /** Offset in the program cache to the CLIP program pre-gen6 */
991 uint32_t prog_offset
;
992 uint32_t state_offset
;
997 struct brw_wm_prog_data
*prog_data
;
999 /** offsets in the batch to sampler default colors (texture border color)
1001 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
1005 drm_intel_bo
*scratch_bo
;
1008 * Buffer object used in place of multisampled null render targets on
1009 * Gen6. See brw_update_null_renderbuffer_surface().
1011 drm_intel_bo
*multisampled_null_render_target_bo
;
1013 /** Offset in the program cache to the WM program */
1014 uint32_t prog_offset
;
1016 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
1018 drm_intel_bo
*const_bo
; /* pull constant buffer. */
1020 * This is offset in the batch to the push constants on gen6.
1022 * Pre-gen6, push constants live in the CURBE.
1024 uint32_t push_const_offset
;
1026 /** Binding table of pointers to surf_bo entries */
1027 uint32_t bind_bo_offset
;
1028 uint32_t surf_offset
[BRW_MAX_WM_SURFACES
];
1031 struct ra_regs
*regs
;
1033 /** Array of the ra classes for the unaligned contiguous
1034 * register block sizes used.
1039 * Mapping for register-allocated objects in *regs to the first
1040 * GRF for that object.
1042 uint8_t *ra_reg_to_grf
;
1045 * ra class for the aligned pairs we use for PLN, which doesn't
1046 * appear in *classes.
1048 int aligned_pairs_class
;
1054 uint32_t state_offset
;
1055 uint32_t blend_state_offset
;
1056 uint32_t depth_stencil_state_offset
;
1061 struct brw_query_object
*obj
;
1066 const struct brw_tracked_state
**atoms
;
1068 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1072 enum state_struct_type type
;
1073 } *state_batch_list
;
1074 int state_batch_count
;
1076 struct brw_sol_state
{
1077 uint32_t svbi_0_starting_index
;
1078 uint32_t svbi_0_max_index
;
1079 uint32_t offset_0_batch_start
;
1080 uint32_t primitives_generated
;
1081 uint32_t primitives_written
;
1082 bool counting_primitives_generated
;
1083 bool counting_primitives_written
;
1086 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1087 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1089 /* PrimitiveRestart */
1092 bool enable_cut_index
;
1095 /** Computed depth/stencil/hiz state from the current attached
1096 * renderbuffers, valid only during the drawing state upload loop after
1097 * brw_workaround_depthstencil_alignment().
1100 struct intel_mipmap_tree
*depth_mt
;
1101 struct intel_mipmap_tree
*stencil_mt
;
1103 /* Inter-tile (page-aligned) byte offsets. */
1104 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1105 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1106 uint32_t tile_x
, tile_y
;
1109 uint32_t num_instances
;
1114 struct gl_shader_program
**shader_programs
;
1115 struct gl_program
**programs
;
1116 enum shader_time_shader_type
*types
;
1117 uint64_t *cumulative
;
1124 /*======================================================================
1127 void brwInitVtbl( struct brw_context
*brw
);
1129 /*======================================================================
1132 bool brwCreateContext(int api
,
1133 const struct gl_config
*mesaVis
,
1134 __DRIcontext
*driContextPriv
,
1135 unsigned major_version
,
1136 unsigned minor_version
,
1139 void *sharedContextPrivate
);
1141 /*======================================================================
1144 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1145 uint32_t depth_level
,
1146 uint32_t depth_layer
,
1147 struct intel_mipmap_tree
*stencil_mt
,
1148 uint32_t *out_tile_mask_x
,
1149 uint32_t *out_tile_mask_y
);
1150 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1151 GLbitfield clear_mask
);
1153 /*======================================================================
1156 void brw_init_queryobj_functions(struct dd_function_table
*functions
);
1157 void brw_emit_query_begin(struct brw_context
*brw
);
1158 void brw_emit_query_end(struct brw_context
*brw
);
1160 /*======================================================================
1163 void brw_debug_batch(struct intel_context
*intel
);
1164 void brw_annotate_aub(struct intel_context
*intel
);
1166 /*======================================================================
1169 void brw_validate_textures( struct brw_context
*brw
);
1172 /*======================================================================
1175 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1177 int brw_get_scratch_size(int size
);
1178 void brw_get_scratch_bo(struct intel_context
*intel
,
1179 drm_intel_bo
**scratch_bo
, int size
);
1180 void brw_init_shader_time(struct brw_context
*brw
);
1181 int brw_get_shader_time_index(struct brw_context
*brw
,
1182 struct gl_shader_program
*shader_prog
,
1183 struct gl_program
*prog
,
1184 enum shader_time_shader_type type
);
1185 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1186 void brw_destroy_shader_time(struct brw_context
*brw
);
1190 void brw_upload_urb_fence(struct brw_context
*brw
);
1194 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1196 /* brw_fs_reg_allocate.cpp
1198 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1201 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1204 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1206 /* brw_wm_surface_state.c */
1207 void brw_init_surface_formats(struct brw_context
*brw
);
1209 brw_update_sol_surface(struct brw_context
*brw
,
1210 struct gl_buffer_object
*buffer_obj
,
1211 uint32_t *out_offset
, unsigned num_vector_components
,
1212 unsigned stride_dwords
, unsigned offset_dwords
);
1213 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1214 struct gl_shader
*shader
,
1215 uint32_t *surf_offsets
);
1219 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1220 struct gl_transform_feedback_object
*obj
);
1222 brw_end_transform_feedback(struct gl_context
*ctx
,
1223 struct gl_transform_feedback_object
*obj
);
1225 /* gen7_sol_state.c */
1227 gen7_end_transform_feedback(struct gl_context
*ctx
,
1228 struct gl_transform_feedback_object
*obj
);
1230 /* brw_blorp_blit.cpp */
1232 brw_blorp_framebuffer(struct intel_context
*intel
,
1233 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1234 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1235 GLbitfield mask
, GLenum filter
);
1238 brw_blorp_copytexsubimage(struct intel_context
*intel
,
1239 struct gl_renderbuffer
*src_rb
,
1240 struct gl_texture_image
*dst_image
,
1241 int srcX0
, int srcY0
,
1242 int dstX0
, int dstY0
,
1243 int width
, int height
);
1245 /* gen6_multisample_state.c */
1247 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1248 unsigned num_samples
);
1250 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
,
1251 unsigned num_samples
, float coverage
,
1252 bool coverage_invert
, unsigned sample_mask
);
1254 gen6_get_sample_position(struct gl_context
*ctx
,
1255 struct gl_framebuffer
*fb
,
1261 gen7_allocate_push_constants(struct brw_context
*brw
);
1264 gen7_emit_urb_state(struct brw_context
*brw
, GLuint nr_vs_entries
,
1265 GLuint vs_size
, GLuint vs_start
);
1269 /*======================================================================
1270 * Inline conversion functions. These are better-typed than the
1271 * macros used previously:
1273 static INLINE
struct brw_context
*
1274 brw_context( struct gl_context
*ctx
)
1276 return (struct brw_context
*)ctx
;
1279 static INLINE
struct brw_vertex_program
*
1280 brw_vertex_program(struct gl_vertex_program
*p
)
1282 return (struct brw_vertex_program
*) p
;
1285 static INLINE
const struct brw_vertex_program
*
1286 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1288 return (const struct brw_vertex_program
*) p
;
1291 static INLINE
struct brw_fragment_program
*
1292 brw_fragment_program(struct gl_fragment_program
*p
)
1294 return (struct brw_fragment_program
*) p
;
1297 static INLINE
const struct brw_fragment_program
*
1298 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1300 return (const struct brw_fragment_program
*) p
;
1304 * Pre-gen6, the register file of the EUs was shared between threads,
1305 * and each thread used some subset allocated on a 16-register block
1306 * granularity. The unit states wanted these block counts.
1309 brw_register_blocks(int reg_count
)
1311 return ALIGN(reg_count
, 16) / 16 - 1;
1314 static inline uint32_t
1315 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1316 uint32_t prog_offset
)
1318 struct intel_context
*intel
= &brw
->intel
;
1320 if (intel
->gen
>= 5) {
1321 /* Using state base address. */
1325 drm_intel_bo_emit_reloc(intel
->batch
.bo
,
1329 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1331 return brw
->cache
.bo
->offset
+ prog_offset
;
1334 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1335 bool brw_lower_texture_gradients(struct exec_list
*instructions
);
1337 struct opcode_desc
{
1343 extern const struct opcode_desc opcode_descs
[128];
1346 brw_emit_depthbuffer(struct brw_context
*brw
);
1349 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1350 struct intel_mipmap_tree
*depth_mt
,
1351 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1352 uint32_t depth_surface_type
,
1353 struct intel_mipmap_tree
*stencil_mt
,
1354 bool hiz
, bool separate_stencil
,
1355 uint32_t width
, uint32_t height
,
1356 uint32_t tile_x
, uint32_t tile_y
);
1359 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1360 struct intel_mipmap_tree
*depth_mt
,
1361 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1362 uint32_t depth_surface_type
,
1363 struct intel_mipmap_tree
*stencil_mt
,
1364 bool hiz
, bool separate_stencil
,
1365 uint32_t width
, uint32_t height
,
1366 uint32_t tile_x
, uint32_t tile_y
);