2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "main/errors.h"
41 #include "brw_structs.h"
42 #include "brw_pipe_control.h"
43 #include "compiler/brw_compiler.h"
46 #include "blorp/blorp.h"
48 #include <brw_bufmgr.h>
50 #include "common/gen_debug.h"
51 #include "intel_screen.h"
52 #include "intel_tex_obj.h"
59 * URB - uniform resource buffer. A mid-sized buffer which is
60 * partitioned between the fixed function units and used for passing
61 * values (vertices, primitives, constants) between them.
63 * CURBE - constant URB entry. An urb region (entry) used to hold
64 * constant values which the fixed function units can be instructed to
65 * preload into the GRF when spawning a thread.
67 * VUE - vertex URB entry. An urb entry holding a vertex and usually
68 * a vertex header. The header contains control information and
69 * things like primitive type, Begin/end flags and clip codes.
71 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
72 * unit holding rasterization and interpolation parameters.
74 * GRF - general register file. One of several register files
75 * addressable by programmed threads. The inputs (r0, payload, curbe,
76 * urb) of the thread are preloaded to this area before the thread is
77 * spawned. The registers are individually 8 dwords wide and suitable
78 * for general usage. Registers holding thread input values are not
79 * special and may be overwritten.
81 * MRF - message register file. Threads communicate (and terminate)
82 * by sending messages. Message parameters are placed in contiguous
83 * MRF registers. All program output is via these messages. URB
84 * entries are populated by sending a message to the shared URB
85 * function containing the new data, together with a control word,
86 * often an unmodified copy of R0.
88 * R0 - GRF register 0. Typically holds control information used when
89 * sending messages to other threads.
91 * EU or GEN4 EU: The name of the programmable subsystem of the
92 * i965 hardware. Threads are executed by the EU, the registers
93 * described above are part of the EU architecture.
95 * Fixed function units:
97 * CS - Command streamer. Notional first unit, little software
98 * interaction. Holds the URB entries used for constant data, ie the
101 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
102 * this unit is responsible for pulling vertices out of vertex buffers
103 * in vram and injecting them into the processing pipe as VUEs. If
104 * enabled, it first passes them to a VS thread which is a good place
105 * for the driver to implement any active vertex shader.
107 * HS - Hull Shader (Tessellation Control Shader)
109 * TE - Tessellation Engine (Tessellation Primitive Generation)
111 * DS - Domain Shader (Tessellation Evaluation Shader)
113 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
114 * enabled, incoming strips etc are passed to GS threads in individual
115 * line/triangle/point units. The GS thread may perform arbitary
116 * computation and emit whatever primtives with whatever vertices it
117 * chooses. This makes GS an excellent place to implement GL's
118 * unfilled polygon modes, though of course it is capable of much
119 * more. Additionally, GS is used to translate away primitives not
120 * handled by latter units, including Quads and Lineloops.
122 * CS - Clipper. Mesa's clipping algorithms are imported to run on
123 * this unit. The fixed function part performs cliptesting against
124 * the 6 fixed clipplanes and makes descisions on whether or not the
125 * incoming primitive needs to be passed to a thread for clipping.
126 * User clip planes are handled via cooperation with the VS thread.
128 * SF - Strips Fans or Setup: Triangles are prepared for
129 * rasterization. Interpolation coefficients are calculated.
130 * Flatshading and two-side lighting usually performed here.
132 * WM - Windower. Interpolation of vertex attributes performed here.
133 * Fragment shader implemented here. SIMD aspects of EU taken full
134 * advantage of, as pixels are processed in blocks of 16.
136 * CC - Color Calculator. No EU threads associated with this unit.
137 * Handles blending and (presumably) depth and stencil testing.
142 struct brw_vs_prog_key
;
143 struct brw_vue_prog_key
;
144 struct brw_wm_prog_key
;
145 struct brw_wm_prog_data
;
146 struct brw_cs_prog_key
;
147 struct brw_cs_prog_data
;
151 BRW_COMPUTE_PIPELINE
,
158 BRW_CACHE_BLORP_PROG
,
161 BRW_CACHE_FF_GS_PROG
,
172 /* brw_cache_ids must come first - see brw_program_cache.c */
173 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
174 BRW_STATE_FRAGMENT_PROGRAM
,
175 BRW_STATE_GEOMETRY_PROGRAM
,
176 BRW_STATE_TESS_PROGRAMS
,
177 BRW_STATE_VERTEX_PROGRAM
,
178 BRW_STATE_REDUCED_PRIMITIVE
,
179 BRW_STATE_PATCH_PRIMITIVE
,
184 BRW_STATE_BINDING_TABLE_POINTERS
,
187 BRW_STATE_DEFAULT_TESS_LEVELS
,
189 BRW_STATE_INDEX_BUFFER
,
190 BRW_STATE_VS_CONSTBUF
,
191 BRW_STATE_TCS_CONSTBUF
,
192 BRW_STATE_TES_CONSTBUF
,
193 BRW_STATE_GS_CONSTBUF
,
194 BRW_STATE_PROGRAM_CACHE
,
195 BRW_STATE_STATE_BASE_ADDRESS
,
196 BRW_STATE_VUE_MAP_GEOM_OUT
,
197 BRW_STATE_TRANSFORM_FEEDBACK
,
198 BRW_STATE_RASTERIZER_DISCARD
,
200 BRW_STATE_UNIFORM_BUFFER
,
201 BRW_STATE_IMAGE_UNITS
,
202 BRW_STATE_META_IN_PROGRESS
,
203 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
204 BRW_STATE_NUM_SAMPLES
,
205 BRW_STATE_TEXTURE_BUFFER
,
206 BRW_STATE_GEN4_UNIT_STATE
,
210 BRW_STATE_SAMPLER_STATE_TABLE
,
211 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
212 BRW_STATE_COMPUTE_PROGRAM
,
213 BRW_STATE_CS_WORK_GROUPS
,
217 BRW_STATE_VIEWPORT_COUNT
,
218 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
225 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
227 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
228 * When the currently bound shader program differs from the previous draw
229 * call, these will be flagged. They cover brw->{stage}_program and
230 * ctx->{Stage}Program->_Current.
232 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
233 * driver perspective. Even if the same shader is bound at the API level,
234 * we may need to switch between multiple versions of that shader to handle
235 * changes in non-orthagonal state.
237 * Additionally, multiple shader programs may have identical vertex shaders
238 * (for example), or compile down to the same code in the backend. We combine
239 * those into a single program cache entry.
241 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
242 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
244 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
245 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
246 * use the normal state upload paths), but the cache is still used. To avoid
247 * polluting the brw_program_cache code with special cases, we retain the
248 * dirty bit for now. It should eventually be removed.
250 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
251 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
252 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
253 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
254 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
255 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
256 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
257 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
258 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
259 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
260 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
261 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
262 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
263 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
264 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
265 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
266 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
267 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
268 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
269 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
270 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
271 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
272 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
273 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
275 * Used for any batch entry with a relocated pointer that will be used
276 * by any 3D rendering.
278 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
279 /** \see brw.state.depth_region */
280 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
281 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
282 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
283 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
284 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
285 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
286 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
287 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
288 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
289 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
290 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
291 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
292 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
293 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
294 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
295 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
296 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
297 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
298 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
299 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
300 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
301 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
302 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
303 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
304 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
305 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
306 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
307 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
308 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
309 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
310 #define BRW_NEW_DRAW_CALL (1ull << BRW_STATE_DRAW_CALL)
311 #define BRW_NEW_AUX_STATE (1ull << BRW_STATE_AUX)
313 struct brw_state_flags
{
314 /** State update flags signalled by mesa internals */
317 * State update flags signalled as the result of brw_tracked_state updates
323 /** Subclass of Mesa program */
325 struct gl_program program
;
332 struct brw_ff_gs_prog_data
{
333 GLuint urb_read_length
;
337 * Gen6 transform feedback: Amount by which the streaming vertex buffer
338 * indices should be incremented each time the GS is invoked.
340 unsigned svbi_postincrement_value
;
343 /** Number of texture sampler units */
344 #define BRW_MAX_TEX_UNIT 32
346 /** Max number of UBOs in a shader */
347 #define BRW_MAX_UBO 14
349 /** Max number of SSBOs in a shader */
350 #define BRW_MAX_SSBO 12
352 /** Max number of atomic counter buffer objects in a shader */
353 #define BRW_MAX_ABO 16
355 /** Max number of image uniforms in a shader */
356 #define BRW_MAX_IMAGES 32
358 /** Maximum number of actual buffers used for stream output */
359 #define BRW_MAX_SOL_BUFFERS 4
361 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
362 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
367 2 + /* shader time, pull constants */ \
368 1 /* cs num work groups */)
371 struct brw_context
*brw
;
373 struct brw_cache_item
**items
;
376 GLuint size
, n_items
;
378 uint32_t next_offset
;
381 #define perf_debug(...) do { \
382 static GLuint msg_id = 0; \
383 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \
384 dbg_printf(__VA_ARGS__); \
385 if (brw->perf_debug) \
386 _mesa_gl_debug(&brw->ctx, &msg_id, \
387 MESA_DEBUG_SOURCE_API, \
388 MESA_DEBUG_TYPE_PERFORMANCE, \
389 MESA_DEBUG_SEVERITY_MEDIUM, \
393 #define WARN_ONCE(cond, fmt...) do { \
394 if (unlikely(cond)) { \
395 static bool _warned = false; \
396 static GLuint msg_id = 0; \
398 fprintf(stderr, "WARNING: "); \
399 fprintf(stderr, fmt); \
402 _mesa_gl_debug(ctx, &msg_id, \
403 MESA_DEBUG_SOURCE_API, \
404 MESA_DEBUG_TYPE_OTHER, \
405 MESA_DEBUG_SEVERITY_HIGH, fmt); \
410 /* Considered adding a member to this struct to document which flags
411 * an update might raise so that ordering of the state atoms can be
412 * checked or derived at runtime. Dropped the idea in favor of having
413 * a debug mode where the state is monitored for flags which are
414 * raised that have already been tested against.
416 struct brw_tracked_state
{
417 struct brw_state_flags dirty
;
418 void (*emit
)( struct brw_context
*brw
);
421 enum shader_time_shader_type
{
432 struct brw_vertex_buffer
{
433 /** Buffer object containing the uploaded vertex data */
437 /** Byte stride between elements in the uploaded array */
441 struct brw_vertex_element
{
442 const struct gl_vertex_array
*glarray
;
446 /** Offset of the first element within the buffer object */
450 struct brw_query_object
{
451 struct gl_query_object Base
;
453 /** Last query BO associated with this query. */
456 /** Last index in bo with query data for this object. */
459 /** True if we know the batch has been flushed since we ended the query. */
469 struct brw_reloc_list
{
470 struct drm_i915_gem_relocation_entry
*relocs
;
472 int reloc_array_size
;
475 struct brw_growing_bo
{
478 struct brw_bo
*partial_bo
;
479 uint32_t *partial_bo_map
;
480 unsigned partial_bytes
;
483 struct intel_batchbuffer
{
484 /** Current batchbuffer being queued up. */
485 struct brw_growing_bo batch
;
486 /** Current statebuffer being queued up. */
487 struct brw_growing_bo state
;
489 /** Last batchbuffer submitted to the hardware. Used for glFinish(). */
490 struct brw_bo
*last_bo
;
493 uint16_t emit
, total
;
498 enum brw_gpu_ring ring
;
499 bool use_shadow_copy
;
500 bool use_batch_first
;
501 bool needs_sol_reset
;
502 bool state_base_address_emitted
;
505 struct brw_reloc_list batch_relocs
;
506 struct brw_reloc_list state_relocs
;
507 unsigned int valid_reloc_flags
;
509 /** The validation list */
510 struct drm_i915_gem_exec_object2
*validation_list
;
511 struct brw_bo
**exec_bos
;
515 /** The amount of aperture space (in bytes) used by all exec_bos */
520 int batch_reloc_count
;
521 int state_reloc_count
;
525 /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */
526 struct hash_table
*state_batch_sizes
;
529 #define BRW_MAX_XFB_STREAMS 4
531 struct brw_transform_feedback_counter
{
533 * Index of the first entry of this counter within the primitive count BO.
534 * An entry is considered to be an N-tuple of 64bit values, where N is the
535 * number of vertex streams supported by the platform.
540 * Index one past the last entry of this counter within the primitive
546 * Primitive count values accumulated while this counter was active,
547 * excluding any entries buffered between \c bo_start and \c bo_end, which
548 * haven't been accounted for yet.
550 uint64_t accum
[BRW_MAX_XFB_STREAMS
];
554 brw_reset_transform_feedback_counter(
555 struct brw_transform_feedback_counter
*counter
)
557 counter
->bo_start
= counter
->bo_end
;
558 memset(&counter
->accum
, 0, sizeof(counter
->accum
));
561 struct brw_transform_feedback_object
{
562 struct gl_transform_feedback_object base
;
564 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
565 struct brw_bo
*offset_bo
;
567 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
570 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
571 GLenum primitive_mode
;
574 * The maximum number of vertices that we can write without overflowing
575 * any of the buffers currently being used for transform feedback.
579 struct brw_bo
*prim_count_bo
;
582 * Count of primitives generated during this transform feedback operation.
584 struct brw_transform_feedback_counter counter
;
587 * Count of primitives generated during the previous transform feedback
588 * operation. Used to implement DrawTransformFeedback().
590 struct brw_transform_feedback_counter previous_counter
;
593 * Number of vertices written between last Begin/EndTransformFeedback().
595 * Used to implement DrawTransformFeedback().
597 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
598 bool vertices_written_valid
;
602 * Data shared between each programmable stage in the pipeline (vs, gs, and
605 struct brw_stage_state
607 gl_shader_stage stage
;
608 struct brw_stage_prog_data
*prog_data
;
611 * Optional scratch buffer used to store spilled register values and
612 * variably-indexed GRF arrays.
614 * The contents of this buffer are short-lived so the same memory can be
615 * re-used at will for multiple shader programs (executed by the same fixed
616 * function). However reusing a scratch BO for which shader invocations
617 * are still in flight with a per-thread scratch slot size other than the
618 * original can cause threads with different scratch slot size and FFTID
619 * (which may be executed in parallel depending on the shader stage and
620 * hardware generation) to map to an overlapping region of the scratch
621 * space, which can potentially lead to mutual scratch space corruption.
622 * For that reason if you borrow this scratch buffer you should only be
623 * using the slot size given by the \c per_thread_scratch member below,
624 * unless you're taking additional measures to synchronize thread execution
625 * across slot size changes.
627 struct brw_bo
*scratch_bo
;
630 * Scratch slot size allocated for each thread in the buffer object given
633 uint32_t per_thread_scratch
;
635 /** Offset in the program cache to the program */
636 uint32_t prog_offset
;
638 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
639 uint32_t state_offset
;
641 struct brw_bo
*push_const_bo
; /* NULL if using the batchbuffer */
642 uint32_t push_const_offset
; /* Offset in the push constant BO or batch */
643 int push_const_size
; /* in 256-bit register increments */
645 /* Binding table: pointers to SURFACE_STATE entries. */
646 uint32_t bind_bo_offset
;
647 uint32_t surf_offset
[BRW_MAX_SURFACES
];
649 /** SAMPLER_STATE count and table offset */
650 uint32_t sampler_count
;
651 uint32_t sampler_offset
;
653 struct brw_image_param image_param
[BRW_MAX_IMAGES
];
655 /** Need to re-emit 3DSTATE_CONSTANT_XS? */
656 bool push_constants_dirty
;
659 enum brw_predicate_state
{
660 /* The first two states are used if we can determine whether to draw
661 * without having to look at the values in the query object buffer. This
662 * will happen if there is no conditional render in progress, if the query
663 * object is already completed or if something else has already added
664 * samples to the preliminary result such as via a BLT command.
666 BRW_PREDICATE_STATE_RENDER
,
667 BRW_PREDICATE_STATE_DONT_RENDER
,
668 /* In this case whether to draw or not depends on the result of an
669 * MI_PREDICATE command so the predicate enable bit needs to be checked.
671 BRW_PREDICATE_STATE_USE_BIT
,
672 /* In this case, either MI_PREDICATE doesn't exist or we lack the
673 * necessary kernel features to use it. Stall for the query result.
675 BRW_PREDICATE_STATE_STALL_FOR_QUERY
,
680 struct gen_l3_config
;
682 enum brw_query_kind
{
687 struct brw_perf_query_register_prog
{
692 struct brw_perf_query_info
694 enum brw_query_kind kind
;
697 struct brw_perf_query_counter
*counters
;
702 uint64_t oa_metrics_set_id
;
705 /* For indexing into the accumulator[] ... */
707 int gpu_clock_offset
;
712 /* Register programming for a given query */
713 struct brw_perf_query_register_prog
*flex_regs
;
714 uint32_t n_flex_regs
;
716 struct brw_perf_query_register_prog
*mux_regs
;
719 struct brw_perf_query_register_prog
*b_counter_regs
;
720 uint32_t n_b_counter_regs
;
723 struct brw_uploader
{
724 struct brw_bufmgr
*bufmgr
;
727 uint32_t next_offset
;
728 unsigned default_size
;
732 * brw_context is derived from gl_context.
736 struct gl_context ctx
; /**< base class, must be first field */
741 * Send the appropriate state packets to configure depth, stencil, and
742 * HiZ buffers (i965+ only)
744 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
745 struct intel_mipmap_tree
*depth_mt
,
746 uint32_t depth_offset
,
747 uint32_t depthbuffer_format
,
748 uint32_t depth_surface_type
,
749 struct intel_mipmap_tree
*stencil_mt
,
750 bool hiz
, bool separate_stencil
,
751 uint32_t width
, uint32_t height
,
752 uint32_t tile_x
, uint32_t tile_y
);
755 * Emit an MI_REPORT_PERF_COUNT command packet.
757 * This asks the GPU to write a report of the current OA counter values
758 * into @bo at the given offset and containing the given @report_id
759 * which we can cross-reference when parsing the report (gen7+ only).
761 void (*emit_mi_report_perf_count
)(struct brw_context
*brw
,
763 uint32_t offset_in_bytes
,
767 struct brw_bufmgr
*bufmgr
;
771 /** BO for post-sync nonzero writes for gen6 workaround. */
772 struct brw_bo
*workaround_bo
;
773 uint8_t pipe_controls_since_last_cs_stall
;
776 * Set of struct brw_bo * that have been rendered to within this batchbuffer
777 * and would need flushing before being used from another cache domain that
778 * isn't coherent with it (i.e. the sampler).
780 struct hash_table
*render_cache
;
783 * Set of struct brw_bo * that have been used as a depth buffer within this
784 * batchbuffer and would need flushing before being used from another cache
785 * domain that isn't coherent with it (i.e. the sampler).
787 struct set
*depth_cache
;
790 * Number of resets observed in the system at context creation.
792 * This is tracked in the context so that we can determine that another
793 * reset has occurred.
795 uint32_t reset_count
;
797 struct intel_batchbuffer batch
;
799 struct brw_uploader upload
;
802 * Set if rendering has occurred to the drawable's front buffer.
804 * This is used in the DRI2 case to detect that glFlush should also copy
805 * the contents of the fake front buffer to the real front buffer.
807 bool front_buffer_dirty
;
809 /** Framerate throttling: @{ */
810 struct brw_bo
*throttle_batch
[2];
812 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
813 * frame of rendering to complete. This gives a very precise cap to the
814 * latency between input and output such that rendering never gets more
815 * than a frame behind the user. (With the caveat that we technically are
816 * not using the SwapBuffers itself as a barrier but the first batch
817 * submitted afterwards, which may be immediately prior to the next
820 bool need_swap_throttle
;
822 /** General throttling, not caught by throttling between SwapBuffers */
823 bool need_flush_throttle
;
833 bool always_flush_batch
;
834 bool always_flush_cache
;
835 bool disable_throttling
;
837 bool dual_color_blend_by_location
;
839 driOptionCache optionCache
;
842 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
844 GLenum reduced_primitive
;
847 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
848 * variable is set, this is the flag indicating to do expensive work that
849 * might lead to a perf_debug() call.
853 uint64_t max_gtt_map_object_size
;
856 bool has_separate_stencil
;
859 /** Derived stencil states. */
860 bool stencil_enabled
;
861 bool stencil_two_sided
;
862 bool stencil_write_enabled
;
863 /** Derived polygon state. */
864 bool polygon_front_bit
; /**< 0=GL_CCW, 1=GL_CW */
866 struct isl_device isl_dev
;
868 struct blorp_context blorp
;
872 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
875 enum brw_pipeline last_pipeline
;
877 struct brw_cache cache
;
879 /* Whether a meta-operation is in progress. */
880 bool meta_in_progress
;
882 /* Whether the last depth/stencil packets were both NULL. */
883 bool no_depth_or_stencil
;
885 /* The last PMA stall bits programmed. */
886 uint32_t pma_stall_bits
;
891 * Either the value of gl_BaseVertex for indexed draw calls or the
892 * value of the argument <first> for non-indexed draw calls for the
893 * current _mesa_prim.
897 /** The value of gl_BaseInstance for the current _mesa_prim. */
902 * Buffer and offset used for GL_ARB_shader_draw_parameters
903 * (for now, only gl_BaseVertex).
905 struct brw_bo
*draw_params_bo
;
906 uint32_t draw_params_offset
;
909 * The value of gl_DrawID for the current _mesa_prim. This always comes
910 * in from it's own vertex buffer since it's not part of the indirect
914 struct brw_bo
*draw_id_bo
;
915 uint32_t draw_id_offset
;
918 * Pointer to the the buffer storing the indirect draw parameters. It
919 * currently only stores the number of requested draw calls but more
920 * parameters could potentially be added.
922 struct brw_bo
*draw_params_count_bo
;
923 uint32_t draw_params_count_offset
;
928 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
929 * an indirect call, and num_work_groups_offset is valid. Otherwise,
930 * num_work_groups is set based on glDispatchCompute.
932 struct brw_bo
*num_work_groups_bo
;
933 GLintptr num_work_groups_offset
;
934 const GLuint
*num_work_groups
;
938 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
939 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
941 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
945 /* Summary of size and varying of active arrays, so we can check
946 * for changes to this state:
948 bool index_bounds_valid
;
949 unsigned int min_index
, max_index
;
951 /* Offset from start of vertex buffer so we can avoid redefining
952 * the same VB packed over and over again.
954 unsigned int start_vertex_bias
;
957 * Certain vertex attribute formats aren't natively handled by the
958 * hardware and require special VS code to fix up their values.
960 * These bitfields indicate which workarounds are needed.
962 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
964 /* For the initial pushdown, keep the list of vbo inputs. */
965 struct vbo_inputs draw_arrays
;
970 * Index buffer for this draw_prims call.
972 * Updates are signaled by BRW_NEW_INDICES.
974 const struct _mesa_index_buffer
*ib
;
976 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
981 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
982 * avoid re-uploading the IB packet over and over if we're actually
983 * referencing the same index buffer.
985 unsigned int start_vertex_offset
;
988 /* Active vertex program:
990 struct gl_program
*programs
[MESA_SHADER_STAGES
];
993 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
994 * that we don't have to reemit that state every time we change FBOs.
996 unsigned int num_samples
;
998 /* BRW_NEW_URB_ALLOCATIONS:
1001 GLuint vsize
; /* vertex size plus header in urb registers */
1002 GLuint gsize
; /* GS output size in urb registers */
1003 GLuint hsize
; /* Tessellation control output size in urb registers */
1004 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
1005 GLuint csize
; /* constant buffer size in urb registers */
1006 GLuint sfsize
; /* setup data size in urb registers */
1010 GLuint nr_vs_entries
;
1011 GLuint nr_hs_entries
;
1012 GLuint nr_ds_entries
;
1013 GLuint nr_gs_entries
;
1014 GLuint nr_clip_entries
;
1015 GLuint nr_sf_entries
;
1016 GLuint nr_cs_entries
;
1026 * URB size in the current configuration. The units this is expressed
1027 * in are somewhat inconsistent, see gen_device_info::urb::size.
1029 * FINISHME: Represent the URB size consistently in KB on all platforms.
1033 /* True if the most recently sent _3DSTATE_URB message allocated
1034 * URB space for the GS.
1038 /* True if the most recently sent _3DSTATE_URB message allocated
1039 * URB space for the HS and DS.
1045 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1047 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1048 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1056 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1057 * for upload to the CURBE.
1059 struct brw_bo
*curbe_bo
;
1060 /** Offset within curbe_bo of space for current curbe entry */
1061 GLuint curbe_offset
;
1065 * Layout of vertex data exiting the geometry portion of the pipleine.
1066 * This comes from the last enabled shader stage (GS, DS, or VS).
1068 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1070 struct brw_vue_map vue_map_geom_out
;
1073 struct brw_stage_state base
;
1077 struct brw_stage_state base
;
1081 struct brw_stage_state base
;
1085 struct brw_stage_state base
;
1088 * True if the 3DSTATE_GS command most recently emitted to the 3D
1089 * pipeline enabled the GS; false otherwise.
1095 struct brw_ff_gs_prog_data
*prog_data
;
1098 /** Offset in the program cache to the CLIP program pre-gen6 */
1099 uint32_t prog_offset
;
1100 uint32_t state_offset
;
1102 uint32_t bind_bo_offset
;
1104 * Surface offsets for the binding table. We only need surfaces to
1105 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1106 * need in this case.
1108 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1112 struct brw_clip_prog_data
*prog_data
;
1114 /** Offset in the program cache to the CLIP program pre-gen6 */
1115 uint32_t prog_offset
;
1117 /* Offset in the batch to the CLIP state on pre-gen6. */
1118 uint32_t state_offset
;
1120 /* As of gen6, this is the offset in the batch to the CLIP VP,
1126 * The number of viewports to use. If gl_ViewportIndex is written,
1127 * we can have up to ctx->Const.MaxViewports viewports. If not,
1128 * the viewport index is always 0, so we can only emit one.
1130 uint8_t viewport_count
;
1135 struct brw_sf_prog_data
*prog_data
;
1137 /** Offset in the program cache to the CLIP program pre-gen6 */
1138 uint32_t prog_offset
;
1139 uint32_t state_offset
;
1144 struct brw_stage_state base
;
1147 * Buffer object used in place of multisampled null render targets on
1148 * Gen6. See brw_emit_null_surface_state().
1150 struct brw_bo
*multisampled_null_render_target_bo
;
1156 struct brw_stage_state base
;
1160 uint32_t state_offset
;
1161 uint32_t blend_state_offset
;
1162 uint32_t depth_stencil_state_offset
;
1167 struct brw_query_object
*obj
;
1172 enum brw_predicate_state state
;
1177 /* Variables referenced in the XML meta data for OA performance
1178 * counters, e.g in the normalization equations.
1180 * All uint64_t for consistent operand types in generated code
1183 uint64_t timestamp_frequency
; /** $GpuTimestampFrequency */
1184 uint64_t n_eus
; /** $EuCoresTotalCount */
1185 uint64_t n_eu_slices
; /** $EuSlicesTotalCount */
1186 uint64_t n_eu_sub_slices
; /** $EuSubslicesTotalCount */
1187 uint64_t eu_threads_count
; /** $EuThreadsCount */
1188 uint64_t slice_mask
; /** $SliceMask */
1189 uint64_t subslice_mask
; /** $SubsliceMask */
1190 uint64_t gt_min_freq
; /** $GpuMinFrequency */
1191 uint64_t gt_max_freq
; /** $GpuMaxFrequency */
1192 uint64_t revision
; /** $SkuRevisionId */
1195 /* OA metric sets, indexed by GUID, as know by Mesa at build time,
1196 * to cross-reference with the GUIDs of configs advertised by the
1199 struct hash_table
*oa_metrics_table
;
1201 /* Location of the device's sysfs entry. */
1202 char sysfs_dev_dir
[256];
1204 struct brw_perf_query_info
*queries
;
1207 /* The i915 perf stream we open to setup + enable the OA counters */
1210 /* An i915 perf stream fd gives exclusive access to the OA unit that will
1211 * report counter snapshots for a specific counter set/profile in a
1212 * specific layout/format so we can only start OA queries that are
1213 * compatible with the currently open fd...
1215 int current_oa_metrics_set_id
;
1216 int current_oa_format
;
1218 /* List of buffers containing OA reports */
1219 struct exec_list sample_buffers
;
1221 /* Cached list of empty sample buffers */
1222 struct exec_list free_sample_buffers
;
1224 int n_active_oa_queries
;
1225 int n_active_pipeline_stats_queries
;
1227 /* The number of queries depending on running OA counters which
1228 * extends beyond brw_end_perf_query() since we need to wait until
1229 * the last MI_RPC command has parsed by the GPU.
1231 * Accurate accounting is important here as emitting an
1232 * MI_REPORT_PERF_COUNT command while the OA unit is disabled will
1233 * effectively hang the gpu.
1237 /* To help catch an spurious problem with the hardware or perf
1238 * forwarding samples, we emit each MI_REPORT_PERF_COUNT command
1239 * with a unique ID that we can explicitly check for...
1241 int next_query_start_report_id
;
1244 * An array of queries whose results haven't yet been assembled
1245 * based on the data in buffer objects.
1247 * These may be active, or have already ended. However, the
1248 * results have not been requested.
1250 struct brw_perf_query_object
**unaccumulated
;
1251 int unaccumulated_elements
;
1252 int unaccumulated_array_size
;
1254 /* The total number of query objects so we can relinquish
1255 * our exclusive access to perf if the application deletes
1256 * all of its objects. (NB: We only disable perf while
1257 * there are no active queries)
1259 int n_query_instances
;
1262 int num_atoms
[BRW_NUM_PIPELINES
];
1263 const struct brw_tracked_state render_atoms
[76];
1264 const struct brw_tracked_state compute_atoms
[11];
1266 const enum isl_format
*mesa_to_isl_render_format
;
1267 const bool *mesa_format_supports_render
;
1269 /* PrimitiveRestart */
1272 bool enable_cut_index
;
1275 /** Computed depth/stencil/hiz state from the current attached
1276 * renderbuffers, valid only during the drawing state upload loop after
1277 * brw_workaround_depthstencil_alignment().
1280 /* Inter-tile (page-aligned) byte offsets. */
1281 uint32_t depth_offset
;
1282 /* Intra-tile x,y offsets for drawing to combined depth-stencil. Only
1285 uint32_t tile_x
, tile_y
;
1288 uint32_t num_instances
;
1293 const struct gen_l3_config
*config
;
1300 enum shader_time_shader_type
*types
;
1301 struct shader_times
*cumulative
;
1307 struct brw_fast_clear_state
*fast_clear_state
;
1309 /* Array of aux usages to use for drawing. Aux usage for render targets is
1310 * a bit more complex than simply calling a single function so we need some
1311 * way of passing it form brw_draw.c to surface state setup.
1313 enum isl_aux_usage draw_aux_usage
[MAX_DRAW_BUFFERS
];
1315 __DRIcontext
*driContext
;
1316 struct intel_screen
*screen
;
1320 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1322 /*======================================================================
1325 extern const char *const brw_vendor_string
;
1328 brw_get_renderer_string(const struct intel_screen
*screen
);
1331 DRI_CONF_BO_REUSE_DISABLED
,
1332 DRI_CONF_BO_REUSE_ALL
1335 void intel_update_renderbuffers(__DRIcontext
*context
,
1336 __DRIdrawable
*drawable
);
1337 void intel_prepare_render(struct brw_context
*brw
);
1339 void brw_predraw_resolve_inputs(struct brw_context
*brw
, bool rendering
,
1340 bool *draw_aux_buffer_disabled
);
1342 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1343 __DRIdrawable
*drawable
);
1345 GLboolean
brwCreateContext(gl_api api
,
1346 const struct gl_config
*mesaVis
,
1347 __DRIcontext
*driContextPriv
,
1348 const struct __DriverContextConfig
*ctx_config
,
1350 void *sharedContextPrivate
);
1352 /*======================================================================
1356 brw_meta_resolve_color(struct brw_context
*brw
,
1357 struct intel_mipmap_tree
*mt
);
1359 /*======================================================================
1362 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1363 GLbitfield clear_mask
);
1365 /* brw_object_purgeable.c */
1366 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1368 /*======================================================================
1371 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1372 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1373 void brw_emit_query_begin(struct brw_context
*brw
);
1374 void brw_emit_query_end(struct brw_context
*brw
);
1375 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1376 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1377 uint64_t brw_timebase_scale(struct brw_context
*brw
, uint64_t gpu_timestamp
);
1378 uint64_t brw_raw_timestamp_delta(struct brw_context
*brw
,
1379 uint64_t time0
, uint64_t time1
);
1381 /** gen6_queryobj.c */
1382 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1383 void brw_write_timestamp(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1384 void brw_write_depth_count(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1386 /** hsw_queryobj.c */
1387 void hsw_overflow_result_to_gpr0(struct brw_context
*brw
,
1388 struct brw_query_object
*query
,
1390 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1392 /** brw_conditional_render.c */
1393 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1394 bool brw_check_conditional_render(struct brw_context
*brw
);
1396 /** intel_batchbuffer.c */
1397 void brw_load_register_mem(struct brw_context
*brw
,
1401 void brw_load_register_mem64(struct brw_context
*brw
,
1405 void brw_store_register_mem32(struct brw_context
*brw
,
1406 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1407 void brw_store_register_mem64(struct brw_context
*brw
,
1408 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1409 void brw_load_register_imm32(struct brw_context
*brw
,
1410 uint32_t reg
, uint32_t imm
);
1411 void brw_load_register_imm64(struct brw_context
*brw
,
1412 uint32_t reg
, uint64_t imm
);
1413 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1415 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1417 void brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1418 uint32_t offset
, uint32_t imm
);
1419 void brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1420 uint32_t offset
, uint64_t imm
);
1422 /*======================================================================
1423 * intel_tex_validate.c
1425 void brw_validate_textures( struct brw_context
*brw
);
1428 /*======================================================================
1432 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1435 perf_debug(" %s %d->%d\n", name
, a
, b
);
1441 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1443 void brw_get_scratch_bo(struct brw_context
*brw
,
1444 struct brw_bo
**scratch_bo
, int size
);
1445 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1446 struct brw_stage_state
*stage_state
,
1447 unsigned per_thread_size
);
1448 void brw_init_shader_time(struct brw_context
*brw
);
1449 int brw_get_shader_time_index(struct brw_context
*brw
,
1450 struct gl_program
*prog
,
1451 enum shader_time_shader_type type
,
1453 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1454 void brw_destroy_shader_time(struct brw_context
*brw
);
1458 void brw_calculate_urb_fence(struct brw_context
*brw
, unsigned csize
,
1459 unsigned vsize
, unsigned sfsize
);
1460 void brw_upload_urb_fence(struct brw_context
*brw
);
1464 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1467 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1469 /* brw_draw_upload.c */
1470 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1471 const struct gl_array_attributes
*glattr
);
1473 static inline unsigned
1474 brw_get_index_type(unsigned index_size
)
1476 /* The hw needs 0x00, 0x01, and 0x02 for ubyte, ushort, and uint,
1479 return index_size
>> 1;
1482 void brw_prepare_vertices(struct brw_context
*brw
);
1484 /* brw_wm_surface_state.c */
1485 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1487 uint32_t *surf_offset
);
1489 brw_update_sol_surface(struct brw_context
*brw
,
1490 struct gl_buffer_object
*buffer_obj
,
1491 uint32_t *out_offset
, unsigned num_vector_components
,
1492 unsigned stride_dwords
, unsigned offset_dwords
);
1493 void brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1494 struct brw_stage_state
*stage_state
,
1495 struct brw_stage_prog_data
*prog_data
);
1496 void brw_upload_image_surfaces(struct brw_context
*brw
,
1497 const struct gl_program
*prog
,
1498 struct brw_stage_state
*stage_state
,
1499 struct brw_stage_prog_data
*prog_data
);
1501 /* brw_surface_formats.c */
1502 void intel_screen_init_surface_formats(struct intel_screen
*screen
);
1503 void brw_init_surface_formats(struct brw_context
*brw
);
1504 bool brw_render_target_supported(struct brw_context
*brw
,
1505 struct gl_renderbuffer
*rb
);
1506 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1508 /* brw_performance_query.c */
1509 void brw_init_performance_queries(struct brw_context
*brw
);
1511 /* intel_extensions.c */
1512 extern void intelInitExtensions(struct gl_context
*ctx
);
1515 extern int intel_translate_shadow_compare_func(GLenum func
);
1516 extern int intel_translate_compare_func(GLenum func
);
1517 extern int intel_translate_stencil_op(GLenum op
);
1520 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1523 struct gl_transform_feedback_object
*
1524 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1526 brw_delete_transform_feedback(struct gl_context
*ctx
,
1527 struct gl_transform_feedback_object
*obj
);
1529 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1530 struct gl_transform_feedback_object
*obj
);
1532 brw_end_transform_feedback(struct gl_context
*ctx
,
1533 struct gl_transform_feedback_object
*obj
);
1535 brw_pause_transform_feedback(struct gl_context
*ctx
,
1536 struct gl_transform_feedback_object
*obj
);
1538 brw_resume_transform_feedback(struct gl_context
*ctx
,
1539 struct gl_transform_feedback_object
*obj
);
1541 brw_save_primitives_written_counters(struct brw_context
*brw
,
1542 struct brw_transform_feedback_object
*obj
);
1544 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1545 struct gl_transform_feedback_object
*obj
,
1548 /* gen7_sol_state.c */
1550 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1551 struct gl_transform_feedback_object
*obj
);
1553 gen7_end_transform_feedback(struct gl_context
*ctx
,
1554 struct gl_transform_feedback_object
*obj
);
1556 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1557 struct gl_transform_feedback_object
*obj
);
1559 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1560 struct gl_transform_feedback_object
*obj
);
1564 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1565 struct gl_transform_feedback_object
*obj
);
1567 hsw_end_transform_feedback(struct gl_context
*ctx
,
1568 struct gl_transform_feedback_object
*obj
);
1570 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1571 struct gl_transform_feedback_object
*obj
);
1573 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1574 struct gl_transform_feedback_object
*obj
);
1576 /* brw_blorp_blit.cpp */
1578 brw_blorp_framebuffer(struct brw_context
*brw
,
1579 struct gl_framebuffer
*readFb
,
1580 struct gl_framebuffer
*drawFb
,
1581 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1582 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1583 GLbitfield mask
, GLenum filter
);
1586 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1587 struct gl_renderbuffer
*src_rb
,
1588 struct gl_texture_image
*dst_image
,
1590 int srcX0
, int srcY0
,
1591 int dstX0
, int dstY0
,
1592 int width
, int height
);
1594 /* brw_generate_mipmap.c */
1595 void brw_generate_mipmap(struct gl_context
*ctx
, GLenum target
,
1596 struct gl_texture_object
*tex_obj
);
1599 gen6_get_sample_position(struct gl_context
*ctx
,
1600 struct gl_framebuffer
*fb
,
1604 gen6_set_sample_maps(struct gl_context
*ctx
);
1606 /* gen8_multisample_state.c */
1607 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1611 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1612 unsigned hs_size
, unsigned ds_size
,
1613 unsigned gs_size
, unsigned fs_size
);
1616 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1617 bool gs_present
, unsigned gs_size
);
1619 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1620 bool gs_present
, bool tess_present
);
1624 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1626 brw_check_for_reset(struct brw_context
*brw
);
1630 brw_init_compute_functions(struct dd_function_table
*functions
);
1632 /* brw_program_binary.c */
1634 brw_program_binary_init(unsigned device_id
);
1636 brw_get_program_binary_driver_sha1(struct gl_context
*ctx
, uint8_t *sha1
);
1638 brw_deserialize_program_binary(struct gl_context
*ctx
,
1639 struct gl_shader_program
*shProg
,
1640 struct gl_program
*prog
);
1642 brw_program_serialize_nir(struct gl_context
*ctx
, struct gl_program
*prog
);
1644 brw_program_deserialize_nir(struct gl_context
*ctx
, struct gl_program
*prog
,
1645 gl_shader_stage stage
);
1647 /*======================================================================
1648 * Inline conversion functions. These are better-typed than the
1649 * macros used previously:
1651 static inline struct brw_context
*
1652 brw_context( struct gl_context
*ctx
)
1654 return (struct brw_context
*)ctx
;
1657 static inline struct brw_program
*
1658 brw_program(struct gl_program
*p
)
1660 return (struct brw_program
*) p
;
1663 static inline const struct brw_program
*
1664 brw_program_const(const struct gl_program
*p
)
1666 return (const struct brw_program
*) p
;
1670 brw_depth_writes_enabled(const struct brw_context
*brw
)
1672 const struct gl_context
*ctx
= &brw
->ctx
;
1674 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1675 * because it would just overwrite the existing depth value with itself.
1677 * These bonus depth writes not only use bandwidth, but they also can
1678 * prevent early depth processing. For example, if the pixel shader
1679 * discards, the hardware must invoke the to determine whether or not
1680 * to do the depth write. If writes are disabled, we may still be able
1681 * to do the depth test before the shader, and skip the shader execution.
1683 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1684 * a programming note saying to disable depth writes for EQUAL.
1686 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1690 brw_emit_depthbuffer(struct brw_context
*brw
);
1693 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1694 struct intel_mipmap_tree
*depth_mt
,
1695 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1696 uint32_t depth_surface_type
,
1697 struct intel_mipmap_tree
*stencil_mt
,
1698 bool hiz
, bool separate_stencil
,
1699 uint32_t width
, uint32_t height
,
1700 uint32_t tile_x
, uint32_t tile_y
);
1703 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1704 struct intel_mipmap_tree
*depth_mt
,
1705 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1706 uint32_t depth_surface_type
,
1707 struct intel_mipmap_tree
*stencil_mt
,
1708 bool hiz
, bool separate_stencil
,
1709 uint32_t width
, uint32_t height
,
1710 uint32_t tile_x
, uint32_t tile_y
);
1713 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1714 struct intel_mipmap_tree
*depth_mt
,
1715 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1716 uint32_t depth_surface_type
,
1717 struct intel_mipmap_tree
*stencil_mt
,
1718 bool hiz
, bool separate_stencil
,
1719 uint32_t width
, uint32_t height
,
1720 uint32_t tile_x
, uint32_t tile_y
);
1722 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1723 struct intel_mipmap_tree
*depth_mt
,
1724 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1725 uint32_t depth_surface_type
,
1726 struct intel_mipmap_tree
*stencil_mt
,
1727 bool hiz
, bool separate_stencil
,
1728 uint32_t width
, uint32_t height
,
1729 uint32_t tile_x
, uint32_t tile_y
);
1731 uint32_t get_hw_prim_for_gl_prim(int mode
);
1734 gen6_upload_push_constants(struct brw_context
*brw
,
1735 const struct gl_program
*prog
,
1736 const struct brw_stage_prog_data
*prog_data
,
1737 struct brw_stage_state
*stage_state
);
1740 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1741 const struct intel_mipmap_tree
*mt
);
1743 /* brw_queryformat.c */
1744 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1745 GLenum internalFormat
, GLenum pname
,