2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
44 #include "blorp/blorp.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
52 #include <intel_bufmgr.h>
61 #include "intel_debug.h"
62 #include "intel_screen.h"
63 #include "intel_tex_obj.h"
64 #include "intel_resolve_map.h"
68 * URB - uniform resource buffer. A mid-sized buffer which is
69 * partitioned between the fixed function units and used for passing
70 * values (vertices, primitives, constants) between them.
72 * CURBE - constant URB entry. An urb region (entry) used to hold
73 * constant values which the fixed function units can be instructed to
74 * preload into the GRF when spawning a thread.
76 * VUE - vertex URB entry. An urb entry holding a vertex and usually
77 * a vertex header. The header contains control information and
78 * things like primitive type, Begin/end flags and clip codes.
80 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
81 * unit holding rasterization and interpolation parameters.
83 * GRF - general register file. One of several register files
84 * addressable by programmed threads. The inputs (r0, payload, curbe,
85 * urb) of the thread are preloaded to this area before the thread is
86 * spawned. The registers are individually 8 dwords wide and suitable
87 * for general usage. Registers holding thread input values are not
88 * special and may be overwritten.
90 * MRF - message register file. Threads communicate (and terminate)
91 * by sending messages. Message parameters are placed in contiguous
92 * MRF registers. All program output is via these messages. URB
93 * entries are populated by sending a message to the shared URB
94 * function containing the new data, together with a control word,
95 * often an unmodified copy of R0.
97 * R0 - GRF register 0. Typically holds control information used when
98 * sending messages to other threads.
100 * EU or GEN4 EU: The name of the programmable subsystem of the
101 * i965 hardware. Threads are executed by the EU, the registers
102 * described above are part of the EU architecture.
104 * Fixed function units:
106 * CS - Command streamer. Notional first unit, little software
107 * interaction. Holds the URB entries used for constant data, ie the
110 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
111 * this unit is responsible for pulling vertices out of vertex buffers
112 * in vram and injecting them into the processing pipe as VUEs. If
113 * enabled, it first passes them to a VS thread which is a good place
114 * for the driver to implement any active vertex shader.
116 * HS - Hull Shader (Tessellation Control Shader)
118 * TE - Tessellation Engine (Tessellation Primitive Generation)
120 * DS - Domain Shader (Tessellation Evaluation Shader)
122 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
123 * enabled, incoming strips etc are passed to GS threads in individual
124 * line/triangle/point units. The GS thread may perform arbitary
125 * computation and emit whatever primtives with whatever vertices it
126 * chooses. This makes GS an excellent place to implement GL's
127 * unfilled polygon modes, though of course it is capable of much
128 * more. Additionally, GS is used to translate away primitives not
129 * handled by latter units, including Quads and Lineloops.
131 * CS - Clipper. Mesa's clipping algorithms are imported to run on
132 * this unit. The fixed function part performs cliptesting against
133 * the 6 fixed clipplanes and makes descisions on whether or not the
134 * incoming primitive needs to be passed to a thread for clipping.
135 * User clip planes are handled via cooperation with the VS thread.
137 * SF - Strips Fans or Setup: Triangles are prepared for
138 * rasterization. Interpolation coefficients are calculated.
139 * Flatshading and two-side lighting usually performed here.
141 * WM - Windower. Interpolation of vertex attributes performed here.
142 * Fragment shader implemented here. SIMD aspects of EU taken full
143 * advantage of, as pixels are processed in blocks of 16.
145 * CC - Color Calculator. No EU threads associated with this unit.
146 * Handles blending and (presumably) depth and stencil testing.
151 struct brw_vs_prog_key
;
152 struct brw_vue_prog_key
;
153 struct brw_wm_prog_key
;
154 struct brw_wm_prog_data
;
155 struct brw_cs_prog_key
;
156 struct brw_cs_prog_data
;
160 BRW_COMPUTE_PIPELINE
,
167 BRW_CACHE_BLORP_PROG
,
170 BRW_CACHE_FF_GS_PROG
,
181 /* brw_cache_ids must come first - see brw_state_cache.c */
182 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
183 BRW_STATE_FRAGMENT_PROGRAM
,
184 BRW_STATE_GEOMETRY_PROGRAM
,
185 BRW_STATE_TESS_PROGRAMS
,
186 BRW_STATE_VERTEX_PROGRAM
,
187 BRW_STATE_CURBE_OFFSETS
,
188 BRW_STATE_REDUCED_PRIMITIVE
,
189 BRW_STATE_PATCH_PRIMITIVE
,
194 BRW_STATE_BINDING_TABLE_POINTERS
,
197 BRW_STATE_DEFAULT_TESS_LEVELS
,
199 BRW_STATE_INDEX_BUFFER
,
200 BRW_STATE_VS_CONSTBUF
,
201 BRW_STATE_TCS_CONSTBUF
,
202 BRW_STATE_TES_CONSTBUF
,
203 BRW_STATE_GS_CONSTBUF
,
204 BRW_STATE_PROGRAM_CACHE
,
205 BRW_STATE_STATE_BASE_ADDRESS
,
206 BRW_STATE_VUE_MAP_GEOM_OUT
,
207 BRW_STATE_TRANSFORM_FEEDBACK
,
208 BRW_STATE_RASTERIZER_DISCARD
,
210 BRW_STATE_UNIFORM_BUFFER
,
211 BRW_STATE_ATOMIC_BUFFER
,
212 BRW_STATE_IMAGE_UNITS
,
213 BRW_STATE_META_IN_PROGRESS
,
214 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
215 BRW_STATE_NUM_SAMPLES
,
216 BRW_STATE_TEXTURE_BUFFER
,
217 BRW_STATE_GEN4_UNIT_STATE
,
221 BRW_STATE_SAMPLER_STATE_TABLE
,
222 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
223 BRW_STATE_COMPUTE_PROGRAM
,
224 BRW_STATE_CS_WORK_GROUPS
,
228 BRW_STATE_VIEWPORT_COUNT
,
233 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
235 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
236 * When the currently bound shader program differs from the previous draw
237 * call, these will be flagged. They cover brw->{stage}_program and
238 * ctx->{Stage}Program->_Current.
240 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
241 * driver perspective. Even if the same shader is bound at the API level,
242 * we may need to switch between multiple versions of that shader to handle
243 * changes in non-orthagonal state.
245 * Additionally, multiple shader programs may have identical vertex shaders
246 * (for example), or compile down to the same code in the backend. We combine
247 * those into a single program cache entry.
249 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
250 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
252 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
253 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
254 * use the normal state upload paths), but the cache is still used. To avoid
255 * polluting the brw_state_cache code with special cases, we retain the dirty
256 * bit for now. It should eventually be removed.
258 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
259 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
260 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
261 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
262 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
263 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
264 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
265 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
266 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
267 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
268 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
269 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
270 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
271 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
272 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
273 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
274 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
275 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
276 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
277 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
278 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
279 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
280 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
281 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
282 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
284 * Used for any batch entry with a relocated pointer that will be used
285 * by any 3D rendering.
287 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
288 /** \see brw.state.depth_region */
289 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
290 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
291 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
292 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
293 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
294 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
295 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
296 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
297 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
298 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
299 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
300 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
301 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
302 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
303 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
304 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
305 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
306 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
307 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
308 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
309 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
310 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
311 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
312 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
313 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
314 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
315 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
316 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
317 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
318 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
320 struct brw_state_flags
{
321 /** State update flags signalled by mesa internals */
324 * State update flags signalled as the result of brw_tracked_state updates
329 /** Subclass of Mesa vertex program */
330 struct brw_vertex_program
{
331 struct gl_program program
;
336 /** Subclass of Mesa tessellation control program */
337 struct brw_tess_ctrl_program
{
338 struct gl_program program
;
339 unsigned id
; /**< serial no. to identify tess ctrl progs, never re-used */
343 /** Subclass of Mesa tessellation evaluation program */
344 struct brw_tess_eval_program
{
345 struct gl_program program
;
346 unsigned id
; /**< serial no. to identify tess eval progs, never re-used */
350 /** Subclass of Mesa geometry program */
351 struct brw_geometry_program
{
352 struct gl_program program
;
353 unsigned id
; /**< serial no. to identify geom progs, never re-used */
357 /** Subclass of Mesa fragment program */
358 struct brw_fragment_program
{
359 struct gl_fragment_program program
;
360 GLuint id
; /**< serial no. to identify frag progs, never re-used */
364 struct gen4_fragment_program
{
365 struct brw_fragment_program base
;
367 bool contains_flat_varying
;
368 bool contains_noperspective_varying
;
371 * Mapping of varying slots to interpolation modes.
372 * Used Gen4/5 by the clip|sf|wm stages.
374 unsigned char interp_mode
[BRW_VARYING_SLOT_COUNT
];
378 /** Subclass of Mesa compute program */
379 struct brw_compute_program
{
380 struct gl_program program
;
381 unsigned id
; /**< serial no. to identify compute progs, never re-used */
386 struct gl_linked_shader base
;
392 * Bitmask indicating which fragment shader inputs represent varyings (and
393 * hence have to be delivered to the fragment shader by the SF/SBE stage).
395 #define BRW_FS_VARYING_INPUT_MASK \
396 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
397 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
400 struct brw_sf_prog_data
{
401 GLuint urb_read_length
;
404 /* Each vertex may have upto 12 attributes, 4 components each,
405 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
408 * Actually we use 4 for each, so call it 12 rows.
410 GLuint urb_entry_size
;
415 * We always program SF to start reading at an offset of 1 (2 varying slots)
416 * from the start of the vertex URB entry. This causes it to skip:
417 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
418 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
420 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
423 struct brw_clip_prog_data
{
424 GLuint curb_read_length
; /* user planes? */
426 GLuint urb_read_length
;
430 struct brw_ff_gs_prog_data
{
431 GLuint urb_read_length
;
435 * Gen6 transform feedback: Amount by which the streaming vertex buffer
436 * indices should be incremented each time the GS is invoked.
438 unsigned svbi_postincrement_value
;
441 /** Number of texture sampler units */
442 #define BRW_MAX_TEX_UNIT 32
444 /** Max number of render targets in a shader */
445 #define BRW_MAX_DRAW_BUFFERS 8
447 /** Max number of UBOs in a shader */
448 #define BRW_MAX_UBO 14
450 /** Max number of SSBOs in a shader */
451 #define BRW_MAX_SSBO 12
453 /** Max number of atomic counter buffer objects in a shader */
454 #define BRW_MAX_ABO 16
456 /** Max number of image uniforms in a shader */
457 #define BRW_MAX_IMAGES 32
460 * Max number of binding table entries used for stream output.
462 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
463 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
465 * On Gen6, the size of transform feedback data is limited not by the number
466 * of components but by the number of binding table entries we set aside. We
467 * use one binding table entry for a float, one entry for a vector, and one
468 * entry per matrix column. Since the only way we can communicate our
469 * transform feedback capabilities to the client is via
470 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
471 * worst case, in which all the varyings are floats, so we use up one binding
472 * table entry per component. Therefore we need to set aside at least 64
473 * binding table entries for use by transform feedback.
475 * Note: since we don't currently pack varyings, it is currently impossible
476 * for the client to actually use up all of these binding table entries--if
477 * all of their varyings were floats, they would run out of varying slots and
478 * fail to link. But that's a bug, so it seems prudent to go ahead and
479 * allocate the number of binding table entries we will need once the bug is
482 #define BRW_MAX_SOL_BINDINGS 64
484 /** Maximum number of actual buffers used for stream output */
485 #define BRW_MAX_SOL_BUFFERS 4
487 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
488 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
493 2 + /* shader time, pull constants */ \
494 1 /* cs num work groups */)
496 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
499 * Stride in bytes between shader_time entries.
501 * We separate entries by a cacheline to reduce traffic between EUs writing to
504 #define SHADER_TIME_STRIDE 64
506 struct brw_cache_item
{
508 * Effectively part of the key, cache_id identifies what kind of state
509 * buffer is involved, and also which dirty flag should set.
511 enum brw_cache_id cache_id
;
512 /** 32-bit hash of the key data */
514 GLuint key_size
; /* for variable-sized keys */
521 struct brw_cache_item
*next
;
526 struct brw_context
*brw
;
528 struct brw_cache_item
**items
;
530 GLuint size
, n_items
;
532 uint32_t next_offset
;
537 /* Considered adding a member to this struct to document which flags
538 * an update might raise so that ordering of the state atoms can be
539 * checked or derived at runtime. Dropped the idea in favor of having
540 * a debug mode where the state is monitored for flags which are
541 * raised that have already been tested against.
543 struct brw_tracked_state
{
544 struct brw_state_flags dirty
;
545 void (*emit
)( struct brw_context
*brw
);
548 enum shader_time_shader_type
{
559 struct brw_vertex_buffer
{
560 /** Buffer object containing the uploaded vertex data */
564 /** Byte stride between elements in the uploaded array */
568 struct brw_vertex_element
{
569 const struct gl_client_array
*glarray
;
573 /** Offset of the first element within the buffer object */
577 struct brw_query_object
{
578 struct gl_query_object Base
;
580 /** Last query BO associated with this query. */
583 /** Last index in bo with query data for this object. */
586 /** True if we know the batch has been flushed since we ended the query. */
596 struct intel_batchbuffer
{
597 /** Current batchbuffer being queued up. */
599 /** Last BO submitted to the hardware. Used for glFinish(). */
600 drm_intel_bo
*last_bo
;
603 uint16_t emit
, total
;
605 uint16_t reserved_space
;
609 #define BATCH_SZ (8192*sizeof(uint32_t))
611 uint32_t state_batch_offset
;
612 enum brw_gpu_ring ring
;
613 bool needs_sol_reset
;
614 bool state_base_address_emitted
;
622 #define MAX_GS_INPUT_VERTICES 6
624 #define BRW_MAX_XFB_STREAMS 4
626 struct brw_transform_feedback_object
{
627 struct gl_transform_feedback_object base
;
629 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
630 drm_intel_bo
*offset_bo
;
632 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
635 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
636 GLenum primitive_mode
;
639 * Count of primitives generated during this transform feedback operation.
642 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
643 drm_intel_bo
*prim_count_bo
;
644 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
648 * Number of vertices written between last Begin/EndTransformFeedback().
650 * Used to implement DrawTransformFeedback().
652 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
653 bool vertices_written_valid
;
657 * Data shared between each programmable stage in the pipeline (vs, gs, and
660 struct brw_stage_state
662 gl_shader_stage stage
;
663 struct brw_stage_prog_data
*prog_data
;
666 * Optional scratch buffer used to store spilled register values and
667 * variably-indexed GRF arrays.
669 * The contents of this buffer are short-lived so the same memory can be
670 * re-used at will for multiple shader programs (executed by the same fixed
671 * function). However reusing a scratch BO for which shader invocations
672 * are still in flight with a per-thread scratch slot size other than the
673 * original can cause threads with different scratch slot size and FFTID
674 * (which may be executed in parallel depending on the shader stage and
675 * hardware generation) to map to an overlapping region of the scratch
676 * space, which can potentially lead to mutual scratch space corruption.
677 * For that reason if you borrow this scratch buffer you should only be
678 * using the slot size given by the \c per_thread_scratch member below,
679 * unless you're taking additional measures to synchronize thread execution
680 * across slot size changes.
682 drm_intel_bo
*scratch_bo
;
685 * Scratch slot size allocated for each thread in the buffer object given
688 uint32_t per_thread_scratch
;
690 /** Offset in the program cache to the program */
691 uint32_t prog_offset
;
693 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
694 uint32_t state_offset
;
696 uint32_t push_const_offset
; /* Offset in the batchbuffer */
697 int push_const_size
; /* in 256-bit register increments */
699 /* Binding table: pointers to SURFACE_STATE entries. */
700 uint32_t bind_bo_offset
;
701 uint32_t surf_offset
[BRW_MAX_SURFACES
];
703 /** SAMPLER_STATE count and table offset */
704 uint32_t sampler_count
;
705 uint32_t sampler_offset
;
708 enum brw_predicate_state
{
709 /* The first two states are used if we can determine whether to draw
710 * without having to look at the values in the query object buffer. This
711 * will happen if there is no conditional render in progress, if the query
712 * object is already completed or if something else has already added
713 * samples to the preliminary result such as via a BLT command.
715 BRW_PREDICATE_STATE_RENDER
,
716 BRW_PREDICATE_STATE_DONT_RENDER
,
717 /* In this case whether to draw or not depends on the result of an
718 * MI_PREDICATE command so the predicate enable bit needs to be checked.
720 BRW_PREDICATE_STATE_USE_BIT
725 struct gen_l3_config
;
728 * brw_context is derived from gl_context.
732 struct gl_context ctx
; /**< base class, must be first field */
736 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
737 struct gl_renderbuffer
*rb
,
738 uint32_t flags
, unsigned unit
,
739 uint32_t surf_index
);
740 void (*emit_null_surface_state
)(struct brw_context
*brw
,
744 uint32_t *out_offset
);
747 * Send the appropriate state packets to configure depth, stencil, and
748 * HiZ buffers (i965+ only)
750 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
751 struct intel_mipmap_tree
*depth_mt
,
752 uint32_t depth_offset
,
753 uint32_t depthbuffer_format
,
754 uint32_t depth_surface_type
,
755 struct intel_mipmap_tree
*stencil_mt
,
756 bool hiz
, bool separate_stencil
,
757 uint32_t width
, uint32_t height
,
758 uint32_t tile_x
, uint32_t tile_y
);
764 drm_intel_context
*hw_ctx
;
766 /** BO for post-sync nonzero writes for gen6 workaround. */
767 drm_intel_bo
*workaround_bo
;
768 uint8_t pipe_controls_since_last_cs_stall
;
771 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
772 * and would need flushing before being used from another cache domain that
773 * isn't coherent with it (i.e. the sampler).
775 struct set
*render_cache
;
778 * Number of resets observed in the system at context creation.
780 * This is tracked in the context so that we can determine that another
781 * reset has occurred.
783 uint32_t reset_count
;
785 struct intel_batchbuffer batch
;
790 uint32_t next_offset
;
794 * Set if rendering has occurred to the drawable's front buffer.
796 * This is used in the DRI2 case to detect that glFlush should also copy
797 * the contents of the fake front buffer to the real front buffer.
799 bool front_buffer_dirty
;
801 /** Framerate throttling: @{ */
802 drm_intel_bo
*throttle_batch
[2];
804 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
805 * frame of rendering to complete. This gives a very precise cap to the
806 * latency between input and output such that rendering never gets more
807 * than a frame behind the user. (With the caveat that we technically are
808 * not using the SwapBuffers itself as a barrier but the first batch
809 * submitted afterwards, which may be immediately prior to the next
812 bool need_swap_throttle
;
814 /** General throttling, not caught by throttling between SwapBuffers */
815 bool need_flush_throttle
;
825 bool always_flush_batch
;
826 bool always_flush_cache
;
827 bool disable_throttling
;
829 bool dual_color_blend_by_location
;
831 driOptionCache optionCache
;
834 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
836 GLenum reduced_primitive
;
839 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
840 * variable is set, this is the flag indicating to do expensive work that
841 * might lead to a perf_debug() call.
845 uint64_t max_gtt_map_object_size
;
857 bool has_separate_stencil
;
858 bool must_use_separate_stencil
;
861 bool has_surface_tile_offset
;
863 bool has_negative_rhw_bug
;
867 bool use_resource_streamer
;
870 * Whether LRI can be used to write register values from the batch buffer.
872 bool can_do_pipelined_register_writes
;
875 * Some versions of Gen hardware don't do centroid interpolation correctly
876 * on unlit pixels, causing incorrect values for derivatives near triangle
877 * edges. Enabling this flag causes the fragment shader to use
878 * non-centroid interpolation for unlit pixels, at the expense of two extra
879 * fragment shader instructions.
881 bool needs_unlit_centroid_workaround
;
883 struct isl_device isl_dev
;
885 struct blorp_context blorp
;
889 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
892 enum brw_pipeline last_pipeline
;
894 struct brw_cache cache
;
896 /** IDs for meta stencil blit shader programs. */
897 struct gl_shader_program
*meta_stencil_blit_programs
[2];
899 /* Whether a meta-operation is in progress. */
900 bool meta_in_progress
;
902 /* Whether the last depth/stencil packets were both NULL. */
903 bool no_depth_or_stencil
;
905 /* The last PMA stall bits programmed. */
906 uint32_t pma_stall_bits
;
910 /** The value of gl_BaseVertex for the current _mesa_prim. */
913 /** The value of gl_BaseInstance for the current _mesa_prim. */
918 * Buffer and offset used for GL_ARB_shader_draw_parameters
919 * (for now, only gl_BaseVertex).
921 drm_intel_bo
*draw_params_bo
;
922 uint32_t draw_params_offset
;
925 * The value of gl_DrawID for the current _mesa_prim. This always comes
926 * in from it's own vertex buffer since it's not part of the indirect
930 drm_intel_bo
*draw_id_bo
;
931 uint32_t draw_id_offset
;
936 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
937 * an indirect call, and num_work_groups_offset is valid. Otherwise,
938 * num_work_groups is set based on glDispatchCompute.
940 drm_intel_bo
*num_work_groups_bo
;
941 GLintptr num_work_groups_offset
;
942 const GLuint
*num_work_groups
;
946 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
947 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
949 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
953 /* Summary of size and varying of active arrays, so we can check
954 * for changes to this state:
956 bool index_bounds_valid
;
957 unsigned int min_index
, max_index
;
959 /* Offset from start of vertex buffer so we can avoid redefining
960 * the same VB packed over and over again.
962 unsigned int start_vertex_bias
;
965 * Certain vertex attribute formats aren't natively handled by the
966 * hardware and require special VS code to fix up their values.
968 * These bitfields indicate which workarounds are needed.
970 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
975 * Index buffer for this draw_prims call.
977 * Updates are signaled by BRW_NEW_INDICES.
979 const struct _mesa_index_buffer
*ib
;
981 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
986 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
987 * avoid re-uploading the IB packet over and over if we're actually
988 * referencing the same index buffer.
990 unsigned int start_vertex_offset
;
993 /* Active vertex program:
995 const struct gl_program
*vertex_program
;
996 const struct gl_program
*geometry_program
;
997 const struct gl_program
*tess_ctrl_program
;
998 const struct gl_program
*tess_eval_program
;
999 const struct gl_fragment_program
*fragment_program
;
1000 const struct gl_program
*compute_program
;
1003 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1004 * that we don't have to reemit that state every time we change FBOs.
1008 /* BRW_NEW_URB_ALLOCATIONS:
1011 GLuint vsize
; /* vertex size plus header in urb registers */
1012 GLuint gsize
; /* GS output size in urb registers */
1013 GLuint hsize
; /* Tessellation control output size in urb registers */
1014 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
1015 GLuint csize
; /* constant buffer size in urb registers */
1016 GLuint sfsize
; /* setup data size in urb registers */
1020 GLuint nr_vs_entries
;
1021 GLuint nr_hs_entries
;
1022 GLuint nr_ds_entries
;
1023 GLuint nr_gs_entries
;
1024 GLuint nr_clip_entries
;
1025 GLuint nr_sf_entries
;
1026 GLuint nr_cs_entries
;
1036 * URB size in the current configuration. The units this is expressed
1037 * in are somewhat inconsistent, see gen_device_info::urb::size.
1039 * FINISHME: Represent the URB size consistently in KB on all platforms.
1043 /* True if the most recently sent _3DSTATE_URB message allocated
1044 * URB space for the GS.
1048 /* True if the most recently sent _3DSTATE_URB message allocated
1049 * URB space for the HS and DS.
1055 /* BRW_NEW_CURBE_OFFSETS:
1058 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1059 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1067 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1068 * for upload to the CURBE.
1070 drm_intel_bo
*curbe_bo
;
1071 /** Offset within curbe_bo of space for current curbe entry */
1072 GLuint curbe_offset
;
1076 * Layout of vertex data exiting the geometry portion of the pipleine.
1077 * This comes from the last enabled shader stage (GS, DS, or VS).
1079 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1081 struct brw_vue_map vue_map_geom_out
;
1084 struct brw_stage_state base
;
1088 struct brw_stage_state base
;
1091 * True if the 3DSTATE_HS command most recently emitted to the 3D
1092 * pipeline enabled the HS; false otherwise.
1098 struct brw_stage_state base
;
1101 * True if the 3DSTATE_DS command most recently emitted to the 3D
1102 * pipeline enabled the DS; false otherwise.
1108 struct brw_stage_state base
;
1111 * True if the 3DSTATE_GS command most recently emitted to the 3D
1112 * pipeline enabled the GS; false otherwise.
1118 struct brw_ff_gs_prog_data
*prog_data
;
1121 /** Offset in the program cache to the CLIP program pre-gen6 */
1122 uint32_t prog_offset
;
1123 uint32_t state_offset
;
1125 uint32_t bind_bo_offset
;
1127 * Surface offsets for the binding table. We only need surfaces to
1128 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1129 * need in this case.
1131 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1135 struct brw_clip_prog_data
*prog_data
;
1137 /** Offset in the program cache to the CLIP program pre-gen6 */
1138 uint32_t prog_offset
;
1140 /* Offset in the batch to the CLIP state on pre-gen6. */
1141 uint32_t state_offset
;
1143 /* As of gen6, this is the offset in the batch to the CLIP VP,
1149 * The number of viewports to use. If gl_ViewportIndex is written,
1150 * we can have up to ctx->Const.MaxViewports viewports. If not,
1151 * the viewport index is always 0, so we can only emit one.
1153 uint8_t viewport_count
;
1158 struct brw_sf_prog_data
*prog_data
;
1160 /** Offset in the program cache to the CLIP program pre-gen6 */
1161 uint32_t prog_offset
;
1162 uint32_t state_offset
;
1164 bool viewport_transform_enable
;
1168 struct brw_stage_state base
;
1173 * Buffer object used in place of multisampled null render targets on
1174 * Gen6. See brw_emit_null_surface_state().
1176 drm_intel_bo
*multisampled_null_render_target_bo
;
1177 uint32_t fast_clear_op
;
1183 struct brw_stage_state base
;
1186 /* RS hardware binding table */
1189 uint32_t next_offset
;
1193 uint32_t state_offset
;
1194 uint32_t blend_state_offset
;
1195 uint32_t depth_stencil_state_offset
;
1200 struct brw_query_object
*obj
;
1205 enum brw_predicate_state state
;
1210 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1211 const int *statistics_registers
;
1213 /** The number of active monitors using OA counters. */
1217 * A buffer object storing OA counter snapshots taken at the start and
1218 * end of each batch (creating "bookends" around the batch).
1220 drm_intel_bo
*bookend_bo
;
1222 /** The number of snapshots written to bookend_bo. */
1223 int bookend_snapshots
;
1226 * An array of monitors whose results haven't yet been assembled based on
1227 * the data in buffer objects.
1229 * These may be active, or have already ended. However, the results
1230 * have not been requested.
1232 struct brw_perf_monitor_object
**unresolved
;
1233 int unresolved_elements
;
1234 int unresolved_array_size
;
1237 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1238 * the counter which MI_REPORT_PERF_COUNT stores there.
1240 const int *oa_snapshot_layout
;
1242 /** Number of 32-bit entries in a hardware counter snapshot. */
1243 int entries_per_oa_snapshot
;
1246 int num_atoms
[BRW_NUM_PIPELINES
];
1247 const struct brw_tracked_state render_atoms
[76];
1248 const struct brw_tracked_state compute_atoms
[11];
1250 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1254 enum aub_state_struct_type type
;
1256 } *state_batch_list
;
1257 int state_batch_count
;
1259 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1260 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1262 /* PrimitiveRestart */
1265 bool enable_cut_index
;
1268 /** Computed depth/stencil/hiz state from the current attached
1269 * renderbuffers, valid only during the drawing state upload loop after
1270 * brw_workaround_depthstencil_alignment().
1273 struct intel_mipmap_tree
*depth_mt
;
1274 struct intel_mipmap_tree
*stencil_mt
;
1276 /* Inter-tile (page-aligned) byte offsets. */
1277 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1278 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1279 uint32_t tile_x
, tile_y
;
1282 uint32_t num_instances
;
1287 const struct gen_l3_config
*config
;
1294 enum shader_time_shader_type
*types
;
1295 struct shader_times
*cumulative
;
1301 struct brw_fast_clear_state
*fast_clear_state
;
1303 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1304 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1305 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1307 * This is needed in case the same underlying buffer is also configured
1308 * to be sampled but with a format that the sampling engine can't treat
1309 * compressed or fast cleared.
1311 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1313 __DRIcontext
*driContext
;
1314 struct intel_screen
*screen
;
1317 /*======================================================================
1320 void brwInitVtbl( struct brw_context
*brw
);
1323 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1325 /*======================================================================
1328 extern const char *const brw_vendor_string
;
1331 brw_get_renderer_string(const struct intel_screen
*screen
);
1334 DRI_CONF_BO_REUSE_DISABLED
,
1335 DRI_CONF_BO_REUSE_ALL
1338 void intel_update_renderbuffers(__DRIcontext
*context
,
1339 __DRIdrawable
*drawable
);
1340 void intel_prepare_render(struct brw_context
*brw
);
1342 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1343 __DRIdrawable
*drawable
);
1345 GLboolean
brwCreateContext(gl_api api
,
1346 const struct gl_config
*mesaVis
,
1347 __DRIcontext
*driContextPriv
,
1348 unsigned major_version
,
1349 unsigned minor_version
,
1353 void *sharedContextPrivate
);
1355 /*======================================================================
1359 brw_meta_resolve_color(struct brw_context
*brw
,
1360 struct intel_mipmap_tree
*mt
);
1362 /*======================================================================
1365 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1366 uint32_t depth_level
,
1367 uint32_t depth_layer
,
1368 struct intel_mipmap_tree
*stencil_mt
,
1369 uint32_t *out_tile_mask_x
,
1370 uint32_t *out_tile_mask_y
);
1371 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1372 GLbitfield clear_mask
);
1374 /* brw_object_purgeable.c */
1375 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1377 /*======================================================================
1380 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1381 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1382 void brw_emit_query_begin(struct brw_context
*brw
);
1383 void brw_emit_query_end(struct brw_context
*brw
);
1384 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1385 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1387 /** gen6_queryobj.c */
1388 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1389 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1390 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1392 /** hsw_queryobj.c */
1393 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1395 /** brw_conditional_render.c */
1396 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1397 bool brw_check_conditional_render(struct brw_context
*brw
);
1399 /** intel_batchbuffer.c */
1400 void brw_load_register_mem(struct brw_context
*brw
,
1403 uint32_t read_domains
, uint32_t write_domain
,
1405 void brw_load_register_mem64(struct brw_context
*brw
,
1408 uint32_t read_domains
, uint32_t write_domain
,
1410 void brw_store_register_mem32(struct brw_context
*brw
,
1411 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1412 void brw_store_register_mem64(struct brw_context
*brw
,
1413 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1414 void brw_load_register_imm32(struct brw_context
*brw
,
1415 uint32_t reg
, uint32_t imm
);
1416 void brw_load_register_imm64(struct brw_context
*brw
,
1417 uint32_t reg
, uint64_t imm
);
1418 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1420 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1422 void brw_store_data_imm32(struct brw_context
*brw
, drm_intel_bo
*bo
,
1423 uint32_t offset
, uint32_t imm
);
1424 void brw_store_data_imm64(struct brw_context
*brw
, drm_intel_bo
*bo
,
1425 uint32_t offset
, uint64_t imm
);
1427 /*======================================================================
1430 void brw_debug_batch(struct brw_context
*brw
);
1431 void brw_annotate_aub(struct brw_context
*brw
);
1433 /*======================================================================
1434 * intel_tex_validate.c
1436 void brw_validate_textures( struct brw_context
*brw
);
1439 /*======================================================================
1443 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1446 perf_debug(" %s %d->%d\n", name
, a
, b
);
1452 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1454 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1456 brw_get_scratch_size(int size
)
1458 return MAX2(1024, util_next_power_of_two(size
));
1460 void brw_get_scratch_bo(struct brw_context
*brw
,
1461 drm_intel_bo
**scratch_bo
, int size
);
1462 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1463 struct brw_stage_state
*stage_state
,
1464 unsigned per_thread_size
,
1465 unsigned thread_count
);
1466 void brw_init_shader_time(struct brw_context
*brw
);
1467 int brw_get_shader_time_index(struct brw_context
*brw
,
1468 struct gl_shader_program
*shader_prog
,
1469 struct gl_program
*prog
,
1470 enum shader_time_shader_type type
);
1471 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1472 void brw_destroy_shader_time(struct brw_context
*brw
);
1476 void brw_upload_urb_fence(struct brw_context
*brw
);
1480 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1482 /* brw_fs_reg_allocate.cpp
1484 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1486 /* brw_vec4_reg_allocate.cpp */
1487 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1490 int brw_disassemble_inst(FILE *file
, const struct gen_device_info
*devinfo
,
1491 struct brw_inst
*inst
, bool is_compacted
);
1494 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1496 /* brw_draw_upload.c */
1497 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1498 const struct gl_client_array
*glarray
);
1500 static inline unsigned
1501 brw_get_index_type(GLenum type
)
1503 assert((type
== GL_UNSIGNED_BYTE
)
1504 || (type
== GL_UNSIGNED_SHORT
)
1505 || (type
== GL_UNSIGNED_INT
));
1507 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1508 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1509 * to map to scale factors of 0, 1, and 2, respectively. These scale
1510 * factors are then left-shfited by 8 to be in the correct position in the
1511 * CMD_INDEX_BUFFER packet.
1513 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1514 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1515 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1517 return (type
- 0x1401) << 7;
1520 void brw_prepare_vertices(struct brw_context
*brw
);
1522 /* brw_wm_surface_state.c */
1523 void brw_init_surface_formats(struct brw_context
*brw
);
1524 void brw_create_constant_surface(struct brw_context
*brw
,
1528 uint32_t *out_offset
);
1529 void brw_create_buffer_surface(struct brw_context
*brw
,
1533 uint32_t *out_offset
);
1534 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1536 uint32_t *surf_offset
);
1538 brw_update_sol_surface(struct brw_context
*brw
,
1539 struct gl_buffer_object
*buffer_obj
,
1540 uint32_t *out_offset
, unsigned num_vector_components
,
1541 unsigned stride_dwords
, unsigned offset_dwords
);
1542 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1543 struct gl_linked_shader
*shader
,
1544 struct brw_stage_state
*stage_state
,
1545 struct brw_stage_prog_data
*prog_data
);
1546 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1547 struct gl_linked_shader
*shader
,
1548 struct brw_stage_state
*stage_state
,
1549 struct brw_stage_prog_data
*prog_data
);
1550 void brw_upload_image_surfaces(struct brw_context
*brw
,
1551 struct gl_linked_shader
*shader
,
1552 struct brw_stage_state
*stage_state
,
1553 struct brw_stage_prog_data
*prog_data
);
1555 /* brw_surface_formats.c */
1556 bool brw_render_target_supported(struct brw_context
*brw
,
1557 struct gl_renderbuffer
*rb
);
1558 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1560 /* brw_performance_monitor.c */
1561 void brw_init_performance_monitors(struct brw_context
*brw
);
1562 void brw_dump_perf_monitors(struct brw_context
*brw
);
1563 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1564 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1566 /* intel_buffer_objects.c */
1567 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1568 const char *bo_name
);
1569 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1570 const char *bo_name
);
1572 /* intel_extensions.c */
1573 extern void intelInitExtensions(struct gl_context
*ctx
);
1576 extern int intel_translate_shadow_compare_func(GLenum func
);
1577 extern int intel_translate_compare_func(GLenum func
);
1578 extern int intel_translate_stencil_op(GLenum op
);
1579 extern int intel_translate_logic_op(GLenum opcode
);
1582 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1585 struct gl_transform_feedback_object
*
1586 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1588 brw_delete_transform_feedback(struct gl_context
*ctx
,
1589 struct gl_transform_feedback_object
*obj
);
1591 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1592 struct gl_transform_feedback_object
*obj
);
1594 brw_end_transform_feedback(struct gl_context
*ctx
,
1595 struct gl_transform_feedback_object
*obj
);
1597 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1598 struct gl_transform_feedback_object
*obj
,
1601 /* gen7_sol_state.c */
1603 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1604 struct gl_transform_feedback_object
*obj
);
1606 gen7_end_transform_feedback(struct gl_context
*ctx
,
1607 struct gl_transform_feedback_object
*obj
);
1609 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1610 struct gl_transform_feedback_object
*obj
);
1612 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1613 struct gl_transform_feedback_object
*obj
);
1617 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1618 struct gl_transform_feedback_object
*obj
);
1620 hsw_end_transform_feedback(struct gl_context
*ctx
,
1621 struct gl_transform_feedback_object
*obj
);
1623 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1624 struct gl_transform_feedback_object
*obj
);
1626 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1627 struct gl_transform_feedback_object
*obj
);
1629 /* brw_blorp_blit.cpp */
1631 brw_blorp_framebuffer(struct brw_context
*brw
,
1632 struct gl_framebuffer
*readFb
,
1633 struct gl_framebuffer
*drawFb
,
1634 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1635 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1636 GLbitfield mask
, GLenum filter
);
1639 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1640 struct gl_renderbuffer
*src_rb
,
1641 struct gl_texture_image
*dst_image
,
1643 int srcX0
, int srcY0
,
1644 int dstX0
, int dstY0
,
1645 int width
, int height
);
1647 /* gen6_multisample_state.c */
1649 gen6_determine_sample_mask(struct brw_context
*brw
);
1652 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1653 unsigned num_samples
);
1655 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1657 gen6_get_sample_position(struct gl_context
*ctx
,
1658 struct gl_framebuffer
*fb
,
1662 gen6_set_sample_maps(struct gl_context
*ctx
);
1664 /* gen8_multisample_state.c */
1665 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1666 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1670 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1671 unsigned hs_size
, unsigned ds_size
,
1672 unsigned gs_size
, unsigned fs_size
);
1675 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1676 bool gs_present
, unsigned gs_size
);
1678 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1679 bool gs_present
, bool tess_present
);
1683 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1685 brw_check_for_reset(struct brw_context
*brw
);
1689 brw_init_compute_functions(struct dd_function_table
*functions
);
1691 /*======================================================================
1692 * Inline conversion functions. These are better-typed than the
1693 * macros used previously:
1695 static inline struct brw_context
*
1696 brw_context( struct gl_context
*ctx
)
1698 return (struct brw_context
*)ctx
;
1701 static inline struct brw_vertex_program
*
1702 brw_vertex_program(struct gl_program
*p
)
1704 return (struct brw_vertex_program
*) p
;
1707 static inline const struct brw_vertex_program
*
1708 brw_vertex_program_const(const struct gl_program
*p
)
1710 return (const struct brw_vertex_program
*) p
;
1713 static inline struct brw_tess_ctrl_program
*
1714 brw_tess_ctrl_program(struct gl_program
*p
)
1716 return (struct brw_tess_ctrl_program
*) p
;
1719 static inline struct brw_tess_eval_program
*
1720 brw_tess_eval_program(struct gl_program
*p
)
1722 return (struct brw_tess_eval_program
*) p
;
1725 static inline struct brw_geometry_program
*
1726 brw_geometry_program(struct gl_program
*p
)
1728 return (struct brw_geometry_program
*) p
;
1731 static inline struct brw_fragment_program
*
1732 brw_fragment_program(struct gl_fragment_program
*p
)
1734 return (struct brw_fragment_program
*) p
;
1737 static inline const struct brw_fragment_program
*
1738 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1740 return (const struct brw_fragment_program
*) p
;
1743 static inline struct brw_compute_program
*
1744 brw_compute_program(struct gl_program
*p
)
1746 return (struct brw_compute_program
*) p
;
1750 * Pre-gen6, the register file of the EUs was shared between threads,
1751 * and each thread used some subset allocated on a 16-register block
1752 * granularity. The unit states wanted these block counts.
1755 brw_register_blocks(int reg_count
)
1757 return ALIGN(reg_count
, 16) / 16 - 1;
1760 static inline uint32_t
1761 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1762 uint32_t prog_offset
)
1764 if (brw
->gen
>= 5) {
1765 /* Using state base address. */
1769 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1773 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1775 return brw
->cache
.bo
->offset64
+ prog_offset
;
1778 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1779 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1780 struct exec_list
*instructions
);
1782 extern const char * const conditional_modifier
[16];
1783 extern const char *const pred_ctrl_align16
[16];
1786 brw_emit_depthbuffer(struct brw_context
*brw
);
1789 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1790 struct intel_mipmap_tree
*depth_mt
,
1791 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1792 uint32_t depth_surface_type
,
1793 struct intel_mipmap_tree
*stencil_mt
,
1794 bool hiz
, bool separate_stencil
,
1795 uint32_t width
, uint32_t height
,
1796 uint32_t tile_x
, uint32_t tile_y
);
1799 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1800 struct intel_mipmap_tree
*depth_mt
,
1801 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1802 uint32_t depth_surface_type
,
1803 struct intel_mipmap_tree
*stencil_mt
,
1804 bool hiz
, bool separate_stencil
,
1805 uint32_t width
, uint32_t height
,
1806 uint32_t tile_x
, uint32_t tile_y
);
1809 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1810 struct intel_mipmap_tree
*depth_mt
,
1811 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1812 uint32_t depth_surface_type
,
1813 struct intel_mipmap_tree
*stencil_mt
,
1814 bool hiz
, bool separate_stencil
,
1815 uint32_t width
, uint32_t height
,
1816 uint32_t tile_x
, uint32_t tile_y
);
1818 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1819 struct intel_mipmap_tree
*depth_mt
,
1820 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1821 uint32_t depth_surface_type
,
1822 struct intel_mipmap_tree
*stencil_mt
,
1823 bool hiz
, bool separate_stencil
,
1824 uint32_t width
, uint32_t height
,
1825 uint32_t tile_x
, uint32_t tile_y
);
1827 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1828 unsigned int level
, unsigned int layer
, enum blorp_hiz_op op
);
1830 uint32_t get_hw_prim_for_gl_prim(int mode
);
1833 gen6_upload_push_constants(struct brw_context
*brw
,
1834 const struct gl_program
*prog
,
1835 const struct brw_stage_prog_data
*prog_data
,
1836 struct brw_stage_state
*stage_state
,
1837 enum aub_state_struct_type type
);
1840 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1841 const struct intel_mipmap_tree
*mt
);
1843 /* brw_pipe_control.c */
1844 int brw_init_pipe_control(struct brw_context
*brw
,
1845 const struct gen_device_info
*info
);
1846 void brw_fini_pipe_control(struct brw_context
*brw
);
1848 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1849 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1850 drm_intel_bo
*bo
, uint32_t offset
,
1851 uint32_t imm_lower
, uint32_t imm_upper
);
1852 void brw_emit_mi_flush(struct brw_context
*brw
);
1853 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1854 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1855 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1856 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1858 /* brw_queryformat.c */
1859 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1860 GLenum internalFormat
, GLenum pname
,