2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
46 * URB - uniform resource buffer. A mid-sized buffer which is
47 * partitioned between the fixed function units and used for passing
48 * values (vertices, primitives, constants) between them.
50 * CURBE - constant URB entry. An urb region (entry) used to hold
51 * constant values which the fixed function units can be instructed to
52 * preload into the GRF when spawning a thread.
54 * VUE - vertex URB entry. An urb entry holding a vertex and usually
55 * a vertex header. The header contains control information and
56 * things like primitive type, Begin/end flags and clip codes.
58 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
59 * unit holding rasterization and interpolation parameters.
61 * GRF - general register file. One of several register files
62 * addressable by programmed threads. The inputs (r0, payload, curbe,
63 * urb) of the thread are preloaded to this area before the thread is
64 * spawned. The registers are individually 8 dwords wide and suitable
65 * for general usage. Registers holding thread input values are not
66 * special and may be overwritten.
68 * MRF - message register file. Threads communicate (and terminate)
69 * by sending messages. Message parameters are placed in contiguous
70 * MRF registers. All program output is via these messages. URB
71 * entries are populated by sending a message to the shared URB
72 * function containing the new data, together with a control word,
73 * often an unmodified copy of R0.
75 * R0 - GRF register 0. Typically holds control information used when
76 * sending messages to other threads.
78 * EU or GEN4 EU: The name of the programmable subsystem of the
79 * i965 hardware. Threads are executed by the EU, the registers
80 * described above are part of the EU architecture.
82 * Fixed function units:
84 * CS - Command streamer. Notional first unit, little software
85 * interaction. Holds the URB entries used for constant data, ie the
88 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
89 * this unit is responsible for pulling vertices out of vertex buffers
90 * in vram and injecting them into the processing pipe as VUEs. If
91 * enabled, it first passes them to a VS thread which is a good place
92 * for the driver to implement any active vertex shader.
94 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
95 * enabled, incoming strips etc are passed to GS threads in individual
96 * line/triangle/point units. The GS thread may perform arbitary
97 * computation and emit whatever primtives with whatever vertices it
98 * chooses. This makes GS an excellent place to implement GL's
99 * unfilled polygon modes, though of course it is capable of much
100 * more. Additionally, GS is used to translate away primitives not
101 * handled by latter units, including Quads and Lineloops.
103 * CS - Clipper. Mesa's clipping algorithms are imported to run on
104 * this unit. The fixed function part performs cliptesting against
105 * the 6 fixed clipplanes and makes descisions on whether or not the
106 * incoming primitive needs to be passed to a thread for clipping.
107 * User clip planes are handled via cooperation with the VS thread.
109 * SF - Strips Fans or Setup: Triangles are prepared for
110 * rasterization. Interpolation coefficients are calculated.
111 * Flatshading and two-side lighting usually performed here.
113 * WM - Windower. Interpolation of vertex attributes performed here.
114 * Fragment shader implemented here. SIMD aspects of EU taken full
115 * advantage of, as pixels are processed in blocks of 16.
117 * CC - Color Calculator. No EU threads associated with this unit.
118 * Handles blending and (presumably) depth and stencil testing.
122 #define BRW_MAX_CURBE (32*16)
125 struct brw_instruction
;
126 struct brw_vs_prog_key
;
127 struct brw_wm_prog_key
;
128 struct brw_wm_prog_data
;
132 BRW_STATE_FRAGMENT_PROGRAM
,
133 BRW_STATE_VERTEX_PROGRAM
,
134 BRW_STATE_INPUT_DIMENSIONS
,
135 BRW_STATE_CURBE_OFFSETS
,
136 BRW_STATE_REDUCED_PRIMITIVE
,
139 BRW_STATE_WM_INPUT_DIMENSIONS
,
142 BRW_STATE_VS_BINDING_TABLE
,
143 BRW_STATE_GS_BINDING_TABLE
,
144 BRW_STATE_PS_BINDING_TABLE
,
148 BRW_STATE_NR_WM_SURFACES
,
149 BRW_STATE_NR_VS_SURFACES
,
150 BRW_STATE_INDEX_BUFFER
,
151 BRW_STATE_VS_CONSTBUF
,
152 BRW_STATE_PROGRAM_CACHE
,
153 BRW_STATE_STATE_BASE_ADDRESS
,
154 BRW_STATE_SOL_INDICES
,
157 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
158 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
159 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
160 #define BRW_NEW_INPUT_DIMENSIONS (1 << BRW_STATE_INPUT_DIMENSIONS)
161 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
162 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
163 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
164 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
165 #define BRW_NEW_WM_INPUT_DIMENSIONS (1 << BRW_STATE_WM_INPUT_DIMENSIONS)
166 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
167 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
168 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
169 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
170 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
171 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
172 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
174 * Used for any batch entry with a relocated pointer that will be used
175 * by any 3D rendering.
177 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
178 /** \see brw.state.depth_region */
179 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
180 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
181 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
182 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
183 #define BRW_NEW_SOL_INDICES (1 << BRW_STATE_SOL_INDICES)
185 struct brw_state_flags
{
186 /** State update flags signalled by mesa internals */
189 * State update flags signalled as the result of brw_tracked_state updates
192 /** State update flags signalled by brw_state_cache.c searches */
196 #define AUB_TRACE_TYPE_MASK 0x0000ff00
197 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
198 #define AUB_TRACE_TYPE_BATCH (1 << 8)
199 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
200 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
201 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
202 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
203 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
204 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
205 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
206 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
207 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
208 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
211 * state_struct_type enum values are encoded with the top 16 bits representing
212 * the type to be delivered to the .aub file, and the bottom 16 bits
213 * representing the subtype. This macro performs the encoding.
215 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
217 enum state_struct_type
{
218 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
219 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
220 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
221 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
222 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
223 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
224 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
225 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
226 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
227 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
228 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
229 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
230 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
232 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
233 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
234 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
236 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
237 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
238 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
239 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
240 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
244 * Decode a state_struct_type value to determine the type that should be
245 * stored in the .aub file.
247 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
249 return (ss_type
& 0xFFFF0000) >> 16;
253 * Decode a state_struct_type value to determine the subtype that should be
254 * stored in the .aub file.
256 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
258 return ss_type
& 0xFFFF;
261 /** Subclass of Mesa vertex program */
262 struct brw_vertex_program
{
263 struct gl_vertex_program program
;
265 bool use_const_buffer
;
269 /** Subclass of Mesa fragment program */
270 struct brw_fragment_program
{
271 struct gl_fragment_program program
;
272 GLuint id
; /**< serial no. to identify frag progs, never re-used */
276 struct gl_shader base
;
278 /** Shader IR transformed for native compile, at link time. */
279 struct exec_list
*ir
;
282 struct brw_shader_program
{
283 struct gl_shader_program base
;
286 /* Data about a particular attempt to compile a program. Note that
287 * there can be many of these, each in a different GL state
288 * corresponding to a different brw_wm_prog_key struct, with different
291 struct brw_wm_prog_data
{
292 GLuint curb_read_length
;
293 GLuint urb_read_length
;
295 GLuint first_curbe_grf
;
296 GLuint first_curbe_grf_16
;
298 GLuint reg_blocks_16
;
299 GLuint total_scratch
;
301 GLuint nr_params
; /**< number of float params/constants */
302 GLuint nr_pull_params
;
306 uint32_t prog_offset_16
;
309 * Mask of which interpolation modes are required by the fragment shader.
310 * Used in hardware setup on gen6+.
312 uint32_t barycentric_interp_modes
;
314 /* Pointer to tracked values (only valid once
315 * _mesa_load_state_parameters has been called at runtime).
317 const float *param
[MAX_UNIFORMS
* 4]; /* should be: BRW_MAX_CURBE */
318 const float *pull_param
[MAX_UNIFORMS
* 4];
322 * Enum representing the i965-specific vertex results that don't correspond
323 * exactly to any element of gl_vert_result. The values of this enum are
324 * assigned such that they don't conflict with gl_vert_result.
328 BRW_VERT_RESULT_NDC
= VERT_RESULT_MAX
,
329 BRW_VERT_RESULT_HPOS_DUPLICATE
,
332 * It's actually not a vert_result but just a _mark_ to let sf aware that
333 * he need do something special to handle gl_PointCoord builtin variable
334 * correctly. see compile_sf_prog() for more info.
336 BRW_VERT_RESULT_PNTC
,
342 * Data structure recording the relationship between the gl_vert_result enum
343 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
344 * single octaword within the VUE (128 bits).
346 * Note that each BRW register contains 256 bits (2 octawords), so when
347 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
348 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
349 * in a vertex shader), each register corresponds to a single VUE slot, since
350 * it contains data for two separate vertices.
354 * Map from gl_vert_result value to VUE slot. For gl_vert_results that are
355 * not stored in a slot (because they are not written, or because
356 * additional processing is applied before storing them in the VUE), the
359 int vert_result_to_slot
[BRW_VERT_RESULT_MAX
];
362 * Map from VUE slot to gl_vert_result value. For slots that do not
363 * directly correspond to a gl_vert_result, the value comes from
366 * For slots that are not in use, the value is BRW_VERT_RESULT_MAX (this
367 * simplifies code that uses the value stored in slot_to_vert_result to
368 * create a bit mask).
370 int slot_to_vert_result
[BRW_VERT_RESULT_MAX
];
373 * Total number of VUE slots in use
379 * Convert a VUE slot number into a byte offset within the VUE.
381 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
387 * Convert a vert_result into a byte offset within the VUE.
389 static inline GLuint
brw_vert_result_to_offset(struct brw_vue_map
*vue_map
,
392 return brw_vue_slot_to_offset(vue_map
->vert_result_to_slot
[vert_result
]);
396 struct brw_sf_prog_data
{
397 GLuint urb_read_length
;
400 /* Each vertex may have upto 12 attributes, 4 components each,
401 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
404 * Actually we use 4 for each, so call it 12 rows.
406 GLuint urb_entry_size
;
409 struct brw_clip_prog_data
{
410 GLuint curb_read_length
; /* user planes? */
412 GLuint urb_read_length
;
416 struct brw_gs_prog_data
{
417 GLuint urb_read_length
;
421 * Gen6 transform feedback: Amount by which the streaming vertex buffer
422 * indices should be incremented each time the GS is invoked.
424 unsigned svbi_postincrement_value
;
427 struct brw_vs_prog_data
{
428 struct brw_vue_map vue_map
;
430 GLuint curb_read_length
;
431 GLuint urb_read_length
;
433 GLbitfield64 outputs_written
;
434 GLuint nr_params
; /**< number of float params/constants */
435 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
436 GLuint total_scratch
;
438 GLbitfield64 inputs_read
;
440 /* Used for calculating urb partitions:
442 GLuint urb_entry_size
;
444 const float *param
[MAX_UNIFORMS
* 4]; /* should be: BRW_MAX_CURBE */
445 const float *pull_param
[MAX_UNIFORMS
* 4];
447 bool uses_new_param_layout
;
455 /* Size == 0 if output either not written, or always [0,0,0,1]
457 struct brw_vs_ouput_sizes
{
458 GLubyte output_size
[VERT_RESULT_MAX
];
462 /** Number of texture sampler units */
463 #define BRW_MAX_TEX_UNIT 16
465 /** Max number of render targets in a shader */
466 #define BRW_MAX_DRAW_BUFFERS 8
469 * Max number of binding table entries used for stream output.
471 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
472 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
474 * On Gen6, the size of transform feedback data is limited not by the number
475 * of components but by the number of binding table entries we set aside. We
476 * use one binding table entry for a float, one entry for a vector, and one
477 * entry per matrix column. Since the only way we can communicate our
478 * transform feedback capabilities to the client is via
479 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
480 * worst case, in which all the varyings are floats, so we use up one binding
481 * table entry per component. Therefore we need to set aside at least 64
482 * binding table entries for use by transform feedback.
484 * Note: since we don't currently pack varyings, it is currently impossible
485 * for the client to actually use up all of these binding table entries--if
486 * all of their varyings were floats, they would run out of varying slots and
487 * fail to link. But that's a bug, so it seems prudent to go ahead and
488 * allocate the number of binding table entries we will need once the bug is
491 #define BRW_MAX_SOL_BINDINGS 64
493 /** Maximum number of actual buffers used for stream output */
494 #define BRW_MAX_SOL_BUFFERS 4
497 * Helpers to create Surface Binding Table indexes for draw buffers,
498 * textures, and constant buffers.
500 * Shader threads access surfaces via numeric handles, rather than directly
501 * using pointers. The binding table maps these numeric handles to the
502 * address of the actual buffer.
504 * For example, a shader might ask to sample from "surface 7." In this case,
505 * bind[7] would contain a pointer to a texture.
507 * Currently, our WM binding tables are (arbitrarily) programmed as follows:
509 * +-------------------------------+
510 * | 0 | Draw buffer 0 |
513 * | 7 | Draw buffer 7 |
514 * |-----|-------------------------|
515 * | 8 | WM Pull Constant Buffer |
516 * |-----|-------------------------|
520 * | 24 | Texture 15 |
521 * +-------------------------------+
523 * Our VS binding tables are programmed as follows:
525 * +-----+-------------------------+
526 * | 0 | VS Pull Constant Buffer |
527 * +-----+-------------------------+
531 * | 16 | Texture 15 |
532 * +-------------------------------+
534 * Our (gen6) GS binding tables are programmed as follows:
536 * +-----+-------------------------+
537 * | 0 | SOL Binding 0 |
540 * | 63 | SOL Binding 63 |
541 * +-----+-------------------------+
543 * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be
544 * the identity function or things will break. We do want to keep draw buffers
545 * first so we can use headerless render target writes for RT 0.
547 #define SURF_INDEX_DRAW(d) (d)
548 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
549 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
551 /** Maximum size of the binding table. */
552 #define BRW_MAX_WM_SURFACES SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT)
554 #define SURF_INDEX_VERT_CONST_BUFFER (0)
555 #define SURF_INDEX_VS_TEXTURE(t) (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t))
556 #define BRW_MAX_VS_SURFACES SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT)
558 #define SURF_INDEX_SOL_BINDING(t) ((t))
559 #define BRW_MAX_GS_SURFACES SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
563 BRW_DEPTH_STENCIL_STATE
,
564 BRW_COLOR_CALC_STATE
,
573 BRW_SF_UNIT
, /* scissor state on gen6 */
585 struct brw_cache_item
{
587 * Effectively part of the key, cache_id identifies what kind of state
588 * buffer is involved, and also which brw->state.dirty.cache flag should
589 * be set when this cache item is chosen.
591 enum brw_cache_id cache_id
;
592 /** 32-bit hash of the key data */
594 GLuint key_size
; /* for variable-sized keys */
601 struct brw_cache_item
*next
;
607 struct brw_context
*brw
;
609 struct brw_cache_item
**items
;
611 GLuint size
, n_items
;
613 uint32_t next_offset
;
618 /* Considered adding a member to this struct to document which flags
619 * an update might raise so that ordering of the state atoms can be
620 * checked or derived at runtime. Dropped the idea in favor of having
621 * a debug mode where the state is monitored for flags which are
622 * raised that have already been tested against.
624 struct brw_tracked_state
{
625 struct brw_state_flags dirty
;
626 void (*emit
)( struct brw_context
*brw
);
629 /* Flags for brw->state.cache.
631 #define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE)
632 #define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE)
633 #define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE)
634 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
635 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
636 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
637 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
638 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
639 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
640 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
641 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
642 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
643 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
644 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
645 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
646 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
647 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
648 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
650 struct brw_cached_batch_item
{
651 struct header
*header
;
653 struct brw_cached_batch_item
*next
;
658 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
659 * be easier if C allowed arrays of packed elements?
661 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
663 struct brw_vertex_buffer
{
664 /** Buffer object containing the uploaded vertex data */
667 /** Byte stride between elements in the uploaded array */
671 struct brw_vertex_element
{
672 const struct gl_client_array
*glarray
;
676 /** The corresponding Mesa vertex attribute */
677 gl_vert_attrib attrib
;
678 /** Size of a complete element */
680 /** Offset of the first element within the buffer object */
686 struct brw_vertex_info
{
687 GLuint sizes
[ATTRIB_BIT_DWORDS
* 2]; /* sizes:2[VERT_ATTRIB_MAX] */
690 struct brw_query_object
{
691 struct gl_query_object Base
;
693 /** Last query BO associated with this query. */
695 /** First index in bo with query data for this object. */
697 /** Last index in bo with query data for this object. */
703 * brw_context is derived from intel_context.
707 struct intel_context intel
; /**< base class, must be first field */
708 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
710 bool emit_state_always
;
711 bool has_surface_tile_offset
;
713 bool has_negative_rhw_bug
;
714 bool has_aa_line_parameters
;
719 * Some versions of Gen hardware don't do centroid interpolation correctly
720 * on unlit pixels, causing incorrect values for derivatives near triangle
721 * edges. Enabling this flag causes the fragment shader to use
722 * non-centroid interpolation for unlit pixels, at the expense of two extra
723 * fragment shader instructions.
725 bool needs_unlit_centroid_workaround
;
728 struct brw_state_flags dirty
;
731 struct brw_cache cache
;
732 struct brw_cached_batch_item
*cached_batch_items
;
735 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
736 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
742 } current_buffers
[VERT_ATTRIB_MAX
];
744 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
746 GLuint nr_buffers
, nr_current_buffers
;
748 /* Summary of size and varying of active arrays, so we can check
749 * for changes to this state:
751 struct brw_vertex_info info
;
752 unsigned int min_index
, max_index
;
754 /* Offset from start of vertex buffer so we can avoid redefining
755 * the same VB packed over and over again.
757 unsigned int start_vertex_bias
;
762 * Index buffer for this draw_prims call.
764 * Updates are signaled by BRW_NEW_INDICES.
766 const struct _mesa_index_buffer
*ib
;
768 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
772 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
773 * avoid re-uploading the IB packet over and over if we're actually
774 * referencing the same index buffer.
776 unsigned int start_vertex_offset
;
779 /* Active vertex program:
781 const struct gl_vertex_program
*vertex_program
;
782 const struct gl_fragment_program
*fragment_program
;
784 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
785 uint32_t CMD_VF_STATISTICS
;
786 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
787 uint32_t CMD_PIPELINE_SELECT
;
790 * Platform specific constants containing the maximum number of threads
791 * for each pipeline stage.
797 /* BRW_NEW_URB_ALLOCATIONS:
800 GLuint vsize
; /* vertex size plus header in urb registers */
801 GLuint csize
; /* constant buffer size in urb registers */
802 GLuint sfsize
; /* setup data size in urb registers */
806 GLuint max_vs_entries
; /* Maximum number of VS entries */
807 GLuint max_gs_entries
; /* Maximum number of GS entries */
809 GLuint nr_vs_entries
;
810 GLuint nr_gs_entries
;
811 GLuint nr_clip_entries
;
812 GLuint nr_sf_entries
;
813 GLuint nr_cs_entries
;
816 * The length of each URB entry owned by the VS (or GS), as
817 * a number of 1024-bit (128-byte) rows. Should be >= 1.
819 * gen7: Same meaning, but in 512-bit (64-byte) rows.
829 GLuint size
; /* Hardware URB size, in KB. */
831 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
832 * URB space for the GS.
834 bool gen6_gs_previously_active
;
838 /* BRW_NEW_CURBE_OFFSETS:
841 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
842 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
849 drm_intel_bo
*curbe_bo
;
850 /** Offset within curbe_bo of space for current curbe entry */
852 /** Offset within curbe_bo of space for next curbe entry */
853 GLuint curbe_next_offset
;
856 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
857 * in brw_curbe.c with the same set of constant data to be uploaded,
858 * so we'd rather not upload new constants in that case (it can cause
859 * a pipeline bubble since only up to 4 can be pipelined at a time).
863 * Allocation for where to calculate the next set of CURBEs.
864 * It's a hot enough path that malloc/free of that data matters.
870 /** SAMPLER_STATE count and offset */
877 struct brw_vs_prog_data
*prog_data
;
878 int8_t *constant_map
; /* variable array following prog_data */
880 drm_intel_bo
*scratch_bo
;
881 drm_intel_bo
*const_bo
;
882 /** Offset in the program cache to the VS program */
883 uint32_t prog_offset
;
884 uint32_t state_offset
;
886 uint32_t push_const_offset
; /* Offset in the batchbuffer */
887 int push_const_size
; /* in 256-bit register increments */
889 /** @{ register allocator */
891 struct ra_regs
*regs
;
894 * Array of the ra classes for the unaligned contiguous register
900 * Mapping for register-allocated objects in *regs to the first
901 * GRF for that object.
903 uint8_t *ra_reg_to_grf
;
906 uint32_t bind_bo_offset
;
907 uint32_t surf_offset
[BRW_MAX_VS_SURFACES
];
911 struct brw_gs_prog_data
*prog_data
;
914 /** Offset in the program cache to the CLIP program pre-gen6 */
915 uint32_t prog_offset
;
916 uint32_t state_offset
;
918 uint32_t bind_bo_offset
;
919 uint32_t surf_offset
[BRW_MAX_GS_SURFACES
];
923 struct brw_clip_prog_data
*prog_data
;
925 /** Offset in the program cache to the CLIP program pre-gen6 */
926 uint32_t prog_offset
;
928 /* Offset in the batch to the CLIP state on pre-gen6. */
929 uint32_t state_offset
;
931 /* As of gen6, this is the offset in the batch to the CLIP VP,
939 struct brw_sf_prog_data
*prog_data
;
941 /** Offset in the program cache to the CLIP program pre-gen6 */
942 uint32_t prog_offset
;
943 uint32_t state_offset
;
948 struct brw_wm_prog_data
*prog_data
;
949 struct brw_wm_compile
*compile_data
;
951 /** Input sizes, calculated from active vertex program.
952 * One bit per fragment program input attribute.
954 GLbitfield input_size_masks
[4];
956 /** offsets in the batch to sampler default colors (texture border color)
958 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
962 drm_intel_bo
*scratch_bo
;
965 * Buffer object used in place of multisampled null render targets on
966 * Gen6. See brw_update_null_renderbuffer_surface().
968 drm_intel_bo
*multisampled_null_render_target_bo
;
970 /** Offset in the program cache to the WM program */
971 uint32_t prog_offset
;
973 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
975 drm_intel_bo
*const_bo
; /* pull constant buffer. */
977 * This is offset in the batch to the push constants on gen6.
979 * Pre-gen6, push constants live in the CURBE.
981 uint32_t push_const_offset
;
983 /** Binding table of pointers to surf_bo entries */
984 uint32_t bind_bo_offset
;
985 uint32_t surf_offset
[BRW_MAX_WM_SURFACES
];
987 /** @{ register allocator */
989 struct ra_regs
*regs
;
991 /** Array of the ra classes for the unaligned contiguous
992 * register block sizes used.
997 * Mapping for register-allocated objects in *regs to the first
998 * GRF for that object.
1000 uint8_t *ra_reg_to_grf
;
1003 * ra class for the aligned pairs we use for PLN, which doesn't
1004 * appear in *classes.
1006 int aligned_pairs_class
;
1013 uint32_t state_offset
;
1014 uint32_t blend_state_offset
;
1015 uint32_t depth_stencil_state_offset
;
1020 struct brw_query_object
*obj
;
1025 /* Used to give every program string a unique id
1030 const struct brw_tracked_state
**atoms
;
1032 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1036 enum state_struct_type type
;
1037 } *state_batch_list
;
1038 int state_batch_count
;
1040 struct brw_sol_state
{
1041 uint32_t svbi_0_starting_index
;
1042 uint32_t svbi_0_max_index
;
1043 uint32_t offset_0_batch_start
;
1044 uint32_t primitives_generated
;
1045 uint32_t primitives_written
;
1046 bool counting_primitives_generated
;
1047 bool counting_primitives_written
;
1050 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1051 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1053 /* PrimitiveRestart */
1056 bool enable_cut_index
;
1059 uint32_t num_instances
;
1064 #define BRW_PACKCOLOR8888(r,g,b,a) ((r<<24) | (g<<16) | (b<<8) | a)
1066 struct brw_instruction_info
{
1072 extern const struct brw_instruction_info brw_opcodes
[128];
1074 /*======================================================================
1077 void brwInitVtbl( struct brw_context
*brw
);
1079 /*======================================================================
1082 bool brwCreateContext(int api
,
1083 const struct gl_config
*mesaVis
,
1084 __DRIcontext
*driContextPriv
,
1085 void *sharedContextPrivate
);
1087 /*======================================================================
1090 void brw_init_queryobj_functions(struct dd_function_table
*functions
);
1091 void brw_prepare_query_begin(struct brw_context
*brw
);
1092 void brw_emit_query_begin(struct brw_context
*brw
);
1093 void brw_emit_query_end(struct brw_context
*brw
);
1095 /*======================================================================
1098 void brw_debug_batch(struct intel_context
*intel
);
1099 void brw_annotate_aub(struct intel_context
*intel
);
1101 /*======================================================================
1104 void brw_validate_textures( struct brw_context
*brw
);
1107 /*======================================================================
1110 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1112 int brw_get_scratch_size(int size
);
1113 void brw_get_scratch_bo(struct intel_context
*intel
,
1114 drm_intel_bo
**scratch_bo
, int size
);
1119 void brw_upload_urb_fence(struct brw_context
*brw
);
1123 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1126 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1129 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1131 /* brw_wm_surface_state.c */
1132 void brw_init_surface_formats(struct brw_context
*brw
);
1134 brw_update_sol_surface(struct brw_context
*brw
,
1135 struct gl_buffer_object
*buffer_obj
,
1136 uint32_t *out_offset
, unsigned num_vector_components
,
1137 unsigned stride_dwords
, unsigned offset_dwords
);
1141 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1142 struct gl_transform_feedback_object
*obj
);
1144 brw_end_transform_feedback(struct gl_context
*ctx
,
1145 struct gl_transform_feedback_object
*obj
);
1147 /* gen7_sol_state.c */
1149 gen7_end_transform_feedback(struct gl_context
*ctx
,
1150 struct gl_transform_feedback_object
*obj
);
1152 /* brw_blorp_blit.cpp */
1154 brw_blorp_framebuffer(struct intel_context
*intel
,
1155 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1156 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1157 GLbitfield mask
, GLenum filter
);
1159 /* gen6_multisample_state.c */
1161 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1162 unsigned num_samples
);
1164 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
,
1165 unsigned num_samples
, float coverage
,
1166 bool coverage_invert
);
1170 gen7_allocate_push_constants(struct brw_context
*brw
);
1173 gen7_emit_urb_state(struct brw_context
*brw
, GLuint nr_vs_entries
,
1174 GLuint vs_size
, GLuint vs_start
);
1178 /*======================================================================
1179 * Inline conversion functions. These are better-typed than the
1180 * macros used previously:
1182 static INLINE
struct brw_context
*
1183 brw_context( struct gl_context
*ctx
)
1185 return (struct brw_context
*)ctx
;
1188 static INLINE
struct brw_vertex_program
*
1189 brw_vertex_program(struct gl_vertex_program
*p
)
1191 return (struct brw_vertex_program
*) p
;
1194 static INLINE
const struct brw_vertex_program
*
1195 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1197 return (const struct brw_vertex_program
*) p
;
1200 static INLINE
struct brw_fragment_program
*
1201 brw_fragment_program(struct gl_fragment_program
*p
)
1203 return (struct brw_fragment_program
*) p
;
1206 static INLINE
const struct brw_fragment_program
*
1207 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1209 return (const struct brw_fragment_program
*) p
;
1213 * Pre-gen6, the register file of the EUs was shared between threads,
1214 * and each thread used some subset allocated on a 16-register block
1215 * granularity. The unit states wanted these block counts.
1218 brw_register_blocks(int reg_count
)
1220 return ALIGN(reg_count
, 16) / 16 - 1;
1223 static inline uint32_t
1224 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1225 uint32_t prog_offset
)
1227 struct intel_context
*intel
= &brw
->intel
;
1229 if (intel
->gen
>= 5) {
1230 /* Using state base address. */
1234 drm_intel_bo_emit_reloc(intel
->batch
.bo
,
1238 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1240 return brw
->cache
.bo
->offset
+ prog_offset
;
1243 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1244 bool brw_lower_texture_gradients(struct exec_list
*instructions
);