2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
47 * URB - uniform resource buffer. A mid-sized buffer which is
48 * partitioned between the fixed function units and used for passing
49 * values (vertices, primitives, constants) between them.
51 * CURBE - constant URB entry. An urb region (entry) used to hold
52 * constant values which the fixed function units can be instructed to
53 * preload into the GRF when spawning a thread.
55 * VUE - vertex URB entry. An urb entry holding a vertex and usually
56 * a vertex header. The header contains control information and
57 * things like primitive type, Begin/end flags and clip codes.
59 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
60 * unit holding rasterization and interpolation parameters.
62 * GRF - general register file. One of several register files
63 * addressable by programmed threads. The inputs (r0, payload, curbe,
64 * urb) of the thread are preloaded to this area before the thread is
65 * spawned. The registers are individually 8 dwords wide and suitable
66 * for general usage. Registers holding thread input values are not
67 * special and may be overwritten.
69 * MRF - message register file. Threads communicate (and terminate)
70 * by sending messages. Message parameters are placed in contiguous
71 * MRF registers. All program output is via these messages. URB
72 * entries are populated by sending a message to the shared URB
73 * function containing the new data, together with a control word,
74 * often an unmodified copy of R0.
76 * R0 - GRF register 0. Typically holds control information used when
77 * sending messages to other threads.
79 * EU or GEN4 EU: The name of the programmable subsystem of the
80 * i965 hardware. Threads are executed by the EU, the registers
81 * described above are part of the EU architecture.
83 * Fixed function units:
85 * CS - Command streamer. Notional first unit, little software
86 * interaction. Holds the URB entries used for constant data, ie the
89 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
90 * this unit is responsible for pulling vertices out of vertex buffers
91 * in vram and injecting them into the processing pipe as VUEs. If
92 * enabled, it first passes them to a VS thread which is a good place
93 * for the driver to implement any active vertex shader.
95 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
96 * enabled, incoming strips etc are passed to GS threads in individual
97 * line/triangle/point units. The GS thread may perform arbitary
98 * computation and emit whatever primtives with whatever vertices it
99 * chooses. This makes GS an excellent place to implement GL's
100 * unfilled polygon modes, though of course it is capable of much
101 * more. Additionally, GS is used to translate away primitives not
102 * handled by latter units, including Quads and Lineloops.
104 * CS - Clipper. Mesa's clipping algorithms are imported to run on
105 * this unit. The fixed function part performs cliptesting against
106 * the 6 fixed clipplanes and makes descisions on whether or not the
107 * incoming primitive needs to be passed to a thread for clipping.
108 * User clip planes are handled via cooperation with the VS thread.
110 * SF - Strips Fans or Setup: Triangles are prepared for
111 * rasterization. Interpolation coefficients are calculated.
112 * Flatshading and two-side lighting usually performed here.
114 * WM - Windower. Interpolation of vertex attributes performed here.
115 * Fragment shader implemented here. SIMD aspects of EU taken full
116 * advantage of, as pixels are processed in blocks of 16.
118 * CC - Color Calculator. No EU threads associated with this unit.
119 * Handles blending and (presumably) depth and stencil testing.
123 #define BRW_MAX_CURBE (32*16)
126 struct brw_instruction
;
127 struct brw_vs_prog_key
;
128 struct brw_vec4_prog_key
;
129 struct brw_wm_prog_key
;
130 struct brw_wm_prog_data
;
134 BRW_STATE_FRAGMENT_PROGRAM
,
135 BRW_STATE_GEOMETRY_PROGRAM
,
136 BRW_STATE_VERTEX_PROGRAM
,
137 BRW_STATE_CURBE_OFFSETS
,
138 BRW_STATE_REDUCED_PRIMITIVE
,
143 BRW_STATE_VS_BINDING_TABLE
,
144 BRW_STATE_GS_BINDING_TABLE
,
145 BRW_STATE_PS_BINDING_TABLE
,
149 BRW_STATE_INDEX_BUFFER
,
150 BRW_STATE_VS_CONSTBUF
,
151 BRW_STATE_GS_CONSTBUF
,
152 BRW_STATE_PROGRAM_CACHE
,
153 BRW_STATE_STATE_BASE_ADDRESS
,
154 BRW_STATE_VUE_MAP_VS
,
155 BRW_STATE_VUE_MAP_GEOM_OUT
,
156 BRW_STATE_TRANSFORM_FEEDBACK
,
157 BRW_STATE_RASTERIZER_DISCARD
,
159 BRW_STATE_UNIFORM_BUFFER
,
160 BRW_STATE_META_IN_PROGRESS
,
161 BRW_STATE_INTERPOLATION_MAP
,
162 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
166 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
167 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
168 #define BRW_NEW_GEOMETRY_PROGRAM (1 << BRW_STATE_GEOMETRY_PROGRAM)
169 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
170 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
171 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
172 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
173 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
174 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
175 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
176 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
177 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
178 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
179 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
180 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
182 * Used for any batch entry with a relocated pointer that will be used
183 * by any 3D rendering.
185 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
186 /** \see brw.state.depth_region */
187 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
188 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
189 #define BRW_NEW_GS_CONSTBUF (1 << BRW_STATE_GS_CONSTBUF)
190 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
191 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
192 #define BRW_NEW_VUE_MAP_VS (1 << BRW_STATE_VUE_MAP_VS)
193 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
194 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
195 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
196 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
197 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
198 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
199 #define BRW_NEW_INTERPOLATION_MAP (1 << BRW_STATE_INTERPOLATION_MAP)
200 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1 << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
202 struct brw_state_flags
{
203 /** State update flags signalled by mesa internals */
206 * State update flags signalled as the result of brw_tracked_state updates
209 /** State update flags signalled by brw_state_cache.c searches */
213 #define AUB_TRACE_TYPE_MASK 0x0000ff00
214 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
215 #define AUB_TRACE_TYPE_BATCH (1 << 8)
216 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
217 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
218 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
219 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
220 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
221 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
222 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
223 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
224 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
225 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
228 * state_struct_type enum values are encoded with the top 16 bits representing
229 * the type to be delivered to the .aub file, and the bottom 16 bits
230 * representing the subtype. This macro performs the encoding.
232 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
234 enum state_struct_type
{
235 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
236 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
237 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
238 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
239 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
240 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
241 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
242 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
243 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
244 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
245 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
246 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
247 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
249 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
250 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
251 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
253 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
254 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
255 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
256 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
257 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
261 * Decode a state_struct_type value to determine the type that should be
262 * stored in the .aub file.
264 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
266 return (ss_type
& 0xFFFF0000) >> 16;
270 * Decode a state_struct_type value to determine the subtype that should be
271 * stored in the .aub file.
273 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
275 return ss_type
& 0xFFFF;
278 /** Subclass of Mesa vertex program */
279 struct brw_vertex_program
{
280 struct gl_vertex_program program
;
285 /** Subclass of Mesa geometry program */
286 struct brw_geometry_program
{
287 struct gl_geometry_program program
;
288 unsigned id
; /**< serial no. to identify geom progs, never re-used */
292 /** Subclass of Mesa fragment program */
293 struct brw_fragment_program
{
294 struct gl_fragment_program program
;
295 GLuint id
; /**< serial no. to identify frag progs, never re-used */
299 struct gl_shader base
;
303 /** Shader IR transformed for native compile, at link time. */
304 struct exec_list
*ir
;
307 /* Data about a particular attempt to compile a program. Note that
308 * there can be many of these, each in a different GL state
309 * corresponding to a different brw_wm_prog_key struct, with different
312 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
315 struct brw_wm_prog_data
{
316 GLuint curb_read_length
;
317 GLuint num_varying_inputs
;
319 GLuint first_curbe_grf
;
320 GLuint first_curbe_grf_16
;
322 GLuint reg_blocks_16
;
323 GLuint total_scratch
;
325 unsigned binding_table_size
;
327 GLuint nr_params
; /**< number of float params/constants */
328 GLuint nr_pull_params
;
331 uint32_t prog_offset_16
;
334 * Mask of which interpolation modes are required by the fragment shader.
335 * Used in hardware setup on gen6+.
337 uint32_t barycentric_interp_modes
;
340 * Map from gl_varying_slot to the position within the FS setup data
341 * payload where the varying's attribute vertex deltas should be delivered.
342 * For varying slots that are not used by the FS, the value is -1.
344 int urb_setup
[VARYING_SLOT_MAX
];
346 /* Pointers to tracked values (only valid once
347 * _mesa_load_state_parameters has been called at runtime).
349 * These must be the last fields of the struct (see
350 * brw_wm_prog_data_compare()).
353 const float **pull_param
;
357 * Enum representing the i965-specific vertex results that don't correspond
358 * exactly to any element of gl_varying_slot. The values of this enum are
359 * assigned such that they don't conflict with gl_varying_slot.
363 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
364 BRW_VARYING_SLOT_PAD
,
366 * Technically this is not a varying but just a placeholder that
367 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
368 * builtin variable to be compiled correctly. see compile_sf_prog() for
371 BRW_VARYING_SLOT_PNTC
,
372 BRW_VARYING_SLOT_COUNT
377 * Data structure recording the relationship between the gl_varying_slot enum
378 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
379 * single octaword within the VUE (128 bits).
381 * Note that each BRW register contains 256 bits (2 octawords), so when
382 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
383 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
384 * in a vertex shader), each register corresponds to a single VUE slot, since
385 * it contains data for two separate vertices.
389 * Bitfield representing all varying slots that are (a) stored in this VUE
390 * map, and (b) actually written by the shader. Does not include any of
391 * the additional varying slots defined in brw_varying_slot.
393 GLbitfield64 slots_valid
;
396 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
397 * not stored in a slot (because they are not written, or because
398 * additional processing is applied before storing them in the VUE), the
401 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
404 * Map from VUE slot to gl_varying_slot value. For slots that do not
405 * directly correspond to a gl_varying_slot, the value comes from
408 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
409 * simplifies code that uses the value stored in slot_to_varying to
410 * create a bit mask).
412 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
415 * Total number of VUE slots in use
421 * Convert a VUE slot number into a byte offset within the VUE.
423 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
429 * Convert a vertex output (brw_varying_slot) into a byte offset within the
432 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
435 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
438 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
439 GLbitfield64 slots_valid
);
443 * Bitmask indicating which fragment shader inputs represent varyings (and
444 * hence have to be delivered to the fragment shader by the SF/SBE stage).
446 #define BRW_FS_VARYING_INPUT_MASK \
447 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
448 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
452 * Mapping of VUE map slots to interpolation modes.
454 struct interpolation_mode_map
{
455 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
458 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
460 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
461 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
467 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
469 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
470 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
477 struct brw_sf_prog_data
{
478 GLuint urb_read_length
;
481 /* Each vertex may have upto 12 attributes, 4 components each,
482 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
485 * Actually we use 4 for each, so call it 12 rows.
487 GLuint urb_entry_size
;
492 * We always program SF to start reading at an offset of 1 (2 varying slots)
493 * from the start of the vertex URB entry. This causes it to skip:
494 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
495 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
497 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
500 struct brw_clip_prog_data
{
501 GLuint curb_read_length
; /* user planes? */
503 GLuint urb_read_length
;
507 struct brw_ff_gs_prog_data
{
508 GLuint urb_read_length
;
512 * Gen6 transform feedback: Amount by which the streaming vertex buffer
513 * indices should be incremented each time the GS is invoked.
515 unsigned svbi_postincrement_value
;
519 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
522 struct brw_vec4_prog_data
{
523 struct brw_vue_map vue_map
;
526 * Register where the thread expects to find input data from the URB
527 * (typically uniforms, followed by per-vertex inputs).
529 unsigned dispatch_grf_start_reg
;
531 GLuint curb_read_length
;
532 GLuint urb_read_length
;
534 GLuint nr_params
; /**< number of float params/constants */
535 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
536 GLuint total_scratch
;
538 /* Used for calculating urb partitions. In the VS, this is the size of the
539 * URB entry used for both input and output to the thread. In the GS, this
540 * is the size of the URB entry used for output.
542 GLuint urb_entry_size
;
544 unsigned binding_table_size
;
546 /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
548 const float **pull_param
;
552 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
555 struct brw_vs_prog_data
{
556 struct brw_vec4_prog_data base
;
558 GLbitfield64 inputs_read
;
564 /* Note: brw_gs_prog_data_compare() must be updated when adding fields to
567 struct brw_gs_prog_data
569 struct brw_vec4_prog_data base
;
572 * Size of an output vertex, measured in HWORDS (32 bytes).
574 unsigned output_vertex_size_hwords
;
576 unsigned output_topology
;
579 * Size of the control data (cut bits or StreamID bits), in hwords (32
580 * bytes). 0 if there is no control data.
582 unsigned control_data_header_size_hwords
;
585 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
586 * if the control data is StreamID bits, or
587 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
588 * Ignored if control_data_header_size is 0.
590 unsigned control_data_format
;
593 /** Number of texture sampler units */
594 #define BRW_MAX_TEX_UNIT 16
596 /** Max number of render targets in a shader */
597 #define BRW_MAX_DRAW_BUFFERS 8
600 * Max number of binding table entries used for stream output.
602 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
603 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
605 * On Gen6, the size of transform feedback data is limited not by the number
606 * of components but by the number of binding table entries we set aside. We
607 * use one binding table entry for a float, one entry for a vector, and one
608 * entry per matrix column. Since the only way we can communicate our
609 * transform feedback capabilities to the client is via
610 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
611 * worst case, in which all the varyings are floats, so we use up one binding
612 * table entry per component. Therefore we need to set aside at least 64
613 * binding table entries for use by transform feedback.
615 * Note: since we don't currently pack varyings, it is currently impossible
616 * for the client to actually use up all of these binding table entries--if
617 * all of their varyings were floats, they would run out of varying slots and
618 * fail to link. But that's a bug, so it seems prudent to go ahead and
619 * allocate the number of binding table entries we will need once the bug is
622 #define BRW_MAX_SOL_BINDINGS 64
624 /** Maximum number of actual buffers used for stream output */
625 #define BRW_MAX_SOL_BUFFERS 4
627 #define BRW_MAX_WM_UBOS 12
628 #define BRW_MAX_VS_UBOS 12
631 * Helpers to create Surface Binding Table indexes for draw buffers,
632 * textures, and constant buffers.
634 * Shader threads access surfaces via numeric handles, rather than directly
635 * using pointers. The binding table maps these numeric handles to the
636 * address of the actual buffer.
638 * For example, a shader might ask to sample from "surface 7." In this case,
639 * bind[7] would contain a pointer to a texture.
641 * Currently, our WM binding tables are (arbitrarily) programmed as follows:
643 * +-------------------------------+
644 * | 0 | Draw buffer 0 |
647 * | 7 | Draw buffer 7 |
648 * |-----|-------------------------|
649 * | 8 | WM Pull Constant Buffer |
650 * |-----|-------------------------|
654 * | 24 | Texture 15 |
655 * |-----|-------------------------|
660 * +-------------------------------+
662 * Our VS (and Gen7 GS) binding tables are programmed as follows:
664 * +-----+-------------------------+
665 * | 0 | Pull Constant Buffer |
666 * +-----+-------------------------+
670 * | 16 | Texture 15 |
671 * +-----+-------------------------+
676 * +-------------------------------+
678 * Our (gen6) GS binding tables are programmed as follows:
680 * +-----+-------------------------+
681 * | 0 | SOL Binding 0 |
684 * | 63 | SOL Binding 63 |
685 * +-----+-------------------------+
687 #define SURF_INDEX_DRAW(d) (d)
688 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
689 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
690 #define SURF_INDEX_WM_UBO(u) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)
691 #define SURF_INDEX_WM_SHADER_TIME (SURF_INDEX_WM_UBO(12))
692 /** Maximum size of the binding table. */
693 #define BRW_MAX_WM_SURFACES (SURF_INDEX_WM_SHADER_TIME + 1)
695 #define SURF_INDEX_VEC4_CONST_BUFFER (0)
696 #define SURF_INDEX_VEC4_TEXTURE(t) (SURF_INDEX_VEC4_CONST_BUFFER + 1 + (t))
697 #define SURF_INDEX_VEC4_UBO(u) (SURF_INDEX_VEC4_TEXTURE(BRW_MAX_TEX_UNIT) + u)
698 #define SURF_INDEX_VEC4_SHADER_TIME (SURF_INDEX_VEC4_UBO(12))
699 #define BRW_MAX_VEC4_SURFACES (SURF_INDEX_VEC4_SHADER_TIME + 1)
701 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
702 #define BRW_MAX_GEN6_GS_SURFACES SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
705 * Stride in bytes between shader_time entries.
707 * We separate entries by a cacheline to reduce traffic between EUs writing to
710 #define SHADER_TIME_STRIDE 64
717 BRW_BLORP_CONST_COLOR_PROG
,
722 BRW_SF_UNIT
, /* scissor state on gen6 */
735 struct brw_cache_item
{
737 * Effectively part of the key, cache_id identifies what kind of state
738 * buffer is involved, and also which brw->state.dirty.cache flag should
739 * be set when this cache item is chosen.
741 enum brw_cache_id cache_id
;
742 /** 32-bit hash of the key data */
744 GLuint key_size
; /* for variable-sized keys */
751 struct brw_cache_item
*next
;
755 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
,
756 int aux_size
, const void *key
);
757 typedef void (*cache_aux_free_func
)(const void *aux
);
760 struct brw_context
*brw
;
762 struct brw_cache_item
**items
;
764 GLuint size
, n_items
;
766 uint32_t next_offset
;
770 * Optional functions used in determining whether the prog_data for a new
771 * cache item matches an existing cache item (in case there's relevant data
772 * outside of the prog_data). If NULL, a plain memcmp is done.
774 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
775 /** Optional functions for freeing other pointers attached to a prog_data. */
776 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
780 /* Considered adding a member to this struct to document which flags
781 * an update might raise so that ordering of the state atoms can be
782 * checked or derived at runtime. Dropped the idea in favor of having
783 * a debug mode where the state is monitored for flags which are
784 * raised that have already been tested against.
786 struct brw_tracked_state
{
787 struct brw_state_flags dirty
;
788 void (*emit
)( struct brw_context
*brw
);
791 enum shader_time_shader_type
{
804 /* Flags for brw->state.cache.
806 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
807 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
808 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
809 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
810 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
811 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
812 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
813 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
814 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
815 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
816 #define CACHE_NEW_FF_GS_UNIT (1<<BRW_FF_GS_UNIT)
817 #define CACHE_NEW_FF_GS_PROG (1<<BRW_FF_GS_PROG)
818 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
819 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
820 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
821 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
823 struct brw_cached_batch_item
{
824 struct header
*header
;
826 struct brw_cached_batch_item
*next
;
829 struct brw_vertex_buffer
{
830 /** Buffer object containing the uploaded vertex data */
833 /** Byte stride between elements in the uploaded array */
837 struct brw_vertex_element
{
838 const struct gl_client_array
*glarray
;
842 /** The corresponding Mesa vertex attribute */
843 gl_vert_attrib attrib
;
844 /** Offset of the first element within the buffer object */
848 struct brw_query_object
{
849 struct gl_query_object Base
;
851 /** Last query BO associated with this query. */
854 /** Last index in bo with query data for this object. */
860 * Data shared between brw_context::vs and brw_context::gs
862 struct brw_stage_state
865 * Optional scratch buffer used to store spilled register values and
866 * variably-indexed GRF arrays.
868 drm_intel_bo
*scratch_bo
;
870 /** Pull constant buffer */
871 drm_intel_bo
*const_bo
;
873 /** Offset in the program cache to the program */
874 uint32_t prog_offset
;
876 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
877 uint32_t state_offset
;
879 uint32_t push_const_offset
; /* Offset in the batchbuffer */
880 int push_const_size
; /* in 256-bit register increments */
882 /* Binding table: pointers to SURFACE_STATE entries. */
883 uint32_t bind_bo_offset
;
884 uint32_t surf_offset
[BRW_MAX_WM_SURFACES
];
886 /** SAMPLER_STATE count and table offset */
887 uint32_t sampler_count
;
888 uint32_t sampler_offset
;
890 /** Offsets in the batch to sampler default colors (texture border color) */
891 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
896 * brw_context is derived from gl_context.
900 struct gl_context ctx
; /**< base class, must be first field */
904 void (*destroy
) (struct brw_context
* brw
);
905 void (*finish_batch
) (struct brw_context
* brw
);
906 void (*new_batch
) (struct brw_context
* brw
);
908 void (*update_texture_surface
)(struct gl_context
*ctx
,
910 uint32_t *surf_offset
);
911 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
912 struct gl_renderbuffer
*rb
,
915 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
917 void (*create_constant_surface
)(struct brw_context
*brw
,
921 uint32_t *out_offset
,
924 /** Upload a SAMPLER_STATE table. */
925 void (*upload_sampler_state_table
)(struct brw_context
*brw
,
926 struct gl_program
*prog
,
927 uint32_t sampler_count
,
928 uint32_t *sst_offset
,
929 uint32_t *sdc_offset
);
932 * Send the appropriate state packets to configure depth, stencil, and
933 * HiZ buffers (i965+ only)
935 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
936 struct intel_mipmap_tree
*depth_mt
,
937 uint32_t depth_offset
,
938 uint32_t depthbuffer_format
,
939 uint32_t depth_surface_type
,
940 struct intel_mipmap_tree
*stencil_mt
,
941 bool hiz
, bool separate_stencil
,
942 uint32_t width
, uint32_t height
,
943 uint32_t tile_x
, uint32_t tile_y
);
949 drm_intel_context
*hw_ctx
;
951 struct intel_batchbuffer batch
;
958 uint32_t buffer_offset
;
963 * Set if rendering has occured to the drawable's front buffer.
965 * This is used in the DRI2 case to detect that glFlush should also copy
966 * the contents of the fake front buffer to the real front buffer.
968 bool front_buffer_dirty
;
971 * Track whether front-buffer rendering is currently enabled
973 * A separate flag is used to track this in order to support MRT more
976 bool is_front_buffer_rendering
;
979 * Track whether front-buffer is the current read target.
981 * This is closely associated with is_front_buffer_rendering, but may
982 * be set separately. The DRI2 fake front buffer must be referenced
985 bool is_front_buffer_reading
;
987 /** Framerate throttling: @{ */
988 drm_intel_bo
*first_post_swapbuffers_batch
;
999 bool always_flush_batch
;
1000 bool always_flush_cache
;
1001 bool disable_throttling
;
1004 driOptionCache optionCache
;
1007 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1009 GLenum reduced_primitive
;
1012 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1013 * variable is set, this is the flag indicating to do expensive work that
1014 * might lead to a perf_debug() call.
1018 uint32_t max_gtt_map_object_size
;
1020 bool emit_state_always
;
1030 bool has_separate_stencil
;
1031 bool must_use_separate_stencil
;
1034 bool has_surface_tile_offset
;
1036 bool has_negative_rhw_bug
;
1037 bool has_aa_line_parameters
;
1041 * Some versions of Gen hardware don't do centroid interpolation correctly
1042 * on unlit pixels, causing incorrect values for derivatives near triangle
1043 * edges. Enabling this flag causes the fragment shader to use
1044 * non-centroid interpolation for unlit pixels, at the expense of two extra
1045 * fragment shader instructions.
1047 bool needs_unlit_centroid_workaround
;
1051 struct brw_state_flags dirty
;
1054 struct brw_cache cache
;
1055 struct brw_cached_batch_item
*cached_batch_items
;
1057 /* Whether a meta-operation is in progress. */
1058 bool meta_in_progress
;
1061 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1062 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1064 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1068 /* Summary of size and varying of active arrays, so we can check
1069 * for changes to this state:
1071 unsigned int min_index
, max_index
;
1073 /* Offset from start of vertex buffer so we can avoid redefining
1074 * the same VB packed over and over again.
1076 unsigned int start_vertex_bias
;
1081 * Index buffer for this draw_prims call.
1083 * Updates are signaled by BRW_NEW_INDICES.
1085 const struct _mesa_index_buffer
*ib
;
1087 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1091 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1092 * avoid re-uploading the IB packet over and over if we're actually
1093 * referencing the same index buffer.
1095 unsigned int start_vertex_offset
;
1098 /* Active vertex program:
1100 const struct gl_vertex_program
*vertex_program
;
1101 const struct gl_geometry_program
*geometry_program
;
1102 const struct gl_fragment_program
*fragment_program
;
1104 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
1105 uint32_t CMD_VF_STATISTICS
;
1106 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
1107 uint32_t CMD_PIPELINE_SELECT
;
1110 * Platform specific constants containing the maximum number of threads
1111 * for each pipeline stage.
1117 /* BRW_NEW_URB_ALLOCATIONS:
1120 GLuint vsize
; /* vertex size plus header in urb registers */
1121 GLuint csize
; /* constant buffer size in urb registers */
1122 GLuint sfsize
; /* setup data size in urb registers */
1126 GLuint min_vs_entries
; /* Minimum number of VS entries */
1127 GLuint max_vs_entries
; /* Maximum number of VS entries */
1128 GLuint max_gs_entries
; /* Maximum number of GS entries */
1130 GLuint nr_vs_entries
;
1131 GLuint nr_gs_entries
;
1132 GLuint nr_clip_entries
;
1133 GLuint nr_sf_entries
;
1134 GLuint nr_cs_entries
;
1141 GLuint size
; /* Hardware URB size, in KB. */
1143 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
1144 * URB space for the GS.
1146 bool gen6_gs_previously_active
;
1150 /* BRW_NEW_CURBE_OFFSETS:
1153 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1154 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1161 drm_intel_bo
*curbe_bo
;
1162 /** Offset within curbe_bo of space for current curbe entry */
1163 GLuint curbe_offset
;
1164 /** Offset within curbe_bo of space for next curbe entry */
1165 GLuint curbe_next_offset
;
1168 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
1169 * in brw_curbe.c with the same set of constant data to be uploaded,
1170 * so we'd rather not upload new constants in that case (it can cause
1171 * a pipeline bubble since only up to 4 can be pipelined at a time).
1175 * Allocation for where to calculate the next set of CURBEs.
1176 * It's a hot enough path that malloc/free of that data matters.
1183 * Layout of vertex data exiting the vertex shader.
1185 * BRW_NEW_VUE_MAP_VS is flagged when this VUE map changes.
1187 struct brw_vue_map vue_map_vs
;
1190 * Layout of vertex data exiting the geometry portion of the pipleine.
1191 * This comes from the geometry shader if one exists, otherwise from the
1194 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1196 struct brw_vue_map vue_map_geom_out
;
1199 * Data structures used by all vec4 program compiles (not specific to any
1200 * particular program).
1203 struct ra_regs
*regs
;
1206 * Array of the ra classes for the unaligned contiguous register
1212 * Mapping for register-allocated objects in *regs to the first
1213 * GRF for that object.
1215 uint8_t *ra_reg_to_grf
;
1219 struct brw_stage_state base
;
1220 struct brw_vs_prog_data
*prog_data
;
1224 struct brw_stage_state base
;
1225 struct brw_gs_prog_data
*prog_data
;
1229 struct brw_ff_gs_prog_data
*prog_data
;
1232 /** Offset in the program cache to the CLIP program pre-gen6 */
1233 uint32_t prog_offset
;
1234 uint32_t state_offset
;
1236 uint32_t bind_bo_offset
;
1237 uint32_t surf_offset
[BRW_MAX_GEN6_GS_SURFACES
];
1241 struct brw_clip_prog_data
*prog_data
;
1243 /** Offset in the program cache to the CLIP program pre-gen6 */
1244 uint32_t prog_offset
;
1246 /* Offset in the batch to the CLIP state on pre-gen6. */
1247 uint32_t state_offset
;
1249 /* As of gen6, this is the offset in the batch to the CLIP VP,
1257 struct brw_sf_prog_data
*prog_data
;
1259 /** Offset in the program cache to the CLIP program pre-gen6 */
1260 uint32_t prog_offset
;
1261 uint32_t state_offset
;
1266 struct brw_stage_state base
;
1267 struct brw_wm_prog_data
*prog_data
;
1272 * Buffer object used in place of multisampled null render targets on
1273 * Gen6. See brw_update_null_renderbuffer_surface().
1275 drm_intel_bo
*multisampled_null_render_target_bo
;
1278 struct ra_regs
*regs
;
1280 /** Array of the ra classes for the unaligned contiguous
1281 * register block sizes used.
1286 * Mapping for register-allocated objects in *regs to the first
1287 * GRF for that object.
1289 uint8_t *ra_reg_to_grf
;
1292 * ra class for the aligned pairs we use for PLN, which doesn't
1293 * appear in *classes.
1295 int aligned_pairs_class
;
1301 uint32_t state_offset
;
1302 uint32_t blend_state_offset
;
1303 uint32_t depth_stencil_state_offset
;
1308 struct brw_query_object
*obj
;
1313 const struct brw_tracked_state
**atoms
;
1315 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1319 enum state_struct_type type
;
1320 } *state_batch_list
;
1321 int state_batch_count
;
1323 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1324 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1326 /* Interpolation modes, one byte per vue slot.
1327 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1329 struct interpolation_mode_map interpolation_mode
;
1331 /* PrimitiveRestart */
1334 bool enable_cut_index
;
1337 /** Computed depth/stencil/hiz state from the current attached
1338 * renderbuffers, valid only during the drawing state upload loop after
1339 * brw_workaround_depthstencil_alignment().
1342 struct intel_mipmap_tree
*depth_mt
;
1343 struct intel_mipmap_tree
*stencil_mt
;
1345 /* Inter-tile (page-aligned) byte offsets. */
1346 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1347 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1348 uint32_t tile_x
, tile_y
;
1351 uint32_t num_instances
;
1356 struct gl_shader_program
**shader_programs
;
1357 struct gl_program
**programs
;
1358 enum shader_time_shader_type
*types
;
1359 uint64_t *cumulative
;
1365 __DRIcontext
*driContext
;
1366 struct intel_screen
*intelScreen
;
1367 void (*saved_viewport
)(struct gl_context
*ctx
,
1368 GLint x
, GLint y
, GLsizei width
, GLsizei height
);
1371 /*======================================================================
1374 void brwInitVtbl( struct brw_context
*brw
);
1376 /*======================================================================
1379 bool brwCreateContext(int api
,
1380 const struct gl_config
*mesaVis
,
1381 __DRIcontext
*driContextPriv
,
1382 unsigned major_version
,
1383 unsigned minor_version
,
1386 void *sharedContextPrivate
);
1388 /*======================================================================
1391 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1392 uint32_t depth_level
,
1393 uint32_t depth_layer
,
1394 struct intel_mipmap_tree
*stencil_mt
,
1395 uint32_t *out_tile_mask_x
,
1396 uint32_t *out_tile_mask_y
);
1397 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1398 GLbitfield clear_mask
);
1400 /* brw_object_purgeable.c */
1401 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1403 /*======================================================================
1406 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1407 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1408 void brw_emit_query_begin(struct brw_context
*brw
);
1409 void brw_emit_query_end(struct brw_context
*brw
);
1411 /** gen6_queryobj.c */
1412 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1414 /*======================================================================
1417 void brw_debug_batch(struct brw_context
*brw
);
1418 void brw_annotate_aub(struct brw_context
*brw
);
1420 /*======================================================================
1423 void brw_validate_textures( struct brw_context
*brw
);
1426 /*======================================================================
1429 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1431 int brw_get_scratch_size(int size
);
1432 void brw_get_scratch_bo(struct brw_context
*brw
,
1433 drm_intel_bo
**scratch_bo
, int size
);
1434 void brw_init_shader_time(struct brw_context
*brw
);
1435 int brw_get_shader_time_index(struct brw_context
*brw
,
1436 struct gl_shader_program
*shader_prog
,
1437 struct gl_program
*prog
,
1438 enum shader_time_shader_type type
);
1439 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1440 void brw_destroy_shader_time(struct brw_context
*brw
);
1444 void brw_upload_urb_fence(struct brw_context
*brw
);
1448 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1450 /* brw_fs_reg_allocate.cpp
1452 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1454 /* brw_vec4_reg_allocate.cpp */
1455 void brw_vec4_alloc_reg_set(struct brw_context
*brw
);
1458 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1461 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1463 /* brw_draw_upload.c */
1464 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1465 const struct gl_client_array
*glarray
);
1466 unsigned brw_get_index_type(GLenum type
);
1468 /* brw_wm_surface_state.c */
1469 void brw_init_surface_formats(struct brw_context
*brw
);
1471 brw_update_sol_surface(struct brw_context
*brw
,
1472 struct gl_buffer_object
*buffer_obj
,
1473 uint32_t *out_offset
, unsigned num_vector_components
,
1474 unsigned stride_dwords
, unsigned offset_dwords
);
1475 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1476 struct gl_shader
*shader
,
1477 uint32_t *surf_offsets
);
1479 /* brw_surface_formats.c */
1480 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, gl_format format
);
1481 bool brw_render_target_supported(struct brw_context
*brw
,
1482 struct gl_renderbuffer
*rb
);
1486 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1487 struct gl_transform_feedback_object
*obj
);
1489 brw_end_transform_feedback(struct gl_context
*ctx
,
1490 struct gl_transform_feedback_object
*obj
);
1492 /* gen7_sol_state.c */
1494 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1495 struct gl_transform_feedback_object
*obj
);
1497 gen7_end_transform_feedback(struct gl_context
*ctx
,
1498 struct gl_transform_feedback_object
*obj
);
1500 /* brw_blorp_blit.cpp */
1502 brw_blorp_framebuffer(struct brw_context
*brw
,
1503 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1504 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1505 GLbitfield mask
, GLenum filter
);
1508 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1509 struct gl_renderbuffer
*src_rb
,
1510 struct gl_texture_image
*dst_image
,
1512 int srcX0
, int srcY0
,
1513 int dstX0
, int dstY0
,
1514 int width
, int height
);
1516 /* gen6_multisample_state.c */
1518 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1519 unsigned num_samples
);
1521 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
,
1522 unsigned num_samples
, float coverage
,
1523 bool coverage_invert
, unsigned sample_mask
);
1525 gen6_get_sample_position(struct gl_context
*ctx
,
1526 struct gl_framebuffer
*fb
,
1532 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1533 unsigned gs_size
, unsigned fs_size
);
1536 gen7_emit_urb_state(struct brw_context
*brw
,
1537 unsigned nr_vs_entries
, unsigned vs_size
,
1538 unsigned vs_start
, unsigned nr_gs_entries
,
1539 unsigned gs_size
, unsigned gs_start
);
1543 /*======================================================================
1544 * Inline conversion functions. These are better-typed than the
1545 * macros used previously:
1547 static INLINE
struct brw_context
*
1548 brw_context( struct gl_context
*ctx
)
1550 return (struct brw_context
*)ctx
;
1553 static INLINE
struct brw_vertex_program
*
1554 brw_vertex_program(struct gl_vertex_program
*p
)
1556 return (struct brw_vertex_program
*) p
;
1559 static INLINE
const struct brw_vertex_program
*
1560 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1562 return (const struct brw_vertex_program
*) p
;
1565 static INLINE
struct brw_fragment_program
*
1566 brw_fragment_program(struct gl_fragment_program
*p
)
1568 return (struct brw_fragment_program
*) p
;
1571 static INLINE
const struct brw_fragment_program
*
1572 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1574 return (const struct brw_fragment_program
*) p
;
1578 * Pre-gen6, the register file of the EUs was shared between threads,
1579 * and each thread used some subset allocated on a 16-register block
1580 * granularity. The unit states wanted these block counts.
1583 brw_register_blocks(int reg_count
)
1585 return ALIGN(reg_count
, 16) / 16 - 1;
1588 static inline uint32_t
1589 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1590 uint32_t prog_offset
)
1592 if (brw
->gen
>= 5) {
1593 /* Using state base address. */
1597 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1601 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1603 return brw
->cache
.bo
->offset
+ prog_offset
;
1606 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1607 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1608 struct exec_list
*instructions
);
1610 struct opcode_desc
{
1616 extern const struct opcode_desc opcode_descs
[128];
1619 brw_emit_depthbuffer(struct brw_context
*brw
);
1622 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1623 struct intel_mipmap_tree
*depth_mt
,
1624 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1625 uint32_t depth_surface_type
,
1626 struct intel_mipmap_tree
*stencil_mt
,
1627 bool hiz
, bool separate_stencil
,
1628 uint32_t width
, uint32_t height
,
1629 uint32_t tile_x
, uint32_t tile_y
);
1632 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1633 struct intel_mipmap_tree
*depth_mt
,
1634 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1635 uint32_t depth_surface_type
,
1636 struct intel_mipmap_tree
*stencil_mt
,
1637 bool hiz
, bool separate_stencil
,
1638 uint32_t width
, uint32_t height
,
1639 uint32_t tile_x
, uint32_t tile_y
);
1641 extern const GLuint prim_to_hw_prim
[GL_POLYGON
+1];
1644 brw_setup_vec4_key_clip_info(struct brw_context
*brw
,
1645 struct brw_vec4_prog_key
*key
,
1646 bool program_uses_clip_distance
);
1649 gen6_upload_vec4_push_constants(struct brw_context
*brw
,
1650 const struct gl_program
*prog
,
1651 const struct brw_vec4_prog_data
*prog_data
,
1652 struct brw_stage_state
*stage_state
,
1653 enum state_struct_type type
);