2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
45 /* Evil hack for using libdrm in a c++ compiler. */
49 #include <intel_bufmgr.h>
58 #include "intel_debug.h"
59 #include "intel_screen.h"
60 #include "intel_tex_obj.h"
61 #include "intel_resolve_map.h"
65 * URB - uniform resource buffer. A mid-sized buffer which is
66 * partitioned between the fixed function units and used for passing
67 * values (vertices, primitives, constants) between them.
69 * CURBE - constant URB entry. An urb region (entry) used to hold
70 * constant values which the fixed function units can be instructed to
71 * preload into the GRF when spawning a thread.
73 * VUE - vertex URB entry. An urb entry holding a vertex and usually
74 * a vertex header. The header contains control information and
75 * things like primitive type, Begin/end flags and clip codes.
77 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
78 * unit holding rasterization and interpolation parameters.
80 * GRF - general register file. One of several register files
81 * addressable by programmed threads. The inputs (r0, payload, curbe,
82 * urb) of the thread are preloaded to this area before the thread is
83 * spawned. The registers are individually 8 dwords wide and suitable
84 * for general usage. Registers holding thread input values are not
85 * special and may be overwritten.
87 * MRF - message register file. Threads communicate (and terminate)
88 * by sending messages. Message parameters are placed in contiguous
89 * MRF registers. All program output is via these messages. URB
90 * entries are populated by sending a message to the shared URB
91 * function containing the new data, together with a control word,
92 * often an unmodified copy of R0.
94 * R0 - GRF register 0. Typically holds control information used when
95 * sending messages to other threads.
97 * EU or GEN4 EU: The name of the programmable subsystem of the
98 * i965 hardware. Threads are executed by the EU, the registers
99 * described above are part of the EU architecture.
101 * Fixed function units:
103 * CS - Command streamer. Notional first unit, little software
104 * interaction. Holds the URB entries used for constant data, ie the
107 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
108 * this unit is responsible for pulling vertices out of vertex buffers
109 * in vram and injecting them into the processing pipe as VUEs. If
110 * enabled, it first passes them to a VS thread which is a good place
111 * for the driver to implement any active vertex shader.
113 * HS - Hull Shader (Tessellation Control Shader)
115 * TE - Tessellation Engine (Tessellation Primitive Generation)
117 * DS - Domain Shader (Tessellation Evaluation Shader)
119 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
120 * enabled, incoming strips etc are passed to GS threads in individual
121 * line/triangle/point units. The GS thread may perform arbitary
122 * computation and emit whatever primtives with whatever vertices it
123 * chooses. This makes GS an excellent place to implement GL's
124 * unfilled polygon modes, though of course it is capable of much
125 * more. Additionally, GS is used to translate away primitives not
126 * handled by latter units, including Quads and Lineloops.
128 * CS - Clipper. Mesa's clipping algorithms are imported to run on
129 * this unit. The fixed function part performs cliptesting against
130 * the 6 fixed clipplanes and makes descisions on whether or not the
131 * incoming primitive needs to be passed to a thread for clipping.
132 * User clip planes are handled via cooperation with the VS thread.
134 * SF - Strips Fans or Setup: Triangles are prepared for
135 * rasterization. Interpolation coefficients are calculated.
136 * Flatshading and two-side lighting usually performed here.
138 * WM - Windower. Interpolation of vertex attributes performed here.
139 * Fragment shader implemented here. SIMD aspects of EU taken full
140 * advantage of, as pixels are processed in blocks of 16.
142 * CC - Color Calculator. No EU threads associated with this unit.
143 * Handles blending and (presumably) depth and stencil testing.
148 struct brw_vs_prog_key
;
149 struct brw_vue_prog_key
;
150 struct brw_wm_prog_key
;
151 struct brw_wm_prog_data
;
152 struct brw_cs_prog_key
;
153 struct brw_cs_prog_data
;
157 BRW_COMPUTE_PIPELINE
,
164 BRW_CACHE_BLORP_BLIT_PROG
,
167 BRW_CACHE_FF_GS_PROG
,
178 /* brw_cache_ids must come first - see brw_state_cache.c */
179 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
180 BRW_STATE_FRAGMENT_PROGRAM
,
181 BRW_STATE_GEOMETRY_PROGRAM
,
182 BRW_STATE_TESS_CTRL_PROGRAM
,
183 BRW_STATE_TESS_EVAL_PROGRAM
,
184 BRW_STATE_VERTEX_PROGRAM
,
185 BRW_STATE_CURBE_OFFSETS
,
186 BRW_STATE_REDUCED_PRIMITIVE
,
187 BRW_STATE_PATCH_PRIMITIVE
,
192 BRW_STATE_BINDING_TABLE_POINTERS
,
196 BRW_STATE_INDEX_BUFFER
,
197 BRW_STATE_VS_CONSTBUF
,
198 BRW_STATE_GS_CONSTBUF
,
199 BRW_STATE_PROGRAM_CACHE
,
200 BRW_STATE_STATE_BASE_ADDRESS
,
201 BRW_STATE_VUE_MAP_GEOM_OUT
,
202 BRW_STATE_TRANSFORM_FEEDBACK
,
203 BRW_STATE_RASTERIZER_DISCARD
,
205 BRW_STATE_UNIFORM_BUFFER
,
206 BRW_STATE_ATOMIC_BUFFER
,
207 BRW_STATE_IMAGE_UNITS
,
208 BRW_STATE_META_IN_PROGRESS
,
209 BRW_STATE_INTERPOLATION_MAP
,
210 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
211 BRW_STATE_NUM_SAMPLES
,
212 BRW_STATE_TEXTURE_BUFFER
,
213 BRW_STATE_GEN4_UNIT_STATE
,
217 BRW_STATE_SAMPLER_STATE_TABLE
,
218 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
219 BRW_STATE_COMPUTE_PROGRAM
,
220 BRW_STATE_CS_WORK_GROUPS
,
226 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
228 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
229 * When the currently bound shader program differs from the previous draw
230 * call, these will be flagged. They cover brw->{stage}_program and
231 * ctx->{Stage}Program->_Current.
233 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
234 * driver perspective. Even if the same shader is bound at the API level,
235 * we may need to switch between multiple versions of that shader to handle
236 * changes in non-orthagonal state.
238 * Additionally, multiple shader programs may have identical vertex shaders
239 * (for example), or compile down to the same code in the backend. We combine
240 * those into a single program cache entry.
242 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
243 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
245 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
246 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
247 * use the normal state upload paths), but the cache is still used. To avoid
248 * polluting the brw_state_cache code with special cases, we retain the dirty
249 * bit for now. It should eventually be removed.
251 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
252 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
253 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
254 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
255 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
256 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
257 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
258 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
259 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
260 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
261 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
262 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
263 #define BRW_NEW_TESS_EVAL_PROGRAM (1ull << BRW_STATE_TESS_EVAL_PROGRAM)
264 #define BRW_NEW_TESS_CTRL_PROGRAM (1ull << BRW_STATE_TESS_CTRL_PROGRAM)
265 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
266 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
267 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
268 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
269 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
270 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
271 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
272 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
273 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
274 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
275 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
277 * Used for any batch entry with a relocated pointer that will be used
278 * by any 3D rendering.
280 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
281 /** \see brw.state.depth_region */
282 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
283 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
284 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
285 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
286 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
287 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
288 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
289 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
290 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
291 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
292 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
293 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
294 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
295 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
296 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
297 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
298 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
299 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
300 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
301 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
302 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
303 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
304 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
305 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
306 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
307 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
309 struct brw_state_flags
{
310 /** State update flags signalled by mesa internals */
313 * State update flags signalled as the result of brw_tracked_state updates
318 /** Subclass of Mesa vertex program */
319 struct brw_vertex_program
{
320 struct gl_vertex_program program
;
325 /** Subclass of Mesa tessellation control program */
326 struct brw_tess_ctrl_program
{
327 struct gl_tess_ctrl_program program
;
328 unsigned id
; /**< serial no. to identify tess ctrl progs, never re-used */
332 /** Subclass of Mesa tessellation evaluation program */
333 struct brw_tess_eval_program
{
334 struct gl_tess_eval_program program
;
335 unsigned id
; /**< serial no. to identify tess eval progs, never re-used */
339 /** Subclass of Mesa geometry program */
340 struct brw_geometry_program
{
341 struct gl_geometry_program program
;
342 unsigned id
; /**< serial no. to identify geom progs, never re-used */
346 /** Subclass of Mesa fragment program */
347 struct brw_fragment_program
{
348 struct gl_fragment_program program
;
349 GLuint id
; /**< serial no. to identify frag progs, never re-used */
353 /** Subclass of Mesa compute program */
354 struct brw_compute_program
{
355 struct gl_compute_program program
;
356 unsigned id
; /**< serial no. to identify compute progs, never re-used */
361 struct gl_shader base
;
367 * Bitmask indicating which fragment shader inputs represent varyings (and
368 * hence have to be delivered to the fragment shader by the SF/SBE stage).
370 #define BRW_FS_VARYING_INPUT_MASK \
371 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
372 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
376 * Mapping of VUE map slots to interpolation modes.
378 struct interpolation_mode_map
{
379 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
382 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
384 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
385 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
391 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
393 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
394 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
401 struct brw_sf_prog_data
{
402 GLuint urb_read_length
;
405 /* Each vertex may have upto 12 attributes, 4 components each,
406 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
409 * Actually we use 4 for each, so call it 12 rows.
411 GLuint urb_entry_size
;
416 * We always program SF to start reading at an offset of 1 (2 varying slots)
417 * from the start of the vertex URB entry. This causes it to skip:
418 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
419 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
421 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
424 struct brw_clip_prog_data
{
425 GLuint curb_read_length
; /* user planes? */
427 GLuint urb_read_length
;
431 struct brw_ff_gs_prog_data
{
432 GLuint urb_read_length
;
436 * Gen6 transform feedback: Amount by which the streaming vertex buffer
437 * indices should be incremented each time the GS is invoked.
439 unsigned svbi_postincrement_value
;
442 /** Number of texture sampler units */
443 #define BRW_MAX_TEX_UNIT 32
445 /** Max number of render targets in a shader */
446 #define BRW_MAX_DRAW_BUFFERS 8
448 /** Max number of UBOs in a shader */
449 #define BRW_MAX_UBO 14
451 /** Max number of SSBOs in a shader */
452 #define BRW_MAX_SSBO 12
454 /** Max number of atomic counter buffer objects in a shader */
455 #define BRW_MAX_ABO 16
457 /** Max number of image uniforms in a shader */
458 #define BRW_MAX_IMAGES 32
461 * Max number of binding table entries used for stream output.
463 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
464 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
466 * On Gen6, the size of transform feedback data is limited not by the number
467 * of components but by the number of binding table entries we set aside. We
468 * use one binding table entry for a float, one entry for a vector, and one
469 * entry per matrix column. Since the only way we can communicate our
470 * transform feedback capabilities to the client is via
471 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
472 * worst case, in which all the varyings are floats, so we use up one binding
473 * table entry per component. Therefore we need to set aside at least 64
474 * binding table entries for use by transform feedback.
476 * Note: since we don't currently pack varyings, it is currently impossible
477 * for the client to actually use up all of these binding table entries--if
478 * all of their varyings were floats, they would run out of varying slots and
479 * fail to link. But that's a bug, so it seems prudent to go ahead and
480 * allocate the number of binding table entries we will need once the bug is
483 #define BRW_MAX_SOL_BINDINGS 64
485 /** Maximum number of actual buffers used for stream output */
486 #define BRW_MAX_SOL_BUFFERS 4
488 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
489 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
494 2 + /* shader time, pull constants */ \
495 1 /* cs num work groups */)
497 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
500 * Stride in bytes between shader_time entries.
502 * We separate entries by a cacheline to reduce traffic between EUs writing to
505 #define SHADER_TIME_STRIDE 64
507 struct brw_cache_item
{
509 * Effectively part of the key, cache_id identifies what kind of state
510 * buffer is involved, and also which dirty flag should set.
512 enum brw_cache_id cache_id
;
513 /** 32-bit hash of the key data */
515 GLuint key_size
; /* for variable-sized keys */
522 struct brw_cache_item
*next
;
527 struct brw_context
*brw
;
529 struct brw_cache_item
**items
;
531 GLuint size
, n_items
;
533 uint32_t next_offset
;
538 /* Considered adding a member to this struct to document which flags
539 * an update might raise so that ordering of the state atoms can be
540 * checked or derived at runtime. Dropped the idea in favor of having
541 * a debug mode where the state is monitored for flags which are
542 * raised that have already been tested against.
544 struct brw_tracked_state
{
545 struct brw_state_flags dirty
;
546 void (*emit
)( struct brw_context
*brw
);
549 enum shader_time_shader_type
{
560 struct brw_vertex_buffer
{
561 /** Buffer object containing the uploaded vertex data */
564 /** Byte stride between elements in the uploaded array */
568 struct brw_vertex_element
{
569 const struct gl_client_array
*glarray
;
573 /** Offset of the first element within the buffer object */
577 struct brw_query_object
{
578 struct gl_query_object Base
;
580 /** Last query BO associated with this query. */
583 /** Last index in bo with query data for this object. */
586 /** True if we know the batch has been flushed since we ended the query. */
596 struct intel_batchbuffer
{
597 /** Current batchbuffer being queued up. */
599 /** Last BO submitted to the hardware. Used for glFinish(). */
600 drm_intel_bo
*last_bo
;
603 uint16_t emit
, total
;
605 uint16_t reserved_space
;
609 #define BATCH_SZ (8192*sizeof(uint32_t))
611 uint32_t state_batch_offset
;
612 enum brw_gpu_ring ring
;
613 bool needs_sol_reset
;
621 #define MAX_GS_INPUT_VERTICES 6
623 #define BRW_MAX_XFB_STREAMS 4
625 struct brw_transform_feedback_object
{
626 struct gl_transform_feedback_object base
;
628 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
629 drm_intel_bo
*offset_bo
;
631 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
634 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
635 GLenum primitive_mode
;
638 * Count of primitives generated during this transform feedback operation.
641 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
642 drm_intel_bo
*prim_count_bo
;
643 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
647 * Number of vertices written between last Begin/EndTransformFeedback().
649 * Used to implement DrawTransformFeedback().
651 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
652 bool vertices_written_valid
;
656 * Data shared between each programmable stage in the pipeline (vs, gs, and
659 struct brw_stage_state
661 gl_shader_stage stage
;
662 struct brw_stage_prog_data
*prog_data
;
665 * Optional scratch buffer used to store spilled register values and
666 * variably-indexed GRF arrays.
668 drm_intel_bo
*scratch_bo
;
670 /** Offset in the program cache to the program */
671 uint32_t prog_offset
;
673 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
674 uint32_t state_offset
;
676 uint32_t push_const_offset
; /* Offset in the batchbuffer */
677 int push_const_size
; /* in 256-bit register increments */
679 /* Binding table: pointers to SURFACE_STATE entries. */
680 uint32_t bind_bo_offset
;
681 uint32_t surf_offset
[BRW_MAX_SURFACES
];
683 /** SAMPLER_STATE count and table offset */
684 uint32_t sampler_count
;
685 uint32_t sampler_offset
;
688 enum brw_predicate_state
{
689 /* The first two states are used if we can determine whether to draw
690 * without having to look at the values in the query object buffer. This
691 * will happen if there is no conditional render in progress, if the query
692 * object is already completed or if something else has already added
693 * samples to the preliminary result such as via a BLT command.
695 BRW_PREDICATE_STATE_RENDER
,
696 BRW_PREDICATE_STATE_DONT_RENDER
,
697 /* In this case whether to draw or not depends on the result of an
698 * MI_PREDICATE command so the predicate enable bit needs to be checked.
700 BRW_PREDICATE_STATE_USE_BIT
705 struct brw_l3_config
;
708 * brw_context is derived from gl_context.
712 struct gl_context ctx
; /**< base class, must be first field */
716 void (*update_texture_surface
)(struct gl_context
*ctx
,
718 uint32_t *surf_offset
,
720 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
721 struct gl_renderbuffer
*rb
,
722 bool layered
, unsigned unit
,
723 uint32_t surf_index
);
725 void (*emit_texture_surface_state
)(struct brw_context
*brw
,
726 struct intel_mipmap_tree
*mt
,
734 uint32_t *surf_offset
,
735 bool rw
, bool for_gather
);
736 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
737 uint32_t *out_offset
,
739 unsigned buffer_offset
,
740 unsigned surface_format
,
741 unsigned buffer_size
,
744 void (*emit_null_surface_state
)(struct brw_context
*brw
,
748 uint32_t *out_offset
);
751 * Send the appropriate state packets to configure depth, stencil, and
752 * HiZ buffers (i965+ only)
754 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
755 struct intel_mipmap_tree
*depth_mt
,
756 uint32_t depth_offset
,
757 uint32_t depthbuffer_format
,
758 uint32_t depth_surface_type
,
759 struct intel_mipmap_tree
*stencil_mt
,
760 bool hiz
, bool separate_stencil
,
761 uint32_t width
, uint32_t height
,
762 uint32_t tile_x
, uint32_t tile_y
);
768 drm_intel_context
*hw_ctx
;
770 /** BO for post-sync nonzero writes for gen6 workaround. */
771 drm_intel_bo
*workaround_bo
;
772 uint8_t pipe_controls_since_last_cs_stall
;
775 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
776 * and would need flushing before being used from another cache domain that
777 * isn't coherent with it (i.e. the sampler).
779 struct set
*render_cache
;
782 * Number of resets observed in the system at context creation.
784 * This is tracked in the context so that we can determine that another
785 * reset has occurred.
787 uint32_t reset_count
;
789 struct intel_batchbuffer batch
;
794 uint32_t next_offset
;
798 * Set if rendering has occurred to the drawable's front buffer.
800 * This is used in the DRI2 case to detect that glFlush should also copy
801 * the contents of the fake front buffer to the real front buffer.
803 bool front_buffer_dirty
;
805 /** Framerate throttling: @{ */
806 drm_intel_bo
*throttle_batch
[2];
808 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
809 * frame of rendering to complete. This gives a very precise cap to the
810 * latency between input and output such that rendering never gets more
811 * than a frame behind the user. (With the caveat that we technically are
812 * not using the SwapBuffers itself as a barrier but the first batch
813 * submitted afterwards, which may be immediately prior to the next
816 bool need_swap_throttle
;
818 /** General throttling, not caught by throttling between SwapBuffers */
819 bool need_flush_throttle
;
829 bool always_flush_batch
;
830 bool always_flush_cache
;
831 bool disable_throttling
;
834 driOptionCache optionCache
;
837 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
839 GLenum reduced_primitive
;
842 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
843 * variable is set, this is the flag indicating to do expensive work that
844 * might lead to a perf_debug() call.
848 uint32_t max_gtt_map_object_size
;
860 bool has_separate_stencil
;
861 bool must_use_separate_stencil
;
864 bool has_surface_tile_offset
;
866 bool has_negative_rhw_bug
;
870 bool use_resource_streamer
;
873 * Whether LRI can be used to write register values from the batch buffer.
875 bool can_do_pipelined_register_writes
;
878 * Some versions of Gen hardware don't do centroid interpolation correctly
879 * on unlit pixels, causing incorrect values for derivatives near triangle
880 * edges. Enabling this flag causes the fragment shader to use
881 * non-centroid interpolation for unlit pixels, at the expense of two extra
882 * fragment shader instructions.
884 bool needs_unlit_centroid_workaround
;
888 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
891 enum brw_pipeline last_pipeline
;
893 struct brw_cache cache
;
895 /** IDs for meta stencil blit shader programs. */
896 unsigned meta_stencil_blit_programs
[2];
898 /* Whether a meta-operation is in progress. */
899 bool meta_in_progress
;
901 /* Whether the last depth/stencil packets were both NULL. */
902 bool no_depth_or_stencil
;
904 /* The last PMA stall bits programmed. */
905 uint32_t pma_stall_bits
;
908 /** The value of gl_BaseVertex for the current _mesa_prim. */
912 * Buffer and offset used for GL_ARB_shader_draw_parameters
913 * (for now, only gl_BaseVertex).
915 drm_intel_bo
*draw_params_bo
;
916 uint32_t draw_params_offset
;
921 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
922 * an indirect call, and num_work_groups_offset is valid. Otherwise,
923 * num_work_groups is set based on glDispatchCompute.
925 drm_intel_bo
*num_work_groups_bo
;
926 GLintptr num_work_groups_offset
;
927 const GLuint
*num_work_groups
;
931 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
932 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
934 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
938 /* Summary of size and varying of active arrays, so we can check
939 * for changes to this state:
941 unsigned int min_index
, max_index
;
943 /* Offset from start of vertex buffer so we can avoid redefining
944 * the same VB packed over and over again.
946 unsigned int start_vertex_bias
;
949 * Certain vertex attribute formats aren't natively handled by the
950 * hardware and require special VS code to fix up their values.
952 * These bitfields indicate which workarounds are needed.
954 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
959 * Index buffer for this draw_prims call.
961 * Updates are signaled by BRW_NEW_INDICES.
963 const struct _mesa_index_buffer
*ib
;
965 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
969 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
970 * avoid re-uploading the IB packet over and over if we're actually
971 * referencing the same index buffer.
973 unsigned int start_vertex_offset
;
976 /* Active vertex program:
978 const struct gl_vertex_program
*vertex_program
;
979 const struct gl_geometry_program
*geometry_program
;
980 const struct gl_tess_ctrl_program
*tess_ctrl_program
;
981 const struct gl_tess_eval_program
*tess_eval_program
;
982 const struct gl_fragment_program
*fragment_program
;
983 const struct gl_compute_program
*compute_program
;
986 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
987 * that we don't have to reemit that state every time we change FBOs.
992 * Platform specific constants containing the maximum number of threads
993 * for each pipeline stage.
995 unsigned max_vs_threads
;
996 unsigned max_hs_threads
;
997 unsigned max_ds_threads
;
998 unsigned max_gs_threads
;
999 unsigned max_wm_threads
;
1000 unsigned max_cs_threads
;
1002 /* BRW_NEW_URB_ALLOCATIONS:
1005 GLuint vsize
; /* vertex size plus header in urb registers */
1006 GLuint gsize
; /* GS output size in urb registers */
1007 GLuint csize
; /* constant buffer size in urb registers */
1008 GLuint sfsize
; /* setup data size in urb registers */
1012 GLuint min_vs_entries
; /* Minimum number of VS entries */
1013 GLuint max_vs_entries
; /* Maximum number of VS entries */
1014 GLuint max_hs_entries
; /* Maximum number of HS entries */
1015 GLuint max_ds_entries
; /* Maximum number of DS entries */
1016 GLuint max_gs_entries
; /* Maximum number of GS entries */
1018 GLuint nr_vs_entries
;
1019 GLuint nr_gs_entries
;
1020 GLuint nr_clip_entries
;
1021 GLuint nr_sf_entries
;
1022 GLuint nr_cs_entries
;
1030 * URB size in the current configuration. The units this is expressed
1031 * in are somewhat inconsistent, see brw_device_info::urb::size.
1033 * FINISHME: Represent the URB size consistently in KB on all platforms.
1037 /* True if the most recently sent _3DSTATE_URB message allocated
1038 * URB space for the GS.
1044 /* BRW_NEW_CURBE_OFFSETS:
1047 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1048 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1056 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1057 * for upload to the CURBE.
1059 drm_intel_bo
*curbe_bo
;
1060 /** Offset within curbe_bo of space for current curbe entry */
1061 GLuint curbe_offset
;
1065 * Layout of vertex data exiting the geometry portion of the pipleine.
1066 * This comes from the last enabled shader stage (GS, DS, or VS).
1068 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1070 struct brw_vue_map vue_map_geom_out
;
1073 struct brw_stage_state base
;
1074 struct brw_vs_prog_data
*prog_data
;
1078 struct brw_stage_state base
;
1079 struct brw_tcs_prog_data
*prog_data
;
1082 * True if the 3DSTATE_HS command most recently emitted to the 3D
1083 * pipeline enabled the HS; false otherwise.
1089 struct brw_stage_state base
;
1090 struct brw_tes_prog_data
*prog_data
;
1093 * True if the 3DSTATE_DS command most recently emitted to the 3D
1094 * pipeline enabled the DS; false otherwise.
1100 struct brw_stage_state base
;
1101 struct brw_gs_prog_data
*prog_data
;
1104 * True if the 3DSTATE_GS command most recently emitted to the 3D
1105 * pipeline enabled the GS; false otherwise.
1111 struct brw_ff_gs_prog_data
*prog_data
;
1114 /** Offset in the program cache to the CLIP program pre-gen6 */
1115 uint32_t prog_offset
;
1116 uint32_t state_offset
;
1118 uint32_t bind_bo_offset
;
1120 * Surface offsets for the binding table. We only need surfaces to
1121 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1122 * need in this case.
1124 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1128 struct brw_clip_prog_data
*prog_data
;
1130 /** Offset in the program cache to the CLIP program pre-gen6 */
1131 uint32_t prog_offset
;
1133 /* Offset in the batch to the CLIP state on pre-gen6. */
1134 uint32_t state_offset
;
1136 /* As of gen6, this is the offset in the batch to the CLIP VP,
1144 struct brw_sf_prog_data
*prog_data
;
1146 /** Offset in the program cache to the CLIP program pre-gen6 */
1147 uint32_t prog_offset
;
1148 uint32_t state_offset
;
1150 bool viewport_transform_enable
;
1154 struct brw_stage_state base
;
1155 struct brw_wm_prog_data
*prog_data
;
1160 * Buffer object used in place of multisampled null render targets on
1161 * Gen6. See brw_emit_null_surface_state().
1163 drm_intel_bo
*multisampled_null_render_target_bo
;
1164 uint32_t fast_clear_op
;
1170 struct brw_stage_state base
;
1171 struct brw_cs_prog_data
*prog_data
;
1174 /* RS hardware binding table */
1177 uint32_t next_offset
;
1181 uint32_t state_offset
;
1182 uint32_t blend_state_offset
;
1183 uint32_t depth_stencil_state_offset
;
1188 struct brw_query_object
*obj
;
1193 enum brw_predicate_state state
;
1198 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1199 const int *statistics_registers
;
1201 /** The number of active monitors using OA counters. */
1205 * A buffer object storing OA counter snapshots taken at the start and
1206 * end of each batch (creating "bookends" around the batch).
1208 drm_intel_bo
*bookend_bo
;
1210 /** The number of snapshots written to bookend_bo. */
1211 int bookend_snapshots
;
1214 * An array of monitors whose results haven't yet been assembled based on
1215 * the data in buffer objects.
1217 * These may be active, or have already ended. However, the results
1218 * have not been requested.
1220 struct brw_perf_monitor_object
**unresolved
;
1221 int unresolved_elements
;
1222 int unresolved_array_size
;
1225 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1226 * the counter which MI_REPORT_PERF_COUNT stores there.
1228 const int *oa_snapshot_layout
;
1230 /** Number of 32-bit entries in a hardware counter snapshot. */
1231 int entries_per_oa_snapshot
;
1234 int num_atoms
[BRW_NUM_PIPELINES
];
1235 const struct brw_tracked_state render_atoms
[62];
1236 const struct brw_tracked_state compute_atoms
[10];
1238 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1242 enum aub_state_struct_type type
;
1244 } *state_batch_list
;
1245 int state_batch_count
;
1247 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1248 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1250 /* Interpolation modes, one byte per vue slot.
1251 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1253 struct interpolation_mode_map interpolation_mode
;
1255 /* PrimitiveRestart */
1258 bool enable_cut_index
;
1261 /** Computed depth/stencil/hiz state from the current attached
1262 * renderbuffers, valid only during the drawing state upload loop after
1263 * brw_workaround_depthstencil_alignment().
1266 struct intel_mipmap_tree
*depth_mt
;
1267 struct intel_mipmap_tree
*stencil_mt
;
1269 /* Inter-tile (page-aligned) byte offsets. */
1270 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1271 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1272 uint32_t tile_x
, tile_y
;
1275 uint32_t num_instances
;
1279 const struct brw_l3_config
*config
;
1286 enum shader_time_shader_type
*types
;
1287 struct shader_times
*cumulative
;
1293 struct brw_fast_clear_state
*fast_clear_state
;
1295 __DRIcontext
*driContext
;
1296 struct intel_screen
*intelScreen
;
1299 /*======================================================================
1302 void brwInitVtbl( struct brw_context
*brw
);
1305 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1307 /*======================================================================
1310 extern const char *const brw_vendor_string
;
1312 extern const char *brw_get_renderer_string(unsigned deviceID
);
1315 DRI_CONF_BO_REUSE_DISABLED
,
1316 DRI_CONF_BO_REUSE_ALL
1319 void intel_update_renderbuffers(__DRIcontext
*context
,
1320 __DRIdrawable
*drawable
);
1321 void intel_prepare_render(struct brw_context
*brw
);
1323 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1324 __DRIdrawable
*drawable
);
1326 GLboolean
brwCreateContext(gl_api api
,
1327 const struct gl_config
*mesaVis
,
1328 __DRIcontext
*driContextPriv
,
1329 unsigned major_version
,
1330 unsigned minor_version
,
1334 void *sharedContextPrivate
);
1336 /*======================================================================
1339 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1340 struct intel_mipmap_tree
*mt
,
1341 unsigned level
, unsigned layer
, bool flat
);
1343 void brw_meta_updownsample(struct brw_context
*brw
,
1344 struct intel_mipmap_tree
*src
,
1345 struct intel_mipmap_tree
*dst
);
1347 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1348 struct gl_framebuffer
*read_fb
,
1349 struct gl_framebuffer
*draw_fb
,
1350 GLfloat srcX0
, GLfloat srcY0
,
1351 GLfloat srcX1
, GLfloat srcY1
,
1352 GLfloat dstX0
, GLfloat dstY0
,
1353 GLfloat dstX1
, GLfloat dstY1
);
1355 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1356 struct intel_mipmap_tree
*src
,
1357 struct intel_mipmap_tree
*dst
);
1359 bool brw_meta_fast_clear(struct brw_context
*brw
,
1360 struct gl_framebuffer
*fb
,
1362 bool partial_clear
);
1365 brw_meta_resolve_color(struct brw_context
*brw
,
1366 struct intel_mipmap_tree
*mt
);
1368 brw_meta_fast_clear_free(struct brw_context
*brw
);
1371 /*======================================================================
1374 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1375 uint32_t depth_level
,
1376 uint32_t depth_layer
,
1377 struct intel_mipmap_tree
*stencil_mt
,
1378 uint32_t *out_tile_mask_x
,
1379 uint32_t *out_tile_mask_y
);
1380 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1381 GLbitfield clear_mask
);
1383 /* brw_object_purgeable.c */
1384 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1386 /*======================================================================
1389 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1390 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1391 void brw_emit_query_begin(struct brw_context
*brw
);
1392 void brw_emit_query_end(struct brw_context
*brw
);
1394 /** gen6_queryobj.c */
1395 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1396 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1397 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1398 void brw_store_register_mem64(struct brw_context
*brw
,
1399 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1401 /** brw_conditional_render.c */
1402 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1403 bool brw_check_conditional_render(struct brw_context
*brw
);
1405 /** intel_batchbuffer.c */
1406 void brw_load_register_mem(struct brw_context
*brw
,
1409 uint32_t read_domains
, uint32_t write_domain
,
1411 void brw_load_register_mem64(struct brw_context
*brw
,
1414 uint32_t read_domains
, uint32_t write_domain
,
1417 /*======================================================================
1420 void brw_debug_batch(struct brw_context
*brw
);
1421 void brw_annotate_aub(struct brw_context
*brw
);
1423 /*======================================================================
1426 void brw_validate_textures( struct brw_context
*brw
);
1429 /*======================================================================
1433 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1436 perf_debug(" %s %d->%d\n", name
, a
, b
);
1442 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1444 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1446 brw_get_scratch_size(int size
)
1448 return util_next_power_of_two(size
| 1023);
1450 void brw_get_scratch_bo(struct brw_context
*brw
,
1451 drm_intel_bo
**scratch_bo
, int size
);
1452 void brw_init_shader_time(struct brw_context
*brw
);
1453 int brw_get_shader_time_index(struct brw_context
*brw
,
1454 struct gl_shader_program
*shader_prog
,
1455 struct gl_program
*prog
,
1456 enum shader_time_shader_type type
);
1457 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1458 void brw_destroy_shader_time(struct brw_context
*brw
);
1462 void brw_upload_urb_fence(struct brw_context
*brw
);
1466 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1468 /* brw_fs_reg_allocate.cpp
1470 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1472 /* brw_vec4_reg_allocate.cpp */
1473 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1476 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1477 struct brw_inst
*inst
, bool is_compacted
);
1480 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1482 /* brw_draw_upload.c */
1483 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1484 const struct gl_client_array
*glarray
);
1486 static inline unsigned
1487 brw_get_index_type(GLenum type
)
1489 assert((type
== GL_UNSIGNED_BYTE
)
1490 || (type
== GL_UNSIGNED_SHORT
)
1491 || (type
== GL_UNSIGNED_INT
));
1493 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1494 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1495 * to map to scale factors of 0, 1, and 2, respectively. These scale
1496 * factors are then left-shfited by 8 to be in the correct position in the
1497 * CMD_INDEX_BUFFER packet.
1499 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1500 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1501 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1503 return (type
- 0x1401) << 7;
1506 void brw_prepare_vertices(struct brw_context
*brw
);
1508 /* brw_wm_surface_state.c */
1509 void brw_init_surface_formats(struct brw_context
*brw
);
1510 void brw_create_constant_surface(struct brw_context
*brw
,
1514 uint32_t *out_offset
);
1515 void brw_create_buffer_surface(struct brw_context
*brw
,
1519 uint32_t *out_offset
);
1520 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1522 uint32_t *surf_offset
);
1524 brw_update_sol_surface(struct brw_context
*brw
,
1525 struct gl_buffer_object
*buffer_obj
,
1526 uint32_t *out_offset
, unsigned num_vector_components
,
1527 unsigned stride_dwords
, unsigned offset_dwords
);
1528 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1529 struct gl_shader
*shader
,
1530 struct brw_stage_state
*stage_state
,
1531 struct brw_stage_prog_data
*prog_data
);
1532 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1533 struct gl_shader
*shader
,
1534 struct brw_stage_state
*stage_state
,
1535 struct brw_stage_prog_data
*prog_data
);
1536 void brw_upload_image_surfaces(struct brw_context
*brw
,
1537 struct gl_shader
*shader
,
1538 struct brw_stage_state
*stage_state
,
1539 struct brw_stage_prog_data
*prog_data
);
1541 /* brw_surface_formats.c */
1542 bool brw_render_target_supported(struct brw_context
*brw
,
1543 struct gl_renderbuffer
*rb
);
1544 bool brw_losslessly_compressible_format(struct brw_context
*brw
,
1545 uint32_t brw_format
);
1546 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1547 mesa_format
brw_lower_mesa_image_format(const struct brw_device_info
*devinfo
,
1548 mesa_format format
);
1550 /* brw_performance_monitor.c */
1551 void brw_init_performance_monitors(struct brw_context
*brw
);
1552 void brw_dump_perf_monitors(struct brw_context
*brw
);
1553 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1554 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1556 /* intel_buffer_objects.c */
1557 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1558 const char *bo_name
);
1559 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1560 const char *bo_name
);
1562 /* intel_extensions.c */
1563 extern void intelInitExtensions(struct gl_context
*ctx
);
1566 extern int intel_translate_shadow_compare_func(GLenum func
);
1567 extern int intel_translate_compare_func(GLenum func
);
1568 extern int intel_translate_stencil_op(GLenum op
);
1569 extern int intel_translate_logic_op(GLenum opcode
);
1571 /* intel_syncobj.c */
1572 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1575 struct gl_transform_feedback_object
*
1576 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1578 brw_delete_transform_feedback(struct gl_context
*ctx
,
1579 struct gl_transform_feedback_object
*obj
);
1581 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1582 struct gl_transform_feedback_object
*obj
);
1584 brw_end_transform_feedback(struct gl_context
*ctx
,
1585 struct gl_transform_feedback_object
*obj
);
1587 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1588 struct gl_transform_feedback_object
*obj
,
1591 /* gen7_sol_state.c */
1593 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1594 struct gl_transform_feedback_object
*obj
);
1596 gen7_end_transform_feedback(struct gl_context
*ctx
,
1597 struct gl_transform_feedback_object
*obj
);
1599 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1600 struct gl_transform_feedback_object
*obj
);
1602 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1603 struct gl_transform_feedback_object
*obj
);
1605 /* brw_blorp_blit.cpp */
1607 brw_blorp_framebuffer(struct brw_context
*brw
,
1608 struct gl_framebuffer
*readFb
,
1609 struct gl_framebuffer
*drawFb
,
1610 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1611 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1612 GLbitfield mask
, GLenum filter
);
1615 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1616 struct gl_renderbuffer
*src_rb
,
1617 struct gl_texture_image
*dst_image
,
1619 int srcX0
, int srcY0
,
1620 int dstX0
, int dstY0
,
1621 int width
, int height
);
1623 /* gen6_multisample_state.c */
1625 gen6_determine_sample_mask(struct brw_context
*brw
);
1628 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1629 unsigned num_samples
);
1631 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1633 gen6_get_sample_position(struct gl_context
*ctx
,
1634 struct gl_framebuffer
*fb
,
1638 gen6_set_sample_maps(struct gl_context
*ctx
);
1640 /* gen8_multisample_state.c */
1641 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1642 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1646 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1647 unsigned gs_size
, unsigned fs_size
);
1650 gen7_emit_urb_state(struct brw_context
*brw
,
1651 unsigned nr_vs_entries
, unsigned vs_size
,
1652 unsigned vs_start
, unsigned nr_gs_entries
,
1653 unsigned gs_size
, unsigned gs_start
);
1658 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1662 brw_init_compute_functions(struct dd_function_table
*functions
);
1664 /*======================================================================
1665 * Inline conversion functions. These are better-typed than the
1666 * macros used previously:
1668 static inline struct brw_context
*
1669 brw_context( struct gl_context
*ctx
)
1671 return (struct brw_context
*)ctx
;
1674 static inline struct brw_vertex_program
*
1675 brw_vertex_program(struct gl_vertex_program
*p
)
1677 return (struct brw_vertex_program
*) p
;
1680 static inline const struct brw_vertex_program
*
1681 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1683 return (const struct brw_vertex_program
*) p
;
1686 static inline struct brw_geometry_program
*
1687 brw_geometry_program(struct gl_geometry_program
*p
)
1689 return (struct brw_geometry_program
*) p
;
1692 static inline struct brw_fragment_program
*
1693 brw_fragment_program(struct gl_fragment_program
*p
)
1695 return (struct brw_fragment_program
*) p
;
1698 static inline const struct brw_fragment_program
*
1699 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1701 return (const struct brw_fragment_program
*) p
;
1704 static inline struct brw_compute_program
*
1705 brw_compute_program(struct gl_compute_program
*p
)
1707 return (struct brw_compute_program
*) p
;
1711 * Pre-gen6, the register file of the EUs was shared between threads,
1712 * and each thread used some subset allocated on a 16-register block
1713 * granularity. The unit states wanted these block counts.
1716 brw_register_blocks(int reg_count
)
1718 return ALIGN(reg_count
, 16) / 16 - 1;
1721 static inline uint32_t
1722 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1723 uint32_t prog_offset
)
1725 if (brw
->gen
>= 5) {
1726 /* Using state base address. */
1730 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1734 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1736 return brw
->cache
.bo
->offset64
+ prog_offset
;
1739 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1740 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1741 struct exec_list
*instructions
);
1742 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
1744 struct opcode_desc
{
1750 extern const struct opcode_desc opcode_descs
[128];
1751 extern const char * const conditional_modifier
[16];
1752 extern const char *const pred_ctrl_align16
[16];
1755 brw_emit_depthbuffer(struct brw_context
*brw
);
1758 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1759 struct intel_mipmap_tree
*depth_mt
,
1760 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1761 uint32_t depth_surface_type
,
1762 struct intel_mipmap_tree
*stencil_mt
,
1763 bool hiz
, bool separate_stencil
,
1764 uint32_t width
, uint32_t height
,
1765 uint32_t tile_x
, uint32_t tile_y
);
1768 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1769 struct intel_mipmap_tree
*depth_mt
,
1770 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1771 uint32_t depth_surface_type
,
1772 struct intel_mipmap_tree
*stencil_mt
,
1773 bool hiz
, bool separate_stencil
,
1774 uint32_t width
, uint32_t height
,
1775 uint32_t tile_x
, uint32_t tile_y
);
1778 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1779 struct intel_mipmap_tree
*depth_mt
,
1780 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1781 uint32_t depth_surface_type
,
1782 struct intel_mipmap_tree
*stencil_mt
,
1783 bool hiz
, bool separate_stencil
,
1784 uint32_t width
, uint32_t height
,
1785 uint32_t tile_x
, uint32_t tile_y
);
1787 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1788 struct intel_mipmap_tree
*depth_mt
,
1789 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1790 uint32_t depth_surface_type
,
1791 struct intel_mipmap_tree
*stencil_mt
,
1792 bool hiz
, bool separate_stencil
,
1793 uint32_t width
, uint32_t height
,
1794 uint32_t tile_x
, uint32_t tile_y
);
1796 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1797 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1799 uint32_t get_hw_prim_for_gl_prim(int mode
);
1802 gen6_upload_push_constants(struct brw_context
*brw
,
1803 const struct gl_program
*prog
,
1804 const struct brw_stage_prog_data
*prog_data
,
1805 struct brw_stage_state
*stage_state
,
1806 enum aub_state_struct_type type
);
1809 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1810 const struct intel_mipmap_tree
*mt
);
1812 /* brw_pipe_control.c */
1813 int brw_init_pipe_control(struct brw_context
*brw
,
1814 const struct brw_device_info
*info
);
1815 void brw_fini_pipe_control(struct brw_context
*brw
);
1817 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1818 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1819 drm_intel_bo
*bo
, uint32_t offset
,
1820 uint32_t imm_lower
, uint32_t imm_upper
);
1821 void brw_emit_mi_flush(struct brw_context
*brw
);
1822 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1823 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1824 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1825 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);