2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_pipe_control.h"
41 #include "compiler/brw_compiler.h"
44 #include "blorp/blorp.h"
46 #include <brw_bufmgr.h>
48 #include "common/gen_debug.h"
49 #include "intel_screen.h"
50 #include "intel_tex_obj.h"
57 * URB - uniform resource buffer. A mid-sized buffer which is
58 * partitioned between the fixed function units and used for passing
59 * values (vertices, primitives, constants) between them.
61 * CURBE - constant URB entry. An urb region (entry) used to hold
62 * constant values which the fixed function units can be instructed to
63 * preload into the GRF when spawning a thread.
65 * VUE - vertex URB entry. An urb entry holding a vertex and usually
66 * a vertex header. The header contains control information and
67 * things like primitive type, Begin/end flags and clip codes.
69 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
70 * unit holding rasterization and interpolation parameters.
72 * GRF - general register file. One of several register files
73 * addressable by programmed threads. The inputs (r0, payload, curbe,
74 * urb) of the thread are preloaded to this area before the thread is
75 * spawned. The registers are individually 8 dwords wide and suitable
76 * for general usage. Registers holding thread input values are not
77 * special and may be overwritten.
79 * MRF - message register file. Threads communicate (and terminate)
80 * by sending messages. Message parameters are placed in contiguous
81 * MRF registers. All program output is via these messages. URB
82 * entries are populated by sending a message to the shared URB
83 * function containing the new data, together with a control word,
84 * often an unmodified copy of R0.
86 * R0 - GRF register 0. Typically holds control information used when
87 * sending messages to other threads.
89 * EU or GEN4 EU: The name of the programmable subsystem of the
90 * i965 hardware. Threads are executed by the EU, the registers
91 * described above are part of the EU architecture.
93 * Fixed function units:
95 * CS - Command streamer. Notional first unit, little software
96 * interaction. Holds the URB entries used for constant data, ie the
99 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
100 * this unit is responsible for pulling vertices out of vertex buffers
101 * in vram and injecting them into the processing pipe as VUEs. If
102 * enabled, it first passes them to a VS thread which is a good place
103 * for the driver to implement any active vertex shader.
105 * HS - Hull Shader (Tessellation Control Shader)
107 * TE - Tessellation Engine (Tessellation Primitive Generation)
109 * DS - Domain Shader (Tessellation Evaluation Shader)
111 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
112 * enabled, incoming strips etc are passed to GS threads in individual
113 * line/triangle/point units. The GS thread may perform arbitary
114 * computation and emit whatever primtives with whatever vertices it
115 * chooses. This makes GS an excellent place to implement GL's
116 * unfilled polygon modes, though of course it is capable of much
117 * more. Additionally, GS is used to translate away primitives not
118 * handled by latter units, including Quads and Lineloops.
120 * CS - Clipper. Mesa's clipping algorithms are imported to run on
121 * this unit. The fixed function part performs cliptesting against
122 * the 6 fixed clipplanes and makes descisions on whether or not the
123 * incoming primitive needs to be passed to a thread for clipping.
124 * User clip planes are handled via cooperation with the VS thread.
126 * SF - Strips Fans or Setup: Triangles are prepared for
127 * rasterization. Interpolation coefficients are calculated.
128 * Flatshading and two-side lighting usually performed here.
130 * WM - Windower. Interpolation of vertex attributes performed here.
131 * Fragment shader implemented here. SIMD aspects of EU taken full
132 * advantage of, as pixels are processed in blocks of 16.
134 * CC - Color Calculator. No EU threads associated with this unit.
135 * Handles blending and (presumably) depth and stencil testing.
140 struct brw_vs_prog_key
;
141 struct brw_vue_prog_key
;
142 struct brw_wm_prog_key
;
143 struct brw_wm_prog_data
;
144 struct brw_cs_prog_key
;
145 struct brw_cs_prog_data
;
149 BRW_COMPUTE_PIPELINE
,
156 BRW_CACHE_BLORP_PROG
,
159 BRW_CACHE_FF_GS_PROG
,
170 /* brw_cache_ids must come first - see brw_program_cache.c */
171 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
172 BRW_STATE_FRAGMENT_PROGRAM
,
173 BRW_STATE_GEOMETRY_PROGRAM
,
174 BRW_STATE_TESS_PROGRAMS
,
175 BRW_STATE_VERTEX_PROGRAM
,
176 BRW_STATE_REDUCED_PRIMITIVE
,
177 BRW_STATE_PATCH_PRIMITIVE
,
182 BRW_STATE_BINDING_TABLE_POINTERS
,
185 BRW_STATE_DEFAULT_TESS_LEVELS
,
187 BRW_STATE_INDEX_BUFFER
,
188 BRW_STATE_VS_CONSTBUF
,
189 BRW_STATE_TCS_CONSTBUF
,
190 BRW_STATE_TES_CONSTBUF
,
191 BRW_STATE_GS_CONSTBUF
,
192 BRW_STATE_PROGRAM_CACHE
,
193 BRW_STATE_STATE_BASE_ADDRESS
,
194 BRW_STATE_VUE_MAP_GEOM_OUT
,
195 BRW_STATE_TRANSFORM_FEEDBACK
,
196 BRW_STATE_RASTERIZER_DISCARD
,
198 BRW_STATE_UNIFORM_BUFFER
,
199 BRW_STATE_IMAGE_UNITS
,
200 BRW_STATE_META_IN_PROGRESS
,
201 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
202 BRW_STATE_NUM_SAMPLES
,
203 BRW_STATE_TEXTURE_BUFFER
,
204 BRW_STATE_GEN4_UNIT_STATE
,
208 BRW_STATE_SAMPLER_STATE_TABLE
,
209 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
210 BRW_STATE_COMPUTE_PROGRAM
,
211 BRW_STATE_CS_WORK_GROUPS
,
215 BRW_STATE_VIEWPORT_COUNT
,
216 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
223 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
225 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
226 * When the currently bound shader program differs from the previous draw
227 * call, these will be flagged. They cover brw->{stage}_program and
228 * ctx->{Stage}Program->_Current.
230 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
231 * driver perspective. Even if the same shader is bound at the API level,
232 * we may need to switch between multiple versions of that shader to handle
233 * changes in non-orthagonal state.
235 * Additionally, multiple shader programs may have identical vertex shaders
236 * (for example), or compile down to the same code in the backend. We combine
237 * those into a single program cache entry.
239 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
240 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
242 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
243 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
244 * use the normal state upload paths), but the cache is still used. To avoid
245 * polluting the brw_program_cache code with special cases, we retain the
246 * dirty bit for now. It should eventually be removed.
248 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
249 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
250 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
251 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
252 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
253 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
254 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
255 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
256 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
257 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
258 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
259 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
260 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
261 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
262 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
263 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
264 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
265 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
266 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
267 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
268 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
269 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
270 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
271 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
273 * Used for any batch entry with a relocated pointer that will be used
274 * by any 3D rendering.
276 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
277 /** \see brw.state.depth_region */
278 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
279 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
280 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
281 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
282 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
283 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
284 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
285 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
286 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
287 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
288 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
289 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
290 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
291 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
292 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
293 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
294 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
295 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
296 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
297 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
298 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
299 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
300 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
301 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
302 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
303 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
304 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
305 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
306 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
307 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
308 #define BRW_NEW_DRAW_CALL (1ull << BRW_STATE_DRAW_CALL)
309 #define BRW_NEW_AUX_STATE (1ull << BRW_STATE_AUX)
311 struct brw_state_flags
{
312 /** State update flags signalled by mesa internals */
315 * State update flags signalled as the result of brw_tracked_state updates
321 /** Subclass of Mesa program */
323 struct gl_program program
;
330 struct brw_ff_gs_prog_data
{
331 GLuint urb_read_length
;
335 * Gen6 transform feedback: Amount by which the streaming vertex buffer
336 * indices should be incremented each time the GS is invoked.
338 unsigned svbi_postincrement_value
;
341 /** Number of texture sampler units */
342 #define BRW_MAX_TEX_UNIT 32
344 /** Max number of UBOs in a shader */
345 #define BRW_MAX_UBO 14
347 /** Max number of SSBOs in a shader */
348 #define BRW_MAX_SSBO 12
350 /** Max number of atomic counter buffer objects in a shader */
351 #define BRW_MAX_ABO 16
353 /** Max number of image uniforms in a shader */
354 #define BRW_MAX_IMAGES 32
356 /** Maximum number of actual buffers used for stream output */
357 #define BRW_MAX_SOL_BUFFERS 4
359 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
360 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
365 2 + /* shader time, pull constants */ \
366 1 /* cs num work groups */)
369 struct brw_context
*brw
;
371 struct brw_cache_item
**items
;
374 GLuint size
, n_items
;
376 uint32_t next_offset
;
379 #define perf_debug(...) do { \
380 static GLuint msg_id = 0; \
381 if (unlikely(INTEL_DEBUG & DEBUG_PERF)) \
382 dbg_printf(__VA_ARGS__); \
383 if (brw->perf_debug) \
384 _mesa_gl_debug(&brw->ctx, &msg_id, \
385 MESA_DEBUG_SOURCE_API, \
386 MESA_DEBUG_TYPE_PERFORMANCE, \
387 MESA_DEBUG_SEVERITY_MEDIUM, \
391 #define WARN_ONCE(cond, fmt...) do { \
392 if (unlikely(cond)) { \
393 static bool _warned = false; \
394 static GLuint msg_id = 0; \
396 fprintf(stderr, "WARNING: "); \
397 fprintf(stderr, fmt); \
400 _mesa_gl_debug(ctx, &msg_id, \
401 MESA_DEBUG_SOURCE_API, \
402 MESA_DEBUG_TYPE_OTHER, \
403 MESA_DEBUG_SEVERITY_HIGH, fmt); \
408 /* Considered adding a member to this struct to document which flags
409 * an update might raise so that ordering of the state atoms can be
410 * checked or derived at runtime. Dropped the idea in favor of having
411 * a debug mode where the state is monitored for flags which are
412 * raised that have already been tested against.
414 struct brw_tracked_state
{
415 struct brw_state_flags dirty
;
416 void (*emit
)( struct brw_context
*brw
);
419 enum shader_time_shader_type
{
430 struct brw_vertex_buffer
{
431 /** Buffer object containing the uploaded vertex data */
435 /** Byte stride between elements in the uploaded array */
439 struct brw_vertex_element
{
440 const struct gl_vertex_array
*glarray
;
444 /** Offset of the first element within the buffer object */
448 struct brw_query_object
{
449 struct gl_query_object Base
;
451 /** Last query BO associated with this query. */
454 /** Last index in bo with query data for this object. */
457 /** True if we know the batch has been flushed since we ended the query. */
467 struct brw_reloc_list
{
468 struct drm_i915_gem_relocation_entry
*relocs
;
470 int reloc_array_size
;
473 struct brw_growing_bo
{
479 struct intel_batchbuffer
{
480 /** Current batchbuffer being queued up. */
481 struct brw_growing_bo batch
;
482 /** Current statebuffer being queued up. */
483 struct brw_growing_bo state
;
485 /** Last batchbuffer submitted to the hardware. Used for glFinish(). */
486 struct brw_bo
*last_bo
;
489 uint16_t emit
, total
;
494 enum brw_gpu_ring ring
;
495 bool use_batch_first
;
496 bool needs_sol_reset
;
497 bool state_base_address_emitted
;
500 struct brw_reloc_list batch_relocs
;
501 struct brw_reloc_list state_relocs
;
502 unsigned int valid_reloc_flags
;
504 /** The validation list */
505 struct drm_i915_gem_exec_object2
*validation_list
;
506 struct brw_bo
**exec_bos
;
510 /** The amount of aperture space (in bytes) used by all exec_bos */
515 int batch_reloc_count
;
516 int state_reloc_count
;
520 /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */
521 struct hash_table
*state_batch_sizes
;
524 #define BRW_MAX_XFB_STREAMS 4
526 struct brw_transform_feedback_counter
{
528 * Index of the first entry of this counter within the primitive count BO.
529 * An entry is considered to be an N-tuple of 64bit values, where N is the
530 * number of vertex streams supported by the platform.
535 * Index one past the last entry of this counter within the primitive
541 * Primitive count values accumulated while this counter was active,
542 * excluding any entries buffered between \c bo_start and \c bo_end, which
543 * haven't been accounted for yet.
545 uint64_t accum
[BRW_MAX_XFB_STREAMS
];
549 brw_reset_transform_feedback_counter(
550 struct brw_transform_feedback_counter
*counter
)
552 counter
->bo_start
= counter
->bo_end
;
553 memset(&counter
->accum
, 0, sizeof(counter
->accum
));
556 struct brw_transform_feedback_object
{
557 struct gl_transform_feedback_object base
;
559 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
560 struct brw_bo
*offset_bo
;
562 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
565 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
566 GLenum primitive_mode
;
569 * The maximum number of vertices that we can write without overflowing
570 * any of the buffers currently being used for transform feedback.
574 struct brw_bo
*prim_count_bo
;
577 * Count of primitives generated during this transform feedback operation.
579 struct brw_transform_feedback_counter counter
;
582 * Count of primitives generated during the previous transform feedback
583 * operation. Used to implement DrawTransformFeedback().
585 struct brw_transform_feedback_counter previous_counter
;
588 * Number of vertices written between last Begin/EndTransformFeedback().
590 * Used to implement DrawTransformFeedback().
592 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
593 bool vertices_written_valid
;
597 * Data shared between each programmable stage in the pipeline (vs, gs, and
600 struct brw_stage_state
602 gl_shader_stage stage
;
603 struct brw_stage_prog_data
*prog_data
;
606 * Optional scratch buffer used to store spilled register values and
607 * variably-indexed GRF arrays.
609 * The contents of this buffer are short-lived so the same memory can be
610 * re-used at will for multiple shader programs (executed by the same fixed
611 * function). However reusing a scratch BO for which shader invocations
612 * are still in flight with a per-thread scratch slot size other than the
613 * original can cause threads with different scratch slot size and FFTID
614 * (which may be executed in parallel depending on the shader stage and
615 * hardware generation) to map to an overlapping region of the scratch
616 * space, which can potentially lead to mutual scratch space corruption.
617 * For that reason if you borrow this scratch buffer you should only be
618 * using the slot size given by the \c per_thread_scratch member below,
619 * unless you're taking additional measures to synchronize thread execution
620 * across slot size changes.
622 struct brw_bo
*scratch_bo
;
625 * Scratch slot size allocated for each thread in the buffer object given
628 uint32_t per_thread_scratch
;
630 /** Offset in the program cache to the program */
631 uint32_t prog_offset
;
633 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
634 uint32_t state_offset
;
636 struct brw_bo
*push_const_bo
; /* NULL if using the batchbuffer */
637 uint32_t push_const_offset
; /* Offset in the push constant BO or batch */
638 int push_const_size
; /* in 256-bit register increments */
640 /* Binding table: pointers to SURFACE_STATE entries. */
641 uint32_t bind_bo_offset
;
642 uint32_t surf_offset
[BRW_MAX_SURFACES
];
644 /** SAMPLER_STATE count and table offset */
645 uint32_t sampler_count
;
646 uint32_t sampler_offset
;
648 struct brw_image_param image_param
[BRW_MAX_IMAGES
];
650 /** Need to re-emit 3DSTATE_CONSTANT_XS? */
651 bool push_constants_dirty
;
654 enum brw_predicate_state
{
655 /* The first two states are used if we can determine whether to draw
656 * without having to look at the values in the query object buffer. This
657 * will happen if there is no conditional render in progress, if the query
658 * object is already completed or if something else has already added
659 * samples to the preliminary result such as via a BLT command.
661 BRW_PREDICATE_STATE_RENDER
,
662 BRW_PREDICATE_STATE_DONT_RENDER
,
663 /* In this case whether to draw or not depends on the result of an
664 * MI_PREDICATE command so the predicate enable bit needs to be checked.
666 BRW_PREDICATE_STATE_USE_BIT
,
667 /* In this case, either MI_PREDICATE doesn't exist or we lack the
668 * necessary kernel features to use it. Stall for the query result.
670 BRW_PREDICATE_STATE_STALL_FOR_QUERY
,
675 struct gen_l3_config
;
677 enum brw_query_kind
{
682 struct brw_perf_query_register_prog
{
687 struct brw_perf_query_info
689 enum brw_query_kind kind
;
692 struct brw_perf_query_counter
*counters
;
697 uint64_t oa_metrics_set_id
;
700 /* For indexing into the accumulator[] ... */
702 int gpu_clock_offset
;
707 /* Register programming for a given query */
708 struct brw_perf_query_register_prog
*flex_regs
;
709 uint32_t n_flex_regs
;
711 struct brw_perf_query_register_prog
*mux_regs
;
714 struct brw_perf_query_register_prog
*b_counter_regs
;
715 uint32_t n_b_counter_regs
;
719 * brw_context is derived from gl_context.
723 struct gl_context ctx
; /**< base class, must be first field */
728 * Send the appropriate state packets to configure depth, stencil, and
729 * HiZ buffers (i965+ only)
731 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
732 struct intel_mipmap_tree
*depth_mt
,
733 uint32_t depth_offset
,
734 uint32_t depthbuffer_format
,
735 uint32_t depth_surface_type
,
736 struct intel_mipmap_tree
*stencil_mt
,
737 bool hiz
, bool separate_stencil
,
738 uint32_t width
, uint32_t height
,
739 uint32_t tile_x
, uint32_t tile_y
);
742 * Emit an MI_REPORT_PERF_COUNT command packet.
744 * This asks the GPU to write a report of the current OA counter values
745 * into @bo at the given offset and containing the given @report_id
746 * which we can cross-reference when parsing the report (gen7+ only).
748 void (*emit_mi_report_perf_count
)(struct brw_context
*brw
,
750 uint32_t offset_in_bytes
,
754 struct brw_bufmgr
*bufmgr
;
758 /** BO for post-sync nonzero writes for gen6 workaround. */
759 struct brw_bo
*workaround_bo
;
760 uint8_t pipe_controls_since_last_cs_stall
;
763 * Set of struct brw_bo * that have been rendered to within this batchbuffer
764 * and would need flushing before being used from another cache domain that
765 * isn't coherent with it (i.e. the sampler).
767 struct hash_table
*render_cache
;
770 * Set of struct brw_bo * that have been used as a depth buffer within this
771 * batchbuffer and would need flushing before being used from another cache
772 * domain that isn't coherent with it (i.e. the sampler).
774 struct set
*depth_cache
;
777 * Number of resets observed in the system at context creation.
779 * This is tracked in the context so that we can determine that another
780 * reset has occurred.
782 uint32_t reset_count
;
784 struct intel_batchbuffer batch
;
789 uint32_t next_offset
;
793 * Set if rendering has occurred to the drawable's front buffer.
795 * This is used in the DRI2 case to detect that glFlush should also copy
796 * the contents of the fake front buffer to the real front buffer.
798 bool front_buffer_dirty
;
800 /** Framerate throttling: @{ */
801 struct brw_bo
*throttle_batch
[2];
803 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
804 * frame of rendering to complete. This gives a very precise cap to the
805 * latency between input and output such that rendering never gets more
806 * than a frame behind the user. (With the caveat that we technically are
807 * not using the SwapBuffers itself as a barrier but the first batch
808 * submitted afterwards, which may be immediately prior to the next
811 bool need_swap_throttle
;
813 /** General throttling, not caught by throttling between SwapBuffers */
814 bool need_flush_throttle
;
824 bool always_flush_batch
;
825 bool always_flush_cache
;
826 bool disable_throttling
;
828 bool dual_color_blend_by_location
;
830 driOptionCache optionCache
;
833 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
835 GLenum reduced_primitive
;
838 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
839 * variable is set, this is the flag indicating to do expensive work that
840 * might lead to a perf_debug() call.
844 uint64_t max_gtt_map_object_size
;
847 bool has_separate_stencil
;
850 /** Derived stencil states. */
851 bool stencil_enabled
;
852 bool stencil_two_sided
;
853 bool stencil_write_enabled
;
854 /** Derived polygon state. */
855 bool polygon_front_bit
; /**< 0=GL_CCW, 1=GL_CW */
857 struct isl_device isl_dev
;
859 struct blorp_context blorp
;
863 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
866 enum brw_pipeline last_pipeline
;
868 struct brw_cache cache
;
870 /* Whether a meta-operation is in progress. */
871 bool meta_in_progress
;
873 /* Whether the last depth/stencil packets were both NULL. */
874 bool no_depth_or_stencil
;
876 /* The last PMA stall bits programmed. */
877 uint32_t pma_stall_bits
;
881 /** The value of gl_BaseVertex for the current _mesa_prim. */
884 /** The value of gl_BaseInstance for the current _mesa_prim. */
889 * Buffer and offset used for GL_ARB_shader_draw_parameters
890 * (for now, only gl_BaseVertex).
892 struct brw_bo
*draw_params_bo
;
893 uint32_t draw_params_offset
;
896 * The value of gl_DrawID for the current _mesa_prim. This always comes
897 * in from it's own vertex buffer since it's not part of the indirect
901 struct brw_bo
*draw_id_bo
;
902 uint32_t draw_id_offset
;
905 * Pointer to the the buffer storing the indirect draw parameters. It
906 * currently only stores the number of requested draw calls but more
907 * parameters could potentially be added.
909 struct brw_bo
*draw_params_count_bo
;
910 uint32_t draw_params_count_offset
;
915 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
916 * an indirect call, and num_work_groups_offset is valid. Otherwise,
917 * num_work_groups is set based on glDispatchCompute.
919 struct brw_bo
*num_work_groups_bo
;
920 GLintptr num_work_groups_offset
;
921 const GLuint
*num_work_groups
;
925 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
926 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
928 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
932 /* Summary of size and varying of active arrays, so we can check
933 * for changes to this state:
935 bool index_bounds_valid
;
936 unsigned int min_index
, max_index
;
938 /* Offset from start of vertex buffer so we can avoid redefining
939 * the same VB packed over and over again.
941 unsigned int start_vertex_bias
;
944 * Certain vertex attribute formats aren't natively handled by the
945 * hardware and require special VS code to fix up their values.
947 * These bitfields indicate which workarounds are needed.
949 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
954 * Index buffer for this draw_prims call.
956 * Updates are signaled by BRW_NEW_INDICES.
958 const struct _mesa_index_buffer
*ib
;
960 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
965 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
966 * avoid re-uploading the IB packet over and over if we're actually
967 * referencing the same index buffer.
969 unsigned int start_vertex_offset
;
972 /* Active vertex program:
974 struct gl_program
*programs
[MESA_SHADER_STAGES
];
977 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
978 * that we don't have to reemit that state every time we change FBOs.
982 /* BRW_NEW_URB_ALLOCATIONS:
985 GLuint vsize
; /* vertex size plus header in urb registers */
986 GLuint gsize
; /* GS output size in urb registers */
987 GLuint hsize
; /* Tessellation control output size in urb registers */
988 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
989 GLuint csize
; /* constant buffer size in urb registers */
990 GLuint sfsize
; /* setup data size in urb registers */
994 GLuint nr_vs_entries
;
995 GLuint nr_hs_entries
;
996 GLuint nr_ds_entries
;
997 GLuint nr_gs_entries
;
998 GLuint nr_clip_entries
;
999 GLuint nr_sf_entries
;
1000 GLuint nr_cs_entries
;
1010 * URB size in the current configuration. The units this is expressed
1011 * in are somewhat inconsistent, see gen_device_info::urb::size.
1013 * FINISHME: Represent the URB size consistently in KB on all platforms.
1017 /* True if the most recently sent _3DSTATE_URB message allocated
1018 * URB space for the GS.
1022 /* True if the most recently sent _3DSTATE_URB message allocated
1023 * URB space for the HS and DS.
1029 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
1031 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1032 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1040 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1041 * for upload to the CURBE.
1043 struct brw_bo
*curbe_bo
;
1044 /** Offset within curbe_bo of space for current curbe entry */
1045 GLuint curbe_offset
;
1049 * Layout of vertex data exiting the geometry portion of the pipleine.
1050 * This comes from the last enabled shader stage (GS, DS, or VS).
1052 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1054 struct brw_vue_map vue_map_geom_out
;
1057 struct brw_stage_state base
;
1061 struct brw_stage_state base
;
1065 struct brw_stage_state base
;
1069 struct brw_stage_state base
;
1072 * True if the 3DSTATE_GS command most recently emitted to the 3D
1073 * pipeline enabled the GS; false otherwise.
1079 struct brw_ff_gs_prog_data
*prog_data
;
1082 /** Offset in the program cache to the CLIP program pre-gen6 */
1083 uint32_t prog_offset
;
1084 uint32_t state_offset
;
1086 uint32_t bind_bo_offset
;
1088 * Surface offsets for the binding table. We only need surfaces to
1089 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1090 * need in this case.
1092 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1096 struct brw_clip_prog_data
*prog_data
;
1098 /** Offset in the program cache to the CLIP program pre-gen6 */
1099 uint32_t prog_offset
;
1101 /* Offset in the batch to the CLIP state on pre-gen6. */
1102 uint32_t state_offset
;
1104 /* As of gen6, this is the offset in the batch to the CLIP VP,
1110 * The number of viewports to use. If gl_ViewportIndex is written,
1111 * we can have up to ctx->Const.MaxViewports viewports. If not,
1112 * the viewport index is always 0, so we can only emit one.
1114 uint8_t viewport_count
;
1119 struct brw_sf_prog_data
*prog_data
;
1121 /** Offset in the program cache to the CLIP program pre-gen6 */
1122 uint32_t prog_offset
;
1123 uint32_t state_offset
;
1128 struct brw_stage_state base
;
1131 * Buffer object used in place of multisampled null render targets on
1132 * Gen6. See brw_emit_null_surface_state().
1134 struct brw_bo
*multisampled_null_render_target_bo
;
1140 struct brw_stage_state base
;
1144 uint32_t state_offset
;
1145 uint32_t blend_state_offset
;
1146 uint32_t depth_stencil_state_offset
;
1151 struct brw_query_object
*obj
;
1156 enum brw_predicate_state state
;
1161 /* Variables referenced in the XML meta data for OA performance
1162 * counters, e.g in the normalization equations.
1164 * All uint64_t for consistent operand types in generated code
1167 uint64_t timestamp_frequency
; /** $GpuTimestampFrequency */
1168 uint64_t n_eus
; /** $EuCoresTotalCount */
1169 uint64_t n_eu_slices
; /** $EuSlicesTotalCount */
1170 uint64_t n_eu_sub_slices
; /** $EuSubslicesTotalCount */
1171 uint64_t eu_threads_count
; /** $EuThreadsCount */
1172 uint64_t slice_mask
; /** $SliceMask */
1173 uint64_t subslice_mask
; /** $SubsliceMask */
1174 uint64_t gt_min_freq
; /** $GpuMinFrequency */
1175 uint64_t gt_max_freq
; /** $GpuMaxFrequency */
1176 uint64_t revision
; /** $SkuRevisionId */
1179 /* OA metric sets, indexed by GUID, as know by Mesa at build time,
1180 * to cross-reference with the GUIDs of configs advertised by the
1183 struct hash_table
*oa_metrics_table
;
1185 struct brw_perf_query_info
*queries
;
1188 /* The i915 perf stream we open to setup + enable the OA counters */
1191 /* An i915 perf stream fd gives exclusive access to the OA unit that will
1192 * report counter snapshots for a specific counter set/profile in a
1193 * specific layout/format so we can only start OA queries that are
1194 * compatible with the currently open fd...
1196 int current_oa_metrics_set_id
;
1197 int current_oa_format
;
1199 /* List of buffers containing OA reports */
1200 struct exec_list sample_buffers
;
1202 /* Cached list of empty sample buffers */
1203 struct exec_list free_sample_buffers
;
1205 int n_active_oa_queries
;
1206 int n_active_pipeline_stats_queries
;
1208 /* The number of queries depending on running OA counters which
1209 * extends beyond brw_end_perf_query() since we need to wait until
1210 * the last MI_RPC command has parsed by the GPU.
1212 * Accurate accounting is important here as emitting an
1213 * MI_REPORT_PERF_COUNT command while the OA unit is disabled will
1214 * effectively hang the gpu.
1218 /* To help catch an spurious problem with the hardware or perf
1219 * forwarding samples, we emit each MI_REPORT_PERF_COUNT command
1220 * with a unique ID that we can explicitly check for...
1222 int next_query_start_report_id
;
1225 * An array of queries whose results haven't yet been assembled
1226 * based on the data in buffer objects.
1228 * These may be active, or have already ended. However, the
1229 * results have not been requested.
1231 struct brw_perf_query_object
**unaccumulated
;
1232 int unaccumulated_elements
;
1233 int unaccumulated_array_size
;
1235 /* The total number of query objects so we can relinquish
1236 * our exclusive access to perf if the application deletes
1237 * all of its objects. (NB: We only disable perf while
1238 * there are no active queries)
1240 int n_query_instances
;
1243 int num_atoms
[BRW_NUM_PIPELINES
];
1244 const struct brw_tracked_state render_atoms
[76];
1245 const struct brw_tracked_state compute_atoms
[11];
1247 const enum isl_format
*mesa_to_isl_render_format
;
1248 const bool *mesa_format_supports_render
;
1250 /* PrimitiveRestart */
1253 bool enable_cut_index
;
1256 /** Computed depth/stencil/hiz state from the current attached
1257 * renderbuffers, valid only during the drawing state upload loop after
1258 * brw_workaround_depthstencil_alignment().
1261 /* Inter-tile (page-aligned) byte offsets. */
1262 uint32_t depth_offset
;
1263 /* Intra-tile x,y offsets for drawing to combined depth-stencil. Only
1266 uint32_t tile_x
, tile_y
;
1269 uint32_t num_instances
;
1274 const struct gen_l3_config
*config
;
1281 enum shader_time_shader_type
*types
;
1282 struct shader_times
*cumulative
;
1288 struct brw_fast_clear_state
*fast_clear_state
;
1290 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1291 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1292 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1294 * This is needed in case the same underlying buffer is also configured
1295 * to be sampled but with a format that the sampling engine can't treat
1296 * compressed or fast cleared.
1298 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1300 __DRIcontext
*driContext
;
1301 struct intel_screen
*screen
;
1305 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1307 /*======================================================================
1310 extern const char *const brw_vendor_string
;
1313 brw_get_renderer_string(const struct intel_screen
*screen
);
1316 DRI_CONF_BO_REUSE_DISABLED
,
1317 DRI_CONF_BO_REUSE_ALL
1320 void intel_update_renderbuffers(__DRIcontext
*context
,
1321 __DRIdrawable
*drawable
);
1322 void intel_prepare_render(struct brw_context
*brw
);
1324 void brw_predraw_resolve_inputs(struct brw_context
*brw
, bool rendering
);
1326 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1327 __DRIdrawable
*drawable
);
1329 GLboolean
brwCreateContext(gl_api api
,
1330 const struct gl_config
*mesaVis
,
1331 __DRIcontext
*driContextPriv
,
1332 const struct __DriverContextConfig
*ctx_config
,
1334 void *sharedContextPrivate
);
1336 /*======================================================================
1340 brw_meta_resolve_color(struct brw_context
*brw
,
1341 struct intel_mipmap_tree
*mt
);
1343 /*======================================================================
1346 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1347 GLbitfield clear_mask
);
1349 /* brw_object_purgeable.c */
1350 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1352 /*======================================================================
1355 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1356 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1357 void brw_emit_query_begin(struct brw_context
*brw
);
1358 void brw_emit_query_end(struct brw_context
*brw
);
1359 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1360 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1361 uint64_t brw_timebase_scale(struct brw_context
*brw
, uint64_t gpu_timestamp
);
1362 uint64_t brw_raw_timestamp_delta(struct brw_context
*brw
,
1363 uint64_t time0
, uint64_t time1
);
1365 /** gen6_queryobj.c */
1366 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1367 void brw_write_timestamp(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1368 void brw_write_depth_count(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1370 /** hsw_queryobj.c */
1371 void hsw_overflow_result_to_gpr0(struct brw_context
*brw
,
1372 struct brw_query_object
*query
,
1374 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1376 /** brw_conditional_render.c */
1377 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1378 bool brw_check_conditional_render(struct brw_context
*brw
);
1380 /** intel_batchbuffer.c */
1381 void brw_load_register_mem(struct brw_context
*brw
,
1385 void brw_load_register_mem64(struct brw_context
*brw
,
1389 void brw_store_register_mem32(struct brw_context
*brw
,
1390 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1391 void brw_store_register_mem64(struct brw_context
*brw
,
1392 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1393 void brw_load_register_imm32(struct brw_context
*brw
,
1394 uint32_t reg
, uint32_t imm
);
1395 void brw_load_register_imm64(struct brw_context
*brw
,
1396 uint32_t reg
, uint64_t imm
);
1397 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1399 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1401 void brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1402 uint32_t offset
, uint32_t imm
);
1403 void brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1404 uint32_t offset
, uint64_t imm
);
1406 /*======================================================================
1407 * intel_tex_validate.c
1409 void brw_validate_textures( struct brw_context
*brw
);
1412 /*======================================================================
1416 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1419 perf_debug(" %s %d->%d\n", name
, a
, b
);
1425 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1427 void brw_get_scratch_bo(struct brw_context
*brw
,
1428 struct brw_bo
**scratch_bo
, int size
);
1429 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1430 struct brw_stage_state
*stage_state
,
1431 unsigned per_thread_size
);
1432 void brw_init_shader_time(struct brw_context
*brw
);
1433 int brw_get_shader_time_index(struct brw_context
*brw
,
1434 struct gl_program
*prog
,
1435 enum shader_time_shader_type type
,
1437 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1438 void brw_destroy_shader_time(struct brw_context
*brw
);
1442 void brw_calculate_urb_fence(struct brw_context
*brw
, unsigned csize
,
1443 unsigned vsize
, unsigned sfsize
);
1444 void brw_upload_urb_fence(struct brw_context
*brw
);
1448 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1451 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1453 /* brw_draw_upload.c */
1454 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1455 const struct gl_vertex_array
*glarray
);
1457 static inline unsigned
1458 brw_get_index_type(unsigned index_size
)
1460 /* The hw needs 0x00, 0x01, and 0x02 for ubyte, ushort, and uint,
1463 return index_size
>> 1;
1466 void brw_prepare_vertices(struct brw_context
*brw
);
1468 /* brw_wm_surface_state.c */
1469 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1471 uint32_t *surf_offset
);
1473 brw_update_sol_surface(struct brw_context
*brw
,
1474 struct gl_buffer_object
*buffer_obj
,
1475 uint32_t *out_offset
, unsigned num_vector_components
,
1476 unsigned stride_dwords
, unsigned offset_dwords
);
1477 void brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1478 struct brw_stage_state
*stage_state
,
1479 struct brw_stage_prog_data
*prog_data
);
1480 void brw_upload_image_surfaces(struct brw_context
*brw
,
1481 const struct gl_program
*prog
,
1482 struct brw_stage_state
*stage_state
,
1483 struct brw_stage_prog_data
*prog_data
);
1485 /* brw_surface_formats.c */
1486 void intel_screen_init_surface_formats(struct intel_screen
*screen
);
1487 void brw_init_surface_formats(struct brw_context
*brw
);
1488 bool brw_render_target_supported(struct brw_context
*brw
,
1489 struct gl_renderbuffer
*rb
);
1490 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1492 /* brw_performance_query.c */
1493 void brw_init_performance_queries(struct brw_context
*brw
);
1495 /* intel_extensions.c */
1496 extern void intelInitExtensions(struct gl_context
*ctx
);
1499 extern int intel_translate_shadow_compare_func(GLenum func
);
1500 extern int intel_translate_compare_func(GLenum func
);
1501 extern int intel_translate_stencil_op(GLenum op
);
1502 extern int intel_translate_logic_op(GLenum opcode
);
1505 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1508 struct gl_transform_feedback_object
*
1509 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1511 brw_delete_transform_feedback(struct gl_context
*ctx
,
1512 struct gl_transform_feedback_object
*obj
);
1514 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1515 struct gl_transform_feedback_object
*obj
);
1517 brw_end_transform_feedback(struct gl_context
*ctx
,
1518 struct gl_transform_feedback_object
*obj
);
1520 brw_pause_transform_feedback(struct gl_context
*ctx
,
1521 struct gl_transform_feedback_object
*obj
);
1523 brw_resume_transform_feedback(struct gl_context
*ctx
,
1524 struct gl_transform_feedback_object
*obj
);
1526 brw_save_primitives_written_counters(struct brw_context
*brw
,
1527 struct brw_transform_feedback_object
*obj
);
1529 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1530 struct gl_transform_feedback_object
*obj
,
1533 /* gen7_sol_state.c */
1535 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1536 struct gl_transform_feedback_object
*obj
);
1538 gen7_end_transform_feedback(struct gl_context
*ctx
,
1539 struct gl_transform_feedback_object
*obj
);
1541 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1542 struct gl_transform_feedback_object
*obj
);
1544 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1545 struct gl_transform_feedback_object
*obj
);
1549 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1550 struct gl_transform_feedback_object
*obj
);
1552 hsw_end_transform_feedback(struct gl_context
*ctx
,
1553 struct gl_transform_feedback_object
*obj
);
1555 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1556 struct gl_transform_feedback_object
*obj
);
1558 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1559 struct gl_transform_feedback_object
*obj
);
1561 /* brw_blorp_blit.cpp */
1563 brw_blorp_framebuffer(struct brw_context
*brw
,
1564 struct gl_framebuffer
*readFb
,
1565 struct gl_framebuffer
*drawFb
,
1566 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1567 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1568 GLbitfield mask
, GLenum filter
);
1571 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1572 struct gl_renderbuffer
*src_rb
,
1573 struct gl_texture_image
*dst_image
,
1575 int srcX0
, int srcY0
,
1576 int dstX0
, int dstY0
,
1577 int width
, int height
);
1580 gen6_get_sample_position(struct gl_context
*ctx
,
1581 struct gl_framebuffer
*fb
,
1585 gen6_set_sample_maps(struct gl_context
*ctx
);
1587 /* gen8_multisample_state.c */
1588 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1592 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1593 unsigned hs_size
, unsigned ds_size
,
1594 unsigned gs_size
, unsigned fs_size
);
1597 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1598 bool gs_present
, unsigned gs_size
);
1600 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1601 bool gs_present
, bool tess_present
);
1605 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1607 brw_check_for_reset(struct brw_context
*brw
);
1611 brw_init_compute_functions(struct dd_function_table
*functions
);
1613 /* brw_program_binary.c */
1615 brw_program_binary_init(unsigned device_id
);
1617 brw_get_program_binary_driver_sha1(struct gl_context
*ctx
, uint8_t *sha1
);
1619 brw_deserialize_program_binary(struct gl_context
*ctx
,
1620 struct gl_shader_program
*shProg
,
1621 struct gl_program
*prog
);
1623 brw_program_serialize_nir(struct gl_context
*ctx
, struct gl_program
*prog
);
1625 brw_program_deserialize_nir(struct gl_context
*ctx
, struct gl_program
*prog
,
1626 gl_shader_stage stage
);
1628 /*======================================================================
1629 * Inline conversion functions. These are better-typed than the
1630 * macros used previously:
1632 static inline struct brw_context
*
1633 brw_context( struct gl_context
*ctx
)
1635 return (struct brw_context
*)ctx
;
1638 static inline struct brw_program
*
1639 brw_program(struct gl_program
*p
)
1641 return (struct brw_program
*) p
;
1644 static inline const struct brw_program
*
1645 brw_program_const(const struct gl_program
*p
)
1647 return (const struct brw_program
*) p
;
1651 brw_depth_writes_enabled(const struct brw_context
*brw
)
1653 const struct gl_context
*ctx
= &brw
->ctx
;
1655 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1656 * because it would just overwrite the existing depth value with itself.
1658 * These bonus depth writes not only use bandwidth, but they also can
1659 * prevent early depth processing. For example, if the pixel shader
1660 * discards, the hardware must invoke the to determine whether or not
1661 * to do the depth write. If writes are disabled, we may still be able
1662 * to do the depth test before the shader, and skip the shader execution.
1664 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1665 * a programming note saying to disable depth writes for EQUAL.
1667 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1671 brw_emit_depthbuffer(struct brw_context
*brw
);
1674 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1675 struct intel_mipmap_tree
*depth_mt
,
1676 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1677 uint32_t depth_surface_type
,
1678 struct intel_mipmap_tree
*stencil_mt
,
1679 bool hiz
, bool separate_stencil
,
1680 uint32_t width
, uint32_t height
,
1681 uint32_t tile_x
, uint32_t tile_y
);
1684 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1685 struct intel_mipmap_tree
*depth_mt
,
1686 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1687 uint32_t depth_surface_type
,
1688 struct intel_mipmap_tree
*stencil_mt
,
1689 bool hiz
, bool separate_stencil
,
1690 uint32_t width
, uint32_t height
,
1691 uint32_t tile_x
, uint32_t tile_y
);
1694 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1695 struct intel_mipmap_tree
*depth_mt
,
1696 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1697 uint32_t depth_surface_type
,
1698 struct intel_mipmap_tree
*stencil_mt
,
1699 bool hiz
, bool separate_stencil
,
1700 uint32_t width
, uint32_t height
,
1701 uint32_t tile_x
, uint32_t tile_y
);
1703 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1704 struct intel_mipmap_tree
*depth_mt
,
1705 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1706 uint32_t depth_surface_type
,
1707 struct intel_mipmap_tree
*stencil_mt
,
1708 bool hiz
, bool separate_stencil
,
1709 uint32_t width
, uint32_t height
,
1710 uint32_t tile_x
, uint32_t tile_y
);
1712 uint32_t get_hw_prim_for_gl_prim(int mode
);
1715 gen6_upload_push_constants(struct brw_context
*brw
,
1716 const struct gl_program
*prog
,
1717 const struct brw_stage_prog_data
*prog_data
,
1718 struct brw_stage_state
*stage_state
);
1721 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1722 const struct intel_mipmap_tree
*mt
);
1724 /* brw_queryformat.c */
1725 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1726 GLenum internalFormat
, GLenum pname
,