2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
36 #include "intel_context.h"
37 #include "brw_structs.h"
38 #include "main/imports.h"
39 #include "main/macros.h"
47 * URB - uniform resource buffer. A mid-sized buffer which is
48 * partitioned between the fixed function units and used for passing
49 * values (vertices, primitives, constants) between them.
51 * CURBE - constant URB entry. An urb region (entry) used to hold
52 * constant values which the fixed function units can be instructed to
53 * preload into the GRF when spawning a thread.
55 * VUE - vertex URB entry. An urb entry holding a vertex and usually
56 * a vertex header. The header contains control information and
57 * things like primitive type, Begin/end flags and clip codes.
59 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
60 * unit holding rasterization and interpolation parameters.
62 * GRF - general register file. One of several register files
63 * addressable by programmed threads. The inputs (r0, payload, curbe,
64 * urb) of the thread are preloaded to this area before the thread is
65 * spawned. The registers are individually 8 dwords wide and suitable
66 * for general usage. Registers holding thread input values are not
67 * special and may be overwritten.
69 * MRF - message register file. Threads communicate (and terminate)
70 * by sending messages. Message parameters are placed in contiguous
71 * MRF registers. All program output is via these messages. URB
72 * entries are populated by sending a message to the shared URB
73 * function containing the new data, together with a control word,
74 * often an unmodified copy of R0.
76 * R0 - GRF register 0. Typically holds control information used when
77 * sending messages to other threads.
79 * EU or GEN4 EU: The name of the programmable subsystem of the
80 * i965 hardware. Threads are executed by the EU, the registers
81 * described above are part of the EU architecture.
83 * Fixed function units:
85 * CS - Command streamer. Notional first unit, little software
86 * interaction. Holds the URB entries used for constant data, ie the
89 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
90 * this unit is responsible for pulling vertices out of vertex buffers
91 * in vram and injecting them into the processing pipe as VUEs. If
92 * enabled, it first passes them to a VS thread which is a good place
93 * for the driver to implement any active vertex shader.
95 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
96 * enabled, incoming strips etc are passed to GS threads in individual
97 * line/triangle/point units. The GS thread may perform arbitary
98 * computation and emit whatever primtives with whatever vertices it
99 * chooses. This makes GS an excellent place to implement GL's
100 * unfilled polygon modes, though of course it is capable of much
101 * more. Additionally, GS is used to translate away primitives not
102 * handled by latter units, including Quads and Lineloops.
104 * CS - Clipper. Mesa's clipping algorithms are imported to run on
105 * this unit. The fixed function part performs cliptesting against
106 * the 6 fixed clipplanes and makes descisions on whether or not the
107 * incoming primitive needs to be passed to a thread for clipping.
108 * User clip planes are handled via cooperation with the VS thread.
110 * SF - Strips Fans or Setup: Triangles are prepared for
111 * rasterization. Interpolation coefficients are calculated.
112 * Flatshading and two-side lighting usually performed here.
114 * WM - Windower. Interpolation of vertex attributes performed here.
115 * Fragment shader implemented here. SIMD aspects of EU taken full
116 * advantage of, as pixels are processed in blocks of 16.
118 * CC - Color Calculator. No EU threads associated with this unit.
119 * Handles blending and (presumably) depth and stencil testing.
123 #define BRW_MAX_CURBE (32*16)
126 struct brw_instruction
;
127 struct brw_vs_prog_key
;
128 struct brw_wm_prog_key
;
129 struct brw_wm_prog_data
;
133 BRW_STATE_FRAGMENT_PROGRAM
,
134 BRW_STATE_VERTEX_PROGRAM
,
135 BRW_STATE_CURBE_OFFSETS
,
136 BRW_STATE_REDUCED_PRIMITIVE
,
141 BRW_STATE_VS_BINDING_TABLE
,
142 BRW_STATE_GS_BINDING_TABLE
,
143 BRW_STATE_PS_BINDING_TABLE
,
147 BRW_STATE_INDEX_BUFFER
,
148 BRW_STATE_VS_CONSTBUF
,
149 BRW_STATE_PROGRAM_CACHE
,
150 BRW_STATE_STATE_BASE_ADDRESS
,
151 BRW_STATE_VUE_MAP_GEOM_OUT
,
152 BRW_STATE_TRANSFORM_FEEDBACK
,
153 BRW_STATE_RASTERIZER_DISCARD
,
155 BRW_STATE_UNIFORM_BUFFER
,
156 BRW_STATE_META_IN_PROGRESS
,
159 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE)
160 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM)
161 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM)
162 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS)
163 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE)
164 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE)
165 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT)
166 #define BRW_NEW_PSP (1 << BRW_STATE_PSP)
167 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES)
168 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE)
169 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE)
170 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE)
171 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES)
172 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES)
174 * Used for any batch entry with a relocated pointer that will be used
175 * by any 3D rendering.
177 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH)
178 /** \see brw.state.depth_region */
179 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER)
180 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF)
181 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE)
182 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS)
183 #define BRW_NEW_VUE_MAP_GEOM_OUT (1 << BRW_STATE_VUE_MAP_GEOM_OUT)
184 #define BRW_NEW_TRANSFORM_FEEDBACK (1 << BRW_STATE_TRANSFORM_FEEDBACK)
185 #define BRW_NEW_RASTERIZER_DISCARD (1 << BRW_STATE_RASTERIZER_DISCARD)
186 #define BRW_NEW_STATS_WM (1 << BRW_STATE_STATS_WM)
187 #define BRW_NEW_UNIFORM_BUFFER (1 << BRW_STATE_UNIFORM_BUFFER)
188 #define BRW_NEW_META_IN_PROGRESS (1 << BRW_STATE_META_IN_PROGRESS)
190 struct brw_state_flags
{
191 /** State update flags signalled by mesa internals */
194 * State update flags signalled as the result of brw_tracked_state updates
197 /** State update flags signalled by brw_state_cache.c searches */
201 #define AUB_TRACE_TYPE_MASK 0x0000ff00
202 #define AUB_TRACE_TYPE_NOTYPE (0 << 8)
203 #define AUB_TRACE_TYPE_BATCH (1 << 8)
204 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8)
205 #define AUB_TRACE_TYPE_2D_MAP (6 << 8)
206 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8)
207 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8)
208 #define AUB_TRACE_TYPE_1D_MAP (10 << 8)
209 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8)
210 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8)
211 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8)
212 #define AUB_TRACE_TYPE_GENERAL (14 << 8)
213 #define AUB_TRACE_TYPE_SURFACE (15 << 8)
216 * state_struct_type enum values are encoded with the top 16 bits representing
217 * the type to be delivered to the .aub file, and the bottom 16 bits
218 * representing the subtype. This macro performs the encoding.
220 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype))
222 enum state_struct_type
{
223 AUB_TRACE_VS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 1),
224 AUB_TRACE_GS_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 2),
225 AUB_TRACE_CLIP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 3),
226 AUB_TRACE_SF_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 4),
227 AUB_TRACE_WM_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 5),
228 AUB_TRACE_CC_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 6),
229 AUB_TRACE_CLIP_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 7),
230 AUB_TRACE_SF_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 8),
231 AUB_TRACE_CC_VP_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x9),
232 AUB_TRACE_SAMPLER_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xa),
233 AUB_TRACE_KERNEL_INSTRUCTIONS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xb),
234 AUB_TRACE_SCRATCH_SPACE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xc),
235 AUB_TRACE_SAMPLER_DEFAULT_COLOR
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0xd),
237 AUB_TRACE_SCISSOR_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x15),
238 AUB_TRACE_BLEND_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x16),
239 AUB_TRACE_DEPTH_STENCIL_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL
, 0x17),
241 AUB_TRACE_VERTEX_BUFFER
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER
, 0),
242 AUB_TRACE_BINDING_TABLE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x100),
243 AUB_TRACE_SURFACE_STATE
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE
, 0x200),
244 AUB_TRACE_VS_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 0),
245 AUB_TRACE_WM_CONSTANTS
= ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER
, 1),
249 * Decode a state_struct_type value to determine the type that should be
250 * stored in the .aub file.
252 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type
)
254 return (ss_type
& 0xFFFF0000) >> 16;
258 * Decode a state_struct_type value to determine the subtype that should be
259 * stored in the .aub file.
261 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type
)
263 return ss_type
& 0xFFFF;
266 /** Subclass of Mesa vertex program */
267 struct brw_vertex_program
{
268 struct gl_vertex_program program
;
273 /** Subclass of Mesa fragment program */
274 struct brw_fragment_program
{
275 struct gl_fragment_program program
;
276 GLuint id
; /**< serial no. to identify frag progs, never re-used */
280 struct gl_shader base
;
284 /** Shader IR transformed for native compile, at link time. */
285 struct exec_list
*ir
;
288 /* Data about a particular attempt to compile a program. Note that
289 * there can be many of these, each in a different GL state
290 * corresponding to a different brw_wm_prog_key struct, with different
293 * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
296 struct brw_wm_prog_data
{
297 GLuint curb_read_length
;
298 GLuint urb_read_length
;
300 GLuint first_curbe_grf
;
301 GLuint first_curbe_grf_16
;
303 GLuint reg_blocks_16
;
304 GLuint total_scratch
;
306 GLuint nr_params
; /**< number of float params/constants */
307 GLuint nr_pull_params
;
310 uint32_t prog_offset_16
;
313 * Mask of which interpolation modes are required by the fragment shader.
314 * Used in hardware setup on gen6+.
316 uint32_t barycentric_interp_modes
;
318 /* Pointers to tracked values (only valid once
319 * _mesa_load_state_parameters has been called at runtime).
321 * These must be the last fields of the struct (see
322 * brw_wm_prog_data_compare()).
325 const float **pull_param
;
329 * Enum representing the i965-specific vertex results that don't correspond
330 * exactly to any element of gl_varying_slot. The values of this enum are
331 * assigned such that they don't conflict with gl_varying_slot.
335 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
336 BRW_VARYING_SLOT_PAD
,
338 * Technically this is not a varying but just a placeholder that
339 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
340 * builtin variable to be compiled correctly. see compile_sf_prog() for
343 BRW_VARYING_SLOT_PNTC
,
344 BRW_VARYING_SLOT_COUNT
349 * Data structure recording the relationship between the gl_varying_slot enum
350 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
351 * single octaword within the VUE (128 bits).
353 * Note that each BRW register contains 256 bits (2 octawords), so when
354 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
355 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
356 * in a vertex shader), each register corresponds to a single VUE slot, since
357 * it contains data for two separate vertices.
361 * Bitfield representing all varying slots that are (a) stored in this VUE
362 * map, and (b) actually written by the shader. Does not include any of
363 * the additional varying slots defined in brw_varying_slot.
365 GLbitfield64 slots_valid
;
368 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
369 * not stored in a slot (because they are not written, or because
370 * additional processing is applied before storing them in the VUE), the
373 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
376 * Map from VUE slot to gl_varying_slot value. For slots that do not
377 * directly correspond to a gl_varying_slot, the value comes from
380 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
381 * simplifies code that uses the value stored in slot_to_varying to
382 * create a bit mask).
384 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
387 * Total number of VUE slots in use
393 * Convert a VUE slot number into a byte offset within the VUE.
395 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
401 * Convert a vertex output (brw_varying_slot) into a byte offset within the
404 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
407 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
410 void brw_compute_vue_map(struct brw_context
*brw
, struct brw_vue_map
*vue_map
,
411 GLbitfield64 slots_valid
, bool userclip_active
);
414 struct brw_sf_prog_data
{
415 GLuint urb_read_length
;
418 /* Each vertex may have upto 12 attributes, 4 components each,
419 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
422 * Actually we use 4 for each, so call it 12 rows.
424 GLuint urb_entry_size
;
427 struct brw_clip_prog_data
{
428 GLuint curb_read_length
; /* user planes? */
430 GLuint urb_read_length
;
434 struct brw_gs_prog_data
{
435 GLuint urb_read_length
;
439 * Gen6 transform feedback: Amount by which the streaming vertex buffer
440 * indices should be incremented each time the GS is invoked.
442 unsigned svbi_postincrement_value
;
446 /* Note: brw_vec4_prog_data_compare() must be updated when adding fields to
449 struct brw_vec4_prog_data
{
450 struct brw_vue_map vue_map
;
452 GLuint curb_read_length
;
453 GLuint urb_read_length
;
455 GLuint nr_params
; /**< number of float params/constants */
456 GLuint nr_pull_params
; /**< number of dwords referenced by pull_param[] */
457 GLuint total_scratch
;
459 /* Used for calculating urb partitions. In the VS, this is the size of the
460 * URB entry used for both input and output to the thread. In the GS, this
461 * is the size of the URB entry used for output.
463 GLuint urb_entry_size
;
467 /* These pointers must appear last. See brw_vec4_prog_data_compare(). */
469 const float **pull_param
;
473 /* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
476 struct brw_vs_prog_data
{
477 struct brw_vec4_prog_data base
;
479 GLbitfield64 inputs_read
;
484 /** Number of texture sampler units */
485 #define BRW_MAX_TEX_UNIT 16
487 /** Max number of render targets in a shader */
488 #define BRW_MAX_DRAW_BUFFERS 8
491 * Max number of binding table entries used for stream output.
493 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
494 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
496 * On Gen6, the size of transform feedback data is limited not by the number
497 * of components but by the number of binding table entries we set aside. We
498 * use one binding table entry for a float, one entry for a vector, and one
499 * entry per matrix column. Since the only way we can communicate our
500 * transform feedback capabilities to the client is via
501 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
502 * worst case, in which all the varyings are floats, so we use up one binding
503 * table entry per component. Therefore we need to set aside at least 64
504 * binding table entries for use by transform feedback.
506 * Note: since we don't currently pack varyings, it is currently impossible
507 * for the client to actually use up all of these binding table entries--if
508 * all of their varyings were floats, they would run out of varying slots and
509 * fail to link. But that's a bug, so it seems prudent to go ahead and
510 * allocate the number of binding table entries we will need once the bug is
513 #define BRW_MAX_SOL_BINDINGS 64
515 /** Maximum number of actual buffers used for stream output */
516 #define BRW_MAX_SOL_BUFFERS 4
518 #define BRW_MAX_WM_UBOS 12
519 #define BRW_MAX_VS_UBOS 12
522 * Helpers to create Surface Binding Table indexes for draw buffers,
523 * textures, and constant buffers.
525 * Shader threads access surfaces via numeric handles, rather than directly
526 * using pointers. The binding table maps these numeric handles to the
527 * address of the actual buffer.
529 * For example, a shader might ask to sample from "surface 7." In this case,
530 * bind[7] would contain a pointer to a texture.
532 * Currently, our WM binding tables are (arbitrarily) programmed as follows:
534 * +-------------------------------+
535 * | 0 | Draw buffer 0 |
538 * | 7 | Draw buffer 7 |
539 * |-----|-------------------------|
540 * | 8 | WM Pull Constant Buffer |
541 * |-----|-------------------------|
545 * | 24 | Texture 15 |
546 * |-----|-------------------------|
551 * +-------------------------------+
553 * Our VS binding tables are programmed as follows:
555 * +-----+-------------------------+
556 * | 0 | VS Pull Constant Buffer |
557 * +-----+-------------------------+
561 * | 16 | Texture 15 |
562 * +-----+-------------------------+
567 * +-------------------------------+
569 * Our (gen6) GS binding tables are programmed as follows:
571 * +-----+-------------------------+
572 * | 0 | SOL Binding 0 |
575 * | 63 | SOL Binding 63 |
576 * +-----+-------------------------+
578 * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be
579 * the identity function or things will break. We do want to keep draw buffers
580 * first so we can use headerless render target writes for RT 0.
582 #define SURF_INDEX_DRAW(d) (d)
583 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1)
584 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t))
585 #define SURF_INDEX_WM_UBO(u) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u)
586 #define SURF_INDEX_WM_SHADER_TIME (SURF_INDEX_WM_UBO(12))
587 /** Maximum size of the binding table. */
588 #define BRW_MAX_WM_SURFACES (SURF_INDEX_WM_SHADER_TIME + 1)
590 #define SURF_INDEX_VERT_CONST_BUFFER (0)
591 #define SURF_INDEX_VS_TEXTURE(t) (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t))
592 #define SURF_INDEX_VS_UBO(u) (SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT) + u)
593 #define SURF_INDEX_VS_SHADER_TIME (SURF_INDEX_VS_UBO(12))
594 #define BRW_MAX_VS_SURFACES (SURF_INDEX_VS_SHADER_TIME + 1)
596 #define SURF_INDEX_SOL_BINDING(t) ((t))
597 #define BRW_MAX_GS_SURFACES SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
600 * Stride in bytes between shader_time entries.
602 * We separate entries by a cacheline to reduce traffic between EUs writing to
605 #define SHADER_TIME_STRIDE 64
612 BRW_BLORP_CONST_COLOR_PROG
,
617 BRW_SF_UNIT
, /* scissor state on gen6 */
629 struct brw_cache_item
{
631 * Effectively part of the key, cache_id identifies what kind of state
632 * buffer is involved, and also which brw->state.dirty.cache flag should
633 * be set when this cache item is chosen.
635 enum brw_cache_id cache_id
;
636 /** 32-bit hash of the key data */
638 GLuint key_size
; /* for variable-sized keys */
645 struct brw_cache_item
*next
;
649 typedef bool (*cache_aux_compare_func
)(const void *a
, const void *b
,
650 int aux_size
, const void *key
);
651 typedef void (*cache_aux_free_func
)(const void *aux
);
654 struct brw_context
*brw
;
656 struct brw_cache_item
**items
;
658 GLuint size
, n_items
;
660 uint32_t next_offset
;
664 * Optional functions used in determining whether the prog_data for a new
665 * cache item matches an existing cache item (in case there's relevant data
666 * outside of the prog_data). If NULL, a plain memcmp is done.
668 cache_aux_compare_func aux_compare
[BRW_MAX_CACHE
];
669 /** Optional functions for freeing other pointers attached to a prog_data. */
670 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
674 /* Considered adding a member to this struct to document which flags
675 * an update might raise so that ordering of the state atoms can be
676 * checked or derived at runtime. Dropped the idea in favor of having
677 * a debug mode where the state is monitored for flags which are
678 * raised that have already been tested against.
680 struct brw_tracked_state
{
681 struct brw_state_flags dirty
;
682 void (*emit
)( struct brw_context
*brw
);
685 enum shader_time_shader_type
{
698 /* Flags for brw->state.cache.
700 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP)
701 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT)
702 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG)
703 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER)
704 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT)
705 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG)
706 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP)
707 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT)
708 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT)
709 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG)
710 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT)
711 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG)
712 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP)
713 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT)
714 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG)
716 struct brw_cached_batch_item
{
717 struct header
*header
;
719 struct brw_cached_batch_item
*next
;
724 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life
725 * be easier if C allowed arrays of packed elements?
727 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32)
729 struct brw_vertex_buffer
{
730 /** Buffer object containing the uploaded vertex data */
733 /** Byte stride between elements in the uploaded array */
737 struct brw_vertex_element
{
738 const struct gl_client_array
*glarray
;
742 /** The corresponding Mesa vertex attribute */
743 gl_vert_attrib attrib
;
744 /** Offset of the first element within the buffer object */
748 struct brw_query_object
{
749 struct gl_query_object Base
;
751 /** Last query BO associated with this query. */
754 /** Last index in bo with query data for this object. */
760 * brw_context is derived from intel_context.
764 struct intel_context intel
; /**< base class, must be first field */
768 void (*destroy
) (struct brw_context
* brw
);
769 void (*finish_batch
) (struct brw_context
* brw
);
770 void (*new_batch
) (struct brw_context
* brw
);
772 void (*update_texture_surface
)(struct gl_context
*ctx
,
774 uint32_t *binding_table
,
775 unsigned surf_index
);
776 void (*update_renderbuffer_surface
)(struct brw_context
*brw
,
777 struct gl_renderbuffer
*rb
,
780 void (*update_null_renderbuffer_surface
)(struct brw_context
*brw
,
782 void (*create_constant_surface
)(struct brw_context
*brw
,
786 uint32_t *out_offset
,
790 * Send the appropriate state packets to configure depth, stencil, and
791 * HiZ buffers (i965+ only)
793 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
794 struct intel_mipmap_tree
*depth_mt
,
795 uint32_t depth_offset
,
796 uint32_t depthbuffer_format
,
797 uint32_t depth_surface_type
,
798 struct intel_mipmap_tree
*stencil_mt
,
799 bool hiz
, bool separate_stencil
,
800 uint32_t width
, uint32_t height
,
801 uint32_t tile_x
, uint32_t tile_y
);
806 * Set if rendering has occured to the drawable's front buffer.
808 * This is used in the DRI2 case to detect that glFlush should also copy
809 * the contents of the fake front buffer to the real front buffer.
811 bool front_buffer_dirty
;
814 * Track whether front-buffer rendering is currently enabled
816 * A separate flag is used to track this in order to support MRT more
819 bool is_front_buffer_rendering
;
822 * Track whether front-buffer is the current read target.
824 * This is closely associated with is_front_buffer_rendering, but may
825 * be set separately. The DRI2 fake front buffer must be referenced
828 bool is_front_buffer_reading
;
835 bool always_flush_batch
;
836 bool always_flush_cache
;
837 bool disable_throttling
;
840 driOptionCache optionCache
;
843 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
845 GLenum reduced_primitive
;
847 bool emit_state_always
;
848 bool has_surface_tile_offset
;
850 bool has_negative_rhw_bug
;
851 bool has_aa_line_parameters
;
855 * Some versions of Gen hardware don't do centroid interpolation correctly
856 * on unlit pixels, causing incorrect values for derivatives near triangle
857 * edges. Enabling this flag causes the fragment shader to use
858 * non-centroid interpolation for unlit pixels, at the expense of two extra
859 * fragment shader instructions.
861 bool needs_unlit_centroid_workaround
;
864 struct brw_state_flags dirty
;
867 struct brw_cache cache
;
868 struct brw_cached_batch_item
*cached_batch_items
;
870 /* Whether a meta-operation is in progress. */
871 bool meta_in_progress
;
874 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
875 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
877 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
881 /* Summary of size and varying of active arrays, so we can check
882 * for changes to this state:
884 unsigned int min_index
, max_index
;
886 /* Offset from start of vertex buffer so we can avoid redefining
887 * the same VB packed over and over again.
889 unsigned int start_vertex_bias
;
894 * Index buffer for this draw_prims call.
896 * Updates are signaled by BRW_NEW_INDICES.
898 const struct _mesa_index_buffer
*ib
;
900 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
904 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
905 * avoid re-uploading the IB packet over and over if we're actually
906 * referencing the same index buffer.
908 unsigned int start_vertex_offset
;
911 /* Active vertex program:
913 const struct gl_vertex_program
*vertex_program
;
914 const struct gl_fragment_program
*fragment_program
;
916 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */
917 uint32_t CMD_VF_STATISTICS
;
918 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */
919 uint32_t CMD_PIPELINE_SELECT
;
922 * Platform specific constants containing the maximum number of threads
923 * for each pipeline stage.
929 /* BRW_NEW_URB_ALLOCATIONS:
932 GLuint vsize
; /* vertex size plus header in urb registers */
933 GLuint csize
; /* constant buffer size in urb registers */
934 GLuint sfsize
; /* setup data size in urb registers */
938 GLuint max_vs_entries
; /* Maximum number of VS entries */
939 GLuint max_gs_entries
; /* Maximum number of GS entries */
941 GLuint nr_vs_entries
;
942 GLuint nr_gs_entries
;
943 GLuint nr_clip_entries
;
944 GLuint nr_sf_entries
;
945 GLuint nr_cs_entries
;
952 GLuint size
; /* Hardware URB size, in KB. */
954 /* gen6: True if the most recently sent _3DSTATE_URB message allocated
955 * URB space for the GS.
957 bool gen6_gs_previously_active
;
961 /* BRW_NEW_CURBE_OFFSETS:
964 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
965 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
972 drm_intel_bo
*curbe_bo
;
973 /** Offset within curbe_bo of space for current curbe entry */
975 /** Offset within curbe_bo of space for next curbe entry */
976 GLuint curbe_next_offset
;
979 * Copy of the last set of CURBEs uploaded. Frequently we'll end up
980 * in brw_curbe.c with the same set of constant data to be uploaded,
981 * so we'd rather not upload new constants in that case (it can cause
982 * a pipeline bubble since only up to 4 can be pipelined at a time).
986 * Allocation for where to calculate the next set of CURBEs.
987 * It's a hot enough path that malloc/free of that data matters.
993 /** SAMPLER_STATE count and offset */
1000 * Layout of vertex data exiting the geometry portion of the pipleine.
1001 * This comes from the geometry shader if one exists, otherwise from the
1004 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1006 struct brw_vue_map vue_map_geom_out
;
1009 struct brw_vs_prog_data
*prog_data
;
1011 drm_intel_bo
*scratch_bo
;
1012 drm_intel_bo
*const_bo
;
1013 /** Offset in the program cache to the VS program */
1014 uint32_t prog_offset
;
1015 uint32_t state_offset
;
1017 uint32_t push_const_offset
; /* Offset in the batchbuffer */
1018 int push_const_size
; /* in 256-bit register increments */
1020 /** @{ register allocator */
1022 struct ra_regs
*regs
;
1025 * Array of the ra classes for the unaligned contiguous register
1031 * Mapping for register-allocated objects in *regs to the first
1032 * GRF for that object.
1034 uint8_t *ra_reg_to_grf
;
1037 uint32_t bind_bo_offset
;
1038 uint32_t surf_offset
[BRW_MAX_VS_SURFACES
];
1042 struct brw_gs_prog_data
*prog_data
;
1045 /** Offset in the program cache to the CLIP program pre-gen6 */
1046 uint32_t prog_offset
;
1047 uint32_t state_offset
;
1049 uint32_t bind_bo_offset
;
1050 uint32_t surf_offset
[BRW_MAX_GS_SURFACES
];
1054 struct brw_clip_prog_data
*prog_data
;
1056 /** Offset in the program cache to the CLIP program pre-gen6 */
1057 uint32_t prog_offset
;
1059 /* Offset in the batch to the CLIP state on pre-gen6. */
1060 uint32_t state_offset
;
1062 /* As of gen6, this is the offset in the batch to the CLIP VP,
1070 struct brw_sf_prog_data
*prog_data
;
1072 /** Offset in the program cache to the CLIP program pre-gen6 */
1073 uint32_t prog_offset
;
1074 uint32_t state_offset
;
1079 struct brw_wm_prog_data
*prog_data
;
1081 /** offsets in the batch to sampler default colors (texture border color)
1083 uint32_t sdc_offset
[BRW_MAX_TEX_UNIT
];
1087 drm_intel_bo
*scratch_bo
;
1090 * Buffer object used in place of multisampled null render targets on
1091 * Gen6. See brw_update_null_renderbuffer_surface().
1093 drm_intel_bo
*multisampled_null_render_target_bo
;
1095 /** Offset in the program cache to the WM program */
1096 uint32_t prog_offset
;
1098 uint32_t state_offset
; /* offset in batchbuffer to pre-gen6 WM state */
1100 drm_intel_bo
*const_bo
; /* pull constant buffer. */
1102 * This is offset in the batch to the push constants on gen6.
1104 * Pre-gen6, push constants live in the CURBE.
1106 uint32_t push_const_offset
;
1108 /** Binding table of pointers to surf_bo entries */
1109 uint32_t bind_bo_offset
;
1110 uint32_t surf_offset
[BRW_MAX_WM_SURFACES
];
1113 struct ra_regs
*regs
;
1115 /** Array of the ra classes for the unaligned contiguous
1116 * register block sizes used.
1121 * Mapping for register-allocated objects in *regs to the first
1122 * GRF for that object.
1124 uint8_t *ra_reg_to_grf
;
1127 * ra class for the aligned pairs we use for PLN, which doesn't
1128 * appear in *classes.
1130 int aligned_pairs_class
;
1136 uint32_t state_offset
;
1137 uint32_t blend_state_offset
;
1138 uint32_t depth_stencil_state_offset
;
1143 struct brw_query_object
*obj
;
1148 const struct brw_tracked_state
**atoms
;
1150 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1154 enum state_struct_type type
;
1155 } *state_batch_list
;
1156 int state_batch_count
;
1158 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1159 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1161 /* PrimitiveRestart */
1164 bool enable_cut_index
;
1167 /** Computed depth/stencil/hiz state from the current attached
1168 * renderbuffers, valid only during the drawing state upload loop after
1169 * brw_workaround_depthstencil_alignment().
1172 struct intel_mipmap_tree
*depth_mt
;
1173 struct intel_mipmap_tree
*stencil_mt
;
1175 /* Inter-tile (page-aligned) byte offsets. */
1176 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1177 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1178 uint32_t tile_x
, tile_y
;
1181 uint32_t num_instances
;
1186 struct gl_shader_program
**shader_programs
;
1187 struct gl_program
**programs
;
1188 enum shader_time_shader_type
*types
;
1189 uint64_t *cumulative
;
1196 /*======================================================================
1199 void brwInitVtbl( struct brw_context
*brw
);
1201 /*======================================================================
1204 bool brwCreateContext(int api
,
1205 const struct gl_config
*mesaVis
,
1206 __DRIcontext
*driContextPriv
,
1207 unsigned major_version
,
1208 unsigned minor_version
,
1211 void *sharedContextPrivate
);
1213 /*======================================================================
1216 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1217 uint32_t depth_level
,
1218 uint32_t depth_layer
,
1219 struct intel_mipmap_tree
*stencil_mt
,
1220 uint32_t *out_tile_mask_x
,
1221 uint32_t *out_tile_mask_y
);
1222 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1223 GLbitfield clear_mask
);
1225 /*======================================================================
1228 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1229 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1230 void brw_emit_query_begin(struct brw_context
*brw
);
1231 void brw_emit_query_end(struct brw_context
*brw
);
1233 /** gen6_queryobj.c */
1234 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1236 /*======================================================================
1239 void brw_debug_batch(struct brw_context
*brw
);
1240 void brw_annotate_aub(struct brw_context
*brw
);
1242 /*======================================================================
1245 void brw_validate_textures( struct brw_context
*brw
);
1248 /*======================================================================
1251 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1253 int brw_get_scratch_size(int size
);
1254 void brw_get_scratch_bo(struct brw_context
*brw
,
1255 drm_intel_bo
**scratch_bo
, int size
);
1256 void brw_init_shader_time(struct brw_context
*brw
);
1257 int brw_get_shader_time_index(struct brw_context
*brw
,
1258 struct gl_shader_program
*shader_prog
,
1259 struct gl_program
*prog
,
1260 enum shader_time_shader_type type
);
1261 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1262 void brw_destroy_shader_time(struct brw_context
*brw
);
1266 void brw_upload_urb_fence(struct brw_context
*brw
);
1270 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1272 /* brw_fs_reg_allocate.cpp
1274 void brw_fs_alloc_reg_sets(struct brw_context
*brw
);
1277 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
);
1280 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1282 /* brw_wm_surface_state.c */
1283 void brw_init_surface_formats(struct brw_context
*brw
);
1285 brw_update_sol_surface(struct brw_context
*brw
,
1286 struct gl_buffer_object
*buffer_obj
,
1287 uint32_t *out_offset
, unsigned num_vector_components
,
1288 unsigned stride_dwords
, unsigned offset_dwords
);
1289 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1290 struct gl_shader
*shader
,
1291 uint32_t *surf_offsets
);
1293 /* brw_surface_formats.c */
1294 bool brw_is_hiz_depth_format(struct brw_context
*ctx
, gl_format format
);
1295 bool brw_render_target_supported(struct brw_context
*brw
,
1296 struct gl_renderbuffer
*rb
);
1300 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1301 struct gl_transform_feedback_object
*obj
);
1303 brw_end_transform_feedback(struct gl_context
*ctx
,
1304 struct gl_transform_feedback_object
*obj
);
1306 /* gen7_sol_state.c */
1308 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1309 struct gl_transform_feedback_object
*obj
);
1311 gen7_end_transform_feedback(struct gl_context
*ctx
,
1312 struct gl_transform_feedback_object
*obj
);
1314 /* brw_blorp_blit.cpp */
1316 brw_blorp_framebuffer(struct brw_context
*brw
,
1317 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1318 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1319 GLbitfield mask
, GLenum filter
);
1322 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1323 struct gl_renderbuffer
*src_rb
,
1324 struct gl_texture_image
*dst_image
,
1326 int srcX0
, int srcY0
,
1327 int dstX0
, int dstY0
,
1328 int width
, int height
);
1330 /* gen6_multisample_state.c */
1332 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1333 unsigned num_samples
);
1335 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
,
1336 unsigned num_samples
, float coverage
,
1337 bool coverage_invert
, unsigned sample_mask
);
1339 gen6_get_sample_position(struct gl_context
*ctx
,
1340 struct gl_framebuffer
*fb
,
1346 gen7_allocate_push_constants(struct brw_context
*brw
);
1349 gen7_emit_urb_state(struct brw_context
*brw
, GLuint nr_vs_entries
,
1350 GLuint vs_size
, GLuint vs_start
);
1354 /*======================================================================
1355 * Inline conversion functions. These are better-typed than the
1356 * macros used previously:
1358 static INLINE
struct brw_context
*
1359 brw_context( struct gl_context
*ctx
)
1361 return (struct brw_context
*)ctx
;
1364 static INLINE
struct brw_vertex_program
*
1365 brw_vertex_program(struct gl_vertex_program
*p
)
1367 return (struct brw_vertex_program
*) p
;
1370 static INLINE
const struct brw_vertex_program
*
1371 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1373 return (const struct brw_vertex_program
*) p
;
1376 static INLINE
struct brw_fragment_program
*
1377 brw_fragment_program(struct gl_fragment_program
*p
)
1379 return (struct brw_fragment_program
*) p
;
1382 static INLINE
const struct brw_fragment_program
*
1383 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1385 return (const struct brw_fragment_program
*) p
;
1389 * Pre-gen6, the register file of the EUs was shared between threads,
1390 * and each thread used some subset allocated on a 16-register block
1391 * granularity. The unit states wanted these block counts.
1394 brw_register_blocks(int reg_count
)
1396 return ALIGN(reg_count
, 16) / 16 - 1;
1399 static inline uint32_t
1400 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1401 uint32_t prog_offset
)
1403 struct intel_context
*intel
= &brw
->intel
;
1405 if (intel
->gen
>= 5) {
1406 /* Using state base address. */
1410 drm_intel_bo_emit_reloc(intel
->batch
.bo
,
1414 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1416 return brw
->cache
.bo
->offset
+ prog_offset
;
1419 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1420 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1421 struct exec_list
*instructions
);
1423 struct opcode_desc
{
1429 extern const struct opcode_desc opcode_descs
[128];
1432 brw_emit_depthbuffer(struct brw_context
*brw
);
1435 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1436 struct intel_mipmap_tree
*depth_mt
,
1437 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1438 uint32_t depth_surface_type
,
1439 struct intel_mipmap_tree
*stencil_mt
,
1440 bool hiz
, bool separate_stencil
,
1441 uint32_t width
, uint32_t height
,
1442 uint32_t tile_x
, uint32_t tile_y
);
1445 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1446 struct intel_mipmap_tree
*depth_mt
,
1447 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1448 uint32_t depth_surface_type
,
1449 struct intel_mipmap_tree
*stencil_mt
,
1450 bool hiz
, bool separate_stencil
,
1451 uint32_t width
, uint32_t height
,
1452 uint32_t tile_x
, uint32_t tile_y
);