2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "brw_compiler.h"
41 #include "intel_aub.h"
47 /* Evil hack for using libdrm in a c++ compiler. */
51 #include <intel_bufmgr.h>
60 #include "intel_debug.h"
61 #include "intel_screen.h"
62 #include "intel_tex_obj.h"
63 #include "intel_resolve_map.h"
67 * URB - uniform resource buffer. A mid-sized buffer which is
68 * partitioned between the fixed function units and used for passing
69 * values (vertices, primitives, constants) between them.
71 * CURBE - constant URB entry. An urb region (entry) used to hold
72 * constant values which the fixed function units can be instructed to
73 * preload into the GRF when spawning a thread.
75 * VUE - vertex URB entry. An urb entry holding a vertex and usually
76 * a vertex header. The header contains control information and
77 * things like primitive type, Begin/end flags and clip codes.
79 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
80 * unit holding rasterization and interpolation parameters.
82 * GRF - general register file. One of several register files
83 * addressable by programmed threads. The inputs (r0, payload, curbe,
84 * urb) of the thread are preloaded to this area before the thread is
85 * spawned. The registers are individually 8 dwords wide and suitable
86 * for general usage. Registers holding thread input values are not
87 * special and may be overwritten.
89 * MRF - message register file. Threads communicate (and terminate)
90 * by sending messages. Message parameters are placed in contiguous
91 * MRF registers. All program output is via these messages. URB
92 * entries are populated by sending a message to the shared URB
93 * function containing the new data, together with a control word,
94 * often an unmodified copy of R0.
96 * R0 - GRF register 0. Typically holds control information used when
97 * sending messages to other threads.
99 * EU or GEN4 EU: The name of the programmable subsystem of the
100 * i965 hardware. Threads are executed by the EU, the registers
101 * described above are part of the EU architecture.
103 * Fixed function units:
105 * CS - Command streamer. Notional first unit, little software
106 * interaction. Holds the URB entries used for constant data, ie the
109 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
110 * this unit is responsible for pulling vertices out of vertex buffers
111 * in vram and injecting them into the processing pipe as VUEs. If
112 * enabled, it first passes them to a VS thread which is a good place
113 * for the driver to implement any active vertex shader.
115 * HS - Hull Shader (Tessellation Control Shader)
117 * TE - Tessellation Engine (Tessellation Primitive Generation)
119 * DS - Domain Shader (Tessellation Evaluation Shader)
121 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
122 * enabled, incoming strips etc are passed to GS threads in individual
123 * line/triangle/point units. The GS thread may perform arbitary
124 * computation and emit whatever primtives with whatever vertices it
125 * chooses. This makes GS an excellent place to implement GL's
126 * unfilled polygon modes, though of course it is capable of much
127 * more. Additionally, GS is used to translate away primitives not
128 * handled by latter units, including Quads and Lineloops.
130 * CS - Clipper. Mesa's clipping algorithms are imported to run on
131 * this unit. The fixed function part performs cliptesting against
132 * the 6 fixed clipplanes and makes descisions on whether or not the
133 * incoming primitive needs to be passed to a thread for clipping.
134 * User clip planes are handled via cooperation with the VS thread.
136 * SF - Strips Fans or Setup: Triangles are prepared for
137 * rasterization. Interpolation coefficients are calculated.
138 * Flatshading and two-side lighting usually performed here.
140 * WM - Windower. Interpolation of vertex attributes performed here.
141 * Fragment shader implemented here. SIMD aspects of EU taken full
142 * advantage of, as pixels are processed in blocks of 16.
144 * CC - Color Calculator. No EU threads associated with this unit.
145 * Handles blending and (presumably) depth and stencil testing.
150 struct brw_vs_prog_key
;
151 struct brw_vue_prog_key
;
152 struct brw_wm_prog_key
;
153 struct brw_wm_prog_data
;
154 struct brw_cs_prog_key
;
155 struct brw_cs_prog_data
;
159 BRW_COMPUTE_PIPELINE
,
166 BRW_CACHE_BLORP_PROG
,
169 BRW_CACHE_FF_GS_PROG
,
180 /* brw_cache_ids must come first - see brw_state_cache.c */
181 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
182 BRW_STATE_FRAGMENT_PROGRAM
,
183 BRW_STATE_GEOMETRY_PROGRAM
,
184 BRW_STATE_TESS_PROGRAMS
,
185 BRW_STATE_VERTEX_PROGRAM
,
186 BRW_STATE_CURBE_OFFSETS
,
187 BRW_STATE_REDUCED_PRIMITIVE
,
188 BRW_STATE_PATCH_PRIMITIVE
,
193 BRW_STATE_BINDING_TABLE_POINTERS
,
196 BRW_STATE_DEFAULT_TESS_LEVELS
,
198 BRW_STATE_INDEX_BUFFER
,
199 BRW_STATE_VS_CONSTBUF
,
200 BRW_STATE_TCS_CONSTBUF
,
201 BRW_STATE_TES_CONSTBUF
,
202 BRW_STATE_GS_CONSTBUF
,
203 BRW_STATE_PROGRAM_CACHE
,
204 BRW_STATE_STATE_BASE_ADDRESS
,
205 BRW_STATE_VUE_MAP_GEOM_OUT
,
206 BRW_STATE_TRANSFORM_FEEDBACK
,
207 BRW_STATE_RASTERIZER_DISCARD
,
209 BRW_STATE_UNIFORM_BUFFER
,
210 BRW_STATE_ATOMIC_BUFFER
,
211 BRW_STATE_IMAGE_UNITS
,
212 BRW_STATE_META_IN_PROGRESS
,
213 BRW_STATE_INTERPOLATION_MAP
,
214 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
215 BRW_STATE_NUM_SAMPLES
,
216 BRW_STATE_TEXTURE_BUFFER
,
217 BRW_STATE_GEN4_UNIT_STATE
,
221 BRW_STATE_SAMPLER_STATE_TABLE
,
222 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
223 BRW_STATE_COMPUTE_PROGRAM
,
224 BRW_STATE_CS_WORK_GROUPS
,
232 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
234 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
235 * When the currently bound shader program differs from the previous draw
236 * call, these will be flagged. They cover brw->{stage}_program and
237 * ctx->{Stage}Program->_Current.
239 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
240 * driver perspective. Even if the same shader is bound at the API level,
241 * we may need to switch between multiple versions of that shader to handle
242 * changes in non-orthagonal state.
244 * Additionally, multiple shader programs may have identical vertex shaders
245 * (for example), or compile down to the same code in the backend. We combine
246 * those into a single program cache entry.
248 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
249 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
251 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
252 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
253 * use the normal state upload paths), but the cache is still used. To avoid
254 * polluting the brw_state_cache code with special cases, we retain the dirty
255 * bit for now. It should eventually be removed.
257 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
258 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
259 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
260 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
261 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
262 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
263 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
264 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
265 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
266 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
267 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
268 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
269 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
270 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
271 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
272 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
273 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
274 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
275 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
276 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
277 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
278 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
279 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
280 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
281 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
283 * Used for any batch entry with a relocated pointer that will be used
284 * by any 3D rendering.
286 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
287 /** \see brw.state.depth_region */
288 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
289 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
290 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
291 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
292 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
293 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
294 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
295 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
296 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
297 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
298 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
299 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
300 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
301 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
302 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
303 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
304 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
305 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
306 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
307 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
308 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
309 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
310 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
311 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
312 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
313 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
314 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
315 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
316 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
317 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
319 struct brw_state_flags
{
320 /** State update flags signalled by mesa internals */
323 * State update flags signalled as the result of brw_tracked_state updates
328 /** Subclass of Mesa vertex program */
329 struct brw_vertex_program
{
330 struct gl_vertex_program program
;
335 /** Subclass of Mesa tessellation control program */
336 struct brw_tess_ctrl_program
{
337 struct gl_tess_ctrl_program program
;
338 unsigned id
; /**< serial no. to identify tess ctrl progs, never re-used */
342 /** Subclass of Mesa tessellation evaluation program */
343 struct brw_tess_eval_program
{
344 struct gl_tess_eval_program program
;
345 unsigned id
; /**< serial no. to identify tess eval progs, never re-used */
349 /** Subclass of Mesa geometry program */
350 struct brw_geometry_program
{
351 struct gl_geometry_program program
;
352 unsigned id
; /**< serial no. to identify geom progs, never re-used */
356 /** Subclass of Mesa fragment program */
357 struct brw_fragment_program
{
358 struct gl_fragment_program program
;
359 GLuint id
; /**< serial no. to identify frag progs, never re-used */
363 /** Subclass of Mesa compute program */
364 struct brw_compute_program
{
365 struct gl_compute_program program
;
366 unsigned id
; /**< serial no. to identify compute progs, never re-used */
371 struct gl_linked_shader base
;
377 * Bitmask indicating which fragment shader inputs represent varyings (and
378 * hence have to be delivered to the fragment shader by the SF/SBE stage).
380 #define BRW_FS_VARYING_INPUT_MASK \
381 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
382 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
386 * Mapping of VUE map slots to interpolation modes.
388 struct interpolation_mode_map
{
389 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
392 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
394 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
395 if (map
->mode
[i
] == INTERP_MODE_FLAT
)
401 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
403 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
404 if (map
->mode
[i
] == INTERP_MODE_NOPERSPECTIVE
)
411 struct brw_sf_prog_data
{
412 GLuint urb_read_length
;
415 /* Each vertex may have upto 12 attributes, 4 components each,
416 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
419 * Actually we use 4 for each, so call it 12 rows.
421 GLuint urb_entry_size
;
426 * We always program SF to start reading at an offset of 1 (2 varying slots)
427 * from the start of the vertex URB entry. This causes it to skip:
428 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
429 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
431 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
434 struct brw_clip_prog_data
{
435 GLuint curb_read_length
; /* user planes? */
437 GLuint urb_read_length
;
441 struct brw_ff_gs_prog_data
{
442 GLuint urb_read_length
;
446 * Gen6 transform feedback: Amount by which the streaming vertex buffer
447 * indices should be incremented each time the GS is invoked.
449 unsigned svbi_postincrement_value
;
452 /** Number of texture sampler units */
453 #define BRW_MAX_TEX_UNIT 32
455 /** Max number of render targets in a shader */
456 #define BRW_MAX_DRAW_BUFFERS 8
458 /** Max number of UBOs in a shader */
459 #define BRW_MAX_UBO 14
461 /** Max number of SSBOs in a shader */
462 #define BRW_MAX_SSBO 12
464 /** Max number of atomic counter buffer objects in a shader */
465 #define BRW_MAX_ABO 16
467 /** Max number of image uniforms in a shader */
468 #define BRW_MAX_IMAGES 32
471 * Max number of binding table entries used for stream output.
473 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
474 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
476 * On Gen6, the size of transform feedback data is limited not by the number
477 * of components but by the number of binding table entries we set aside. We
478 * use one binding table entry for a float, one entry for a vector, and one
479 * entry per matrix column. Since the only way we can communicate our
480 * transform feedback capabilities to the client is via
481 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
482 * worst case, in which all the varyings are floats, so we use up one binding
483 * table entry per component. Therefore we need to set aside at least 64
484 * binding table entries for use by transform feedback.
486 * Note: since we don't currently pack varyings, it is currently impossible
487 * for the client to actually use up all of these binding table entries--if
488 * all of their varyings were floats, they would run out of varying slots and
489 * fail to link. But that's a bug, so it seems prudent to go ahead and
490 * allocate the number of binding table entries we will need once the bug is
493 #define BRW_MAX_SOL_BINDINGS 64
495 /** Maximum number of actual buffers used for stream output */
496 #define BRW_MAX_SOL_BUFFERS 4
498 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
499 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
504 2 + /* shader time, pull constants */ \
505 1 /* cs num work groups */)
507 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
510 * Stride in bytes between shader_time entries.
512 * We separate entries by a cacheline to reduce traffic between EUs writing to
515 #define SHADER_TIME_STRIDE 64
517 struct brw_cache_item
{
519 * Effectively part of the key, cache_id identifies what kind of state
520 * buffer is involved, and also which dirty flag should set.
522 enum brw_cache_id cache_id
;
523 /** 32-bit hash of the key data */
525 GLuint key_size
; /* for variable-sized keys */
532 struct brw_cache_item
*next
;
537 struct brw_context
*brw
;
539 struct brw_cache_item
**items
;
541 GLuint size
, n_items
;
543 uint32_t next_offset
;
548 /* Considered adding a member to this struct to document which flags
549 * an update might raise so that ordering of the state atoms can be
550 * checked or derived at runtime. Dropped the idea in favor of having
551 * a debug mode where the state is monitored for flags which are
552 * raised that have already been tested against.
554 struct brw_tracked_state
{
555 struct brw_state_flags dirty
;
556 void (*emit
)( struct brw_context
*brw
);
559 enum shader_time_shader_type
{
570 struct brw_vertex_buffer
{
571 /** Buffer object containing the uploaded vertex data */
575 /** Byte stride between elements in the uploaded array */
579 struct brw_vertex_element
{
580 const struct gl_client_array
*glarray
;
584 /** Offset of the first element within the buffer object */
588 struct brw_query_object
{
589 struct gl_query_object Base
;
591 /** Last query BO associated with this query. */
594 /** Last index in bo with query data for this object. */
597 /** True if we know the batch has been flushed since we ended the query. */
607 struct intel_batchbuffer
{
608 /** Current batchbuffer being queued up. */
610 /** Last BO submitted to the hardware. Used for glFinish(). */
611 drm_intel_bo
*last_bo
;
614 uint16_t emit
, total
;
616 uint16_t reserved_space
;
620 #define BATCH_SZ (8192*sizeof(uint32_t))
622 uint32_t state_batch_offset
;
623 enum brw_gpu_ring ring
;
624 bool needs_sol_reset
;
625 bool state_base_address_emitted
;
633 #define MAX_GS_INPUT_VERTICES 6
635 #define BRW_MAX_XFB_STREAMS 4
637 struct brw_transform_feedback_object
{
638 struct gl_transform_feedback_object base
;
640 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
641 drm_intel_bo
*offset_bo
;
643 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
646 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
647 GLenum primitive_mode
;
650 * Count of primitives generated during this transform feedback operation.
653 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
654 drm_intel_bo
*prim_count_bo
;
655 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
659 * Number of vertices written between last Begin/EndTransformFeedback().
661 * Used to implement DrawTransformFeedback().
663 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
664 bool vertices_written_valid
;
668 * Data shared between each programmable stage in the pipeline (vs, gs, and
671 struct brw_stage_state
673 gl_shader_stage stage
;
674 struct brw_stage_prog_data
*prog_data
;
677 * Optional scratch buffer used to store spilled register values and
678 * variably-indexed GRF arrays.
680 * The contents of this buffer are short-lived so the same memory can be
681 * re-used at will for multiple shader programs (executed by the same fixed
682 * function). However reusing a scratch BO for which shader invocations
683 * are still in flight with a per-thread scratch slot size other than the
684 * original can cause threads with different scratch slot size and FFTID
685 * (which may be executed in parallel depending on the shader stage and
686 * hardware generation) to map to an overlapping region of the scratch
687 * space, which can potentially lead to mutual scratch space corruption.
688 * For that reason if you borrow this scratch buffer you should only be
689 * using the slot size given by the \c per_thread_scratch member below,
690 * unless you're taking additional measures to synchronize thread execution
691 * across slot size changes.
693 drm_intel_bo
*scratch_bo
;
696 * Scratch slot size allocated for each thread in the buffer object given
699 uint32_t per_thread_scratch
;
701 /** Offset in the program cache to the program */
702 uint32_t prog_offset
;
704 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
705 uint32_t state_offset
;
707 uint32_t push_const_offset
; /* Offset in the batchbuffer */
708 int push_const_size
; /* in 256-bit register increments */
710 /* Binding table: pointers to SURFACE_STATE entries. */
711 uint32_t bind_bo_offset
;
712 uint32_t surf_offset
[BRW_MAX_SURFACES
];
714 /** SAMPLER_STATE count and table offset */
715 uint32_t sampler_count
;
716 uint32_t sampler_offset
;
719 enum brw_predicate_state
{
720 /* The first two states are used if we can determine whether to draw
721 * without having to look at the values in the query object buffer. This
722 * will happen if there is no conditional render in progress, if the query
723 * object is already completed or if something else has already added
724 * samples to the preliminary result such as via a BLT command.
726 BRW_PREDICATE_STATE_RENDER
,
727 BRW_PREDICATE_STATE_DONT_RENDER
,
728 /* In this case whether to draw or not depends on the result of an
729 * MI_PREDICATE command so the predicate enable bit needs to be checked.
731 BRW_PREDICATE_STATE_USE_BIT
736 struct brw_l3_config
;
739 * brw_context is derived from gl_context.
743 struct gl_context ctx
; /**< base class, must be first field */
747 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
748 struct gl_renderbuffer
*rb
,
749 bool layered
, unsigned unit
,
750 uint32_t surf_index
);
751 void (*emit_null_surface_state
)(struct brw_context
*brw
,
755 uint32_t *out_offset
);
758 * Send the appropriate state packets to configure depth, stencil, and
759 * HiZ buffers (i965+ only)
761 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
762 struct intel_mipmap_tree
*depth_mt
,
763 uint32_t depth_offset
,
764 uint32_t depthbuffer_format
,
765 uint32_t depth_surface_type
,
766 struct intel_mipmap_tree
*stencil_mt
,
767 bool hiz
, bool separate_stencil
,
768 uint32_t width
, uint32_t height
,
769 uint32_t tile_x
, uint32_t tile_y
);
775 drm_intel_context
*hw_ctx
;
777 /** BO for post-sync nonzero writes for gen6 workaround. */
778 drm_intel_bo
*workaround_bo
;
779 uint8_t pipe_controls_since_last_cs_stall
;
782 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
783 * and would need flushing before being used from another cache domain that
784 * isn't coherent with it (i.e. the sampler).
786 struct set
*render_cache
;
789 * Number of resets observed in the system at context creation.
791 * This is tracked in the context so that we can determine that another
792 * reset has occurred.
794 uint32_t reset_count
;
796 struct intel_batchbuffer batch
;
801 uint32_t next_offset
;
805 * Set if rendering has occurred to the drawable's front buffer.
807 * This is used in the DRI2 case to detect that glFlush should also copy
808 * the contents of the fake front buffer to the real front buffer.
810 bool front_buffer_dirty
;
812 /** Framerate throttling: @{ */
813 drm_intel_bo
*throttle_batch
[2];
815 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
816 * frame of rendering to complete. This gives a very precise cap to the
817 * latency between input and output such that rendering never gets more
818 * than a frame behind the user. (With the caveat that we technically are
819 * not using the SwapBuffers itself as a barrier but the first batch
820 * submitted afterwards, which may be immediately prior to the next
823 bool need_swap_throttle
;
825 /** General throttling, not caught by throttling between SwapBuffers */
826 bool need_flush_throttle
;
836 bool always_flush_batch
;
837 bool always_flush_cache
;
838 bool disable_throttling
;
840 bool dual_color_blend_by_location
;
842 driOptionCache optionCache
;
845 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
847 GLenum reduced_primitive
;
850 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
851 * variable is set, this is the flag indicating to do expensive work that
852 * might lead to a perf_debug() call.
856 uint64_t max_gtt_map_object_size
;
868 bool has_separate_stencil
;
869 bool must_use_separate_stencil
;
872 bool has_surface_tile_offset
;
874 bool has_negative_rhw_bug
;
878 bool use_resource_streamer
;
881 * Whether LRI can be used to write register values from the batch buffer.
883 bool can_do_pipelined_register_writes
;
886 * Some versions of Gen hardware don't do centroid interpolation correctly
887 * on unlit pixels, causing incorrect values for derivatives near triangle
888 * edges. Enabling this flag causes the fragment shader to use
889 * non-centroid interpolation for unlit pixels, at the expense of two extra
890 * fragment shader instructions.
892 bool needs_unlit_centroid_workaround
;
894 struct isl_device isl_dev
;
898 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
901 enum brw_pipeline last_pipeline
;
903 struct brw_cache cache
;
905 /** IDs for meta stencil blit shader programs. */
906 struct gl_shader_program
*meta_stencil_blit_programs
[2];
908 /* Whether a meta-operation is in progress. */
909 bool meta_in_progress
;
911 /* Whether the last depth/stencil packets were both NULL. */
912 bool no_depth_or_stencil
;
914 /* The last PMA stall bits programmed. */
915 uint32_t pma_stall_bits
;
919 /** The value of gl_BaseVertex for the current _mesa_prim. */
922 /** The value of gl_BaseInstance for the current _mesa_prim. */
927 * Buffer and offset used for GL_ARB_shader_draw_parameters
928 * (for now, only gl_BaseVertex).
930 drm_intel_bo
*draw_params_bo
;
931 uint32_t draw_params_offset
;
934 * The value of gl_DrawID for the current _mesa_prim. This always comes
935 * in from it's own vertex buffer since it's not part of the indirect
939 drm_intel_bo
*draw_id_bo
;
940 uint32_t draw_id_offset
;
945 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
946 * an indirect call, and num_work_groups_offset is valid. Otherwise,
947 * num_work_groups is set based on glDispatchCompute.
949 drm_intel_bo
*num_work_groups_bo
;
950 GLintptr num_work_groups_offset
;
951 const GLuint
*num_work_groups
;
955 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
956 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
958 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
962 /* Summary of size and varying of active arrays, so we can check
963 * for changes to this state:
965 bool index_bounds_valid
;
966 unsigned int min_index
, max_index
;
968 /* Offset from start of vertex buffer so we can avoid redefining
969 * the same VB packed over and over again.
971 unsigned int start_vertex_bias
;
974 * Certain vertex attribute formats aren't natively handled by the
975 * hardware and require special VS code to fix up their values.
977 * These bitfields indicate which workarounds are needed.
979 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
984 * Index buffer for this draw_prims call.
986 * Updates are signaled by BRW_NEW_INDICES.
988 const struct _mesa_index_buffer
*ib
;
990 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
995 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
996 * avoid re-uploading the IB packet over and over if we're actually
997 * referencing the same index buffer.
999 unsigned int start_vertex_offset
;
1002 /* Active vertex program:
1004 const struct gl_vertex_program
*vertex_program
;
1005 const struct gl_geometry_program
*geometry_program
;
1006 const struct gl_tess_ctrl_program
*tess_ctrl_program
;
1007 const struct gl_tess_eval_program
*tess_eval_program
;
1008 const struct gl_fragment_program
*fragment_program
;
1009 const struct gl_compute_program
*compute_program
;
1012 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1013 * that we don't have to reemit that state every time we change FBOs.
1018 * Platform specific constants containing the maximum number of threads
1019 * for each pipeline stage.
1021 unsigned max_vs_threads
;
1022 unsigned max_hs_threads
;
1023 unsigned max_ds_threads
;
1024 unsigned max_gs_threads
;
1025 unsigned max_wm_threads
;
1026 unsigned max_cs_threads
;
1028 /* BRW_NEW_URB_ALLOCATIONS:
1031 GLuint vsize
; /* vertex size plus header in urb registers */
1032 GLuint gsize
; /* GS output size in urb registers */
1033 GLuint hsize
; /* Tessellation control output size in urb registers */
1034 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
1035 GLuint csize
; /* constant buffer size in urb registers */
1036 GLuint sfsize
; /* setup data size in urb registers */
1040 GLuint min_vs_entries
; /* Minimum number of VS entries */
1041 GLuint max_vs_entries
; /* Maximum number of VS entries */
1042 GLuint max_hs_entries
; /* Maximum number of HS entries */
1043 GLuint max_ds_entries
; /* Maximum number of DS entries */
1044 GLuint max_gs_entries
; /* Maximum number of GS entries */
1046 GLuint nr_vs_entries
;
1047 GLuint nr_hs_entries
;
1048 GLuint nr_ds_entries
;
1049 GLuint nr_gs_entries
;
1050 GLuint nr_clip_entries
;
1051 GLuint nr_sf_entries
;
1052 GLuint nr_cs_entries
;
1062 * URB size in the current configuration. The units this is expressed
1063 * in are somewhat inconsistent, see brw_device_info::urb::size.
1065 * FINISHME: Represent the URB size consistently in KB on all platforms.
1069 /* True if the most recently sent _3DSTATE_URB message allocated
1070 * URB space for the GS.
1074 /* True if the most recently sent _3DSTATE_URB message allocated
1075 * URB space for the HS and DS.
1081 /* BRW_NEW_CURBE_OFFSETS:
1084 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1085 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1093 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1094 * for upload to the CURBE.
1096 drm_intel_bo
*curbe_bo
;
1097 /** Offset within curbe_bo of space for current curbe entry */
1098 GLuint curbe_offset
;
1102 * Layout of vertex data exiting the geometry portion of the pipleine.
1103 * This comes from the last enabled shader stage (GS, DS, or VS).
1105 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1107 struct brw_vue_map vue_map_geom_out
;
1110 struct brw_stage_state base
;
1111 struct brw_vs_prog_data
*prog_data
;
1115 struct brw_stage_state base
;
1116 struct brw_tcs_prog_data
*prog_data
;
1119 * True if the 3DSTATE_HS command most recently emitted to the 3D
1120 * pipeline enabled the HS; false otherwise.
1126 struct brw_stage_state base
;
1127 struct brw_tes_prog_data
*prog_data
;
1130 * True if the 3DSTATE_DS command most recently emitted to the 3D
1131 * pipeline enabled the DS; false otherwise.
1137 struct brw_stage_state base
;
1138 struct brw_gs_prog_data
*prog_data
;
1141 * True if the 3DSTATE_GS command most recently emitted to the 3D
1142 * pipeline enabled the GS; false otherwise.
1148 struct brw_ff_gs_prog_data
*prog_data
;
1151 /** Offset in the program cache to the CLIP program pre-gen6 */
1152 uint32_t prog_offset
;
1153 uint32_t state_offset
;
1155 uint32_t bind_bo_offset
;
1157 * Surface offsets for the binding table. We only need surfaces to
1158 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1159 * need in this case.
1161 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1165 struct brw_clip_prog_data
*prog_data
;
1167 /** Offset in the program cache to the CLIP program pre-gen6 */
1168 uint32_t prog_offset
;
1170 /* Offset in the batch to the CLIP state on pre-gen6. */
1171 uint32_t state_offset
;
1173 /* As of gen6, this is the offset in the batch to the CLIP VP,
1181 struct brw_sf_prog_data
*prog_data
;
1183 /** Offset in the program cache to the CLIP program pre-gen6 */
1184 uint32_t prog_offset
;
1185 uint32_t state_offset
;
1187 bool viewport_transform_enable
;
1191 struct brw_stage_state base
;
1192 struct brw_wm_prog_data
*prog_data
;
1197 * Buffer object used in place of multisampled null render targets on
1198 * Gen6. See brw_emit_null_surface_state().
1200 drm_intel_bo
*multisampled_null_render_target_bo
;
1201 uint32_t fast_clear_op
;
1207 struct brw_stage_state base
;
1208 struct brw_cs_prog_data
*prog_data
;
1211 /* RS hardware binding table */
1214 uint32_t next_offset
;
1218 uint32_t state_offset
;
1219 uint32_t blend_state_offset
;
1220 uint32_t depth_stencil_state_offset
;
1225 struct brw_query_object
*obj
;
1230 enum brw_predicate_state state
;
1235 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1236 const int *statistics_registers
;
1238 /** The number of active monitors using OA counters. */
1242 * A buffer object storing OA counter snapshots taken at the start and
1243 * end of each batch (creating "bookends" around the batch).
1245 drm_intel_bo
*bookend_bo
;
1247 /** The number of snapshots written to bookend_bo. */
1248 int bookend_snapshots
;
1251 * An array of monitors whose results haven't yet been assembled based on
1252 * the data in buffer objects.
1254 * These may be active, or have already ended. However, the results
1255 * have not been requested.
1257 struct brw_perf_monitor_object
**unresolved
;
1258 int unresolved_elements
;
1259 int unresolved_array_size
;
1262 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1263 * the counter which MI_REPORT_PERF_COUNT stores there.
1265 const int *oa_snapshot_layout
;
1267 /** Number of 32-bit entries in a hardware counter snapshot. */
1268 int entries_per_oa_snapshot
;
1271 int num_atoms
[BRW_NUM_PIPELINES
];
1272 const struct brw_tracked_state render_atoms
[76];
1273 const struct brw_tracked_state compute_atoms
[11];
1275 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1279 enum aub_state_struct_type type
;
1281 } *state_batch_list
;
1282 int state_batch_count
;
1284 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1285 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1287 /* Interpolation modes, one byte per vue slot.
1288 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1290 struct interpolation_mode_map interpolation_mode
;
1292 /* PrimitiveRestart */
1295 bool enable_cut_index
;
1298 /** Computed depth/stencil/hiz state from the current attached
1299 * renderbuffers, valid only during the drawing state upload loop after
1300 * brw_workaround_depthstencil_alignment().
1303 struct intel_mipmap_tree
*depth_mt
;
1304 struct intel_mipmap_tree
*stencil_mt
;
1306 /* Inter-tile (page-aligned) byte offsets. */
1307 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1308 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1309 uint32_t tile_x
, tile_y
;
1312 uint32_t num_instances
;
1317 const struct brw_l3_config
*config
;
1324 enum shader_time_shader_type
*types
;
1325 struct shader_times
*cumulative
;
1331 struct brw_fast_clear_state
*fast_clear_state
;
1333 __DRIcontext
*driContext
;
1334 struct intel_screen
*intelScreen
;
1337 /*======================================================================
1340 void brwInitVtbl( struct brw_context
*brw
);
1343 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1345 /*======================================================================
1348 extern const char *const brw_vendor_string
;
1351 brw_get_renderer_string(const struct intel_screen
*intelScreen
);
1354 DRI_CONF_BO_REUSE_DISABLED
,
1355 DRI_CONF_BO_REUSE_ALL
1358 void intel_update_renderbuffers(__DRIcontext
*context
,
1359 __DRIdrawable
*drawable
);
1360 void intel_prepare_render(struct brw_context
*brw
);
1362 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1363 __DRIdrawable
*drawable
);
1365 GLboolean
brwCreateContext(gl_api api
,
1366 const struct gl_config
*mesaVis
,
1367 __DRIcontext
*driContextPriv
,
1368 unsigned major_version
,
1369 unsigned minor_version
,
1373 void *sharedContextPrivate
);
1375 /*======================================================================
1379 brw_meta_resolve_color(struct brw_context
*brw
,
1380 struct intel_mipmap_tree
*mt
);
1382 /*======================================================================
1385 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1386 uint32_t depth_level
,
1387 uint32_t depth_layer
,
1388 struct intel_mipmap_tree
*stencil_mt
,
1389 uint32_t *out_tile_mask_x
,
1390 uint32_t *out_tile_mask_y
);
1391 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1392 GLbitfield clear_mask
);
1394 /* brw_object_purgeable.c */
1395 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1397 /*======================================================================
1400 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1401 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1402 void brw_emit_query_begin(struct brw_context
*brw
);
1403 void brw_emit_query_end(struct brw_context
*brw
);
1404 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1405 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1407 /** gen6_queryobj.c */
1408 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1409 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1410 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1412 /** hsw_queryobj.c */
1413 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1415 /** brw_conditional_render.c */
1416 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1417 bool brw_check_conditional_render(struct brw_context
*brw
);
1419 /** intel_batchbuffer.c */
1420 void brw_load_register_mem(struct brw_context
*brw
,
1423 uint32_t read_domains
, uint32_t write_domain
,
1425 void brw_load_register_mem64(struct brw_context
*brw
,
1428 uint32_t read_domains
, uint32_t write_domain
,
1430 void brw_store_register_mem32(struct brw_context
*brw
,
1431 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1432 void brw_store_register_mem64(struct brw_context
*brw
,
1433 drm_intel_bo
*bo
, uint32_t reg
, uint32_t offset
);
1434 void brw_load_register_imm32(struct brw_context
*brw
,
1435 uint32_t reg
, uint32_t imm
);
1436 void brw_load_register_imm64(struct brw_context
*brw
,
1437 uint32_t reg
, uint64_t imm
);
1438 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1440 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1442 void brw_store_data_imm32(struct brw_context
*brw
, drm_intel_bo
*bo
,
1443 uint32_t offset
, uint32_t imm
);
1444 void brw_store_data_imm64(struct brw_context
*brw
, drm_intel_bo
*bo
,
1445 uint32_t offset
, uint64_t imm
);
1447 /*======================================================================
1450 void brw_debug_batch(struct brw_context
*brw
);
1451 void brw_annotate_aub(struct brw_context
*brw
);
1453 /*======================================================================
1454 * intel_tex_validate.c
1456 void brw_validate_textures( struct brw_context
*brw
);
1459 /*======================================================================
1463 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1466 perf_debug(" %s %d->%d\n", name
, a
, b
);
1472 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1474 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1476 brw_get_scratch_size(int size
)
1478 return MAX2(1024, util_next_power_of_two(size
));
1480 void brw_get_scratch_bo(struct brw_context
*brw
,
1481 drm_intel_bo
**scratch_bo
, int size
);
1482 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1483 struct brw_stage_state
*stage_state
,
1484 unsigned per_thread_size
,
1485 unsigned thread_count
);
1486 void brw_init_shader_time(struct brw_context
*brw
);
1487 int brw_get_shader_time_index(struct brw_context
*brw
,
1488 struct gl_shader_program
*shader_prog
,
1489 struct gl_program
*prog
,
1490 enum shader_time_shader_type type
);
1491 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1492 void brw_destroy_shader_time(struct brw_context
*brw
);
1496 void brw_upload_urb_fence(struct brw_context
*brw
);
1500 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1502 /* brw_fs_reg_allocate.cpp
1504 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1506 /* brw_vec4_reg_allocate.cpp */
1507 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1510 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1511 struct brw_inst
*inst
, bool is_compacted
);
1514 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1516 /* brw_draw_upload.c */
1517 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1518 const struct gl_client_array
*glarray
);
1520 static inline unsigned
1521 brw_get_index_type(GLenum type
)
1523 assert((type
== GL_UNSIGNED_BYTE
)
1524 || (type
== GL_UNSIGNED_SHORT
)
1525 || (type
== GL_UNSIGNED_INT
));
1527 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1528 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1529 * to map to scale factors of 0, 1, and 2, respectively. These scale
1530 * factors are then left-shfited by 8 to be in the correct position in the
1531 * CMD_INDEX_BUFFER packet.
1533 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1534 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1535 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1537 return (type
- 0x1401) << 7;
1540 void brw_prepare_vertices(struct brw_context
*brw
);
1542 /* brw_wm_surface_state.c */
1543 void brw_init_surface_formats(struct brw_context
*brw
);
1544 void brw_create_constant_surface(struct brw_context
*brw
,
1548 uint32_t *out_offset
);
1549 void brw_create_buffer_surface(struct brw_context
*brw
,
1553 uint32_t *out_offset
);
1554 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1556 uint32_t *surf_offset
);
1558 brw_update_sol_surface(struct brw_context
*brw
,
1559 struct gl_buffer_object
*buffer_obj
,
1560 uint32_t *out_offset
, unsigned num_vector_components
,
1561 unsigned stride_dwords
, unsigned offset_dwords
);
1562 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1563 struct gl_linked_shader
*shader
,
1564 struct brw_stage_state
*stage_state
,
1565 struct brw_stage_prog_data
*prog_data
);
1566 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1567 struct gl_linked_shader
*shader
,
1568 struct brw_stage_state
*stage_state
,
1569 struct brw_stage_prog_data
*prog_data
);
1570 void brw_upload_image_surfaces(struct brw_context
*brw
,
1571 struct gl_linked_shader
*shader
,
1572 struct brw_stage_state
*stage_state
,
1573 struct brw_stage_prog_data
*prog_data
);
1575 /* brw_surface_formats.c */
1576 bool brw_render_target_supported(struct brw_context
*brw
,
1577 struct gl_renderbuffer
*rb
);
1578 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1580 /* brw_performance_monitor.c */
1581 void brw_init_performance_monitors(struct brw_context
*brw
);
1582 void brw_dump_perf_monitors(struct brw_context
*brw
);
1583 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1584 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1586 /* intel_buffer_objects.c */
1587 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1588 const char *bo_name
);
1589 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1590 const char *bo_name
);
1592 /* intel_extensions.c */
1593 extern void intelInitExtensions(struct gl_context
*ctx
);
1596 extern int intel_translate_shadow_compare_func(GLenum func
);
1597 extern int intel_translate_compare_func(GLenum func
);
1598 extern int intel_translate_stencil_op(GLenum op
);
1599 extern int intel_translate_logic_op(GLenum opcode
);
1601 /* intel_syncobj.c */
1602 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1605 struct gl_transform_feedback_object
*
1606 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1608 brw_delete_transform_feedback(struct gl_context
*ctx
,
1609 struct gl_transform_feedback_object
*obj
);
1611 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1612 struct gl_transform_feedback_object
*obj
);
1614 brw_end_transform_feedback(struct gl_context
*ctx
,
1615 struct gl_transform_feedback_object
*obj
);
1617 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1618 struct gl_transform_feedback_object
*obj
,
1621 /* gen7_sol_state.c */
1623 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1624 struct gl_transform_feedback_object
*obj
);
1626 gen7_end_transform_feedback(struct gl_context
*ctx
,
1627 struct gl_transform_feedback_object
*obj
);
1629 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1630 struct gl_transform_feedback_object
*obj
);
1632 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1633 struct gl_transform_feedback_object
*obj
);
1637 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1638 struct gl_transform_feedback_object
*obj
);
1640 hsw_end_transform_feedback(struct gl_context
*ctx
,
1641 struct gl_transform_feedback_object
*obj
);
1643 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1644 struct gl_transform_feedback_object
*obj
);
1646 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1647 struct gl_transform_feedback_object
*obj
);
1649 /* brw_blorp_blit.cpp */
1651 brw_blorp_framebuffer(struct brw_context
*brw
,
1652 struct gl_framebuffer
*readFb
,
1653 struct gl_framebuffer
*drawFb
,
1654 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1655 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1656 GLbitfield mask
, GLenum filter
);
1659 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1660 struct gl_renderbuffer
*src_rb
,
1661 struct gl_texture_image
*dst_image
,
1663 int srcX0
, int srcY0
,
1664 int dstX0
, int dstY0
,
1665 int width
, int height
);
1667 /* gen6_multisample_state.c */
1669 gen6_determine_sample_mask(struct brw_context
*brw
);
1672 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1673 unsigned num_samples
);
1675 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1677 gen6_get_sample_position(struct gl_context
*ctx
,
1678 struct gl_framebuffer
*fb
,
1682 gen6_set_sample_maps(struct gl_context
*ctx
);
1684 /* gen8_multisample_state.c */
1685 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1686 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1690 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1691 unsigned hs_size
, unsigned ds_size
,
1692 unsigned gs_size
, unsigned fs_size
);
1695 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1696 bool gs_present
, bool tess_present
);
1700 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1702 brw_check_for_reset(struct brw_context
*brw
);
1706 brw_init_compute_functions(struct dd_function_table
*functions
);
1708 /*======================================================================
1709 * Inline conversion functions. These are better-typed than the
1710 * macros used previously:
1712 static inline struct brw_context
*
1713 brw_context( struct gl_context
*ctx
)
1715 return (struct brw_context
*)ctx
;
1718 static inline struct brw_vertex_program
*
1719 brw_vertex_program(struct gl_vertex_program
*p
)
1721 return (struct brw_vertex_program
*) p
;
1724 static inline const struct brw_vertex_program
*
1725 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1727 return (const struct brw_vertex_program
*) p
;
1730 static inline struct brw_tess_ctrl_program
*
1731 brw_tess_ctrl_program(struct gl_tess_ctrl_program
*p
)
1733 return (struct brw_tess_ctrl_program
*) p
;
1736 static inline struct brw_tess_eval_program
*
1737 brw_tess_eval_program(struct gl_tess_eval_program
*p
)
1739 return (struct brw_tess_eval_program
*) p
;
1742 static inline struct brw_geometry_program
*
1743 brw_geometry_program(struct gl_geometry_program
*p
)
1745 return (struct brw_geometry_program
*) p
;
1748 static inline struct brw_fragment_program
*
1749 brw_fragment_program(struct gl_fragment_program
*p
)
1751 return (struct brw_fragment_program
*) p
;
1754 static inline const struct brw_fragment_program
*
1755 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1757 return (const struct brw_fragment_program
*) p
;
1760 static inline struct brw_compute_program
*
1761 brw_compute_program(struct gl_compute_program
*p
)
1763 return (struct brw_compute_program
*) p
;
1767 * Pre-gen6, the register file of the EUs was shared between threads,
1768 * and each thread used some subset allocated on a 16-register block
1769 * granularity. The unit states wanted these block counts.
1772 brw_register_blocks(int reg_count
)
1774 return ALIGN(reg_count
, 16) / 16 - 1;
1777 static inline uint32_t
1778 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
1779 uint32_t prog_offset
)
1781 if (brw
->gen
>= 5) {
1782 /* Using state base address. */
1786 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
1790 I915_GEM_DOMAIN_INSTRUCTION
, 0);
1792 return brw
->cache
.bo
->offset64
+ prog_offset
;
1795 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
1796 bool brw_lower_texture_gradients(struct brw_context
*brw
,
1797 struct exec_list
*instructions
);
1799 extern const char * const conditional_modifier
[16];
1800 extern const char *const pred_ctrl_align16
[16];
1803 brw_emit_depthbuffer(struct brw_context
*brw
);
1806 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1807 struct intel_mipmap_tree
*depth_mt
,
1808 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1809 uint32_t depth_surface_type
,
1810 struct intel_mipmap_tree
*stencil_mt
,
1811 bool hiz
, bool separate_stencil
,
1812 uint32_t width
, uint32_t height
,
1813 uint32_t tile_x
, uint32_t tile_y
);
1816 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1817 struct intel_mipmap_tree
*depth_mt
,
1818 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1819 uint32_t depth_surface_type
,
1820 struct intel_mipmap_tree
*stencil_mt
,
1821 bool hiz
, bool separate_stencil
,
1822 uint32_t width
, uint32_t height
,
1823 uint32_t tile_x
, uint32_t tile_y
);
1826 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1827 struct intel_mipmap_tree
*depth_mt
,
1828 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1829 uint32_t depth_surface_type
,
1830 struct intel_mipmap_tree
*stencil_mt
,
1831 bool hiz
, bool separate_stencil
,
1832 uint32_t width
, uint32_t height
,
1833 uint32_t tile_x
, uint32_t tile_y
);
1835 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1836 struct intel_mipmap_tree
*depth_mt
,
1837 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1838 uint32_t depth_surface_type
,
1839 struct intel_mipmap_tree
*stencil_mt
,
1840 bool hiz
, bool separate_stencil
,
1841 uint32_t width
, uint32_t height
,
1842 uint32_t tile_x
, uint32_t tile_y
);
1844 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
1845 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
1847 uint32_t get_hw_prim_for_gl_prim(int mode
);
1850 gen6_upload_push_constants(struct brw_context
*brw
,
1851 const struct gl_program
*prog
,
1852 const struct brw_stage_prog_data
*prog_data
,
1853 struct brw_stage_state
*stage_state
,
1854 enum aub_state_struct_type type
);
1857 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1858 const struct intel_mipmap_tree
*mt
);
1860 /* brw_pipe_control.c */
1861 int brw_init_pipe_control(struct brw_context
*brw
,
1862 const struct brw_device_info
*info
);
1863 void brw_fini_pipe_control(struct brw_context
*brw
);
1865 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1866 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1867 drm_intel_bo
*bo
, uint32_t offset
,
1868 uint32_t imm_lower
, uint32_t imm_upper
);
1869 void brw_emit_mi_flush(struct brw_context
*brw
);
1870 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1871 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1872 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1873 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1875 /* brw_queryformat.c */
1876 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1877 GLenum internalFormat
, GLenum pname
,