2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
38 #include "main/imports.h"
39 #include "main/macros.h"
41 #include "main/mtypes.h"
42 #include "brw_structs.h"
43 #include "intel_aub.h"
44 #include "program/prog_parameter.h"
48 /* Evil hack for using libdrm in a c++ compiler. */
53 #include <intel_bufmgr.h>
63 #include "intel_debug.h"
64 #include "intel_screen.h"
65 #include "intel_tex_obj.h"
66 #include "intel_resolve_map.h"
70 * URB - uniform resource buffer. A mid-sized buffer which is
71 * partitioned between the fixed function units and used for passing
72 * values (vertices, primitives, constants) between them.
74 * CURBE - constant URB entry. An urb region (entry) used to hold
75 * constant values which the fixed function units can be instructed to
76 * preload into the GRF when spawning a thread.
78 * VUE - vertex URB entry. An urb entry holding a vertex and usually
79 * a vertex header. The header contains control information and
80 * things like primitive type, Begin/end flags and clip codes.
82 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
83 * unit holding rasterization and interpolation parameters.
85 * GRF - general register file. One of several register files
86 * addressable by programmed threads. The inputs (r0, payload, curbe,
87 * urb) of the thread are preloaded to this area before the thread is
88 * spawned. The registers are individually 8 dwords wide and suitable
89 * for general usage. Registers holding thread input values are not
90 * special and may be overwritten.
92 * MRF - message register file. Threads communicate (and terminate)
93 * by sending messages. Message parameters are placed in contiguous
94 * MRF registers. All program output is via these messages. URB
95 * entries are populated by sending a message to the shared URB
96 * function containing the new data, together with a control word,
97 * often an unmodified copy of R0.
99 * R0 - GRF register 0. Typically holds control information used when
100 * sending messages to other threads.
102 * EU or GEN4 EU: The name of the programmable subsystem of the
103 * i965 hardware. Threads are executed by the EU, the registers
104 * described above are part of the EU architecture.
106 * Fixed function units:
108 * CS - Command streamer. Notional first unit, little software
109 * interaction. Holds the URB entries used for constant data, ie the
112 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
113 * this unit is responsible for pulling vertices out of vertex buffers
114 * in vram and injecting them into the processing pipe as VUEs. If
115 * enabled, it first passes them to a VS thread which is a good place
116 * for the driver to implement any active vertex shader.
118 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
119 * enabled, incoming strips etc are passed to GS threads in individual
120 * line/triangle/point units. The GS thread may perform arbitary
121 * computation and emit whatever primtives with whatever vertices it
122 * chooses. This makes GS an excellent place to implement GL's
123 * unfilled polygon modes, though of course it is capable of much
124 * more. Additionally, GS is used to translate away primitives not
125 * handled by latter units, including Quads and Lineloops.
127 * CS - Clipper. Mesa's clipping algorithms are imported to run on
128 * this unit. The fixed function part performs cliptesting against
129 * the 6 fixed clipplanes and makes descisions on whether or not the
130 * incoming primitive needs to be passed to a thread for clipping.
131 * User clip planes are handled via cooperation with the VS thread.
133 * SF - Strips Fans or Setup: Triangles are prepared for
134 * rasterization. Interpolation coefficients are calculated.
135 * Flatshading and two-side lighting usually performed here.
137 * WM - Windower. Interpolation of vertex attributes performed here.
138 * Fragment shader implemented here. SIMD aspects of EU taken full
139 * advantage of, as pixels are processed in blocks of 16.
141 * CC - Color Calculator. No EU threads associated with this unit.
142 * Handles blending and (presumably) depth and stencil testing.
147 struct brw_vs_prog_key
;
148 struct brw_vue_prog_key
;
149 struct brw_wm_prog_key
;
150 struct brw_wm_prog_data
;
151 struct brw_cs_prog_key
;
152 struct brw_cs_prog_data
;
156 BRW_COMPUTE_PIPELINE
,
163 BRW_CACHE_BLORP_BLIT_PROG
,
166 BRW_CACHE_FF_GS_PROG
,
175 /* brw_cache_ids must come first - see brw_state_cache.c */
176 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
177 BRW_STATE_FRAGMENT_PROGRAM
,
178 BRW_STATE_GEOMETRY_PROGRAM
,
179 BRW_STATE_VERTEX_PROGRAM
,
180 BRW_STATE_CURBE_OFFSETS
,
181 BRW_STATE_REDUCED_PRIMITIVE
,
186 BRW_STATE_VS_BINDING_TABLE
,
187 BRW_STATE_GS_BINDING_TABLE
,
188 BRW_STATE_PS_BINDING_TABLE
,
192 BRW_STATE_INDEX_BUFFER
,
193 BRW_STATE_VS_CONSTBUF
,
194 BRW_STATE_GS_CONSTBUF
,
195 BRW_STATE_PROGRAM_CACHE
,
196 BRW_STATE_STATE_BASE_ADDRESS
,
197 BRW_STATE_VUE_MAP_GEOM_OUT
,
198 BRW_STATE_TRANSFORM_FEEDBACK
,
199 BRW_STATE_RASTERIZER_DISCARD
,
201 BRW_STATE_UNIFORM_BUFFER
,
202 BRW_STATE_ATOMIC_BUFFER
,
203 BRW_STATE_IMAGE_UNITS
,
204 BRW_STATE_META_IN_PROGRESS
,
205 BRW_STATE_INTERPOLATION_MAP
,
206 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
207 BRW_STATE_NUM_SAMPLES
,
208 BRW_STATE_TEXTURE_BUFFER
,
209 BRW_STATE_GEN4_UNIT_STATE
,
213 BRW_STATE_SAMPLER_STATE_TABLE
,
214 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
215 BRW_STATE_COMPUTE_PROGRAM
,
216 BRW_STATE_CS_WORK_GROUPS
,
221 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
223 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
224 * When the currently bound shader program differs from the previous draw
225 * call, these will be flagged. They cover brw->{stage}_program and
226 * ctx->{Stage}Program->_Current.
228 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
229 * driver perspective. Even if the same shader is bound at the API level,
230 * we may need to switch between multiple versions of that shader to handle
231 * changes in non-orthagonal state.
233 * Additionally, multiple shader programs may have identical vertex shaders
234 * (for example), or compile down to the same code in the backend. We combine
235 * those into a single program cache entry.
237 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
238 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
240 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
241 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
242 * use the normal state upload paths), but the cache is still used. To avoid
243 * polluting the brw_state_cache code with special cases, we retain the dirty
244 * bit for now. It should eventually be removed.
246 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_BLIT_PROG)
247 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
248 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
249 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
250 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
251 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
252 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
253 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
254 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
255 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
256 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
257 #define BRW_NEW_CURBE_OFFSETS (1ull << BRW_STATE_CURBE_OFFSETS)
258 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
259 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
260 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
261 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
262 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
263 #define BRW_NEW_VS_BINDING_TABLE (1ull << BRW_STATE_VS_BINDING_TABLE)
264 #define BRW_NEW_GS_BINDING_TABLE (1ull << BRW_STATE_GS_BINDING_TABLE)
265 #define BRW_NEW_PS_BINDING_TABLE (1ull << BRW_STATE_PS_BINDING_TABLE)
266 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
267 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
269 * Used for any batch entry with a relocated pointer that will be used
270 * by any 3D rendering.
272 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
273 /** \see brw.state.depth_region */
274 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
275 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
276 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
277 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
278 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
279 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
280 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
281 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
282 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
283 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
284 #define BRW_NEW_ATOMIC_BUFFER (1ull << BRW_STATE_ATOMIC_BUFFER)
285 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
286 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
287 #define BRW_NEW_INTERPOLATION_MAP (1ull << BRW_STATE_INTERPOLATION_MAP)
288 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
289 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
290 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
291 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
292 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
293 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
294 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
295 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
296 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
297 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
298 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
300 struct brw_state_flags
{
301 /** State update flags signalled by mesa internals */
304 * State update flags signalled as the result of brw_tracked_state updates
309 /** Subclass of Mesa vertex program */
310 struct brw_vertex_program
{
311 struct gl_vertex_program program
;
316 /** Subclass of Mesa geometry program */
317 struct brw_geometry_program
{
318 struct gl_geometry_program program
;
319 unsigned id
; /**< serial no. to identify geom progs, never re-used */
323 /** Subclass of Mesa fragment program */
324 struct brw_fragment_program
{
325 struct gl_fragment_program program
;
326 GLuint id
; /**< serial no. to identify frag progs, never re-used */
330 /** Subclass of Mesa compute program */
331 struct brw_compute_program
{
332 struct gl_compute_program program
;
333 unsigned id
; /**< serial no. to identify compute progs, never re-used */
338 struct gl_shader base
;
343 struct brw_stage_prog_data
{
345 /** size of our binding table. */
349 * surface indices for the various groups of surfaces
351 uint32_t pull_constants_start
;
352 uint32_t texture_start
;
353 uint32_t gather_texture_start
;
356 uint32_t image_start
;
357 uint32_t shader_time_start
;
361 uint32_t *map_entries
;
363 uint32_t index_count
;
365 } bind_map
[8]; /* MAX_SETS from vulkan/private.h */
367 GLuint nr_params
; /**< number of float params/constants */
368 GLuint nr_pull_params
;
369 unsigned nr_image_params
;
371 unsigned curb_read_length
;
372 unsigned total_scratch
;
375 * Register where the thread expects to find input data from the URB
376 * (typically uniforms, followed by vertex or fragment attributes).
378 unsigned dispatch_grf_start_reg
;
380 bool use_alt_mode
; /**< Use ALT floating point mode? Otherwise, IEEE. */
382 /* Pointers to tracked values (only valid once
383 * _mesa_load_state_parameters has been called at runtime).
385 const gl_constant_value
**param
;
386 const gl_constant_value
**pull_param
;
388 /** Image metadata passed to the shader as uniforms. */
389 struct brw_image_param
*image_param
;
393 * Image metadata structure as laid out in the shader parameter
394 * buffer. Entries have to be 16B-aligned for the vec4 back-end to be
395 * able to use them. That's okay because the padding and any unused
396 * entries [most of them except when we're doing untyped surface
397 * access] will be removed by the uniform packing pass.
399 #define BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET 0
400 #define BRW_IMAGE_PARAM_OFFSET_OFFSET 4
401 #define BRW_IMAGE_PARAM_SIZE_OFFSET 8
402 #define BRW_IMAGE_PARAM_STRIDE_OFFSET 12
403 #define BRW_IMAGE_PARAM_TILING_OFFSET 16
404 #define BRW_IMAGE_PARAM_SWIZZLING_OFFSET 20
405 #define BRW_IMAGE_PARAM_SIZE 24
407 struct brw_image_param
{
408 /** Surface binding table index. */
409 uint32_t surface_idx
;
411 /** Offset applied to the X and Y surface coordinates. */
414 /** Surface X, Y and Z dimensions. */
417 /** X-stride in bytes, Y-stride in pixels, horizontal slice stride in
418 * pixels, vertical slice stride in pixels.
422 /** Log2 of the tiling modulus in the X, Y and Z dimension. */
426 * Right shift to apply for bit 6 address swizzling. Two different
427 * swizzles can be specified and will be applied one after the other. The
428 * resulting address will be:
430 * addr' = addr ^ ((1 << 6) & ((addr >> swizzling[0]) ^
431 * (addr >> swizzling[1])))
433 * Use \c 0xff if any of the swizzles is not required.
435 uint32_t swizzling
[2];
438 /* Data about a particular attempt to compile a program. Note that
439 * there can be many of these, each in a different GL state
440 * corresponding to a different brw_wm_prog_key struct, with different
443 struct brw_wm_prog_data
{
444 struct brw_stage_prog_data base
;
446 GLuint num_varying_inputs
;
448 GLuint dispatch_grf_start_reg_16
;
450 GLuint reg_blocks_16
;
454 * surface indices the WM-specific surfaces
456 uint32_t render_target_start
;
460 uint8_t computed_depth_mode
;
462 bool early_fragment_tests
;
465 bool uses_pos_offset
;
469 uint32_t prog_offset_16
;
472 * Mask of which interpolation modes are required by the fragment shader.
473 * Used in hardware setup on gen6+.
475 uint32_t barycentric_interp_modes
;
478 * Map from gl_varying_slot to the position within the FS setup data
479 * payload where the varying's attribute vertex deltas should be delivered.
480 * For varying slots that are not used by the FS, the value is -1.
482 int urb_setup
[VARYING_SLOT_MAX
];
485 struct brw_cs_prog_data
{
486 struct brw_stage_prog_data base
;
488 GLuint dispatch_grf_start_reg_16
;
489 unsigned local_size
[3];
492 bool uses_num_work_groups
;
493 unsigned local_invocation_id_regs
;
497 * surface indices the CS-specific surfaces
499 uint32_t work_groups_start
;
505 * Enum representing the i965-specific vertex results that don't correspond
506 * exactly to any element of gl_varying_slot. The values of this enum are
507 * assigned such that they don't conflict with gl_varying_slot.
511 BRW_VARYING_SLOT_NDC
= VARYING_SLOT_MAX
,
512 BRW_VARYING_SLOT_PAD
,
514 * Technically this is not a varying but just a placeholder that
515 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
516 * builtin variable to be compiled correctly. see compile_sf_prog() for
519 BRW_VARYING_SLOT_PNTC
,
520 BRW_VARYING_SLOT_COUNT
525 * Data structure recording the relationship between the gl_varying_slot enum
526 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
527 * single octaword within the VUE (128 bits).
529 * Note that each BRW register contains 256 bits (2 octawords), so when
530 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
531 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
532 * in a vertex shader), each register corresponds to a single VUE slot, since
533 * it contains data for two separate vertices.
537 * Bitfield representing all varying slots that are (a) stored in this VUE
538 * map, and (b) actually written by the shader. Does not include any of
539 * the additional varying slots defined in brw_varying_slot.
541 GLbitfield64 slots_valid
;
544 * Is this VUE map for a separate shader pipeline?
546 * Separable programs (GL_ARB_separate_shader_objects) can be mixed and matched
547 * without the linker having a chance to dead code eliminate unused varyings.
549 * This means that we have to use a fixed slot layout, based on the output's
550 * location field, rather than assigning slots in a compact contiguous block.
555 * Map from gl_varying_slot value to VUE slot. For gl_varying_slots that are
556 * not stored in a slot (because they are not written, or because
557 * additional processing is applied before storing them in the VUE), the
560 signed char varying_to_slot
[BRW_VARYING_SLOT_COUNT
];
563 * Map from VUE slot to gl_varying_slot value. For slots that do not
564 * directly correspond to a gl_varying_slot, the value comes from
567 * For slots that are not in use, the value is BRW_VARYING_SLOT_COUNT (this
568 * simplifies code that uses the value stored in slot_to_varying to
569 * create a bit mask).
571 signed char slot_to_varying
[BRW_VARYING_SLOT_COUNT
];
574 * Total number of VUE slots in use
580 * Convert a VUE slot number into a byte offset within the VUE.
582 static inline GLuint
brw_vue_slot_to_offset(GLuint slot
)
588 * Convert a vertex output (brw_varying_slot) into a byte offset within the
591 static inline GLuint
brw_varying_to_offset(struct brw_vue_map
*vue_map
,
594 return brw_vue_slot_to_offset(vue_map
->varying_to_slot
[varying
]);
597 void brw_compute_vue_map(const struct brw_device_info
*devinfo
,
598 struct brw_vue_map
*vue_map
,
599 GLbitfield64 slots_valid
,
600 bool separate_shader
);
604 * Bitmask indicating which fragment shader inputs represent varyings (and
605 * hence have to be delivered to the fragment shader by the SF/SBE stage).
607 #define BRW_FS_VARYING_INPUT_MASK \
608 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
609 ~VARYING_BIT_POS & ~VARYING_BIT_FACE)
613 * Mapping of VUE map slots to interpolation modes.
615 struct interpolation_mode_map
{
616 unsigned char mode
[BRW_VARYING_SLOT_COUNT
];
619 static inline bool brw_any_flat_varyings(struct interpolation_mode_map
*map
)
621 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
622 if (map
->mode
[i
] == INTERP_QUALIFIER_FLAT
)
628 static inline bool brw_any_noperspective_varyings(struct interpolation_mode_map
*map
)
630 for (int i
= 0; i
< BRW_VARYING_SLOT_COUNT
; i
++)
631 if (map
->mode
[i
] == INTERP_QUALIFIER_NOPERSPECTIVE
)
638 struct brw_sf_prog_data
{
639 GLuint urb_read_length
;
642 /* Each vertex may have upto 12 attributes, 4 components each,
643 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11
646 * Actually we use 4 for each, so call it 12 rows.
648 GLuint urb_entry_size
;
653 * We always program SF to start reading at an offset of 1 (2 varying slots)
654 * from the start of the vertex URB entry. This causes it to skip:
655 * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
656 * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
658 #define BRW_SF_URB_ENTRY_READ_OFFSET 1
661 struct brw_clip_prog_data
{
662 GLuint curb_read_length
; /* user planes? */
664 GLuint urb_read_length
;
668 struct brw_ff_gs_prog_data
{
669 GLuint urb_read_length
;
673 * Gen6 transform feedback: Amount by which the streaming vertex buffer
674 * indices should be incremented each time the GS is invoked.
676 unsigned svbi_postincrement_value
;
679 enum shader_dispatch_mode
{
680 DISPATCH_MODE_4X1_SINGLE
= 0,
681 DISPATCH_MODE_4X2_DUAL_INSTANCE
= 1,
682 DISPATCH_MODE_4X2_DUAL_OBJECT
= 2,
683 DISPATCH_MODE_SIMD8
= 3,
686 struct brw_vue_prog_data
{
687 struct brw_stage_prog_data base
;
688 struct brw_vue_map vue_map
;
690 GLuint urb_read_length
;
693 /* Used for calculating urb partitions. In the VS, this is the size of the
694 * URB entry used for both input and output to the thread. In the GS, this
695 * is the size of the URB entry used for output.
697 GLuint urb_entry_size
;
699 enum shader_dispatch_mode dispatch_mode
;
703 struct brw_vs_prog_data
{
704 struct brw_vue_prog_data base
;
706 GLbitfield64 inputs_read
;
709 bool uses_instanceid
;
712 /** Number of texture sampler units */
713 #define BRW_MAX_TEX_UNIT 32
715 /** Max number of render targets in a shader */
716 #define BRW_MAX_DRAW_BUFFERS 8
718 /** Max number of UBOs in a shader */
719 #define BRW_MAX_UBO 12
721 /** Max number of SSBOs in a shader */
722 #define BRW_MAX_SSBO 12
724 /** Max number of combined UBOs and SSBOs in a shader */
725 #define BRW_MAX_COMBINED_UBO_SSBO (BRW_MAX_UBO + BRW_MAX_SSBO)
727 /** Max number of atomic counter buffer objects in a shader */
728 #define BRW_MAX_ABO 16
730 /** Max number of image uniforms in a shader */
731 #define BRW_MAX_IMAGES 32
734 * Max number of binding table entries used for stream output.
736 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the
737 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64.
739 * On Gen6, the size of transform feedback data is limited not by the number
740 * of components but by the number of binding table entries we set aside. We
741 * use one binding table entry for a float, one entry for a vector, and one
742 * entry per matrix column. Since the only way we can communicate our
743 * transform feedback capabilities to the client is via
744 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the
745 * worst case, in which all the varyings are floats, so we use up one binding
746 * table entry per component. Therefore we need to set aside at least 64
747 * binding table entries for use by transform feedback.
749 * Note: since we don't currently pack varyings, it is currently impossible
750 * for the client to actually use up all of these binding table entries--if
751 * all of their varyings were floats, they would run out of varying slots and
752 * fail to link. But that's a bug, so it seems prudent to go ahead and
753 * allocate the number of binding table entries we will need once the bug is
756 #define BRW_MAX_SOL_BINDINGS 64
758 /** Maximum number of actual buffers used for stream output */
759 #define BRW_MAX_SOL_BUFFERS 4
761 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
762 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
767 2 + /* shader time, pull constants */ \
768 1 /* cs num work groups */)
770 #define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
772 struct brw_gs_prog_data
774 struct brw_vue_prog_data base
;
777 * Size of an output vertex, measured in HWORDS (32 bytes).
779 unsigned output_vertex_size_hwords
;
781 unsigned output_topology
;
784 * Size of the control data (cut bits or StreamID bits), in hwords (32
785 * bytes). 0 if there is no control data.
787 unsigned control_data_header_size_hwords
;
790 * Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
791 * if the control data is StreamID bits, or
792 * GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
793 * Ignored if control_data_header_size is 0.
795 unsigned control_data_format
;
797 bool include_primitive_id
;
800 * The number of vertices emitted, if constant - otherwise -1.
802 int static_vertex_count
;
807 * Gen6 transform feedback enabled flag.
809 bool gen6_xfb_enabled
;
812 * Gen6: Provoking vertex convention for odd-numbered triangles
818 * Gen6: Number of varyings that are output to transform feedback.
820 GLuint num_transform_feedback_bindings
:7; /* 0-BRW_MAX_SOL_BINDINGS */
823 * Gen6: Map from the index of a transform feedback binding table entry to the
824 * gl_varying_slot that should be streamed out through that binding table
827 unsigned char transform_feedback_bindings
[BRW_MAX_SOL_BINDINGS
];
830 * Gen6: Map from the index of a transform feedback binding table entry to the
831 * swizzles that should be used when streaming out data through that
832 * binding table entry.
834 unsigned char transform_feedback_swizzles
[BRW_MAX_SOL_BINDINGS
];
838 * Stride in bytes between shader_time entries.
840 * We separate entries by a cacheline to reduce traffic between EUs writing to
843 #define SHADER_TIME_STRIDE 64
845 struct brw_cache_item
{
847 * Effectively part of the key, cache_id identifies what kind of state
848 * buffer is involved, and also which dirty flag should set.
850 enum brw_cache_id cache_id
;
851 /** 32-bit hash of the key data */
853 GLuint key_size
; /* for variable-sized keys */
860 struct brw_cache_item
*next
;
864 typedef void (*cache_aux_free_func
)(const void *aux
);
867 struct brw_context
*brw
;
869 struct brw_cache_item
**items
;
871 GLuint size
, n_items
;
873 uint32_t next_offset
;
876 /** Optional functions for freeing other pointers attached to a prog_data. */
877 cache_aux_free_func aux_free
[BRW_MAX_CACHE
];
881 /* Considered adding a member to this struct to document which flags
882 * an update might raise so that ordering of the state atoms can be
883 * checked or derived at runtime. Dropped the idea in favor of having
884 * a debug mode where the state is monitored for flags which are
885 * raised that have already been tested against.
887 struct brw_tracked_state
{
888 struct brw_state_flags dirty
;
889 void (*emit
)( struct brw_context
*brw
);
892 enum shader_time_shader_type
{
901 struct brw_vertex_buffer
{
902 /** Buffer object containing the uploaded vertex data */
905 /** Byte stride between elements in the uploaded array */
909 struct brw_vertex_element
{
910 const struct gl_client_array
*glarray
;
914 /** Offset of the first element within the buffer object */
918 struct brw_query_object
{
919 struct gl_query_object Base
;
921 /** Last query BO associated with this query. */
924 /** Last index in bo with query data for this object. */
927 /** True if we know the batch has been flushed since we ended the query. */
937 struct intel_batchbuffer
{
938 /** Current batchbuffer being queued up. */
940 /** Last BO submitted to the hardware. Used for glFinish(). */
941 drm_intel_bo
*last_bo
;
944 uint16_t emit
, total
;
946 uint16_t reserved_space
;
950 #define BATCH_SZ (8192*sizeof(uint32_t))
952 uint32_t state_batch_offset
;
953 enum brw_gpu_ring ring
;
954 bool needs_sol_reset
;
962 #define BRW_MAX_XFB_STREAMS 4
964 struct brw_transform_feedback_object
{
965 struct gl_transform_feedback_object base
;
967 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
968 drm_intel_bo
*offset_bo
;
970 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
973 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
974 GLenum primitive_mode
;
977 * Count of primitives generated during this transform feedback operation.
980 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
981 drm_intel_bo
*prim_count_bo
;
982 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
986 * Number of vertices written between last Begin/EndTransformFeedback().
988 * Used to implement DrawTransformFeedback().
990 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
991 bool vertices_written_valid
;
995 * Data shared between each programmable stage in the pipeline (vs, gs, and
998 struct brw_stage_state
1000 gl_shader_stage stage
;
1001 struct brw_stage_prog_data
*prog_data
;
1004 * Optional scratch buffer used to store spilled register values and
1005 * variably-indexed GRF arrays.
1007 drm_intel_bo
*scratch_bo
;
1009 /** Offset in the program cache to the program */
1010 uint32_t prog_offset
;
1012 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
1013 uint32_t state_offset
;
1015 uint32_t push_const_offset
; /* Offset in the batchbuffer */
1016 int push_const_size
; /* in 256-bit register increments */
1018 /* Binding table: pointers to SURFACE_STATE entries. */
1019 uint32_t bind_bo_offset
;
1020 uint32_t surf_offset
[BRW_MAX_SURFACES
];
1022 /** SAMPLER_STATE count and table offset */
1023 uint32_t sampler_count
;
1024 uint32_t sampler_offset
;
1027 enum brw_predicate_state
{
1028 /* The first two states are used if we can determine whether to draw
1029 * without having to look at the values in the query object buffer. This
1030 * will happen if there is no conditional render in progress, if the query
1031 * object is already completed or if something else has already added
1032 * samples to the preliminary result such as via a BLT command.
1034 BRW_PREDICATE_STATE_RENDER
,
1035 BRW_PREDICATE_STATE_DONT_RENDER
,
1036 /* In this case whether to draw or not depends on the result of an
1037 * MI_PREDICATE command so the predicate enable bit needs to be checked.
1039 BRW_PREDICATE_STATE_USE_BIT
1042 struct shader_times
;
1045 * brw_context is derived from gl_context.
1049 struct gl_context ctx
; /**< base class, must be first field */
1053 void (*update_texture_surface
)(struct gl_context
*ctx
,
1055 uint32_t *surf_offset
,
1057 uint32_t (*update_renderbuffer_surface
)(struct brw_context
*brw
,
1058 struct gl_renderbuffer
*rb
,
1059 bool layered
, unsigned unit
,
1060 uint32_t surf_index
);
1062 void (*emit_texture_surface_state
)(struct brw_context
*brw
,
1063 struct intel_mipmap_tree
*mt
,
1071 uint32_t *surf_offset
,
1072 bool rw
, bool for_gather
);
1073 void (*emit_buffer_surface_state
)(struct brw_context
*brw
,
1074 uint32_t *out_offset
,
1076 unsigned buffer_offset
,
1077 unsigned surface_format
,
1078 unsigned buffer_size
,
1081 void (*emit_null_surface_state
)(struct brw_context
*brw
,
1085 uint32_t *out_offset
);
1088 * Send the appropriate state packets to configure depth, stencil, and
1089 * HiZ buffers (i965+ only)
1091 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
1092 struct intel_mipmap_tree
*depth_mt
,
1093 uint32_t depth_offset
,
1094 uint32_t depthbuffer_format
,
1095 uint32_t depth_surface_type
,
1096 struct intel_mipmap_tree
*stencil_mt
,
1097 bool hiz
, bool separate_stencil
,
1098 uint32_t width
, uint32_t height
,
1099 uint32_t tile_x
, uint32_t tile_y
);
1105 drm_intel_context
*hw_ctx
;
1107 /** BO for post-sync nonzero writes for gen6 workaround. */
1108 drm_intel_bo
*workaround_bo
;
1109 uint8_t pipe_controls_since_last_cs_stall
;
1112 * Set of drm_intel_bo * that have been rendered to within this batchbuffer
1113 * and would need flushing before being used from another cache domain that
1114 * isn't coherent with it (i.e. the sampler).
1116 struct set
*render_cache
;
1119 * Number of resets observed in the system at context creation.
1121 * This is tracked in the context so that we can determine that another
1122 * reset has occurred.
1124 uint32_t reset_count
;
1126 struct intel_batchbuffer batch
;
1131 uint32_t next_offset
;
1135 * Set if rendering has occurred to the drawable's front buffer.
1137 * This is used in the DRI2 case to detect that glFlush should also copy
1138 * the contents of the fake front buffer to the real front buffer.
1140 bool front_buffer_dirty
;
1142 /** Framerate throttling: @{ */
1143 drm_intel_bo
*throttle_batch
[2];
1145 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
1146 * frame of rendering to complete. This gives a very precise cap to the
1147 * latency between input and output such that rendering never gets more
1148 * than a frame behind the user. (With the caveat that we technically are
1149 * not using the SwapBuffers itself as a barrier but the first batch
1150 * submitted afterwards, which may be immediately prior to the next
1153 bool need_swap_throttle
;
1155 /** General throttling, not caught by throttling between SwapBuffers */
1156 bool need_flush_throttle
;
1166 bool always_flush_batch
;
1167 bool always_flush_cache
;
1168 bool disable_throttling
;
1171 driOptionCache optionCache
;
1174 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
1176 GLenum reduced_primitive
;
1179 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
1180 * variable is set, this is the flag indicating to do expensive work that
1181 * might lead to a perf_debug() call.
1185 uint32_t max_gtt_map_object_size
;
1197 bool has_separate_stencil
;
1198 bool must_use_separate_stencil
;
1201 bool has_surface_tile_offset
;
1203 bool has_negative_rhw_bug
;
1207 bool use_resource_streamer
;
1210 * Some versions of Gen hardware don't do centroid interpolation correctly
1211 * on unlit pixels, causing incorrect values for derivatives near triangle
1212 * edges. Enabling this flag causes the fragment shader to use
1213 * non-centroid interpolation for unlit pixels, at the expense of two extra
1214 * fragment shader instructions.
1216 bool needs_unlit_centroid_workaround
;
1220 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
1223 enum brw_pipeline last_pipeline
;
1225 struct brw_cache cache
;
1227 /** IDs for meta stencil blit shader programs. */
1228 unsigned meta_stencil_blit_programs
[2];
1230 /* Whether a meta-operation is in progress. */
1231 bool meta_in_progress
;
1233 /* Whether the last depth/stencil packets were both NULL. */
1234 bool no_depth_or_stencil
;
1236 /* The last PMA stall bits programmed. */
1237 uint32_t pma_stall_bits
;
1240 /** The value of gl_BaseVertex for the current _mesa_prim. */
1244 * Buffer and offset used for GL_ARB_shader_draw_parameters
1245 * (for now, only gl_BaseVertex).
1247 drm_intel_bo
*draw_params_bo
;
1248 uint32_t draw_params_offset
;
1253 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
1254 * an indirect call, and num_work_groups_offset is valid. Otherwise,
1255 * num_work_groups is set based on glDispatchCompute.
1257 drm_intel_bo
*num_work_groups_bo
;
1258 GLintptr num_work_groups_offset
;
1259 const GLuint
*num_work_groups
;
1263 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
1264 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
1266 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
1270 /* Summary of size and varying of active arrays, so we can check
1271 * for changes to this state:
1273 unsigned int min_index
, max_index
;
1275 /* Offset from start of vertex buffer so we can avoid redefining
1276 * the same VB packed over and over again.
1278 unsigned int start_vertex_bias
;
1281 * Certain vertex attribute formats aren't natively handled by the
1282 * hardware and require special VS code to fix up their values.
1284 * These bitfields indicate which workarounds are needed.
1286 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
1291 * Index buffer for this draw_prims call.
1293 * Updates are signaled by BRW_NEW_INDICES.
1295 const struct _mesa_index_buffer
*ib
;
1297 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
1301 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
1302 * avoid re-uploading the IB packet over and over if we're actually
1303 * referencing the same index buffer.
1305 unsigned int start_vertex_offset
;
1308 /* Active vertex program:
1310 const struct gl_vertex_program
*vertex_program
;
1311 const struct gl_geometry_program
*geometry_program
;
1312 const struct gl_fragment_program
*fragment_program
;
1313 const struct gl_compute_program
*compute_program
;
1316 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
1317 * that we don't have to reemit that state every time we change FBOs.
1322 * Platform specific constants containing the maximum number of threads
1323 * for each pipeline stage.
1325 unsigned max_vs_threads
;
1326 unsigned max_hs_threads
;
1327 unsigned max_ds_threads
;
1328 unsigned max_gs_threads
;
1329 unsigned max_wm_threads
;
1330 unsigned max_cs_threads
;
1332 /* BRW_NEW_URB_ALLOCATIONS:
1335 GLuint vsize
; /* vertex size plus header in urb registers */
1336 GLuint gsize
; /* GS output size in urb registers */
1337 GLuint csize
; /* constant buffer size in urb registers */
1338 GLuint sfsize
; /* setup data size in urb registers */
1342 GLuint min_vs_entries
; /* Minimum number of VS entries */
1343 GLuint max_vs_entries
; /* Maximum number of VS entries */
1344 GLuint max_hs_entries
; /* Maximum number of HS entries */
1345 GLuint max_ds_entries
; /* Maximum number of DS entries */
1346 GLuint max_gs_entries
; /* Maximum number of GS entries */
1348 GLuint nr_vs_entries
;
1349 GLuint nr_gs_entries
;
1350 GLuint nr_clip_entries
;
1351 GLuint nr_sf_entries
;
1352 GLuint nr_cs_entries
;
1359 GLuint size
; /* Hardware URB size, in KB. */
1361 /* True if the most recently sent _3DSTATE_URB message allocated
1362 * URB space for the GS.
1368 /* BRW_NEW_CURBE_OFFSETS:
1371 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
1372 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
1380 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
1381 * for upload to the CURBE.
1383 drm_intel_bo
*curbe_bo
;
1384 /** Offset within curbe_bo of space for current curbe entry */
1385 GLuint curbe_offset
;
1389 * Layout of vertex data exiting the geometry portion of the pipleine.
1390 * This comes from the last enabled shader stage (GS, DS, or VS).
1392 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
1394 struct brw_vue_map vue_map_geom_out
;
1397 struct brw_stage_state base
;
1398 struct brw_vs_prog_data
*prog_data
;
1402 struct brw_stage_state base
;
1403 struct brw_gs_prog_data
*prog_data
;
1406 * True if the 3DSTATE_GS command most recently emitted to the 3D
1407 * pipeline enabled the GS; false otherwise.
1413 struct brw_ff_gs_prog_data
*prog_data
;
1416 /** Offset in the program cache to the CLIP program pre-gen6 */
1417 uint32_t prog_offset
;
1418 uint32_t state_offset
;
1420 uint32_t bind_bo_offset
;
1422 * Surface offsets for the binding table. We only need surfaces to
1423 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1424 * need in this case.
1426 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1430 struct brw_clip_prog_data
*prog_data
;
1432 /** Offset in the program cache to the CLIP program pre-gen6 */
1433 uint32_t prog_offset
;
1435 /* Offset in the batch to the CLIP state on pre-gen6. */
1436 uint32_t state_offset
;
1438 /* As of gen6, this is the offset in the batch to the CLIP VP,
1446 struct brw_sf_prog_data
*prog_data
;
1448 /** Offset in the program cache to the CLIP program pre-gen6 */
1449 uint32_t prog_offset
;
1450 uint32_t state_offset
;
1452 bool viewport_transform_enable
;
1456 struct brw_stage_state base
;
1457 struct brw_wm_prog_data
*prog_data
;
1462 * Buffer object used in place of multisampled null render targets on
1463 * Gen6. See brw_emit_null_surface_state().
1465 drm_intel_bo
*multisampled_null_render_target_bo
;
1466 uint32_t fast_clear_op
;
1472 struct brw_stage_state base
;
1473 struct brw_cs_prog_data
*prog_data
;
1476 /* RS hardware binding table */
1479 uint32_t next_offset
;
1483 uint32_t state_offset
;
1484 uint32_t blend_state_offset
;
1485 uint32_t depth_stencil_state_offset
;
1490 struct brw_query_object
*obj
;
1495 enum brw_predicate_state state
;
1500 /** A map from pipeline statistics counter IDs to MMIO addresses. */
1501 const int *statistics_registers
;
1503 /** The number of active monitors using OA counters. */
1507 * A buffer object storing OA counter snapshots taken at the start and
1508 * end of each batch (creating "bookends" around the batch).
1510 drm_intel_bo
*bookend_bo
;
1512 /** The number of snapshots written to bookend_bo. */
1513 int bookend_snapshots
;
1516 * An array of monitors whose results haven't yet been assembled based on
1517 * the data in buffer objects.
1519 * These may be active, or have already ended. However, the results
1520 * have not been requested.
1522 struct brw_perf_monitor_object
**unresolved
;
1523 int unresolved_elements
;
1524 int unresolved_array_size
;
1527 * Mapping from a uint32_t offset within an OA snapshot to the ID of
1528 * the counter which MI_REPORT_PERF_COUNT stores there.
1530 const int *oa_snapshot_layout
;
1532 /** Number of 32-bit entries in a hardware counter snapshot. */
1533 int entries_per_oa_snapshot
;
1536 int num_atoms
[BRW_NUM_PIPELINES
];
1537 const struct brw_tracked_state render_atoms
[60];
1538 const struct brw_tracked_state compute_atoms
[8];
1540 /* If (INTEL_DEBUG & DEBUG_BATCH) */
1544 enum aub_state_struct_type type
;
1546 } *state_batch_list
;
1547 int state_batch_count
;
1549 uint32_t render_target_format
[MESA_FORMAT_COUNT
];
1550 bool format_supported_as_render_target
[MESA_FORMAT_COUNT
];
1552 /* Interpolation modes, one byte per vue slot.
1553 * Used Gen4/5 by the clip|sf|wm stages. Ignored on Gen6+.
1555 struct interpolation_mode_map interpolation_mode
;
1557 /* PrimitiveRestart */
1560 bool enable_cut_index
;
1563 /** Computed depth/stencil/hiz state from the current attached
1564 * renderbuffers, valid only during the drawing state upload loop after
1565 * brw_workaround_depthstencil_alignment().
1568 struct intel_mipmap_tree
*depth_mt
;
1569 struct intel_mipmap_tree
*stencil_mt
;
1571 /* Inter-tile (page-aligned) byte offsets. */
1572 uint32_t depth_offset
, hiz_offset
, stencil_offset
;
1573 /* Intra-tile x,y offsets for drawing to depth/stencil/hiz */
1574 uint32_t tile_x
, tile_y
;
1577 uint32_t num_instances
;
1584 enum shader_time_shader_type
*types
;
1585 struct shader_times
*cumulative
;
1591 struct brw_fast_clear_state
*fast_clear_state
;
1593 __DRIcontext
*driContext
;
1594 struct intel_screen
*intelScreen
;
1597 /*======================================================================
1600 void brwInitVtbl( struct brw_context
*brw
);
1603 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1605 /*======================================================================
1608 extern const char *const brw_vendor_string
;
1610 extern const char *brw_get_renderer_string(unsigned deviceID
);
1613 DRI_CONF_BO_REUSE_DISABLED
,
1614 DRI_CONF_BO_REUSE_ALL
1617 void intel_update_renderbuffers(__DRIcontext
*context
,
1618 __DRIdrawable
*drawable
);
1619 void intel_prepare_render(struct brw_context
*brw
);
1621 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1622 __DRIdrawable
*drawable
);
1624 GLboolean
brwCreateContext(gl_api api
,
1625 const struct gl_config
*mesaVis
,
1626 __DRIcontext
*driContextPriv
,
1627 unsigned major_version
,
1628 unsigned minor_version
,
1632 void *sharedContextPrivate
);
1634 /*======================================================================
1637 GLuint
brw_get_rb_for_slice(struct brw_context
*brw
,
1638 struct intel_mipmap_tree
*mt
,
1639 unsigned level
, unsigned layer
, bool flat
);
1641 void brw_meta_updownsample(struct brw_context
*brw
,
1642 struct intel_mipmap_tree
*src
,
1643 struct intel_mipmap_tree
*dst
);
1645 void brw_meta_fbo_stencil_blit(struct brw_context
*brw
,
1646 struct gl_framebuffer
*read_fb
,
1647 struct gl_framebuffer
*draw_fb
,
1648 GLfloat srcX0
, GLfloat srcY0
,
1649 GLfloat srcX1
, GLfloat srcY1
,
1650 GLfloat dstX0
, GLfloat dstY0
,
1651 GLfloat dstX1
, GLfloat dstY1
);
1653 void brw_meta_stencil_updownsample(struct brw_context
*brw
,
1654 struct intel_mipmap_tree
*src
,
1655 struct intel_mipmap_tree
*dst
);
1657 bool brw_meta_fast_clear(struct brw_context
*brw
,
1658 struct gl_framebuffer
*fb
,
1660 bool partial_clear
);
1663 brw_meta_resolve_color(struct brw_context
*brw
,
1664 struct intel_mipmap_tree
*mt
);
1666 brw_meta_fast_clear_free(struct brw_context
*brw
);
1669 /*======================================================================
1672 void brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
1673 uint32_t depth_level
,
1674 uint32_t depth_layer
,
1675 struct intel_mipmap_tree
*stencil_mt
,
1676 uint32_t *out_tile_mask_x
,
1677 uint32_t *out_tile_mask_y
);
1678 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1679 GLbitfield clear_mask
);
1681 /* brw_object_purgeable.c */
1682 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1684 /*======================================================================
1687 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1688 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1689 void brw_emit_query_begin(struct brw_context
*brw
);
1690 void brw_emit_query_end(struct brw_context
*brw
);
1692 /** gen6_queryobj.c */
1693 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1694 void brw_write_timestamp(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1695 void brw_write_depth_count(struct brw_context
*brw
, drm_intel_bo
*bo
, int idx
);
1696 void brw_store_register_mem64(struct brw_context
*brw
,
1697 drm_intel_bo
*bo
, uint32_t reg
, int idx
);
1699 /** brw_conditional_render.c */
1700 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1701 bool brw_check_conditional_render(struct brw_context
*brw
);
1703 /** intel_batchbuffer.c */
1704 void brw_load_register_mem(struct brw_context
*brw
,
1707 uint32_t read_domains
, uint32_t write_domain
,
1709 void brw_load_register_mem64(struct brw_context
*brw
,
1712 uint32_t read_domains
, uint32_t write_domain
,
1715 /*======================================================================
1718 void brw_debug_batch(struct brw_context
*brw
);
1719 void brw_annotate_aub(struct brw_context
*brw
);
1721 /*======================================================================
1724 void brw_validate_textures( struct brw_context
*brw
);
1727 /*======================================================================
1730 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1732 /* Per-thread scratch space is a power-of-two multiple of 1KB. */
1734 brw_get_scratch_size(int size
)
1736 return util_next_power_of_two(size
| 1023);
1738 void brw_get_scratch_bo(struct brw_context
*brw
,
1739 drm_intel_bo
**scratch_bo
, int size
);
1740 void brw_init_shader_time(struct brw_context
*brw
);
1741 int brw_get_shader_time_index(struct brw_context
*brw
,
1742 struct gl_shader_program
*shader_prog
,
1743 struct gl_program
*prog
,
1744 enum shader_time_shader_type type
);
1745 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1746 void brw_destroy_shader_time(struct brw_context
*brw
);
1750 void brw_upload_urb_fence(struct brw_context
*brw
);
1754 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1756 /* brw_fs_reg_allocate.cpp
1758 void brw_fs_alloc_reg_sets(struct brw_compiler
*compiler
);
1760 /* brw_vec4_reg_allocate.cpp */
1761 void brw_vec4_alloc_reg_set(struct brw_compiler
*compiler
);
1764 int brw_disassemble_inst(FILE *file
, const struct brw_device_info
*devinfo
,
1765 struct brw_inst
*inst
, bool is_compacted
);
1768 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1770 /* brw_draw_upload.c */
1771 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1772 const struct gl_client_array
*glarray
);
1774 static inline unsigned
1775 brw_get_index_type(GLenum type
)
1777 assert((type
== GL_UNSIGNED_BYTE
)
1778 || (type
== GL_UNSIGNED_SHORT
)
1779 || (type
== GL_UNSIGNED_INT
));
1781 /* The possible values for type are GL_UNSIGNED_BYTE (0x1401),
1782 * GL_UNSIGNED_SHORT (0x1403), and GL_UNSIGNED_INT (0x1405) which we want
1783 * to map to scale factors of 0, 1, and 2, respectively. These scale
1784 * factors are then left-shfited by 8 to be in the correct position in the
1785 * CMD_INDEX_BUFFER packet.
1787 * Subtracting 0x1401 gives 0, 2, and 4. Shifting left by 7 afterwards
1788 * gives 0x00000000, 0x00000100, and 0x00000200. These just happen to be
1789 * the values the need to be written in the CMD_INDEX_BUFFER packet.
1791 return (type
- 0x1401) << 7;
1794 void brw_prepare_vertices(struct brw_context
*brw
);
1796 /* brw_wm_surface_state.c */
1797 void brw_init_surface_formats(struct brw_context
*brw
);
1798 void brw_create_constant_surface(struct brw_context
*brw
,
1802 uint32_t *out_offset
,
1804 void brw_create_buffer_surface(struct brw_context
*brw
,
1808 uint32_t *out_offset
,
1810 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1812 uint32_t *surf_offset
);
1814 brw_update_sol_surface(struct brw_context
*brw
,
1815 struct gl_buffer_object
*buffer_obj
,
1816 uint32_t *out_offset
, unsigned num_vector_components
,
1817 unsigned stride_dwords
, unsigned offset_dwords
);
1818 void brw_upload_ubo_surfaces(struct brw_context
*brw
,
1819 struct gl_shader
*shader
,
1820 struct brw_stage_state
*stage_state
,
1821 struct brw_stage_prog_data
*prog_data
,
1823 void brw_upload_abo_surfaces(struct brw_context
*brw
,
1824 struct gl_shader_program
*prog
,
1825 struct brw_stage_state
*stage_state
,
1826 struct brw_stage_prog_data
*prog_data
);
1827 void brw_upload_image_surfaces(struct brw_context
*brw
,
1828 struct gl_shader
*shader
,
1829 struct brw_stage_state
*stage_state
,
1830 struct brw_stage_prog_data
*prog_data
);
1832 /* brw_surface_formats.c */
1833 bool brw_render_target_supported(struct brw_context
*brw
,
1834 struct gl_renderbuffer
*rb
);
1835 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1836 mesa_format
brw_lower_mesa_image_format(const struct brw_device_info
*devinfo
,
1837 mesa_format format
);
1839 /* brw_performance_monitor.c */
1840 void brw_init_performance_monitors(struct brw_context
*brw
);
1841 void brw_dump_perf_monitors(struct brw_context
*brw
);
1842 void brw_perf_monitor_new_batch(struct brw_context
*brw
);
1843 void brw_perf_monitor_finish_batch(struct brw_context
*brw
);
1845 /* intel_buffer_objects.c */
1846 int brw_bo_map(struct brw_context
*brw
, drm_intel_bo
*bo
, int write_enable
,
1847 const char *bo_name
);
1848 int brw_bo_map_gtt(struct brw_context
*brw
, drm_intel_bo
*bo
,
1849 const char *bo_name
);
1851 /* intel_extensions.c */
1852 extern void intelInitExtensions(struct gl_context
*ctx
);
1855 extern int intel_translate_shadow_compare_func(GLenum func
);
1856 extern int intel_translate_compare_func(GLenum func
);
1857 extern int intel_translate_stencil_op(GLenum op
);
1858 extern int intel_translate_logic_op(GLenum opcode
);
1860 /* intel_syncobj.c */
1861 void intel_init_syncobj_functions(struct dd_function_table
*functions
);
1864 struct gl_transform_feedback_object
*
1865 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1867 brw_delete_transform_feedback(struct gl_context
*ctx
,
1868 struct gl_transform_feedback_object
*obj
);
1870 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1871 struct gl_transform_feedback_object
*obj
);
1873 brw_end_transform_feedback(struct gl_context
*ctx
,
1874 struct gl_transform_feedback_object
*obj
);
1876 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1877 struct gl_transform_feedback_object
*obj
,
1880 /* gen7_sol_state.c */
1882 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1883 struct gl_transform_feedback_object
*obj
);
1885 gen7_end_transform_feedback(struct gl_context
*ctx
,
1886 struct gl_transform_feedback_object
*obj
);
1888 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1889 struct gl_transform_feedback_object
*obj
);
1891 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1892 struct gl_transform_feedback_object
*obj
);
1894 /* brw_blorp_blit.cpp */
1896 brw_blorp_framebuffer(struct brw_context
*brw
,
1897 struct gl_framebuffer
*readFb
,
1898 struct gl_framebuffer
*drawFb
,
1899 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1900 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1901 GLbitfield mask
, GLenum filter
);
1904 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1905 struct gl_renderbuffer
*src_rb
,
1906 struct gl_texture_image
*dst_image
,
1908 int srcX0
, int srcY0
,
1909 int dstX0
, int dstY0
,
1910 int width
, int height
);
1912 /* gen6_multisample_state.c */
1914 gen6_determine_sample_mask(struct brw_context
*brw
);
1917 gen6_emit_3dstate_multisample(struct brw_context
*brw
,
1918 unsigned num_samples
);
1920 gen6_emit_3dstate_sample_mask(struct brw_context
*brw
, unsigned mask
);
1922 gen6_get_sample_position(struct gl_context
*ctx
,
1923 struct gl_framebuffer
*fb
,
1927 gen6_set_sample_maps(struct gl_context
*ctx
);
1929 /* gen8_multisample_state.c */
1930 void gen8_emit_3dstate_multisample(struct brw_context
*brw
, unsigned num_samp
);
1931 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1935 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1936 unsigned gs_size
, unsigned fs_size
);
1939 gen7_emit_urb_state(struct brw_context
*brw
,
1940 unsigned nr_vs_entries
, unsigned vs_size
,
1941 unsigned vs_start
, unsigned nr_gs_entries
,
1942 unsigned gs_size
, unsigned gs_start
);
1947 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1951 brw_init_compute_functions(struct dd_function_table
*functions
);
1953 /*======================================================================
1954 * Inline conversion functions. These are better-typed than the
1955 * macros used previously:
1957 static inline struct brw_context
*
1958 brw_context( struct gl_context
*ctx
)
1960 return (struct brw_context
*)ctx
;
1963 static inline struct brw_vertex_program
*
1964 brw_vertex_program(struct gl_vertex_program
*p
)
1966 return (struct brw_vertex_program
*) p
;
1969 static inline const struct brw_vertex_program
*
1970 brw_vertex_program_const(const struct gl_vertex_program
*p
)
1972 return (const struct brw_vertex_program
*) p
;
1975 static inline struct brw_geometry_program
*
1976 brw_geometry_program(struct gl_geometry_program
*p
)
1978 return (struct brw_geometry_program
*) p
;
1981 static inline struct brw_fragment_program
*
1982 brw_fragment_program(struct gl_fragment_program
*p
)
1984 return (struct brw_fragment_program
*) p
;
1987 static inline const struct brw_fragment_program
*
1988 brw_fragment_program_const(const struct gl_fragment_program
*p
)
1990 return (const struct brw_fragment_program
*) p
;
1993 static inline struct brw_compute_program
*
1994 brw_compute_program(struct gl_compute_program
*p
)
1996 return (struct brw_compute_program
*) p
;
2000 * Pre-gen6, the register file of the EUs was shared between threads,
2001 * and each thread used some subset allocated on a 16-register block
2002 * granularity. The unit states wanted these block counts.
2005 brw_register_blocks(int reg_count
)
2007 return ALIGN(reg_count
, 16) / 16 - 1;
2010 static inline uint32_t
2011 brw_program_reloc(struct brw_context
*brw
, uint32_t state_offset
,
2012 uint32_t prog_offset
)
2014 if (brw
->gen
>= 5) {
2015 /* Using state base address. */
2019 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
2023 I915_GEM_DOMAIN_INSTRUCTION
, 0);
2025 return brw
->cache
.bo
->offset64
+ prog_offset
;
2028 bool brw_do_cubemap_normalize(struct exec_list
*instructions
);
2029 bool brw_lower_texture_gradients(struct brw_context
*brw
,
2030 struct exec_list
*instructions
);
2031 bool brw_do_lower_unnormalized_offset(struct exec_list
*instructions
);
2033 struct opcode_desc
{
2039 extern const struct opcode_desc opcode_descs
[128];
2040 extern const char * const conditional_modifier
[16];
2043 brw_emit_depthbuffer(struct brw_context
*brw
);
2046 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
2047 struct intel_mipmap_tree
*depth_mt
,
2048 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2049 uint32_t depth_surface_type
,
2050 struct intel_mipmap_tree
*stencil_mt
,
2051 bool hiz
, bool separate_stencil
,
2052 uint32_t width
, uint32_t height
,
2053 uint32_t tile_x
, uint32_t tile_y
);
2056 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
2057 struct intel_mipmap_tree
*depth_mt
,
2058 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2059 uint32_t depth_surface_type
,
2060 struct intel_mipmap_tree
*stencil_mt
,
2061 bool hiz
, bool separate_stencil
,
2062 uint32_t width
, uint32_t height
,
2063 uint32_t tile_x
, uint32_t tile_y
);
2066 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
2067 struct intel_mipmap_tree
*depth_mt
,
2068 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2069 uint32_t depth_surface_type
,
2070 struct intel_mipmap_tree
*stencil_mt
,
2071 bool hiz
, bool separate_stencil
,
2072 uint32_t width
, uint32_t height
,
2073 uint32_t tile_x
, uint32_t tile_y
);
2075 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
2076 struct intel_mipmap_tree
*depth_mt
,
2077 uint32_t depth_offset
, uint32_t depthbuffer_format
,
2078 uint32_t depth_surface_type
,
2079 struct intel_mipmap_tree
*stencil_mt
,
2080 bool hiz
, bool separate_stencil
,
2081 uint32_t width
, uint32_t height
,
2082 uint32_t tile_x
, uint32_t tile_y
);
2084 void gen8_hiz_exec(struct brw_context
*brw
, struct intel_mipmap_tree
*mt
,
2085 unsigned int level
, unsigned int layer
, enum gen6_hiz_op op
);
2087 uint32_t get_hw_prim_for_gl_prim(int mode
);
2090 gen6_upload_push_constants(struct brw_context
*brw
,
2091 const struct gl_program
*prog
,
2092 const struct brw_stage_prog_data
*prog_data
,
2093 struct brw_stage_state
*stage_state
,
2094 enum aub_state_struct_type type
);
2097 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
2098 const struct intel_mipmap_tree
*mt
);
2100 /* brw_pipe_control.c */
2101 int brw_init_pipe_control(struct brw_context
*brw
,
2102 const struct brw_device_info
*info
);
2103 void brw_fini_pipe_control(struct brw_context
*brw
);
2105 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
2106 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
2107 drm_intel_bo
*bo
, uint32_t offset
,
2108 uint32_t imm_lower
, uint32_t imm_upper
);
2109 void brw_emit_mi_flush(struct brw_context
*brw
);
2110 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
2111 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
2112 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
2113 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);