2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 * Push constant handling for gen4/5.
36 * Push constants are constant values (such as GLSL uniforms) that are
37 * pre-loaded into a shader stage's register space at thread spawn time. On
38 * gen4 and gen5, we create a blob in memory containing all the push constants
39 * for all the stages in order. At CMD_CONST_BUFFER time that blob is loaded
40 * into URB space as a constant URB entry (CURBE) so that it can be accessed
41 * quickly at thread setup time. Each individual fixed function unit's state
42 * (brw_vs_state.c for example) tells the hardware which subset of the CURBE
43 * it wants in its register space, and we calculate those areas here under the
44 * BRW_NEW_CURBE_OFFSETS state flag. The brw_urb.c allocation will control
45 * how many CURBEs can be loaded into the hardware at once before a pipeline
46 * stall occurs at CMD_CONST_BUFFER time.
48 * On gen6+, constant handling becomes a much simpler set of per-unit state.
49 * See gen6_upload_vec4_push_constants() in gen6_vs_state.c for that code.
53 #include "main/glheader.h"
54 #include "main/context.h"
55 #include "main/macros.h"
56 #include "main/enums.h"
57 #include "program/prog_parameter.h"
58 #include "program/prog_print.h"
59 #include "program/prog_statevars.h"
60 #include "intel_batchbuffer.h"
61 #include "intel_buffer_objects.h"
62 #include "brw_context.h"
63 #include "brw_defines.h"
64 #include "brw_state.h"
69 * Partition the CURBE between the various users of constant values.
71 * If the users all fit within the previous allocatation, we avoid changing
72 * the layout because that means reuploading all unit state and uploading new
75 static void calculate_curbe_offsets( struct brw_context
*brw
)
77 struct gl_context
*ctx
= &brw
->ctx
;
78 /* CACHE_NEW_WM_PROG */
79 const GLuint nr_fp_regs
= (brw
->wm
.prog_data
->base
.nr_params
+ 15) / 16;
81 /* CACHE_NEW_VS_PROG */
82 const GLuint nr_vp_regs
= (brw
->vs
.prog_data
->base
.base
.nr_params
+ 15) / 16;
83 GLuint nr_clip_regs
= 0;
87 if (ctx
->Transform
.ClipPlanesEnabled
) {
88 GLuint nr_planes
= 6 + _mesa_bitcount_64(ctx
->Transform
.ClipPlanesEnabled
);
89 nr_clip_regs
= (nr_planes
* 4 + 15) / 16;
93 total_regs
= nr_fp_regs
+ nr_vp_regs
+ nr_clip_regs
;
95 /* The CURBE allocation size is limited to 32 512-bit units (128 EU
96 * registers, or 1024 floats). See CS_URB_STATE in the gen4 or gen5
97 * (volume 1, part 1) PRMs.
99 * Note that in brw_fs.cpp we're only loading up to 16 EU registers of
100 * values as push constants before spilling to pull constants, and in
101 * brw_vec4.cpp we're loading up to 32 registers of push constants. An EU
102 * register is 1/2 of one of these URB entry units, so that leaves us 16 EU
105 assert(total_regs
<= 32);
109 if (nr_fp_regs
> brw
->curbe
.wm_size
||
110 nr_vp_regs
> brw
->curbe
.vs_size
||
111 nr_clip_regs
!= brw
->curbe
.clip_size
||
112 (total_regs
< brw
->curbe
.total_size
/ 4 &&
113 brw
->curbe
.total_size
> 16)) {
117 /* Calculate a new layout:
120 brw
->curbe
.wm_start
= reg
;
121 brw
->curbe
.wm_size
= nr_fp_regs
; reg
+= nr_fp_regs
;
122 brw
->curbe
.clip_start
= reg
;
123 brw
->curbe
.clip_size
= nr_clip_regs
; reg
+= nr_clip_regs
;
124 brw
->curbe
.vs_start
= reg
;
125 brw
->curbe
.vs_size
= nr_vp_regs
; reg
+= nr_vp_regs
;
126 brw
->curbe
.total_size
= reg
;
129 fprintf(stderr
, "curbe wm %d+%d clip %d+%d vs %d+%d\n",
132 brw
->curbe
.clip_start
,
133 brw
->curbe
.clip_size
,
135 brw
->curbe
.vs_size
);
137 brw
->state
.dirty
.brw
|= BRW_NEW_CURBE_OFFSETS
;
142 const struct brw_tracked_state brw_curbe_offsets
= {
144 .mesa
= _NEW_TRANSFORM
,
145 .brw
= BRW_NEW_CONTEXT
,
146 .cache
= CACHE_NEW_VS_PROG
| CACHE_NEW_WM_PROG
148 .emit
= calculate_curbe_offsets
154 /** Uploads the CS_URB_STATE packet.
156 * Just like brw_vs_state.c and brw_wm_state.c define a URB entry size and
157 * number of entries for their stages, constant buffers do so using this state
158 * packet. Having multiple CURBEs in the URB at the same time allows the
159 * hardware to avoid a pipeline stall between primitives using different
160 * constant buffer contents.
162 void brw_upload_cs_urb_state(struct brw_context
*brw
)
165 OUT_BATCH(CMD_CS_URB_STATE
<< 16 | (2-2));
167 /* BRW_NEW_URB_FENCE */
168 if (brw
->urb
.csize
== 0) {
171 /* BRW_NEW_URB_FENCE */
172 assert(brw
->urb
.nr_cs_entries
);
173 OUT_BATCH((brw
->urb
.csize
- 1) << 4 | brw
->urb
.nr_cs_entries
);
178 static GLfloat fixed_plane
[6][4] = {
188 * Gathers together all the uniform values into a block of memory to be
189 * uploaded into the CURBE, then emits the state packet telling the hardware
193 brw_upload_constant_buffer(struct brw_context
*brw
)
195 struct gl_context
*ctx
= &brw
->ctx
;
196 /* BRW_NEW_CURBE_OFFSETS */
197 const GLuint sz
= brw
->curbe
.total_size
;
198 const GLuint bufsz
= sz
* 16 * sizeof(GLfloat
);
199 gl_constant_value
*buf
;
201 gl_clip_plane
*clip_planes
;
207 buf
= intel_upload_space(brw
, bufsz
, 64,
208 &brw
->curbe
.curbe_bo
, &brw
->curbe
.curbe_offset
);
210 STATIC_ASSERT(sizeof(gl_constant_value
) == sizeof(float));
212 /* fragment shader constants */
213 if (brw
->curbe
.wm_size
) {
214 /* BRW_NEW_CURBE_OFFSETS */
215 GLuint offset
= brw
->curbe
.wm_start
* 16;
217 /* CACHE_NEW_WM_PROG | _NEW_PROGRAM_CONSTANTS: copy uniform values */
218 for (i
= 0; i
< brw
->wm
.prog_data
->base
.nr_params
; i
++) {
219 buf
[offset
+ i
] = *brw
->wm
.prog_data
->base
.param
[i
];
223 /* clipper constants */
224 if (brw
->curbe
.clip_size
) {
225 GLuint offset
= brw
->curbe
.clip_start
* 16;
228 /* If any planes are going this way, send them all this way:
230 for (i
= 0; i
< 6; i
++) {
231 buf
[offset
+ i
* 4 + 0].f
= fixed_plane
[i
][0];
232 buf
[offset
+ i
* 4 + 1].f
= fixed_plane
[i
][1];
233 buf
[offset
+ i
* 4 + 2].f
= fixed_plane
[i
][2];
234 buf
[offset
+ i
* 4 + 3].f
= fixed_plane
[i
][3];
237 /* Clip planes: _NEW_TRANSFORM plus _NEW_PROJECTION to get to
240 clip_planes
= brw_select_clip_planes(ctx
);
241 for (j
= 0; j
< MAX_CLIP_PLANES
; j
++) {
242 if (ctx
->Transform
.ClipPlanesEnabled
& (1<<j
)) {
243 buf
[offset
+ i
* 4 + 0].f
= clip_planes
[j
][0];
244 buf
[offset
+ i
* 4 + 1].f
= clip_planes
[j
][1];
245 buf
[offset
+ i
* 4 + 2].f
= clip_planes
[j
][2];
246 buf
[offset
+ i
* 4 + 3].f
= clip_planes
[j
][3];
252 /* vertex shader constants */
253 if (brw
->curbe
.vs_size
) {
254 GLuint offset
= brw
->curbe
.vs_start
* 16;
256 /* CACHE_NEW_VS_PROG | _NEW_PROGRAM_CONSTANTS: copy uniform values */
257 for (i
= 0; i
< brw
->vs
.prog_data
->base
.base
.nr_params
; i
++) {
258 buf
[offset
+ i
] = *brw
->vs
.prog_data
->base
.base
.param
[i
];
263 for (i
= 0; i
< sz
*16; i
+=4)
264 fprintf(stderr
, "curbe %d.%d: %f %f %f %f\n", i
/8, i
&4,
265 buf
[i
+0].f
, buf
[i
+1].f
, buf
[i
+2].f
, buf
[i
+3].f
);
268 /* Because this provokes an action (ie copy the constants into the
269 * URB), it shouldn't be shortcircuited if identical to the
270 * previous time - because eg. the urb destination may have
271 * changed, or the urb contents different to last time.
273 * Note that the data referred to is actually copied internally,
274 * not just used in place according to passed pointer.
276 * It appears that the CS unit takes care of using each available
277 * URB entry (Const URB Entry == CURBE) in turn, and issuing
278 * flushes as necessary when doublebuffering of CURBEs isn't
283 /* BRW_NEW_URB_FENCE: From the gen4 PRM, volume 1, section 3.9.8
284 * (CONSTANT_BUFFER (CURBE Load)):
286 * "Modifying the CS URB allocation via URB_FENCE invalidates any
287 * previous CURBE entries. Therefore software must subsequently
288 * [re]issue a CONSTANT_BUFFER command before CURBE data can be used
292 if (brw
->curbe
.total_size
== 0) {
293 OUT_BATCH((CMD_CONST_BUFFER
<< 16) | (2 - 2));
296 OUT_BATCH((CMD_CONST_BUFFER
<< 16) | (1 << 8) | (2 - 2));
297 OUT_RELOC(brw
->curbe
.curbe_bo
,
298 I915_GEM_DOMAIN_INSTRUCTION
, 0,
299 (brw
->curbe
.total_size
- 1) + brw
->curbe
.curbe_offset
);
304 const struct brw_tracked_state brw_constant_buffer
= {
306 .mesa
= _NEW_PROGRAM_CONSTANTS
,
307 .brw
= (BRW_NEW_URB_FENCE
|
308 BRW_NEW_PSP
| /* Implicit - hardware requires this, not used above */
309 BRW_NEW_CURBE_OFFSETS
|
311 .cache
= (CACHE_NEW_VS_PROG
|
314 .emit
= brw_upload_constant_buffer
,