2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
32 #define INTEL_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low))
33 /* Using the GNU statement expression extension */
34 #define SET_FIELD(value, field) \
36 uint32_t fieldval = (value) << field ## _SHIFT; \
37 assert((fieldval & ~ field ## _MASK) == 0); \
38 fieldval & field ## _MASK; \
41 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
48 #define CMD_3D_PRIM 0x7b00 /* 3DPRIMITIVE */
50 # define GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT 10
51 # define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 15)
52 # define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM (1 << 15)
53 # define GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE (1 << 10)
55 # define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 8)
56 # define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM (1 << 8)
58 #define _3DPRIM_POINTLIST 0x01
59 #define _3DPRIM_LINELIST 0x02
60 #define _3DPRIM_LINESTRIP 0x03
61 #define _3DPRIM_TRILIST 0x04
62 #define _3DPRIM_TRISTRIP 0x05
63 #define _3DPRIM_TRIFAN 0x06
64 #define _3DPRIM_QUADLIST 0x07
65 #define _3DPRIM_QUADSTRIP 0x08
66 #define _3DPRIM_LINELIST_ADJ 0x09
67 #define _3DPRIM_LINESTRIP_ADJ 0x0A
68 #define _3DPRIM_TRILIST_ADJ 0x0B
69 #define _3DPRIM_TRISTRIP_ADJ 0x0C
70 #define _3DPRIM_TRISTRIP_REVERSE 0x0D
71 #define _3DPRIM_POLYGON 0x0E
72 #define _3DPRIM_RECTLIST 0x0F
73 #define _3DPRIM_LINELOOP 0x10
74 #define _3DPRIM_POINTLIST_BF 0x11
75 #define _3DPRIM_LINESTRIP_CONT 0x12
76 #define _3DPRIM_LINESTRIP_BF 0x13
77 #define _3DPRIM_LINESTRIP_CONT_BF 0x14
78 #define _3DPRIM_TRIFAN_NOSTIPPLE 0x15
80 #define BRW_ANISORATIO_2 0
81 #define BRW_ANISORATIO_4 1
82 #define BRW_ANISORATIO_6 2
83 #define BRW_ANISORATIO_8 3
84 #define BRW_ANISORATIO_10 4
85 #define BRW_ANISORATIO_12 5
86 #define BRW_ANISORATIO_14 6
87 #define BRW_ANISORATIO_16 7
89 #define BRW_BLENDFACTOR_ONE 0x1
90 #define BRW_BLENDFACTOR_SRC_COLOR 0x2
91 #define BRW_BLENDFACTOR_SRC_ALPHA 0x3
92 #define BRW_BLENDFACTOR_DST_ALPHA 0x4
93 #define BRW_BLENDFACTOR_DST_COLOR 0x5
94 #define BRW_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6
95 #define BRW_BLENDFACTOR_CONST_COLOR 0x7
96 #define BRW_BLENDFACTOR_CONST_ALPHA 0x8
97 #define BRW_BLENDFACTOR_SRC1_COLOR 0x9
98 #define BRW_BLENDFACTOR_SRC1_ALPHA 0x0A
99 #define BRW_BLENDFACTOR_ZERO 0x11
100 #define BRW_BLENDFACTOR_INV_SRC_COLOR 0x12
101 #define BRW_BLENDFACTOR_INV_SRC_ALPHA 0x13
102 #define BRW_BLENDFACTOR_INV_DST_ALPHA 0x14
103 #define BRW_BLENDFACTOR_INV_DST_COLOR 0x15
104 #define BRW_BLENDFACTOR_INV_CONST_COLOR 0x17
105 #define BRW_BLENDFACTOR_INV_CONST_ALPHA 0x18
106 #define BRW_BLENDFACTOR_INV_SRC1_COLOR 0x19
107 #define BRW_BLENDFACTOR_INV_SRC1_ALPHA 0x1A
109 #define BRW_BLENDFUNCTION_ADD 0
110 #define BRW_BLENDFUNCTION_SUBTRACT 1
111 #define BRW_BLENDFUNCTION_REVERSE_SUBTRACT 2
112 #define BRW_BLENDFUNCTION_MIN 3
113 #define BRW_BLENDFUNCTION_MAX 4
115 #define BRW_ALPHATEST_FORMAT_UNORM8 0
116 #define BRW_ALPHATEST_FORMAT_FLOAT32 1
118 #define BRW_CHROMAKEY_KILL_ON_ANY_MATCH 0
119 #define BRW_CHROMAKEY_REPLACE_BLACK 1
121 #define BRW_CLIP_API_OGL 0
122 #define BRW_CLIP_API_DX 1
124 #define BRW_CLIPMODE_NORMAL 0
125 #define BRW_CLIPMODE_CLIP_ALL 1
126 #define BRW_CLIPMODE_CLIP_NON_REJECTED 2
127 #define BRW_CLIPMODE_REJECT_ALL 3
128 #define BRW_CLIPMODE_ACCEPT_ALL 4
129 #define BRW_CLIPMODE_KERNEL_CLIP 5
131 #define BRW_CLIP_NDCSPACE 0
132 #define BRW_CLIP_SCREENSPACE 1
134 #define BRW_COMPAREFUNCTION_ALWAYS 0
135 #define BRW_COMPAREFUNCTION_NEVER 1
136 #define BRW_COMPAREFUNCTION_LESS 2
137 #define BRW_COMPAREFUNCTION_EQUAL 3
138 #define BRW_COMPAREFUNCTION_LEQUAL 4
139 #define BRW_COMPAREFUNCTION_GREATER 5
140 #define BRW_COMPAREFUNCTION_NOTEQUAL 6
141 #define BRW_COMPAREFUNCTION_GEQUAL 7
143 #define BRW_COVERAGE_PIXELS_HALF 0
144 #define BRW_COVERAGE_PIXELS_1 1
145 #define BRW_COVERAGE_PIXELS_2 2
146 #define BRW_COVERAGE_PIXELS_4 3
148 #define BRW_CULLMODE_BOTH 0
149 #define BRW_CULLMODE_NONE 1
150 #define BRW_CULLMODE_FRONT 2
151 #define BRW_CULLMODE_BACK 3
153 #define BRW_DEFAULTCOLOR_R8G8B8A8_UNORM 0
154 #define BRW_DEFAULTCOLOR_R32G32B32A32_FLOAT 1
156 #define BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0
157 #define BRW_DEPTHFORMAT_D32_FLOAT 1
158 #define BRW_DEPTHFORMAT_D24_UNORM_S8_UINT 2
159 #define BRW_DEPTHFORMAT_D24_UNORM_X8_UINT 3 /* GEN5 */
160 #define BRW_DEPTHFORMAT_D16_UNORM 5
162 #define BRW_FLOATING_POINT_IEEE_754 0
163 #define BRW_FLOATING_POINT_NON_IEEE_754 1
165 #define BRW_FRONTWINDING_CW 0
166 #define BRW_FRONTWINDING_CCW 1
168 #define BRW_SPRITE_POINT_ENABLE 16
170 #define BRW_CUT_INDEX_ENABLE (1 << 10)
172 #define BRW_INDEX_BYTE 0
173 #define BRW_INDEX_WORD 1
174 #define BRW_INDEX_DWORD 2
176 #define BRW_LOGICOPFUNCTION_CLEAR 0
177 #define BRW_LOGICOPFUNCTION_NOR 1
178 #define BRW_LOGICOPFUNCTION_AND_INVERTED 2
179 #define BRW_LOGICOPFUNCTION_COPY_INVERTED 3
180 #define BRW_LOGICOPFUNCTION_AND_REVERSE 4
181 #define BRW_LOGICOPFUNCTION_INVERT 5
182 #define BRW_LOGICOPFUNCTION_XOR 6
183 #define BRW_LOGICOPFUNCTION_NAND 7
184 #define BRW_LOGICOPFUNCTION_AND 8
185 #define BRW_LOGICOPFUNCTION_EQUIV 9
186 #define BRW_LOGICOPFUNCTION_NOOP 10
187 #define BRW_LOGICOPFUNCTION_OR_INVERTED 11
188 #define BRW_LOGICOPFUNCTION_COPY 12
189 #define BRW_LOGICOPFUNCTION_OR_REVERSE 13
190 #define BRW_LOGICOPFUNCTION_OR 14
191 #define BRW_LOGICOPFUNCTION_SET 15
193 #define BRW_MAPFILTER_NEAREST 0x0
194 #define BRW_MAPFILTER_LINEAR 0x1
195 #define BRW_MAPFILTER_ANISOTROPIC 0x2
197 #define BRW_MIPFILTER_NONE 0
198 #define BRW_MIPFILTER_NEAREST 1
199 #define BRW_MIPFILTER_LINEAR 3
201 #define BRW_ADDRESS_ROUNDING_ENABLE_U_MAG 0x20
202 #define BRW_ADDRESS_ROUNDING_ENABLE_U_MIN 0x10
203 #define BRW_ADDRESS_ROUNDING_ENABLE_V_MAG 0x08
204 #define BRW_ADDRESS_ROUNDING_ENABLE_V_MIN 0x04
205 #define BRW_ADDRESS_ROUNDING_ENABLE_R_MAG 0x02
206 #define BRW_ADDRESS_ROUNDING_ENABLE_R_MIN 0x01
208 #define BRW_POLYGON_FRONT_FACING 0
209 #define BRW_POLYGON_BACK_FACING 1
211 #define BRW_PREFILTER_ALWAYS 0x0
212 #define BRW_PREFILTER_NEVER 0x1
213 #define BRW_PREFILTER_LESS 0x2
214 #define BRW_PREFILTER_EQUAL 0x3
215 #define BRW_PREFILTER_LEQUAL 0x4
216 #define BRW_PREFILTER_GREATER 0x5
217 #define BRW_PREFILTER_NOTEQUAL 0x6
218 #define BRW_PREFILTER_GEQUAL 0x7
220 #define BRW_PROVOKING_VERTEX_0 0
221 #define BRW_PROVOKING_VERTEX_1 1
222 #define BRW_PROVOKING_VERTEX_2 2
224 #define BRW_RASTRULE_UPPER_LEFT 0
225 #define BRW_RASTRULE_UPPER_RIGHT 1
226 /* These are listed as "Reserved, but not seen as useful"
227 * in Intel documentation (page 212, "Point Rasterization Rule",
228 * section 7.4 "SF Pipeline State Summary", of document
229 * "Intel® 965 Express Chipset Family and Intel® G35 Express
230 * Chipset Graphics Controller Programmer's Reference Manual,
231 * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
233 * http://intellinuxgraphics.org/documentation.html
234 * at the time of this writing).
236 * These appear to be supported on at least some
237 * i965-family devices, and the BRW_RASTRULE_LOWER_RIGHT
238 * is useful when using OpenGL to render to a FBO
239 * (which has the pixel coordinate Y orientation inverted
240 * with respect to the normal OpenGL pixel coordinate system).
242 #define BRW_RASTRULE_LOWER_LEFT 2
243 #define BRW_RASTRULE_LOWER_RIGHT 3
245 #define BRW_RENDERTARGET_CLAMPRANGE_UNORM 0
246 #define BRW_RENDERTARGET_CLAMPRANGE_SNORM 1
247 #define BRW_RENDERTARGET_CLAMPRANGE_FORMAT 2
249 #define BRW_STENCILOP_KEEP 0
250 #define BRW_STENCILOP_ZERO 1
251 #define BRW_STENCILOP_REPLACE 2
252 #define BRW_STENCILOP_INCRSAT 3
253 #define BRW_STENCILOP_DECRSAT 4
254 #define BRW_STENCILOP_INCR 5
255 #define BRW_STENCILOP_DECR 6
256 #define BRW_STENCILOP_INVERT 7
258 /* Surface state DW0 */
259 #define GEN8_SURFACE_IS_ARRAY (1 << 28)
260 #define GEN8_SURFACE_VALIGN_4 (1 << 16)
261 #define GEN8_SURFACE_VALIGN_8 (2 << 16)
262 #define GEN8_SURFACE_VALIGN_16 (3 << 16)
263 #define GEN8_SURFACE_HALIGN_4 (1 << 14)
264 #define GEN8_SURFACE_HALIGN_8 (2 << 14)
265 #define GEN8_SURFACE_HALIGN_16 (3 << 14)
266 #define GEN8_SURFACE_TILING_NONE (0 << 12)
267 #define GEN8_SURFACE_TILING_W (1 << 12)
268 #define GEN8_SURFACE_TILING_X (2 << 12)
269 #define GEN8_SURFACE_TILING_Y (3 << 12)
270 #define BRW_SURFACE_RC_READ_WRITE (1 << 8)
271 #define BRW_SURFACE_MIPLAYOUT_SHIFT 10
272 #define BRW_SURFACE_MIPMAPLAYOUT_BELOW 0
273 #define BRW_SURFACE_MIPMAPLAYOUT_RIGHT 1
274 #define BRW_SURFACE_CUBEFACE_ENABLES 0x3f
275 #define BRW_SURFACE_BLEND_ENABLED (1 << 13)
276 #define BRW_SURFACE_WRITEDISABLE_B_SHIFT 14
277 #define BRW_SURFACE_WRITEDISABLE_G_SHIFT 15
278 #define BRW_SURFACE_WRITEDISABLE_R_SHIFT 16
279 #define BRW_SURFACE_WRITEDISABLE_A_SHIFT 17
281 #define BRW_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000
282 #define BRW_SURFACEFORMAT_R32G32B32A32_SINT 0x001
283 #define BRW_SURFACEFORMAT_R32G32B32A32_UINT 0x002
284 #define BRW_SURFACEFORMAT_R32G32B32A32_UNORM 0x003
285 #define BRW_SURFACEFORMAT_R32G32B32A32_SNORM 0x004
286 #define BRW_SURFACEFORMAT_R64G64_FLOAT 0x005
287 #define BRW_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006
288 #define BRW_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007
289 #define BRW_SURFACEFORMAT_R32G32B32A32_USCALED 0x008
290 #define BRW_SURFACEFORMAT_R32G32B32A32_SFIXED 0x020
291 #define BRW_SURFACEFORMAT_R64G64_PASSTHRU 0x021
292 #define BRW_SURFACEFORMAT_R32G32B32_FLOAT 0x040
293 #define BRW_SURFACEFORMAT_R32G32B32_SINT 0x041
294 #define BRW_SURFACEFORMAT_R32G32B32_UINT 0x042
295 #define BRW_SURFACEFORMAT_R32G32B32_UNORM 0x043
296 #define BRW_SURFACEFORMAT_R32G32B32_SNORM 0x044
297 #define BRW_SURFACEFORMAT_R32G32B32_SSCALED 0x045
298 #define BRW_SURFACEFORMAT_R32G32B32_USCALED 0x046
299 #define BRW_SURFACEFORMAT_R32G32B32_SFIXED 0x050
300 #define BRW_SURFACEFORMAT_R16G16B16A16_UNORM 0x080
301 #define BRW_SURFACEFORMAT_R16G16B16A16_SNORM 0x081
302 #define BRW_SURFACEFORMAT_R16G16B16A16_SINT 0x082
303 #define BRW_SURFACEFORMAT_R16G16B16A16_UINT 0x083
304 #define BRW_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084
305 #define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085
306 #define BRW_SURFACEFORMAT_R32G32_SINT 0x086
307 #define BRW_SURFACEFORMAT_R32G32_UINT 0x087
308 #define BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088
309 #define BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089
310 #define BRW_SURFACEFORMAT_L32A32_FLOAT 0x08A
311 #define BRW_SURFACEFORMAT_R32G32_UNORM 0x08B
312 #define BRW_SURFACEFORMAT_R32G32_SNORM 0x08C
313 #define BRW_SURFACEFORMAT_R64_FLOAT 0x08D
314 #define BRW_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E
315 #define BRW_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F
316 #define BRW_SURFACEFORMAT_A32X32_FLOAT 0x090
317 #define BRW_SURFACEFORMAT_L32X32_FLOAT 0x091
318 #define BRW_SURFACEFORMAT_I32X32_FLOAT 0x092
319 #define BRW_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093
320 #define BRW_SURFACEFORMAT_R16G16B16A16_USCALED 0x094
321 #define BRW_SURFACEFORMAT_R32G32_SSCALED 0x095
322 #define BRW_SURFACEFORMAT_R32G32_USCALED 0x096
323 #define BRW_SURFACEFORMAT_R32G32_FLOAT_LD 0x097
324 #define BRW_SURFACEFORMAT_R32G32_SFIXED 0x0A0
325 #define BRW_SURFACEFORMAT_R64_PASSTHRU 0x0A1
326 #define BRW_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0
327 #define BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1
328 #define BRW_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2
329 #define BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3
330 #define BRW_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4
331 #define BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5
332 #define BRW_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7
333 #define BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8
334 #define BRW_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9
335 #define BRW_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA
336 #define BRW_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB
337 #define BRW_SURFACEFORMAT_R16G16_UNORM 0x0CC
338 #define BRW_SURFACEFORMAT_R16G16_SNORM 0x0CD
339 #define BRW_SURFACEFORMAT_R16G16_SINT 0x0CE
340 #define BRW_SURFACEFORMAT_R16G16_UINT 0x0CF
341 #define BRW_SURFACEFORMAT_R16G16_FLOAT 0x0D0
342 #define BRW_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1
343 #define BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2
344 #define BRW_SURFACEFORMAT_R11G11B10_FLOAT 0x0D3
345 #define BRW_SURFACEFORMAT_R32_SINT 0x0D6
346 #define BRW_SURFACEFORMAT_R32_UINT 0x0D7
347 #define BRW_SURFACEFORMAT_R32_FLOAT 0x0D8
348 #define BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9
349 #define BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA
350 #define BRW_SURFACEFORMAT_L16A16_UNORM 0x0DF
351 #define BRW_SURFACEFORMAT_I24X8_UNORM 0x0E0
352 #define BRW_SURFACEFORMAT_L24X8_UNORM 0x0E1
353 #define BRW_SURFACEFORMAT_A24X8_UNORM 0x0E2
354 #define BRW_SURFACEFORMAT_I32_FLOAT 0x0E3
355 #define BRW_SURFACEFORMAT_L32_FLOAT 0x0E4
356 #define BRW_SURFACEFORMAT_A32_FLOAT 0x0E5
357 #define BRW_SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9
358 #define BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA
359 #define BRW_SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB
360 #define BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC
361 #define BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED
362 #define BRW_SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE
363 #define BRW_SURFACEFORMAT_L16A16_FLOAT 0x0F0
364 #define BRW_SURFACEFORMAT_R32_UNORM 0x0F1
365 #define BRW_SURFACEFORMAT_R32_SNORM 0x0F2
366 #define BRW_SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3
367 #define BRW_SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4
368 #define BRW_SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5
369 #define BRW_SURFACEFORMAT_R16G16_SSCALED 0x0F6
370 #define BRW_SURFACEFORMAT_R16G16_USCALED 0x0F7
371 #define BRW_SURFACEFORMAT_R32_SSCALED 0x0F8
372 #define BRW_SURFACEFORMAT_R32_USCALED 0x0F9
373 #define BRW_SURFACEFORMAT_B5G6R5_UNORM 0x100
374 #define BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101
375 #define BRW_SURFACEFORMAT_B5G5R5A1_UNORM 0x102
376 #define BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103
377 #define BRW_SURFACEFORMAT_B4G4R4A4_UNORM 0x104
378 #define BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105
379 #define BRW_SURFACEFORMAT_R8G8_UNORM 0x106
380 #define BRW_SURFACEFORMAT_R8G8_SNORM 0x107
381 #define BRW_SURFACEFORMAT_R8G8_SINT 0x108
382 #define BRW_SURFACEFORMAT_R8G8_UINT 0x109
383 #define BRW_SURFACEFORMAT_R16_UNORM 0x10A
384 #define BRW_SURFACEFORMAT_R16_SNORM 0x10B
385 #define BRW_SURFACEFORMAT_R16_SINT 0x10C
386 #define BRW_SURFACEFORMAT_R16_UINT 0x10D
387 #define BRW_SURFACEFORMAT_R16_FLOAT 0x10E
388 #define BRW_SURFACEFORMAT_A8P8_UNORM_PALETTE0 0x10F
389 #define BRW_SURFACEFORMAT_A8P8_UNORM_PALETTE1 0x110
390 #define BRW_SURFACEFORMAT_I16_UNORM 0x111
391 #define BRW_SURFACEFORMAT_L16_UNORM 0x112
392 #define BRW_SURFACEFORMAT_A16_UNORM 0x113
393 #define BRW_SURFACEFORMAT_L8A8_UNORM 0x114
394 #define BRW_SURFACEFORMAT_I16_FLOAT 0x115
395 #define BRW_SURFACEFORMAT_L16_FLOAT 0x116
396 #define BRW_SURFACEFORMAT_A16_FLOAT 0x117
397 #define BRW_SURFACEFORMAT_L8A8_UNORM_SRGB 0x118
398 #define BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119
399 #define BRW_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A
400 #define BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B
401 #define BRW_SURFACEFORMAT_R8G8_SSCALED 0x11C
402 #define BRW_SURFACEFORMAT_R8G8_USCALED 0x11D
403 #define BRW_SURFACEFORMAT_R16_SSCALED 0x11E
404 #define BRW_SURFACEFORMAT_R16_USCALED 0x11F
405 #define BRW_SURFACEFORMAT_P8A8_UNORM_PALETTE0 0x122
406 #define BRW_SURFACEFORMAT_P8A8_UNORM_PALETTE1 0x123
407 #define BRW_SURFACEFORMAT_A1B5G5R5_UNORM 0x124
408 #define BRW_SURFACEFORMAT_A4B4G4R4_UNORM 0x125
409 #define BRW_SURFACEFORMAT_L8A8_UINT 0x126
410 #define BRW_SURFACEFORMAT_L8A8_SINT 0x127
411 #define BRW_SURFACEFORMAT_R8_UNORM 0x140
412 #define BRW_SURFACEFORMAT_R8_SNORM 0x141
413 #define BRW_SURFACEFORMAT_R8_SINT 0x142
414 #define BRW_SURFACEFORMAT_R8_UINT 0x143
415 #define BRW_SURFACEFORMAT_A8_UNORM 0x144
416 #define BRW_SURFACEFORMAT_I8_UNORM 0x145
417 #define BRW_SURFACEFORMAT_L8_UNORM 0x146
418 #define BRW_SURFACEFORMAT_P4A4_UNORM 0x147
419 #define BRW_SURFACEFORMAT_A4P4_UNORM 0x148
420 #define BRW_SURFACEFORMAT_R8_SSCALED 0x149
421 #define BRW_SURFACEFORMAT_R8_USCALED 0x14A
422 #define BRW_SURFACEFORMAT_P8_UNORM_PALETTE0 0x14B
423 #define BRW_SURFACEFORMAT_L8_UNORM_SRGB 0x14C
424 #define BRW_SURFACEFORMAT_P8_UNORM_PALETTE1 0x14D
425 #define BRW_SURFACEFORMAT_P4A4_UNORM_PALETTE1 0x14E
426 #define BRW_SURFACEFORMAT_A4P4_UNORM_PALETTE1 0x14F
427 #define BRW_SURFACEFORMAT_Y8_SNORM 0x150
428 #define BRW_SURFACEFORMAT_L8_UINT 0x152
429 #define BRW_SURFACEFORMAT_L8_SINT 0x153
430 #define BRW_SURFACEFORMAT_I8_UINT 0x154
431 #define BRW_SURFACEFORMAT_I8_SINT 0x155
432 #define BRW_SURFACEFORMAT_DXT1_RGB_SRGB 0x180
433 #define BRW_SURFACEFORMAT_R1_UINT 0x181
434 #define BRW_SURFACEFORMAT_YCRCB_NORMAL 0x182
435 #define BRW_SURFACEFORMAT_YCRCB_SWAPUVY 0x183
436 #define BRW_SURFACEFORMAT_P2_UNORM_PALETTE0 0x184
437 #define BRW_SURFACEFORMAT_P2_UNORM_PALETTE1 0x185
438 #define BRW_SURFACEFORMAT_BC1_UNORM 0x186
439 #define BRW_SURFACEFORMAT_BC2_UNORM 0x187
440 #define BRW_SURFACEFORMAT_BC3_UNORM 0x188
441 #define BRW_SURFACEFORMAT_BC4_UNORM 0x189
442 #define BRW_SURFACEFORMAT_BC5_UNORM 0x18A
443 #define BRW_SURFACEFORMAT_BC1_UNORM_SRGB 0x18B
444 #define BRW_SURFACEFORMAT_BC2_UNORM_SRGB 0x18C
445 #define BRW_SURFACEFORMAT_BC3_UNORM_SRGB 0x18D
446 #define BRW_SURFACEFORMAT_MONO8 0x18E
447 #define BRW_SURFACEFORMAT_YCRCB_SWAPUV 0x18F
448 #define BRW_SURFACEFORMAT_YCRCB_SWAPY 0x190
449 #define BRW_SURFACEFORMAT_DXT1_RGB 0x191
450 #define BRW_SURFACEFORMAT_FXT1 0x192
451 #define BRW_SURFACEFORMAT_R8G8B8_UNORM 0x193
452 #define BRW_SURFACEFORMAT_R8G8B8_SNORM 0x194
453 #define BRW_SURFACEFORMAT_R8G8B8_SSCALED 0x195
454 #define BRW_SURFACEFORMAT_R8G8B8_USCALED 0x196
455 #define BRW_SURFACEFORMAT_R64G64B64A64_FLOAT 0x197
456 #define BRW_SURFACEFORMAT_R64G64B64_FLOAT 0x198
457 #define BRW_SURFACEFORMAT_BC4_SNORM 0x199
458 #define BRW_SURFACEFORMAT_BC5_SNORM 0x19A
459 #define BRW_SURFACEFORMAT_R16G16B16_FLOAT 0x19B
460 #define BRW_SURFACEFORMAT_R16G16B16_UNORM 0x19C
461 #define BRW_SURFACEFORMAT_R16G16B16_SNORM 0x19D
462 #define BRW_SURFACEFORMAT_R16G16B16_SSCALED 0x19E
463 #define BRW_SURFACEFORMAT_R16G16B16_USCALED 0x19F
464 #define BRW_SURFACEFORMAT_BC6H_SF16 0x1A1
465 #define BRW_SURFACEFORMAT_BC7_UNORM 0x1A2
466 #define BRW_SURFACEFORMAT_BC7_UNORM_SRGB 0x1A3
467 #define BRW_SURFACEFORMAT_BC6H_UF16 0x1A4
468 #define BRW_SURFACEFORMAT_PLANAR_420_8 0x1A5
469 #define BRW_SURFACEFORMAT_R8G8B8_UNORM_SRGB 0x1A8
470 #define BRW_SURFACEFORMAT_ETC1_RGB8 0x1A9
471 #define BRW_SURFACEFORMAT_ETC2_RGB8 0x1AA
472 #define BRW_SURFACEFORMAT_EAC_R11 0x1AB
473 #define BRW_SURFACEFORMAT_EAC_RG11 0x1AC
474 #define BRW_SURFACEFORMAT_EAC_SIGNED_R11 0x1AD
475 #define BRW_SURFACEFORMAT_EAC_SIGNED_RG11 0x1AE
476 #define BRW_SURFACEFORMAT_ETC2_SRGB8 0x1AF
477 #define BRW_SURFACEFORMAT_R16G16B16_UINT 0x1B0
478 #define BRW_SURFACEFORMAT_R16G16B16_SINT 0x1B1
479 #define BRW_SURFACEFORMAT_R32_SFIXED 0x1B2
480 #define BRW_SURFACEFORMAT_R10G10B10A2_SNORM 0x1B3
481 #define BRW_SURFACEFORMAT_R10G10B10A2_USCALED 0x1B4
482 #define BRW_SURFACEFORMAT_R10G10B10A2_SSCALED 0x1B5
483 #define BRW_SURFACEFORMAT_R10G10B10A2_SINT 0x1B6
484 #define BRW_SURFACEFORMAT_B10G10R10A2_SNORM 0x1B7
485 #define BRW_SURFACEFORMAT_B10G10R10A2_USCALED 0x1B8
486 #define BRW_SURFACEFORMAT_B10G10R10A2_SSCALED 0x1B9
487 #define BRW_SURFACEFORMAT_B10G10R10A2_UINT 0x1BA
488 #define BRW_SURFACEFORMAT_B10G10R10A2_SINT 0x1BB
489 #define BRW_SURFACEFORMAT_R64G64B64A64_PASSTHRU 0x1BC
490 #define BRW_SURFACEFORMAT_R64G64B64_PASSTHRU 0x1BD
491 #define BRW_SURFACEFORMAT_ETC2_RGB8_PTA 0x1C0
492 #define BRW_SURFACEFORMAT_ETC2_SRGB8_PTA 0x1C1
493 #define BRW_SURFACEFORMAT_ETC2_EAC_RGBA8 0x1C2
494 #define BRW_SURFACEFORMAT_ETC2_EAC_SRGB8_A8 0x1C3
495 #define BRW_SURFACEFORMAT_R8G8B8_UINT 0x1C8
496 #define BRW_SURFACEFORMAT_R8G8B8_SINT 0x1C9
497 #define BRW_SURFACEFORMAT_RAW 0x1FF
498 #define BRW_SURFACE_FORMAT_SHIFT 18
499 #define BRW_SURFACE_FORMAT_MASK INTEL_MASK(26, 18)
501 #define BRW_SURFACERETURNFORMAT_FLOAT32 0
502 #define BRW_SURFACERETURNFORMAT_S1 1
504 #define BRW_SURFACE_TYPE_SHIFT 29
505 #define BRW_SURFACE_TYPE_MASK INTEL_MASK(31, 29)
506 #define BRW_SURFACE_1D 0
507 #define BRW_SURFACE_2D 1
508 #define BRW_SURFACE_3D 2
509 #define BRW_SURFACE_CUBE 3
510 #define BRW_SURFACE_BUFFER 4
511 #define BRW_SURFACE_NULL 7
513 #define GEN7_SURFACE_IS_ARRAY (1 << 28)
514 #define GEN7_SURFACE_VALIGN_2 (0 << 16)
515 #define GEN7_SURFACE_VALIGN_4 (1 << 16)
516 #define GEN7_SURFACE_HALIGN_4 (0 << 15)
517 #define GEN7_SURFACE_HALIGN_8 (1 << 15)
518 #define GEN7_SURFACE_TILING_NONE (0 << 13)
519 #define GEN7_SURFACE_TILING_X (2 << 13)
520 #define GEN7_SURFACE_TILING_Y (3 << 13)
521 #define GEN7_SURFACE_ARYSPC_FULL (0 << 10)
522 #define GEN7_SURFACE_ARYSPC_LOD0 (1 << 10)
524 /* Surface state DW2 */
525 #define BRW_SURFACE_HEIGHT_SHIFT 19
526 #define BRW_SURFACE_HEIGHT_MASK INTEL_MASK(31, 19)
527 #define BRW_SURFACE_WIDTH_SHIFT 6
528 #define BRW_SURFACE_WIDTH_MASK INTEL_MASK(18, 6)
529 #define BRW_SURFACE_LOD_SHIFT 2
530 #define BRW_SURFACE_LOD_MASK INTEL_MASK(5, 2)
531 #define GEN7_SURFACE_HEIGHT_SHIFT 16
532 #define GEN7_SURFACE_HEIGHT_MASK INTEL_MASK(29, 16)
533 #define GEN7_SURFACE_WIDTH_SHIFT 0
534 #define GEN7_SURFACE_WIDTH_MASK INTEL_MASK(13, 0)
536 /* Surface state DW3 */
537 #define BRW_SURFACE_DEPTH_SHIFT 21
538 #define BRW_SURFACE_DEPTH_MASK INTEL_MASK(31, 21)
539 #define BRW_SURFACE_PITCH_SHIFT 3
540 #define BRW_SURFACE_PITCH_MASK INTEL_MASK(19, 3)
541 #define BRW_SURFACE_TILED (1 << 1)
542 #define BRW_SURFACE_TILED_Y (1 << 0)
544 /* Surface state DW4 */
545 #define BRW_SURFACE_MIN_LOD_SHIFT 28
546 #define BRW_SURFACE_MIN_LOD_MASK INTEL_MASK(31, 28)
547 #define BRW_SURFACE_MULTISAMPLECOUNT_1 (0 << 4)
548 #define BRW_SURFACE_MULTISAMPLECOUNT_4 (2 << 4)
549 #define GEN7_SURFACE_MULTISAMPLECOUNT_1 (0 << 3)
550 #define GEN8_SURFACE_MULTISAMPLECOUNT_2 (1 << 3)
551 #define GEN7_SURFACE_MULTISAMPLECOUNT_4 (2 << 3)
552 #define GEN7_SURFACE_MULTISAMPLECOUNT_8 (3 << 3)
553 #define GEN8_SURFACE_MULTISAMPLECOUNT_16 (4 << 3)
554 #define GEN7_SURFACE_MSFMT_MSS (0 << 6)
555 #define GEN7_SURFACE_MSFMT_DEPTH_STENCIL (1 << 6)
556 #define GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT 18
557 #define GEN7_SURFACE_MIN_ARRAY_ELEMENT_MASK INTEL_MASK(28, 18)
558 #define GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT 7
559 #define GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_MASK INTEL_MASK(17, 7)
561 /* Surface state DW5 */
562 #define BRW_SURFACE_X_OFFSET_SHIFT 25
563 #define BRW_SURFACE_X_OFFSET_MASK INTEL_MASK(31, 25)
564 #define BRW_SURFACE_VERTICAL_ALIGN_ENABLE (1 << 24)
565 #define BRW_SURFACE_Y_OFFSET_SHIFT 20
566 #define BRW_SURFACE_Y_OFFSET_MASK INTEL_MASK(23, 20)
567 #define GEN7_SURFACE_MIN_LOD_SHIFT 4
568 #define GEN7_SURFACE_MIN_LOD_MASK INTEL_MASK(7, 4)
569 #define GEN8_SURFACE_Y_OFFSET_SHIFT 21
570 #define GEN8_SURFACE_Y_OFFSET_MASK INTEL_MASK(23, 21)
572 #define GEN7_SURFACE_MOCS_SHIFT 16
573 #define GEN7_SURFACE_MOCS_MASK INTEL_MASK(19, 16)
575 /* Surface state DW6 */
576 #define GEN7_SURFACE_MCS_ENABLE (1 << 0)
577 #define GEN7_SURFACE_MCS_PITCH_SHIFT 3
578 #define GEN7_SURFACE_MCS_PITCH_MASK INTEL_MASK(11, 3)
580 /* Surface state DW7 */
581 #define GEN7_SURFACE_CLEAR_COLOR_SHIFT 28
582 #define GEN7_SURFACE_SCS_R_SHIFT 25
583 #define GEN7_SURFACE_SCS_R_MASK INTEL_MASK(27, 25)
584 #define GEN7_SURFACE_SCS_G_SHIFT 22
585 #define GEN7_SURFACE_SCS_G_MASK INTEL_MASK(24, 22)
586 #define GEN7_SURFACE_SCS_B_SHIFT 19
587 #define GEN7_SURFACE_SCS_B_MASK INTEL_MASK(21, 19)
588 #define GEN7_SURFACE_SCS_A_SHIFT 16
589 #define GEN7_SURFACE_SCS_A_MASK INTEL_MASK(18, 16)
591 /* The actual swizzle values/what channel to use */
592 #define HSW_SCS_ZERO 0
593 #define HSW_SCS_ONE 1
594 #define HSW_SCS_RED 4
595 #define HSW_SCS_GREEN 5
596 #define HSW_SCS_BLUE 6
597 #define HSW_SCS_ALPHA 7
599 #define BRW_TEXCOORDMODE_WRAP 0
600 #define BRW_TEXCOORDMODE_MIRROR 1
601 #define BRW_TEXCOORDMODE_CLAMP 2
602 #define BRW_TEXCOORDMODE_CUBE 3
603 #define BRW_TEXCOORDMODE_CLAMP_BORDER 4
604 #define BRW_TEXCOORDMODE_MIRROR_ONCE 5
606 #define BRW_THREAD_PRIORITY_NORMAL 0
607 #define BRW_THREAD_PRIORITY_HIGH 1
609 #define BRW_TILEWALK_XMAJOR 0
610 #define BRW_TILEWALK_YMAJOR 1
612 #define BRW_VERTEX_SUBPIXEL_PRECISION_8BITS 0
613 #define BRW_VERTEX_SUBPIXEL_PRECISION_4BITS 1
615 /* Execution Unit (EU) defines
618 #define BRW_ALIGN_1 0
619 #define BRW_ALIGN_16 1
621 #define BRW_ADDRESS_DIRECT 0
622 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1
624 #define BRW_CHANNEL_X 0
625 #define BRW_CHANNEL_Y 1
626 #define BRW_CHANNEL_Z 2
627 #define BRW_CHANNEL_W 3
629 enum brw_compression
{
630 BRW_COMPRESSION_NONE
= 0,
631 BRW_COMPRESSION_2NDHALF
= 1,
632 BRW_COMPRESSION_COMPRESSED
= 2,
635 #define GEN6_COMPRESSION_1Q 0
636 #define GEN6_COMPRESSION_2Q 1
637 #define GEN6_COMPRESSION_3Q 2
638 #define GEN6_COMPRESSION_4Q 3
639 #define GEN6_COMPRESSION_1H 0
640 #define GEN6_COMPRESSION_2H 2
642 #define BRW_CONDITIONAL_NONE 0
643 #define BRW_CONDITIONAL_Z 1
644 #define BRW_CONDITIONAL_NZ 2
645 #define BRW_CONDITIONAL_EQ 1 /* Z */
646 #define BRW_CONDITIONAL_NEQ 2 /* NZ */
647 #define BRW_CONDITIONAL_G 3
648 #define BRW_CONDITIONAL_GE 4
649 #define BRW_CONDITIONAL_L 5
650 #define BRW_CONDITIONAL_LE 6
651 #define BRW_CONDITIONAL_R 7
652 #define BRW_CONDITIONAL_O 8
653 #define BRW_CONDITIONAL_U 9
655 #define BRW_DEBUG_NONE 0
656 #define BRW_DEBUG_BREAKPOINT 1
658 #define BRW_DEPENDENCY_NORMAL 0
659 #define BRW_DEPENDENCY_NOTCLEARED 1
660 #define BRW_DEPENDENCY_NOTCHECKED 2
661 #define BRW_DEPENDENCY_DISABLE 3
663 #define BRW_EXECUTE_1 0
664 #define BRW_EXECUTE_2 1
665 #define BRW_EXECUTE_4 2
666 #define BRW_EXECUTE_8 3
667 #define BRW_EXECUTE_16 4
668 #define BRW_EXECUTE_32 5
670 #define BRW_HORIZONTAL_STRIDE_0 0
671 #define BRW_HORIZONTAL_STRIDE_1 1
672 #define BRW_HORIZONTAL_STRIDE_2 2
673 #define BRW_HORIZONTAL_STRIDE_4 3
675 #define BRW_INSTRUCTION_NORMAL 0
676 #define BRW_INSTRUCTION_SATURATE 1
678 #define BRW_MASK_ENABLE 0
679 #define BRW_MASK_DISABLE 1
683 * Gen6 has replaced "mask enable/disable" with WECtrl, which is
684 * effectively the same but much simpler to think about. Now, there
685 * are two contributors ANDed together to whether channels are
686 * executed: The predication on the instruction, and the channel write
690 * This is the default value. It means that a channel's write enable is set
691 * if the per-channel IP is pointing at this instruction.
693 #define BRW_WE_NORMAL 0
695 * This is used like BRW_MASK_DISABLE, and causes all channels to have
696 * their write enable set. Note that predication still contributes to
697 * whether the channel actually gets written.
703 /* These are the actual hardware opcodes. */
714 BRW_OPCODE_CMPN
= 17,
715 BRW_OPCODE_F32TO16
= 19,
716 BRW_OPCODE_F16TO32
= 20,
717 BRW_OPCODE_BFREV
= 23,
719 BRW_OPCODE_BFI1
= 25,
720 BRW_OPCODE_BFI2
= 26,
721 BRW_OPCODE_JMPI
= 32,
724 BRW_OPCODE_ELSE
= 36,
725 BRW_OPCODE_ENDIF
= 37,
727 BRW_OPCODE_WHILE
= 39,
728 BRW_OPCODE_BREAK
= 40,
729 BRW_OPCODE_CONTINUE
= 41,
730 BRW_OPCODE_HALT
= 42,
731 BRW_OPCODE_MSAVE
= 44,
732 BRW_OPCODE_MRESTORE
= 45,
733 BRW_OPCODE_PUSH
= 46,
735 BRW_OPCODE_WAIT
= 48,
736 BRW_OPCODE_SEND
= 49,
737 BRW_OPCODE_SENDC
= 50,
738 BRW_OPCODE_MATH
= 56,
743 BRW_OPCODE_RNDU
= 68,
744 BRW_OPCODE_RNDD
= 69,
745 BRW_OPCODE_RNDE
= 70,
746 BRW_OPCODE_RNDZ
= 71,
748 BRW_OPCODE_MACH
= 73,
752 BRW_OPCODE_CBIT
= 77,
753 BRW_OPCODE_ADDC
= 78,
754 BRW_OPCODE_SUBB
= 79,
755 BRW_OPCODE_SAD2
= 80,
756 BRW_OPCODE_SADA2
= 81,
761 BRW_OPCODE_LINE
= 89,
765 BRW_OPCODE_NOP
= 126,
767 /* These are compiler backend opcodes that get translated into other
770 FS_OPCODE_FB_WRITE
= 128,
771 FS_OPCODE_BLORP_FB_WRITE
,
778 SHADER_OPCODE_INT_QUOTIENT
,
779 SHADER_OPCODE_INT_REMAINDER
,
789 SHADER_OPCODE_TXF_CMS
,
790 SHADER_OPCODE_TXF_UMS
,
791 SHADER_OPCODE_TXF_MCS
,
794 SHADER_OPCODE_TG4_OFFSET
,
796 SHADER_OPCODE_SHADER_TIME_ADD
,
798 SHADER_OPCODE_UNTYPED_ATOMIC
,
799 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
801 SHADER_OPCODE_GEN4_SCRATCH_READ
,
802 SHADER_OPCODE_GEN4_SCRATCH_WRITE
,
803 SHADER_OPCODE_GEN7_SCRATCH_READ
,
811 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
812 FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
,
813 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
,
814 FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
,
815 FS_OPCODE_MOV_DISPATCH_TO_FLAGS
,
816 FS_OPCODE_DISCARD_JUMP
,
818 FS_OPCODE_SET_SAMPLE_ID
,
819 FS_OPCODE_SET_SIMD4X2_OFFSET
,
820 FS_OPCODE_PACK_HALF_2x16_SPLIT
,
821 FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
,
822 FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
,
823 FS_OPCODE_PLACEHOLDER_HALT
,
826 VS_OPCODE_PULL_CONSTANT_LOAD
,
827 VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
,
828 VS_OPCODE_UNPACK_FLAGS_SIMD4X2
,
831 * Write geometry shader output data to the URB.
833 * Unlike VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from
834 * R0 to the first MRF. This allows the geometry shader to override the
835 * "Slot {0,1} Offset" fields in the message header.
840 * Terminate the geometry shader thread by doing an empty URB write.
842 * This opcode doesn't do an implied move from R0 to the first MRF. This
843 * allows the geometry shader to override the "GS Number of Output Vertices
844 * for Slot {0,1}" fields in the message header.
846 GS_OPCODE_THREAD_END
,
849 * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header.
851 * - dst is the MRF containing the message header.
853 * - src0.x indicates which portion of the URB should be written to (e.g. a
856 * - src1 is an immediate multiplier which will be applied to src0
857 * (e.g. the size of a single vertex in the URB).
859 * Note: the hardware will apply this offset *in addition to* the offset in
860 * vec4_instruction::offset.
862 GS_OPCODE_SET_WRITE_OFFSET
,
865 * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a
866 * URB_WRITE message header.
868 * - dst is the MRF containing the message header.
870 * - src0.x is the vertex count. The upper 16 bits will be ignored.
872 GS_OPCODE_SET_VERTEX_COUNT
,
875 * Set DWORD 2 of dst to the immediate value in src. Used by geometry
876 * shaders to initialize DWORD 2 of R0, which needs to be 0 in order for
877 * scratch reads and writes to operate correctly.
879 GS_OPCODE_SET_DWORD_2_IMMED
,
882 * Prepare the dst register for storage in the "Channel Mask" fields of a
883 * URB_WRITE message header.
885 * DWORD 4 of dst is shifted left by 4 bits, so that later,
886 * GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
887 * final channel mask.
889 * Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
890 * form the final channel mask, DWORDs 0 and 4 of the dst register must not
891 * have any extraneous bits set prior to execution of this opcode (that is,
892 * they should be in the range 0x0 to 0xf).
894 GS_OPCODE_PREPARE_CHANNEL_MASKS
,
897 * Set the "Channel Mask" fields of a URB_WRITE message header.
899 * - dst is the MRF containing the message header.
901 * - src.x is the channel mask, as prepared by
902 * GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to
903 * form the final channel mask.
905 GS_OPCODE_SET_CHANNEL_MASKS
,
908 * Get the "Instance ID" fields from the payload.
910 * - dst is the GRF for gl_InvocationID.
912 GS_OPCODE_GET_INSTANCE_ID
,
915 enum brw_urb_write_flags
{
916 BRW_URB_WRITE_NO_FLAGS
= 0,
919 * Causes a new URB entry to be allocated, and its address stored in the
920 * destination register (gen < 7).
922 BRW_URB_WRITE_ALLOCATE
= 0x1,
925 * Causes the current URB entry to be deallocated (gen < 7).
927 BRW_URB_WRITE_UNUSED
= 0x2,
930 * Causes the thread to terminate.
932 BRW_URB_WRITE_EOT
= 0x4,
935 * Indicates that the given URB entry is complete, and may be sent further
936 * down the 3D pipeline (gen < 7).
938 BRW_URB_WRITE_COMPLETE
= 0x8,
941 * Indicates that an additional offset (which may be different for the two
942 * vec4 slots) is stored in the message header (gen == 7).
944 BRW_URB_WRITE_PER_SLOT_OFFSET
= 0x10,
947 * Indicates that the channel masks in the URB_WRITE message header should
948 * not be overridden to 0xff (gen == 7).
950 BRW_URB_WRITE_USE_CHANNEL_MASKS
= 0x20,
953 * Indicates that the data should be sent to the URB using the
954 * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7). This
955 * causes offsets to be interpreted as multiples of an OWORD instead of an
956 * HWORD, and only allows one OWORD to be written.
958 BRW_URB_WRITE_OWORD
= 0x40,
961 * Convenient combination of flags: end the thread while simultaneously
962 * marking the given URB entry as complete.
964 BRW_URB_WRITE_EOT_COMPLETE
= BRW_URB_WRITE_EOT
| BRW_URB_WRITE_COMPLETE
,
967 * Convenient combination of flags: mark the given URB entry as complete
968 * and simultaneously allocate a new one.
970 BRW_URB_WRITE_ALLOCATE_COMPLETE
=
971 BRW_URB_WRITE_ALLOCATE
| BRW_URB_WRITE_COMPLETE
,
976 * Allow brw_urb_write_flags enums to be ORed together.
978 inline brw_urb_write_flags
979 operator|(brw_urb_write_flags x
, brw_urb_write_flags y
)
981 return static_cast<brw_urb_write_flags
>(static_cast<int>(x
) |
982 static_cast<int>(y
));
986 #define BRW_PREDICATE_NONE 0
987 #define BRW_PREDICATE_NORMAL 1
988 #define BRW_PREDICATE_ALIGN1_ANYV 2
989 #define BRW_PREDICATE_ALIGN1_ALLV 3
990 #define BRW_PREDICATE_ALIGN1_ANY2H 4
991 #define BRW_PREDICATE_ALIGN1_ALL2H 5
992 #define BRW_PREDICATE_ALIGN1_ANY4H 6
993 #define BRW_PREDICATE_ALIGN1_ALL4H 7
994 #define BRW_PREDICATE_ALIGN1_ANY8H 8
995 #define BRW_PREDICATE_ALIGN1_ALL8H 9
996 #define BRW_PREDICATE_ALIGN1_ANY16H 10
997 #define BRW_PREDICATE_ALIGN1_ALL16H 11
998 #define BRW_PREDICATE_ALIGN16_REPLICATE_X 2
999 #define BRW_PREDICATE_ALIGN16_REPLICATE_Y 3
1000 #define BRW_PREDICATE_ALIGN16_REPLICATE_Z 4
1001 #define BRW_PREDICATE_ALIGN16_REPLICATE_W 5
1002 #define BRW_PREDICATE_ALIGN16_ANY4H 6
1003 #define BRW_PREDICATE_ALIGN16_ALL4H 7
1005 #define BRW_ARCHITECTURE_REGISTER_FILE 0
1006 #define BRW_GENERAL_REGISTER_FILE 1
1007 #define BRW_MESSAGE_REGISTER_FILE 2
1008 #define BRW_IMMEDIATE_VALUE 3
1010 #define BRW_HW_REG_TYPE_UD 0
1011 #define BRW_HW_REG_TYPE_D 1
1012 #define BRW_HW_REG_TYPE_UW 2
1013 #define BRW_HW_REG_TYPE_W 3
1014 #define BRW_HW_REG_TYPE_F 7
1015 #define GEN8_HW_REG_TYPE_UQ 8
1016 #define GEN8_HW_REG_TYPE_Q 9
1018 #define BRW_HW_REG_NON_IMM_TYPE_UB 4
1019 #define BRW_HW_REG_NON_IMM_TYPE_B 5
1020 #define GEN7_HW_REG_NON_IMM_TYPE_DF 6
1021 #define GEN8_HW_REG_NON_IMM_TYPE_HF 10
1023 #define BRW_HW_REG_IMM_TYPE_UV 4 /* Gen6+ packed unsigned immediate vector */
1024 #define BRW_HW_REG_IMM_TYPE_VF 5 /* packed float immediate vector */
1025 #define BRW_HW_REG_IMM_TYPE_V 6 /* packed int imm. vector; uword dest only */
1026 #define GEN8_HW_REG_IMM_TYPE_DF 10
1027 #define GEN8_HW_REG_IMM_TYPE_HF 11
1029 /* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
1030 * the types were implied. IVB adds BFE and BFI2 that operate on doublewords
1031 * and unsigned doublewords, so a new field is also available in the da3src
1032 * struct (part of struct brw_instruction.bits1 in brw_structs.h) to select
1033 * dst and shared-src types. The values are different from BRW_REGISTER_TYPE_*.
1035 #define BRW_3SRC_TYPE_F 0
1036 #define BRW_3SRC_TYPE_D 1
1037 #define BRW_3SRC_TYPE_UD 2
1038 #define BRW_3SRC_TYPE_DF 3
1040 #define BRW_ARF_NULL 0x00
1041 #define BRW_ARF_ADDRESS 0x10
1042 #define BRW_ARF_ACCUMULATOR 0x20
1043 #define BRW_ARF_FLAG 0x30
1044 #define BRW_ARF_MASK 0x40
1045 #define BRW_ARF_MASK_STACK 0x50
1046 #define BRW_ARF_MASK_STACK_DEPTH 0x60
1047 #define BRW_ARF_STATE 0x70
1048 #define BRW_ARF_CONTROL 0x80
1049 #define BRW_ARF_NOTIFICATION_COUNT 0x90
1050 #define BRW_ARF_IP 0xA0
1051 #define BRW_ARF_TDR 0xB0
1052 #define BRW_ARF_TIMESTAMP 0xC0
1054 #define BRW_MRF_COMPR4 (1 << 7)
1063 #define BRW_THREAD_NORMAL 0
1064 #define BRW_THREAD_ATOMIC 1
1065 #define BRW_THREAD_SWITCH 2
1067 #define BRW_VERTICAL_STRIDE_0 0
1068 #define BRW_VERTICAL_STRIDE_1 1
1069 #define BRW_VERTICAL_STRIDE_2 2
1070 #define BRW_VERTICAL_STRIDE_4 3
1071 #define BRW_VERTICAL_STRIDE_8 4
1072 #define BRW_VERTICAL_STRIDE_16 5
1073 #define BRW_VERTICAL_STRIDE_32 6
1074 #define BRW_VERTICAL_STRIDE_64 7
1075 #define BRW_VERTICAL_STRIDE_128 8
1076 #define BRW_VERTICAL_STRIDE_256 9
1077 #define BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF
1079 #define BRW_WIDTH_1 0
1080 #define BRW_WIDTH_2 1
1081 #define BRW_WIDTH_4 2
1082 #define BRW_WIDTH_8 3
1083 #define BRW_WIDTH_16 4
1085 #define BRW_STATELESS_BUFFER_BOUNDARY_1K 0
1086 #define BRW_STATELESS_BUFFER_BOUNDARY_2K 1
1087 #define BRW_STATELESS_BUFFER_BOUNDARY_4K 2
1088 #define BRW_STATELESS_BUFFER_BOUNDARY_8K 3
1089 #define BRW_STATELESS_BUFFER_BOUNDARY_16K 4
1090 #define BRW_STATELESS_BUFFER_BOUNDARY_32K 5
1091 #define BRW_STATELESS_BUFFER_BOUNDARY_64K 6
1092 #define BRW_STATELESS_BUFFER_BOUNDARY_128K 7
1093 #define BRW_STATELESS_BUFFER_BOUNDARY_256K 8
1094 #define BRW_STATELESS_BUFFER_BOUNDARY_512K 9
1095 #define BRW_STATELESS_BUFFER_BOUNDARY_1M 10
1096 #define BRW_STATELESS_BUFFER_BOUNDARY_2M 11
1098 #define BRW_POLYGON_FACING_FRONT 0
1099 #define BRW_POLYGON_FACING_BACK 1
1102 * Message target: Shared Function ID for where to SEND a message.
1104 * These are enumerated in the ISA reference under "send - Send Message".
1105 * In particular, see the following tables:
1106 * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition"
1107 * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor"
1108 * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs"
1110 enum brw_message_target
{
1112 BRW_SFID_MATH
= 1, /* Only valid on Gen4-5 */
1113 BRW_SFID_SAMPLER
= 2,
1114 BRW_SFID_MESSAGE_GATEWAY
= 3,
1115 BRW_SFID_DATAPORT_READ
= 4,
1116 BRW_SFID_DATAPORT_WRITE
= 5,
1118 BRW_SFID_THREAD_SPAWNER
= 7,
1121 GEN6_SFID_DATAPORT_SAMPLER_CACHE
= 4,
1122 GEN6_SFID_DATAPORT_RENDER_CACHE
= 5,
1123 GEN6_SFID_DATAPORT_CONSTANT_CACHE
= 9,
1125 GEN7_SFID_DATAPORT_DATA_CACHE
= 10,
1126 GEN7_SFID_PIXEL_INTERPOLATOR
= 11,
1127 HSW_SFID_DATAPORT_DATA_CACHE_1
= 12,
1131 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10
1133 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
1134 #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
1135 #define BRW_SAMPLER_RETURN_FORMAT_SINT32 3
1137 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
1138 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
1139 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
1140 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
1141 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
1142 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
1143 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
1144 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
1145 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
1146 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
1147 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0
1148 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1
1149 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1
1150 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
1151 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2
1152 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3
1153 #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
1154 #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
1156 #define GEN5_SAMPLER_MESSAGE_SAMPLE 0
1157 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1
1158 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2
1159 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3
1160 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4
1161 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5
1162 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6
1163 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7
1164 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8
1165 #define GEN5_SAMPLER_MESSAGE_LOD 9
1166 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10
1167 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16
1168 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17
1169 #define GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18
1170 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20
1171 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29
1172 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30
1173 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31
1176 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0
1177 #define BRW_SAMPLER_SIMD_MODE_SIMD8 1
1178 #define BRW_SAMPLER_SIMD_MODE_SIMD16 2
1179 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3
1181 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
1182 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
1183 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
1184 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
1185 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
1187 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
1188 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
1190 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
1191 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
1193 /* This one stays the same across generations. */
1194 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
1196 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
1197 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2
1198 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
1200 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1201 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1202 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3
1203 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1204 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1206 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1
1207 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2
1208 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4
1209 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5
1210 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6
1212 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
1213 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
1214 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
1216 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
1217 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
1218 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
1219 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
1220 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
1222 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
1223 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
1224 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2
1225 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
1226 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
1227 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
1228 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
1231 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7
1232 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8
1233 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9
1234 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10
1235 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11
1236 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12
1237 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13
1238 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14
1241 #define GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 10
1242 #define GEN7_DATAPORT_DC_OWORD_BLOCK_READ 0
1243 #define GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1
1244 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2
1245 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_READ 3
1246 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_READ 4
1247 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ 5
1248 #define GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6
1249 #define GEN7_DATAPORT_DC_MEMORY_FENCE 7
1250 #define GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE 8
1251 #define GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10
1252 #define GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11
1253 #define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12
1254 #define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13
1256 #define GEN7_DATAPORT_SCRATCH_READ ((1 << 18) | \
1258 #define GEN7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \
1260 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12
1263 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0
1264 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ 1
1265 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ 2
1266 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ 3
1267 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ 4
1268 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE 7
1269 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE 8
1270 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE 10
1271 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE 11
1272 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE 12
1274 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ 1
1275 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP 2
1276 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2 3
1277 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ 4
1278 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ 5
1279 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP 6
1280 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 7
1281 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE 9
1282 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE 10
1283 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11
1284 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12
1285 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13
1287 /* dataport atomic operations. */
1288 #define BRW_AOP_AND 1
1289 #define BRW_AOP_OR 2
1290 #define BRW_AOP_XOR 3
1291 #define BRW_AOP_MOV 4
1292 #define BRW_AOP_INC 5
1293 #define BRW_AOP_DEC 6
1294 #define BRW_AOP_ADD 7
1295 #define BRW_AOP_SUB 8
1296 #define BRW_AOP_REVSUB 9
1297 #define BRW_AOP_IMAX 10
1298 #define BRW_AOP_IMIN 11
1299 #define BRW_AOP_UMAX 12
1300 #define BRW_AOP_UMIN 13
1301 #define BRW_AOP_CMPWR 14
1302 #define BRW_AOP_PREDEC 15
1304 #define BRW_MATH_FUNCTION_INV 1
1305 #define BRW_MATH_FUNCTION_LOG 2
1306 #define BRW_MATH_FUNCTION_EXP 3
1307 #define BRW_MATH_FUNCTION_SQRT 4
1308 #define BRW_MATH_FUNCTION_RSQ 5
1309 #define BRW_MATH_FUNCTION_SIN 6
1310 #define BRW_MATH_FUNCTION_COS 7
1311 #define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */
1312 #define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */
1313 #define BRW_MATH_FUNCTION_POW 10
1314 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
1315 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
1316 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
1317 #define GEN8_MATH_FUNCTION_INVM 14
1318 #define GEN8_MATH_FUNCTION_RSQRTM 15
1320 #define BRW_MATH_INTEGER_UNSIGNED 0
1321 #define BRW_MATH_INTEGER_SIGNED 1
1323 #define BRW_MATH_PRECISION_FULL 0
1324 #define BRW_MATH_PRECISION_PARTIAL 1
1326 #define BRW_MATH_SATURATE_NONE 0
1327 #define BRW_MATH_SATURATE_SATURATE 1
1329 #define BRW_MATH_DATA_VECTOR 0
1330 #define BRW_MATH_DATA_SCALAR 1
1332 #define BRW_URB_OPCODE_WRITE_HWORD 0
1333 #define BRW_URB_OPCODE_WRITE_OWORD 1
1335 #define BRW_URB_SWIZZLE_NONE 0
1336 #define BRW_URB_SWIZZLE_INTERLEAVE 1
1337 #define BRW_URB_SWIZZLE_TRANSPOSE 2
1339 #define BRW_SCRATCH_SPACE_SIZE_1K 0
1340 #define BRW_SCRATCH_SPACE_SIZE_2K 1
1341 #define BRW_SCRATCH_SPACE_SIZE_4K 2
1342 #define BRW_SCRATCH_SPACE_SIZE_8K 3
1343 #define BRW_SCRATCH_SPACE_SIZE_16K 4
1344 #define BRW_SCRATCH_SPACE_SIZE_32K 5
1345 #define BRW_SCRATCH_SPACE_SIZE_64K 6
1346 #define BRW_SCRATCH_SPACE_SIZE_128K 7
1347 #define BRW_SCRATCH_SPACE_SIZE_256K 8
1348 #define BRW_SCRATCH_SPACE_SIZE_512K 9
1349 #define BRW_SCRATCH_SPACE_SIZE_1M 10
1350 #define BRW_SCRATCH_SPACE_SIZE_2M 11
1353 #define CMD_URB_FENCE 0x6000
1354 #define CMD_CS_URB_STATE 0x6001
1355 #define CMD_CONST_BUFFER 0x6002
1357 #define CMD_STATE_BASE_ADDRESS 0x6101
1358 #define CMD_STATE_SIP 0x6102
1359 #define CMD_PIPELINE_SELECT_965 0x6104
1360 #define CMD_PIPELINE_SELECT_GM45 0x6904
1362 #define _3DSTATE_PIPELINED_POINTERS 0x7800
1363 #define _3DSTATE_BINDING_TABLE_POINTERS 0x7801
1364 # define GEN6_BINDING_TABLE_MODIFY_VS (1 << 8)
1365 # define GEN6_BINDING_TABLE_MODIFY_GS (1 << 9)
1366 # define GEN6_BINDING_TABLE_MODIFY_PS (1 << 12)
1368 #define _3DSTATE_BINDING_TABLE_POINTERS_VS 0x7826 /* GEN7+ */
1369 #define _3DSTATE_BINDING_TABLE_POINTERS_HS 0x7827 /* GEN7+ */
1370 #define _3DSTATE_BINDING_TABLE_POINTERS_DS 0x7828 /* GEN7+ */
1371 #define _3DSTATE_BINDING_TABLE_POINTERS_GS 0x7829 /* GEN7+ */
1372 #define _3DSTATE_BINDING_TABLE_POINTERS_PS 0x782A /* GEN7+ */
1374 #define _3DSTATE_SAMPLER_STATE_POINTERS 0x7802 /* GEN6+ */
1375 # define PS_SAMPLER_STATE_CHANGE (1 << 12)
1376 # define GS_SAMPLER_STATE_CHANGE (1 << 9)
1377 # define VS_SAMPLER_STATE_CHANGE (1 << 8)
1382 #define _3DSTATE_SAMPLER_STATE_POINTERS_VS 0x782B /* GEN7+ */
1383 #define _3DSTATE_SAMPLER_STATE_POINTERS_GS 0x782E /* GEN7+ */
1384 #define _3DSTATE_SAMPLER_STATE_POINTERS_PS 0x782F /* GEN7+ */
1386 #define _3DSTATE_VERTEX_BUFFERS 0x7808
1387 # define BRW_VB0_INDEX_SHIFT 27
1388 # define GEN6_VB0_INDEX_SHIFT 26
1389 # define BRW_VB0_ACCESS_VERTEXDATA (0 << 26)
1390 # define BRW_VB0_ACCESS_INSTANCEDATA (1 << 26)
1391 # define GEN6_VB0_ACCESS_VERTEXDATA (0 << 20)
1392 # define GEN6_VB0_ACCESS_INSTANCEDATA (1 << 20)
1393 # define GEN7_VB0_ADDRESS_MODIFYENABLE (1 << 14)
1394 # define BRW_VB0_PITCH_SHIFT 0
1396 #define _3DSTATE_VERTEX_ELEMENTS 0x7809
1397 # define BRW_VE0_INDEX_SHIFT 27
1398 # define GEN6_VE0_INDEX_SHIFT 26
1399 # define BRW_VE0_FORMAT_SHIFT 16
1400 # define BRW_VE0_VALID (1 << 26)
1401 # define GEN6_VE0_VALID (1 << 25)
1402 # define GEN6_VE0_EDGE_FLAG_ENABLE (1 << 15)
1403 # define BRW_VE0_SRC_OFFSET_SHIFT 0
1404 # define BRW_VE1_COMPONENT_NOSTORE 0
1405 # define BRW_VE1_COMPONENT_STORE_SRC 1
1406 # define BRW_VE1_COMPONENT_STORE_0 2
1407 # define BRW_VE1_COMPONENT_STORE_1_FLT 3
1408 # define BRW_VE1_COMPONENT_STORE_1_INT 4
1409 # define BRW_VE1_COMPONENT_STORE_VID 5
1410 # define BRW_VE1_COMPONENT_STORE_IID 6
1411 # define BRW_VE1_COMPONENT_STORE_PID 7
1412 # define BRW_VE1_COMPONENT_0_SHIFT 28
1413 # define BRW_VE1_COMPONENT_1_SHIFT 24
1414 # define BRW_VE1_COMPONENT_2_SHIFT 20
1415 # define BRW_VE1_COMPONENT_3_SHIFT 16
1416 # define BRW_VE1_DST_OFFSET_SHIFT 0
1418 #define CMD_INDEX_BUFFER 0x780a
1419 #define GEN4_3DSTATE_VF_STATISTICS 0x780b
1420 #define GM45_3DSTATE_VF_STATISTICS 0x680b
1421 #define _3DSTATE_CC_STATE_POINTERS 0x780e /* GEN6+ */
1422 #define _3DSTATE_BLEND_STATE_POINTERS 0x7824 /* GEN7+ */
1423 #define _3DSTATE_DEPTH_STENCIL_STATE_POINTERS 0x7825 /* GEN7+ */
1425 #define _3DSTATE_URB 0x7805 /* GEN6 */
1426 # define GEN6_URB_VS_SIZE_SHIFT 16
1427 # define GEN6_URB_VS_ENTRIES_SHIFT 0
1428 # define GEN6_URB_GS_ENTRIES_SHIFT 8
1429 # define GEN6_URB_GS_SIZE_SHIFT 0
1431 #define _3DSTATE_VF 0x780c /* GEN7.5+ */
1432 #define HSW_CUT_INDEX_ENABLE (1 << 8)
1434 #define _3DSTATE_VF_INSTANCING 0x7849 /* GEN8+ */
1435 # define GEN8_VF_INSTANCING_ENABLE (1 << 8)
1437 #define _3DSTATE_VF_SGVS 0x784a /* GEN8+ */
1438 # define GEN8_SGVS_ENABLE_INSTANCE_ID (1 << 31)
1439 # define GEN8_SGVS_INSTANCE_ID_COMPONENT_SHIFT 29
1440 # define GEN8_SGVS_INSTANCE_ID_ELEMENT_OFFSET_SHIFT 16
1441 # define GEN8_SGVS_ENABLE_VERTEX_ID (1 << 15)
1442 # define GEN8_SGVS_VERTEX_ID_COMPONENT_SHIFT 13
1443 # define GEN8_SGVS_VERTEX_ID_ELEMENT_OFFSET_SHIFT 0
1445 #define _3DSTATE_VF_TOPOLOGY 0x784b /* GEN8+ */
1447 #define _3DSTATE_WM_CHROMAKEY 0x784c /* GEN8+ */
1449 #define _3DSTATE_URB_VS 0x7830 /* GEN7+ */
1450 #define _3DSTATE_URB_HS 0x7831 /* GEN7+ */
1451 #define _3DSTATE_URB_DS 0x7832 /* GEN7+ */
1452 #define _3DSTATE_URB_GS 0x7833 /* GEN7+ */
1453 # define GEN7_URB_ENTRY_SIZE_SHIFT 16
1454 # define GEN7_URB_STARTING_ADDRESS_SHIFT 25
1456 /* "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
1457 * is 2^9, or 512. It's counted in multiples of 64 bytes.
1459 #define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64)
1461 #define _3DSTATE_PUSH_CONSTANT_ALLOC_VS 0x7912 /* GEN7+ */
1462 #define _3DSTATE_PUSH_CONSTANT_ALLOC_GS 0x7915 /* GEN7+ */
1463 #define _3DSTATE_PUSH_CONSTANT_ALLOC_PS 0x7916 /* GEN7+ */
1464 # define GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT 16
1466 #define _3DSTATE_VIEWPORT_STATE_POINTERS 0x780d /* GEN6+ */
1467 # define GEN6_CC_VIEWPORT_MODIFY (1 << 12)
1468 # define GEN6_SF_VIEWPORT_MODIFY (1 << 11)
1469 # define GEN6_CLIP_VIEWPORT_MODIFY (1 << 10)
1470 # define GEN7_NUM_VIEWPORTS 16
1472 #define _3DSTATE_VIEWPORT_STATE_POINTERS_CC 0x7823 /* GEN7+ */
1473 #define _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL 0x7821 /* GEN7+ */
1475 #define _3DSTATE_SCISSOR_STATE_POINTERS 0x780f /* GEN6+ */
1477 #define _3DSTATE_VS 0x7810 /* GEN6+ */
1479 # define GEN6_VS_SPF_MODE (1 << 31)
1480 # define GEN6_VS_VECTOR_MASK_ENABLE (1 << 30)
1481 # define GEN6_VS_SAMPLER_COUNT_SHIFT 27
1482 # define GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18
1483 # define GEN6_VS_FLOATING_POINT_MODE_IEEE_754 (0 << 16)
1484 # define GEN6_VS_FLOATING_POINT_MODE_ALT (1 << 16)
1486 # define GEN6_VS_DISPATCH_START_GRF_SHIFT 20
1487 # define GEN6_VS_URB_READ_LENGTH_SHIFT 11
1488 # define GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT 4
1490 # define GEN6_VS_MAX_THREADS_SHIFT 25
1491 # define HSW_VS_MAX_THREADS_SHIFT 23
1492 # define GEN6_VS_STATISTICS_ENABLE (1 << 10)
1493 # define GEN6_VS_CACHE_DISABLE (1 << 1)
1494 # define GEN6_VS_ENABLE (1 << 0)
1496 # define GEN8_VS_URB_ENTRY_OUTPUT_OFFSET_SHIFT 21
1497 # define GEN8_VS_URB_OUTPUT_LENGTH_SHIFT 16
1498 # define GEN8_VS_USER_CLIP_DISTANCE_SHIFT 8
1500 #define _3DSTATE_GS 0x7811 /* GEN6+ */
1502 # define GEN6_GS_SPF_MODE (1 << 31)
1503 # define GEN6_GS_VECTOR_MASK_ENABLE (1 << 30)
1504 # define GEN6_GS_SAMPLER_COUNT_SHIFT 27
1505 # define GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18
1506 # define GEN6_GS_FLOATING_POINT_MODE_IEEE_754 (0 << 16)
1507 # define GEN6_GS_FLOATING_POINT_MODE_ALT (1 << 16)
1509 # define GEN7_GS_OUTPUT_VERTEX_SIZE_SHIFT 23
1510 # define GEN7_GS_OUTPUT_TOPOLOGY_SHIFT 17
1511 # define GEN6_GS_URB_READ_LENGTH_SHIFT 11
1512 # define GEN7_GS_INCLUDE_VERTEX_HANDLES (1 << 10)
1513 # define GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT 4
1514 # define GEN6_GS_DISPATCH_START_GRF_SHIFT 0
1516 # define GEN6_GS_MAX_THREADS_SHIFT 25
1517 # define HSW_GS_MAX_THREADS_SHIFT 24
1518 # define IVB_GS_CONTROL_DATA_FORMAT_SHIFT 24
1519 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0
1520 # define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1
1521 # define GEN7_GS_CONTROL_DATA_HEADER_SIZE_SHIFT 20
1522 # define GEN7_GS_INSTANCE_CONTROL_SHIFT 15
1523 # define GEN7_GS_DISPATCH_MODE_SINGLE (0 << 11)
1524 # define GEN7_GS_DISPATCH_MODE_DUAL_INSTANCE (1 << 11)
1525 # define GEN7_GS_DISPATCH_MODE_DUAL_OBJECT (2 << 11)
1526 # define GEN6_GS_STATISTICS_ENABLE (1 << 10)
1527 # define GEN6_GS_SO_STATISTICS_ENABLE (1 << 9)
1528 # define GEN6_GS_RENDERING_ENABLE (1 << 8)
1529 # define GEN7_GS_INCLUDE_PRIMITIVE_ID (1 << 4)
1530 # define GEN7_GS_REORDER_TRAILING (1 << 2)
1531 # define GEN7_GS_ENABLE (1 << 0)
1533 # define HSW_GS_CONTROL_DATA_FORMAT_SHIFT 31
1534 # define GEN6_GS_REORDER (1 << 30)
1535 # define GEN6_GS_DISCARD_ADJACENCY (1 << 29)
1536 # define GEN6_GS_SVBI_PAYLOAD_ENABLE (1 << 28)
1537 # define GEN6_GS_SVBI_POSTINCREMENT_ENABLE (1 << 27)
1538 # define GEN6_GS_SVBI_POSTINCREMENT_VALUE_SHIFT 16
1539 # define GEN6_GS_SVBI_POSTINCREMENT_VALUE_MASK INTEL_MASK(25, 16)
1540 # define GEN6_GS_ENABLE (1 << 15)
1543 # define GEN8_GS_URB_ENTRY_OUTPUT_OFFSET_SHIFT 21
1544 # define GEN8_GS_URB_OUTPUT_LENGTH_SHIFT 16
1545 # define GEN8_GS_USER_CLIP_DISTANCE_SHIFT 8
1547 # define BRW_GS_EDGE_INDICATOR_0 (1 << 8)
1548 # define BRW_GS_EDGE_INDICATOR_1 (1 << 9)
1550 /* GS Thread Payload
1553 # define GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27
1555 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's
1556 * counted in multiples of 16 bytes.
1558 #define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16)
1560 #define _3DSTATE_HS 0x781B /* GEN7+ */
1561 #define _3DSTATE_TE 0x781C /* GEN7+ */
1562 #define _3DSTATE_DS 0x781D /* GEN7+ */
1564 #define _3DSTATE_CLIP 0x7812 /* GEN6+ */
1566 # define GEN7_CLIP_WINDING_CW (0 << 20)
1567 # define GEN7_CLIP_WINDING_CCW (1 << 20)
1568 # define GEN7_CLIP_VERTEX_SUBPIXEL_PRECISION_8 (0 << 19)
1569 # define GEN7_CLIP_VERTEX_SUBPIXEL_PRECISION_4 (1 << 19)
1570 # define GEN7_CLIP_EARLY_CULL (1 << 18)
1571 # define GEN7_CLIP_CULLMODE_BOTH (0 << 16)
1572 # define GEN7_CLIP_CULLMODE_NONE (1 << 16)
1573 # define GEN7_CLIP_CULLMODE_FRONT (2 << 16)
1574 # define GEN7_CLIP_CULLMODE_BACK (3 << 16)
1575 # define GEN6_CLIP_STATISTICS_ENABLE (1 << 10)
1577 * Just does cheap culling based on the clip distance. Bits must be
1578 * disjoint with USER_CLIP_CLIP_DISTANCE bits.
1580 # define GEN6_USER_CLIP_CULL_DISTANCES_SHIFT 0
1582 # define GEN6_CLIP_ENABLE (1 << 31)
1583 # define GEN6_CLIP_API_OGL (0 << 30)
1584 # define GEN6_CLIP_API_D3D (1 << 30)
1585 # define GEN6_CLIP_XY_TEST (1 << 28)
1586 # define GEN6_CLIP_Z_TEST (1 << 27)
1587 # define GEN6_CLIP_GB_TEST (1 << 26)
1588 /** 8-bit field of which user clip distances to clip aganist. */
1589 # define GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT 16
1590 # define GEN6_CLIP_MODE_NORMAL (0 << 13)
1591 # define GEN6_CLIP_MODE_REJECT_ALL (3 << 13)
1592 # define GEN6_CLIP_MODE_ACCEPT_ALL (4 << 13)
1593 # define GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE (1 << 9)
1594 # define GEN6_CLIP_NON_PERSPECTIVE_BARYCENTRIC_ENABLE (1 << 8)
1595 # define GEN6_CLIP_TRI_PROVOKE_SHIFT 4
1596 # define GEN6_CLIP_LINE_PROVOKE_SHIFT 2
1597 # define GEN6_CLIP_TRIFAN_PROVOKE_SHIFT 0
1599 # define GEN6_CLIP_MIN_POINT_WIDTH_SHIFT 17
1600 # define GEN6_CLIP_MAX_POINT_WIDTH_SHIFT 6
1601 # define GEN6_CLIP_FORCE_ZERO_RTAINDEX (1 << 5)
1602 # define GEN6_CLIP_MAX_VP_INDEX_MASK INTEL_MASK(3, 0)
1604 #define _3DSTATE_SF 0x7813 /* GEN6+ */
1605 /* DW1 (for gen6) */
1606 # define GEN6_SF_NUM_OUTPUTS_SHIFT 22
1607 # define GEN6_SF_SWIZZLE_ENABLE (1 << 21)
1608 # define GEN6_SF_POINT_SPRITE_UPPERLEFT (0 << 20)
1609 # define GEN6_SF_POINT_SPRITE_LOWERLEFT (1 << 20)
1610 # define GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT 11
1611 # define GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT 4
1613 # define GEN6_SF_LEGACY_GLOBAL_DEPTH_BIAS (1 << 11)
1614 # define GEN6_SF_STATISTICS_ENABLE (1 << 10)
1615 # define GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID (1 << 9)
1616 # define GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME (1 << 8)
1617 # define GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT (1 << 7)
1618 # define GEN6_SF_FRONT_SOLID (0 << 5)
1619 # define GEN6_SF_FRONT_WIREFRAME (1 << 5)
1620 # define GEN6_SF_FRONT_POINT (2 << 5)
1621 # define GEN6_SF_BACK_SOLID (0 << 3)
1622 # define GEN6_SF_BACK_WIREFRAME (1 << 3)
1623 # define GEN6_SF_BACK_POINT (2 << 3)
1624 # define GEN6_SF_VIEWPORT_TRANSFORM_ENABLE (1 << 1)
1625 # define GEN6_SF_WINDING_CCW (1 << 0)
1627 # define GEN6_SF_LINE_AA_ENABLE (1 << 31)
1628 # define GEN6_SF_CULL_BOTH (0 << 29)
1629 # define GEN6_SF_CULL_NONE (1 << 29)
1630 # define GEN6_SF_CULL_FRONT (2 << 29)
1631 # define GEN6_SF_CULL_BACK (3 << 29)
1632 # define GEN6_SF_LINE_WIDTH_SHIFT 18 /* U3.7 */
1633 # define GEN6_SF_LINE_END_CAP_WIDTH_0_5 (0 << 16)
1634 # define GEN6_SF_LINE_END_CAP_WIDTH_1_0 (1 << 16)
1635 # define GEN6_SF_LINE_END_CAP_WIDTH_2_0 (2 << 16)
1636 # define GEN6_SF_LINE_END_CAP_WIDTH_4_0 (3 << 16)
1637 # define GEN6_SF_SCISSOR_ENABLE (1 << 11)
1638 # define GEN6_SF_MSRAST_OFF_PIXEL (0 << 8)
1639 # define GEN6_SF_MSRAST_OFF_PATTERN (1 << 8)
1640 # define GEN6_SF_MSRAST_ON_PIXEL (2 << 8)
1641 # define GEN6_SF_MSRAST_ON_PATTERN (3 << 8)
1643 # define GEN6_SF_TRI_PROVOKE_SHIFT 29
1644 # define GEN6_SF_LINE_PROVOKE_SHIFT 27
1645 # define GEN6_SF_TRIFAN_PROVOKE_SHIFT 25
1646 # define GEN6_SF_LINE_AA_MODE_MANHATTAN (0 << 14)
1647 # define GEN6_SF_LINE_AA_MODE_TRUE (1 << 14)
1648 # define GEN6_SF_VERTEX_SUBPIXEL_8BITS (0 << 12)
1649 # define GEN6_SF_VERTEX_SUBPIXEL_4BITS (1 << 12)
1650 # define GEN6_SF_USE_STATE_POINT_WIDTH (1 << 11)
1651 # define GEN6_SF_POINT_WIDTH_SHIFT 0 /* U8.3 */
1652 /* DW5: depth offset constant */
1653 /* DW6: depth offset scale */
1654 /* DW7: depth offset clamp */
1656 # define ATTRIBUTE_1_OVERRIDE_W (1 << 31)
1657 # define ATTRIBUTE_1_OVERRIDE_Z (1 << 30)
1658 # define ATTRIBUTE_1_OVERRIDE_Y (1 << 29)
1659 # define ATTRIBUTE_1_OVERRIDE_X (1 << 28)
1660 # define ATTRIBUTE_1_CONST_SOURCE_SHIFT 25
1661 # define ATTRIBUTE_1_SWIZZLE_SHIFT 22
1662 # define ATTRIBUTE_1_SOURCE_SHIFT 16
1663 # define ATTRIBUTE_0_OVERRIDE_W (1 << 15)
1664 # define ATTRIBUTE_0_OVERRIDE_Z (1 << 14)
1665 # define ATTRIBUTE_0_OVERRIDE_Y (1 << 13)
1666 # define ATTRIBUTE_0_OVERRIDE_X (1 << 12)
1667 # define ATTRIBUTE_0_CONST_SOURCE_SHIFT 9
1668 # define ATTRIBUTE_CONST_0000 0
1669 # define ATTRIBUTE_CONST_0001_FLOAT 1
1670 # define ATTRIBUTE_CONST_1111_FLOAT 2
1671 # define ATTRIBUTE_CONST_PRIM_ID 3
1672 # define ATTRIBUTE_0_SWIZZLE_SHIFT 6
1673 # define ATTRIBUTE_0_SOURCE_SHIFT 0
1675 # define ATTRIBUTE_SWIZZLE_INPUTATTR 0
1676 # define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING 1
1677 # define ATTRIBUTE_SWIZZLE_INPUTATTR_W 2
1678 # define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING_W 3
1679 # define ATTRIBUTE_SWIZZLE_SHIFT 6
1681 /* DW16: Point sprite texture coordinate enables */
1682 /* DW17: Constant interpolation enables */
1683 /* DW18: attr 0-7 wrap shortest enables */
1684 /* DW19: attr 8-16 wrap shortest enables */
1686 /* On GEN7, many fields of 3DSTATE_SF were split out into a new command:
1687 * 3DSTATE_SBE. The remaining fields live in different DWords, but retain
1688 * the same bit-offset. The only new field:
1691 # define GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT 12
1693 # define HSW_SF_LINE_STIPPLE_ENABLE 14
1695 # define GEN8_SF_SMOOTH_POINT_ENABLE (1 << 13)
1697 #define _3DSTATE_SBE 0x781F /* GEN7+ */
1699 # define GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH (1 << 29)
1700 # define GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET (1 << 28)
1701 # define GEN7_SBE_SWIZZLE_CONTROL_MODE (1 << 28)
1702 # define GEN7_SBE_NUM_OUTPUTS_SHIFT 22
1703 # define GEN7_SBE_SWIZZLE_ENABLE (1 << 21)
1704 # define GEN7_SBE_POINT_SPRITE_LOWERLEFT (1 << 20)
1705 # define GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT 11
1706 # define GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT 4
1707 # define GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT 5
1708 /* DW2-9: Attribute setup (same as DW8-15 of gen6 _3DSTATE_SF) */
1709 /* DW10: Point sprite texture coordinate enables */
1710 /* DW11: Constant interpolation enables */
1711 /* DW12: attr 0-7 wrap shortest enables */
1712 /* DW13: attr 8-16 wrap shortest enables */
1714 #define _3DSTATE_SBE_SWIZ 0x7851 /* GEN8+ */
1716 #define _3DSTATE_RASTER 0x7850 /* GEN8+ */
1718 # define GEN8_RASTER_FRONT_WINDING_CCW (1 << 21)
1719 # define GEN8_RASTER_CULL_BOTH (0 << 16)
1720 # define GEN8_RASTER_CULL_NONE (1 << 16)
1721 # define GEN8_RASTER_CULL_FRONT (2 << 16)
1722 # define GEN8_RASTER_CULL_BACK (3 << 16)
1723 # define GEN8_RASTER_SMOOTH_POINT_ENABLE (1 << 13)
1724 # define GEN8_RASTER_API_MULTISAMPLE_ENABLE (1 << 12)
1725 # define GEN8_RASTER_LINE_AA_ENABLE (1 << 2)
1726 # define GEN8_RASTER_SCISSOR_ENABLE (1 << 1)
1727 # define GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE (1 << 0)
1729 /* Gen8 BLEND_STATE */
1731 #define GEN8_BLEND_ALPHA_TO_COVERAGE_ENABLE (1 << 31)
1732 #define GEN8_BLEND_INDEPENDENT_ALPHA_BLEND_ENABLE (1 << 30)
1733 #define GEN8_BLEND_ALPHA_TO_ONE_ENABLE (1 << 29)
1734 #define GEN8_BLEND_ALPHA_TO_COVERAGE_DITHER_ENABLE (1 << 28)
1735 #define GEN8_BLEND_ALPHA_TEST_ENABLE (1 << 27)
1736 #define GEN8_BLEND_ALPHA_TEST_FUNCTION_MASK INTEL_MASK(26, 24)
1737 #define GEN8_BLEND_ALPHA_TEST_FUNCTION_SHIFT 24
1738 #define GEN8_BLEND_COLOR_DITHER_ENABLE (1 << 23)
1739 #define GEN8_BLEND_X_DITHER_OFFSET_MASK INTEL_MASK(22, 21)
1740 #define GEN8_BLEND_X_DITHER_OFFSET_SHIFT 21
1741 #define GEN8_BLEND_Y_DITHER_OFFSET_MASK INTEL_MASK(20, 19)
1742 #define GEN8_BLEND_Y_DITHER_OFFSET_SHIFT 19
1744 #define GEN8_BLEND_COLOR_BUFFER_BLEND_ENABLE (1 << 31)
1745 #define GEN8_BLEND_SRC_BLEND_FACTOR_MASK INTEL_MASK(30, 26)
1746 #define GEN8_BLEND_SRC_BLEND_FACTOR_SHIFT 26
1747 #define GEN8_BLEND_DST_BLEND_FACTOR_MASK INTEL_MASK(25, 21)
1748 #define GEN8_BLEND_DST_BLEND_FACTOR_SHIFT 21
1749 #define GEN8_BLEND_COLOR_BLEND_FUNCTION_MASK INTEL_MASK(20, 18)
1750 #define GEN8_BLEND_COLOR_BLEND_FUNCTION_SHIFT 18
1751 #define GEN8_BLEND_SRC_ALPHA_BLEND_FACTOR_MASK INTEL_MASK(17, 13)
1752 #define GEN8_BLEND_SRC_ALPHA_BLEND_FACTOR_SHIFT 13
1753 #define GEN8_BLEND_DST_ALPHA_BLEND_FACTOR_MASK INTEL_MASK(12, 8)
1754 #define GEN8_BLEND_DST_ALPHA_BLEND_FACTOR_SHIFT 8
1755 #define GEN8_BLEND_ALPHA_BLEND_FUNCTION_MASK INTEL_MASK(7, 5)
1756 #define GEN8_BLEND_ALPHA_BLEND_FUNCTION_SHIFT 5
1757 #define GEN8_BLEND_WRITE_DISABLE_ALPHA (1 << 3)
1758 #define GEN8_BLEND_WRITE_DISABLE_RED (1 << 2)
1759 #define GEN8_BLEND_WRITE_DISABLE_GREEN (1 << 1)
1760 #define GEN8_BLEND_WRITE_DISABLE_BLUE (1 << 0)
1762 #define GEN8_BLEND_LOGIC_OP_ENABLE (1 << 31)
1763 #define GEN8_BLEND_LOGIC_OP_FUNCTION_MASK INTEL_MASK(30, 27)
1764 #define GEN8_BLEND_LOGIC_OP_FUNCTION_SHIFT 27
1765 #define GEN8_BLEND_PRE_BLEND_SRC_ONLY_CLAMP_ENABLE (1 << 4)
1766 #define GEN8_BLEND_COLOR_CLAMP_RANGE_RTFORMAT (2 << 2)
1767 #define GEN8_BLEND_PRE_BLEND_COLOR_CLAMP_ENABLE (1 << 1)
1768 #define GEN8_BLEND_POST_BLEND_COLOR_CLAMP_ENABLE (1 << 0)
1770 #define _3DSTATE_WM_HZ_OP 0x7852 /* GEN8+ */
1772 # define GEN8_WM_HZ_STENCIL_CLEAR (1 << 31)
1773 # define GEN8_WM_HZ_DEPTH_CLEAR (1 << 30)
1774 # define GEN8_WM_HZ_DEPTH_RESOLVE (1 << 28)
1775 # define GEN8_WM_HZ_HIZ_RESOLVE (1 << 27)
1776 # define GEN8_WM_HZ_PIXEL_OFFSET_ENABLE (1 << 26)
1777 # define GEN8_WM_HZ_FULL_SURFACE_DEPTH_CLEAR (1 << 25)
1778 # define GEN8_WM_HZ_STENCIL_CLEAR_VALUE_MASK INTEL_MASK(23, 16)
1779 # define GEN8_WM_HZ_STENCIL_CLEAR_VALUE_SHIFT 16
1780 # define GEN8_WM_HZ_NUM_SAMPLES_MASK INTEL_MASK(15, 13)
1781 # define GEN8_WM_HZ_NUM_SAMPLES_SHIFT 13
1783 # define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MIN_MASK INTEL_MASK(31, 16)
1784 # define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MIN_SHIFT 16
1785 # define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MIN_MASK INTEL_MASK(15, 0)
1786 # define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MIN_SHIFT 0
1788 # define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MAX_MASK INTEL_MASK(31, 16)
1789 # define GEN8_WM_HZ_CLEAR_RECTANGLE_Y_MAX_SHIFT 16
1790 # define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MAX_MASK INTEL_MASK(15, 0)
1791 # define GEN8_WM_HZ_CLEAR_RECTANGLE_X_MAX_SHIFT 0
1793 # define GEN8_WM_HZ_SAMPLE_MASK_MASK INTEL_MASK(15, 0)
1794 # define GEN8_WM_HZ_SAMPLE_MASK_SHIFT 0
1797 #define _3DSTATE_PS_BLEND 0x784D /* GEN8+ */
1799 # define GEN8_PS_BLEND_ALPHA_TO_COVERAGE_ENABLE (1 << 31)
1800 # define GEN8_PS_BLEND_HAS_WRITEABLE_RT (1 << 30)
1801 # define GEN8_PS_BLEND_COLOR_BUFFER_BLEND_ENABLE (1 << 29)
1802 # define GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_MASK INTEL_MASK(28, 24)
1803 # define GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_SHIFT 24
1804 # define GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_MASK INTEL_MASK(23, 19)
1805 # define GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_SHIFT 19
1806 # define GEN8_PS_BLEND_SRC_BLEND_FACTOR_MASK INTEL_MASK(18, 14)
1807 # define GEN8_PS_BLEND_SRC_BLEND_FACTOR_SHIFT 14
1808 # define GEN8_PS_BLEND_DST_BLEND_FACTOR_MASK INTEL_MASK(13, 9)
1809 # define GEN8_PS_BLEND_DST_BLEND_FACTOR_SHIFT 9
1810 # define GEN8_PS_BLEND_ALPHA_TEST_ENABLE (1 << 8)
1811 # define GEN8_PS_BLEND_INDEPENDENT_ALPHA_BLEND_ENABLE (1 << 7)
1813 #define _3DSTATE_WM_DEPTH_STENCIL 0x784E /* GEN8+ */
1815 # define GEN8_WM_DS_STENCIL_FAIL_OP_SHIFT 29
1816 # define GEN8_WM_DS_Z_FAIL_OP_SHIFT 26
1817 # define GEN8_WM_DS_Z_PASS_OP_SHIFT 23
1818 # define GEN8_WM_DS_BF_STENCIL_FUNC_SHIFT 20
1819 # define GEN8_WM_DS_BF_STENCIL_FAIL_OP_SHIFT 17
1820 # define GEN8_WM_DS_BF_Z_FAIL_OP_SHIFT 14
1821 # define GEN8_WM_DS_BF_Z_PASS_OP_SHIFT 11
1822 # define GEN8_WM_DS_STENCIL_FUNC_SHIFT 8
1823 # define GEN8_WM_DS_DEPTH_FUNC_SHIFT 5
1824 # define GEN8_WM_DS_DOUBLE_SIDED_STENCIL_ENABLE (1 << 4)
1825 # define GEN8_WM_DS_STENCIL_TEST_ENABLE (1 << 3)
1826 # define GEN8_WM_DS_STENCIL_BUFFER_WRITE_ENABLE (1 << 2)
1827 # define GEN8_WM_DS_DEPTH_TEST_ENABLE (1 << 1)
1828 # define GEN8_WM_DS_DEPTH_BUFFER_WRITE_ENABLE (1 << 0)
1830 # define GEN8_WM_DS_STENCIL_TEST_MASK_MASK INTEL_MASK(31, 24)
1831 # define GEN8_WM_DS_STENCIL_TEST_MASK_SHIFT 24
1832 # define GEN8_WM_DS_STENCIL_WRITE_MASK_MASK INTEL_MASK(23, 16)
1833 # define GEN8_WM_DS_STENCIL_WRITE_MASK_SHIFT 16
1834 # define GEN8_WM_DS_BF_STENCIL_TEST_MASK_MASK INTEL_MASK(15, 8)
1835 # define GEN8_WM_DS_BF_STENCIL_TEST_MASK_SHIFT 8
1836 # define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_MASK INTEL_MASK(7, 0)
1837 # define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_SHIFT 0
1839 #define _3DSTATE_PS_EXTRA 0x784F /* GEN8+ */
1841 # define GEN8_PSX_PIXEL_SHADER_VALID (1 << 31)
1842 # define GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE (1 << 30)
1843 # define GEN8_PSX_OMASK_TO_RENDER_TARGET (1 << 29)
1844 # define GEN8_PSX_KILL_ENABLE (1 << 28)
1845 # define GEN8_PSX_PSCDEPTH_OFF (0 << 26)
1846 # define GEN8_PSX_PSCDEPTH_ON (1 << 26)
1847 # define GEN8_PSX_PSCDEPTH_ON_GE (2 << 26)
1848 # define GEN8_PSX_PSCDEPTH_ON_LE (3 << 26)
1849 # define GEN8_PSX_FORCE_COMPUTED_DEPTH (1 << 25)
1850 # define GEN8_PSX_USES_SOURCE_DEPTH (1 << 24)
1851 # define GEN8_PSX_USES_SOURCE_W (1 << 23)
1852 # define GEN8_PSX_ATTRIBUTE_ENABLE (1 << 8)
1853 # define GEN8_PSX_SHADER_DISABLES_ALPHA_TO_COVERAGE (1 << 7)
1854 # define GEN8_PSX_SHADER_IS_PER_SAMPLE (1 << 6)
1855 # define GEN8_PSX_SHADER_COMPUTES_STENCIL (1 << 5)
1856 # define GEN8_PSX_SHADER_HAS_UAV (1 << 2)
1857 # define GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK (1 << 1)
1859 enum brw_wm_barycentric_interp_mode
{
1860 BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
= 0,
1861 BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
= 1,
1862 BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
= 2,
1863 BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
= 3,
1864 BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
= 4,
1865 BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
= 5,
1866 BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
= 6
1868 #define BRW_WM_NONPERSPECTIVE_BARYCENTRIC_BITS \
1869 ((1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC) | \
1870 (1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC) | \
1871 (1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC))
1873 #define _3DSTATE_WM 0x7814 /* GEN6+ */
1874 /* DW1: kernel pointer */
1876 # define GEN6_WM_SPF_MODE (1 << 31)
1877 # define GEN6_WM_VECTOR_MASK_ENABLE (1 << 30)
1878 # define GEN6_WM_SAMPLER_COUNT_SHIFT 27
1879 # define GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT 18
1880 # define GEN6_WM_FLOATING_POINT_MODE_IEEE_754 (0 << 16)
1881 # define GEN6_WM_FLOATING_POINT_MODE_ALT (1 << 16)
1882 /* DW3: scratch space */
1884 # define GEN6_WM_STATISTICS_ENABLE (1 << 31)
1885 # define GEN6_WM_DEPTH_CLEAR (1 << 30)
1886 # define GEN6_WM_DEPTH_RESOLVE (1 << 28)
1887 # define GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE (1 << 27)
1888 # define GEN6_WM_DISPATCH_START_GRF_SHIFT_0 16
1889 # define GEN6_WM_DISPATCH_START_GRF_SHIFT_1 8
1890 # define GEN6_WM_DISPATCH_START_GRF_SHIFT_2 0
1892 # define GEN6_WM_MAX_THREADS_SHIFT 25
1893 # define GEN6_WM_KILL_ENABLE (1 << 22)
1894 # define GEN6_WM_COMPUTED_DEPTH (1 << 21)
1895 # define GEN6_WM_USES_SOURCE_DEPTH (1 << 20)
1896 # define GEN6_WM_DISPATCH_ENABLE (1 << 19)
1897 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5 (0 << 16)
1898 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_1_0 (1 << 16)
1899 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_2_0 (2 << 16)
1900 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_4_0 (3 << 16)
1901 # define GEN6_WM_LINE_AA_WIDTH_0_5 (0 << 14)
1902 # define GEN6_WM_LINE_AA_WIDTH_1_0 (1 << 14)
1903 # define GEN6_WM_LINE_AA_WIDTH_2_0 (2 << 14)
1904 # define GEN6_WM_LINE_AA_WIDTH_4_0 (3 << 14)
1905 # define GEN6_WM_POLYGON_STIPPLE_ENABLE (1 << 13)
1906 # define GEN6_WM_LINE_STIPPLE_ENABLE (1 << 11)
1907 # define GEN6_WM_OMASK_TO_RENDER_TARGET (1 << 9)
1908 # define GEN6_WM_USES_SOURCE_W (1 << 8)
1909 # define GEN6_WM_DUAL_SOURCE_BLEND_ENABLE (1 << 7)
1910 # define GEN6_WM_32_DISPATCH_ENABLE (1 << 2)
1911 # define GEN6_WM_16_DISPATCH_ENABLE (1 << 1)
1912 # define GEN6_WM_8_DISPATCH_ENABLE (1 << 0)
1914 # define GEN6_WM_NUM_SF_OUTPUTS_SHIFT 20
1915 # define GEN6_WM_POSOFFSET_NONE (0 << 18)
1916 # define GEN6_WM_POSOFFSET_CENTROID (2 << 18)
1917 # define GEN6_WM_POSOFFSET_SAMPLE (3 << 18)
1918 # define GEN6_WM_POSITION_ZW_PIXEL (0 << 16)
1919 # define GEN6_WM_POSITION_ZW_CENTROID (2 << 16)
1920 # define GEN6_WM_POSITION_ZW_SAMPLE (3 << 16)
1921 # define GEN6_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 15)
1922 # define GEN6_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 14)
1923 # define GEN6_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 13)
1924 # define GEN6_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 12)
1925 # define GEN6_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 11)
1926 # define GEN6_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 10)
1927 # define GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT 10
1928 # define GEN6_WM_POINT_RASTRULE_UPPER_RIGHT (1 << 9)
1929 # define GEN6_WM_MSRAST_OFF_PIXEL (0 << 1)
1930 # define GEN6_WM_MSRAST_OFF_PATTERN (1 << 1)
1931 # define GEN6_WM_MSRAST_ON_PIXEL (2 << 1)
1932 # define GEN6_WM_MSRAST_ON_PATTERN (3 << 1)
1933 # define GEN6_WM_MSDISPMODE_PERSAMPLE (0 << 0)
1934 # define GEN6_WM_MSDISPMODE_PERPIXEL (1 << 0)
1935 /* DW7: kernel 1 pointer */
1936 /* DW8: kernel 2 pointer */
1938 #define _3DSTATE_CONSTANT_VS 0x7815 /* GEN6+ */
1939 #define _3DSTATE_CONSTANT_GS 0x7816 /* GEN6+ */
1940 #define _3DSTATE_CONSTANT_PS 0x7817 /* GEN6+ */
1941 # define GEN6_CONSTANT_BUFFER_3_ENABLE (1 << 15)
1942 # define GEN6_CONSTANT_BUFFER_2_ENABLE (1 << 14)
1943 # define GEN6_CONSTANT_BUFFER_1_ENABLE (1 << 13)
1944 # define GEN6_CONSTANT_BUFFER_0_ENABLE (1 << 12)
1946 #define _3DSTATE_CONSTANT_HS 0x7819 /* GEN7+ */
1947 #define _3DSTATE_CONSTANT_DS 0x781A /* GEN7+ */
1949 #define _3DSTATE_STREAMOUT 0x781e /* GEN7+ */
1951 # define SO_FUNCTION_ENABLE (1 << 31)
1952 # define SO_RENDERING_DISABLE (1 << 30)
1953 /* This selects which incoming rendering stream goes down the pipeline. The
1954 * rendering stream is 0 if not defined by special cases in the GS state.
1956 # define SO_RENDER_STREAM_SELECT_SHIFT 27
1957 # define SO_RENDER_STREAM_SELECT_MASK INTEL_MASK(28, 27)
1958 /* Controls reordering of TRISTRIP_* elements in stream output (not rendering).
1960 # define SO_REORDER_TRAILING (1 << 26)
1961 /* Controls SO_NUM_PRIMS_WRITTEN_* and SO_PRIM_STORAGE_* */
1962 # define SO_STATISTICS_ENABLE (1 << 25)
1963 # define SO_BUFFER_ENABLE(n) (1 << (8 + (n)))
1965 # define SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT 29
1966 # define SO_STREAM_3_VERTEX_READ_OFFSET_MASK INTEL_MASK(29, 29)
1967 # define SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT 24
1968 # define SO_STREAM_3_VERTEX_READ_LENGTH_MASK INTEL_MASK(28, 24)
1969 # define SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT 21
1970 # define SO_STREAM_2_VERTEX_READ_OFFSET_MASK INTEL_MASK(21, 21)
1971 # define SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT 16
1972 # define SO_STREAM_2_VERTEX_READ_LENGTH_MASK INTEL_MASK(20, 16)
1973 # define SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT 13
1974 # define SO_STREAM_1_VERTEX_READ_OFFSET_MASK INTEL_MASK(13, 13)
1975 # define SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT 8
1976 # define SO_STREAM_1_VERTEX_READ_LENGTH_MASK INTEL_MASK(12, 8)
1977 # define SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT 5
1978 # define SO_STREAM_0_VERTEX_READ_OFFSET_MASK INTEL_MASK(5, 5)
1979 # define SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT 0
1980 # define SO_STREAM_0_VERTEX_READ_LENGTH_MASK INTEL_MASK(4, 0)
1982 /* 3DSTATE_WM for Gen7 */
1984 # define GEN7_WM_STATISTICS_ENABLE (1 << 31)
1985 # define GEN7_WM_DEPTH_CLEAR (1 << 30)
1986 # define GEN7_WM_DISPATCH_ENABLE (1 << 29)
1987 # define GEN7_WM_DEPTH_RESOLVE (1 << 28)
1988 # define GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE (1 << 27)
1989 # define GEN7_WM_KILL_ENABLE (1 << 25)
1990 # define GEN7_WM_PSCDEPTH_OFF (0 << 23)
1991 # define GEN7_WM_PSCDEPTH_ON (1 << 23)
1992 # define GEN7_WM_PSCDEPTH_ON_GE (2 << 23)
1993 # define GEN7_WM_PSCDEPTH_ON_LE (3 << 23)
1994 # define GEN7_WM_USES_SOURCE_DEPTH (1 << 20)
1995 # define GEN7_WM_USES_SOURCE_W (1 << 19)
1996 # define GEN7_WM_POSITION_ZW_PIXEL (0 << 17)
1997 # define GEN7_WM_POSITION_ZW_CENTROID (2 << 17)
1998 # define GEN7_WM_POSITION_ZW_SAMPLE (3 << 17)
1999 # define GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT 11
2000 # define GEN7_WM_USES_INPUT_COVERAGE_MASK (1 << 10)
2001 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5 (0 << 8)
2002 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_1_0 (1 << 8)
2003 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_2_0 (2 << 8)
2004 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_4_0 (3 << 8)
2005 # define GEN7_WM_LINE_AA_WIDTH_0_5 (0 << 6)
2006 # define GEN7_WM_LINE_AA_WIDTH_1_0 (1 << 6)
2007 # define GEN7_WM_LINE_AA_WIDTH_2_0 (2 << 6)
2008 # define GEN7_WM_LINE_AA_WIDTH_4_0 (3 << 6)
2009 # define GEN7_WM_POLYGON_STIPPLE_ENABLE (1 << 4)
2010 # define GEN7_WM_LINE_STIPPLE_ENABLE (1 << 3)
2011 # define GEN7_WM_POINT_RASTRULE_UPPER_RIGHT (1 << 2)
2012 # define GEN7_WM_MSRAST_OFF_PIXEL (0 << 0)
2013 # define GEN7_WM_MSRAST_OFF_PATTERN (1 << 0)
2014 # define GEN7_WM_MSRAST_ON_PIXEL (2 << 0)
2015 # define GEN7_WM_MSRAST_ON_PATTERN (3 << 0)
2017 # define GEN7_WM_MSDISPMODE_PERSAMPLE (0 << 31)
2018 # define GEN7_WM_MSDISPMODE_PERPIXEL (1 << 31)
2020 #define _3DSTATE_PS 0x7820 /* GEN7+ */
2021 /* DW1: kernel pointer */
2023 # define GEN7_PS_SPF_MODE (1 << 31)
2024 # define GEN7_PS_VECTOR_MASK_ENABLE (1 << 30)
2025 # define GEN7_PS_SAMPLER_COUNT_SHIFT 27
2026 # define GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18
2027 # define GEN7_PS_FLOATING_POINT_MODE_IEEE_754 (0 << 16)
2028 # define GEN7_PS_FLOATING_POINT_MODE_ALT (1 << 16)
2029 /* DW3: scratch space */
2031 # define IVB_PS_MAX_THREADS_SHIFT 24
2032 # define HSW_PS_MAX_THREADS_SHIFT 23
2033 # define HSW_PS_SAMPLE_MASK_SHIFT 12
2034 # define HSW_PS_SAMPLE_MASK_MASK INTEL_MASK(19, 12)
2035 # define GEN7_PS_PUSH_CONSTANT_ENABLE (1 << 11)
2036 # define GEN7_PS_ATTRIBUTE_ENABLE (1 << 10)
2037 # define GEN7_PS_OMASK_TO_RENDER_TARGET (1 << 9)
2038 # define GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE (1 << 8)
2039 # define GEN7_PS_DUAL_SOURCE_BLEND_ENABLE (1 << 7)
2040 # define GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE (1 << 6)
2041 # define GEN7_PS_POSOFFSET_NONE (0 << 3)
2042 # define GEN7_PS_POSOFFSET_CENTROID (2 << 3)
2043 # define GEN7_PS_POSOFFSET_SAMPLE (3 << 3)
2044 # define GEN7_PS_32_DISPATCH_ENABLE (1 << 2)
2045 # define GEN7_PS_16_DISPATCH_ENABLE (1 << 1)
2046 # define GEN7_PS_8_DISPATCH_ENABLE (1 << 0)
2048 # define GEN7_PS_DISPATCH_START_GRF_SHIFT_0 16
2049 # define GEN7_PS_DISPATCH_START_GRF_SHIFT_1 8
2050 # define GEN7_PS_DISPATCH_START_GRF_SHIFT_2 0
2051 /* DW6: kernel 1 pointer */
2052 /* DW7: kernel 2 pointer */
2054 #define _3DSTATE_SAMPLE_MASK 0x7818 /* GEN6+ */
2056 #define _3DSTATE_DRAWING_RECTANGLE 0x7900
2057 #define _3DSTATE_BLEND_CONSTANT_COLOR 0x7901
2058 #define _3DSTATE_CHROMA_KEY 0x7904
2059 #define _3DSTATE_DEPTH_BUFFER 0x7905 /* GEN4-6 */
2060 #define _3DSTATE_POLY_STIPPLE_OFFSET 0x7906
2061 #define _3DSTATE_POLY_STIPPLE_PATTERN 0x7907
2062 #define _3DSTATE_LINE_STIPPLE_PATTERN 0x7908
2063 #define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x7909
2064 #define _3DSTATE_AA_LINE_PARAMETERS 0x790a /* G45+ */
2066 #define _3DSTATE_GS_SVB_INDEX 0x790b /* CTG+ */
2068 # define SVB_INDEX_SHIFT 29
2069 # define SVB_LOAD_INTERNAL_VERTEX_COUNT (1 << 0) /* SNB+ */
2070 /* DW2: SVB index */
2071 /* DW3: SVB maximum index */
2073 #define _3DSTATE_MULTISAMPLE 0x790d /* GEN6+ */
2074 #define GEN8_3DSTATE_MULTISAMPLE 0x780d /* GEN8+ */
2076 # define MS_PIXEL_LOCATION_CENTER (0 << 4)
2077 # define MS_PIXEL_LOCATION_UPPER_LEFT (1 << 4)
2078 # define MS_NUMSAMPLES_1 (0 << 1)
2079 # define MS_NUMSAMPLES_2 (1 << 1)
2080 # define MS_NUMSAMPLES_4 (2 << 1)
2081 # define MS_NUMSAMPLES_8 (3 << 1)
2082 # define MS_NUMSAMPLES_16 (4 << 1)
2084 #define _3DSTATE_SAMPLE_PATTERN 0x791c
2086 #define _3DSTATE_STENCIL_BUFFER 0x790e /* ILK, SNB */
2087 #define _3DSTATE_HIER_DEPTH_BUFFER 0x790f /* ILK, SNB */
2089 #define GEN7_3DSTATE_CLEAR_PARAMS 0x7804
2090 #define GEN7_3DSTATE_DEPTH_BUFFER 0x7805
2091 #define GEN7_3DSTATE_STENCIL_BUFFER 0x7806
2092 # define HSW_STENCIL_ENABLED (1 << 31)
2093 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER 0x7807
2095 #define _3DSTATE_CLEAR_PARAMS 0x7910 /* ILK, SNB */
2096 # define GEN5_DEPTH_CLEAR_VALID (1 << 15)
2097 /* DW1: depth clear value */
2099 # define GEN7_DEPTH_CLEAR_VALID (1 << 0)
2101 #define _3DSTATE_SO_DECL_LIST 0x7917 /* GEN7+ */
2103 # define SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT 12
2104 # define SO_STREAM_TO_BUFFER_SELECTS_3_MASK INTEL_MASK(15, 12)
2105 # define SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT 8
2106 # define SO_STREAM_TO_BUFFER_SELECTS_2_MASK INTEL_MASK(11, 8)
2107 # define SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT 4
2108 # define SO_STREAM_TO_BUFFER_SELECTS_1_MASK INTEL_MASK(7, 4)
2109 # define SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT 0
2110 # define SO_STREAM_TO_BUFFER_SELECTS_0_MASK INTEL_MASK(3, 0)
2112 # define SO_NUM_ENTRIES_3_SHIFT 24
2113 # define SO_NUM_ENTRIES_3_MASK INTEL_MASK(31, 24)
2114 # define SO_NUM_ENTRIES_2_SHIFT 16
2115 # define SO_NUM_ENTRIES_2_MASK INTEL_MASK(23, 16)
2116 # define SO_NUM_ENTRIES_1_SHIFT 8
2117 # define SO_NUM_ENTRIES_1_MASK INTEL_MASK(15, 8)
2118 # define SO_NUM_ENTRIES_0_SHIFT 0
2119 # define SO_NUM_ENTRIES_0_MASK INTEL_MASK(7, 0)
2122 # define SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT 12
2123 # define SO_DECL_OUTPUT_BUFFER_SLOT_MASK INTEL_MASK(13, 12)
2124 # define SO_DECL_HOLE_FLAG (1 << 11)
2125 # define SO_DECL_REGISTER_INDEX_SHIFT 4
2126 # define SO_DECL_REGISTER_INDEX_MASK INTEL_MASK(9, 4)
2127 # define SO_DECL_COMPONENT_MASK_SHIFT 0
2128 # define SO_DECL_COMPONENT_MASK_MASK INTEL_MASK(3, 0)
2130 #define _3DSTATE_SO_BUFFER 0x7918 /* GEN7+ */
2132 # define GEN8_SO_BUFFER_ENABLE (1 << 31)
2133 # define SO_BUFFER_INDEX_SHIFT 29
2134 # define SO_BUFFER_INDEX_MASK INTEL_MASK(30, 29)
2135 # define GEN8_SO_BUFFER_OFFSET_WRITE_ENABLE (1 << 21)
2136 # define GEN8_SO_BUFFER_OFFSET_ADDRESS_ENABLE (1 << 20)
2137 # define SO_BUFFER_PITCH_SHIFT 0
2138 # define SO_BUFFER_PITCH_MASK INTEL_MASK(11, 0)
2139 /* DW2: start address */
2140 /* DW3: end address. */
2142 #define CMD_MI_FLUSH 0x0200
2144 # define BLT_X_SHIFT 0
2145 # define BLT_X_MASK INTEL_MASK(15, 0)
2146 # define BLT_Y_SHIFT 16
2147 # define BLT_Y_MASK INTEL_MASK(31, 16)
2149 #define GEN5_MI_REPORT_PERF_COUNT ((0x26 << 23) | (3 - 2))
2151 # define GEN5_MI_COUNTER_SET_0 (0 << 6)
2152 # define GEN5_MI_COUNTER_SET_1 (1 << 6)
2154 # define MI_COUNTER_ADDRESS_GTT (1 << 0)
2155 /* DW2: a user-defined report ID (written to the buffer but can be anything) */
2157 #define GEN6_MI_REPORT_PERF_COUNT ((0x28 << 23) | (3 - 2))
2159 /* Bitfields for the URB_WRITE message, DW2 of message header: */
2160 #define URB_WRITE_PRIM_END 0x1
2161 #define URB_WRITE_PRIM_START 0x2
2162 #define URB_WRITE_PRIM_TYPE_SHIFT 2
2165 /* Maximum number of entries that can be addressed using a binding table
2166 * pointer of type SURFTYPE_BUFFER
2168 #define BRW_MAX_NUM_BUFFER_ENTRIES (1 << 27)
2170 /* Memory Object Control State:
2171 * Specifying zero for L3 means "uncached in L3", at least on Haswell
2172 * and Baytrail, since there are no PTE flags for setting L3 cacheability.
2173 * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
2174 * may still respect that.
2176 #define GEN7_MOCS_L3 1
2178 /* Ivybridge only: cache in LLC.
2179 * Specifying zero here means to use the PTE values set by the kernel;
2180 * non-zero overrides the PTE values.
2182 #define IVB_MOCS_LLC (1 << 1)
2184 /* Baytrail only: snoop in CPU cache */
2185 #define BYT_MOCS_SNOOP (1 << 1)
2187 /* Haswell only: LLC/eLLC controls (write-back or uncached).
2188 * Specifying zero here means to use the PTE values set by the kernel,
2189 * which is useful since it offers additional control (write-through
2190 * cacheing and age). Non-zero overrides the PTE values.
2192 #define HSW_MOCS_UC_LLC_UC_ELLC (1 << 1)
2193 #define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1)
2194 #define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1)
2196 #include "intel_chipset.h"