2 * Copyright © 2013 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_device_info.h"
28 static const struct brw_device_info brw_device_info_i965
= {
30 .has_negative_rhw_bug
= true,
33 .max_wm_threads
= 8 * 4,
39 static const struct brw_device_info brw_device_info_g4x
= {
43 .has_surface_tile_offset
= true,
47 .max_wm_threads
= 10 * 5,
53 static const struct brw_device_info brw_device_info_ilk
= {
57 .has_surface_tile_offset
= true,
60 .max_wm_threads
= 12 * 6,
66 static const struct brw_device_info brw_device_info_snb_gt1
= {
69 .has_hiz_and_separate_stencil
= true,
72 .has_surface_tile_offset
= true,
73 .needs_unlit_centroid_workaround
= true,
75 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
80 .max_vs_entries
= 256,
81 .max_gs_entries
= 256,
85 static const struct brw_device_info brw_device_info_snb_gt2
= {
88 .has_hiz_and_separate_stencil
= true,
91 .has_surface_tile_offset
= true,
92 .needs_unlit_centroid_workaround
= true,
99 .max_vs_entries
= 256,
100 .max_gs_entries
= 256,
104 #define GEN7_FEATURES \
106 .has_hiz_and_separate_stencil = true, \
107 .must_use_separate_stencil = true, \
110 .has_surface_tile_offset = true
112 static const struct brw_device_info brw_device_info_ivb_gt1
= {
113 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
114 .needs_unlit_centroid_workaround
= true,
115 .max_vs_threads
= 36,
116 .max_hs_threads
= 36,
117 .max_ds_threads
= 36,
118 .max_gs_threads
= 36,
119 .max_wm_threads
= 48,
122 .min_vs_entries
= 32,
123 .max_vs_entries
= 512,
124 .max_hs_entries
= 32,
125 .max_ds_entries
= 288,
126 .max_gs_entries
= 192,
130 static const struct brw_device_info brw_device_info_ivb_gt2
= {
131 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
132 .needs_unlit_centroid_workaround
= true,
133 .max_vs_threads
= 128,
134 .max_hs_threads
= 128,
135 .max_ds_threads
= 128,
136 .max_gs_threads
= 128,
137 .max_wm_threads
= 172,
140 .min_vs_entries
= 32,
141 .max_vs_entries
= 704,
142 .max_hs_entries
= 64,
143 .max_ds_entries
= 448,
144 .max_gs_entries
= 320,
148 static const struct brw_device_info brw_device_info_byt
= {
149 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
150 .needs_unlit_centroid_workaround
= true,
152 .max_vs_threads
= 36,
153 .max_hs_threads
= 36,
154 .max_ds_threads
= 36,
155 .max_gs_threads
= 36,
156 .max_wm_threads
= 48,
159 .min_vs_entries
= 32,
160 .max_vs_entries
= 512,
161 .max_hs_entries
= 32,
162 .max_ds_entries
= 288,
163 .max_gs_entries
= 192,
167 static const struct brw_device_info brw_device_info_hsw_gt1
= {
168 GEN7_FEATURES
, .is_haswell
= true, .gt
= 1,
169 .max_vs_threads
= 70,
170 .max_hs_threads
= 70,
171 .max_ds_threads
= 70,
172 .max_gs_threads
= 70,
173 .max_wm_threads
= 102,
176 .min_vs_entries
= 32,
177 .max_vs_entries
= 640,
178 .max_hs_entries
= 64,
179 .max_ds_entries
= 384,
180 .max_gs_entries
= 256,
184 static const struct brw_device_info brw_device_info_hsw_gt2
= {
185 GEN7_FEATURES
, .is_haswell
= true, .gt
= 2,
186 .max_vs_threads
= 280,
187 .max_hs_threads
= 256,
188 .max_ds_threads
= 280,
189 .max_gs_threads
= 256,
190 .max_wm_threads
= 204,
193 .min_vs_entries
= 64,
194 .max_vs_entries
= 1664,
195 .max_hs_entries
= 128,
196 .max_ds_entries
= 960,
197 .max_gs_entries
= 640,
201 static const struct brw_device_info brw_device_info_hsw_gt3
= {
202 GEN7_FEATURES
, .is_haswell
= true, .gt
= 3,
203 .max_vs_threads
= 280,
204 .max_hs_threads
= 256,
205 .max_ds_threads
= 280,
206 .max_gs_threads
= 256,
207 .max_wm_threads
= 408,
210 .min_vs_entries
= 64,
211 .max_vs_entries
= 1664,
212 .max_hs_entries
= 128,
213 .max_ds_entries
= 960,
214 .max_gs_entries
= 640,
218 #define GEN8_FEATURES \
220 .has_hiz_and_separate_stencil = true, \
221 .must_use_separate_stencil = true, \
224 .max_vs_threads = 504, \
225 .max_hs_threads = 504, \
226 .max_ds_threads = 504, \
227 .max_gs_threads = 504, \
228 .max_wm_threads = 384 \
230 static const struct brw_device_info brw_device_info_bdw_gt1 = {
231 GEN8_FEATURES
, .gt
= 1,
234 .min_vs_entries
= 64,
235 .max_vs_entries
= 2560,
236 .max_hs_entries
= 504,
237 .max_ds_entries
= 1536,
238 .max_gs_entries
= 960,
242 static const struct brw_device_info brw_device_info_bdw_gt2
= {
243 GEN8_FEATURES
, .gt
= 2,
246 .min_vs_entries
= 64,
247 .max_vs_entries
= 2560,
248 .max_hs_entries
= 504,
249 .max_ds_entries
= 1536,
250 .max_gs_entries
= 960,
254 static const struct brw_device_info brw_device_info_bdw_gt3
= {
255 GEN8_FEATURES
, .gt
= 3,
258 .min_vs_entries
= 64,
259 .max_vs_entries
= 2560,
260 .max_hs_entries
= 504,
261 .max_ds_entries
= 1536,
262 .max_gs_entries
= 960,
266 /* Thread counts and URB limits are placeholders, and may not be accurate.
267 * These were copied from Haswell GT1, above.
269 static const struct brw_device_info brw_device_info_chv
= {
270 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
272 .max_vs_threads
= 80,
273 .max_hs_threads
= 80,
274 .max_ds_threads
= 80,
275 .max_gs_threads
= 80,
276 .max_wm_threads
= 128,
279 .min_vs_entries
= 34,
280 .max_vs_entries
= 640,
281 .max_hs_entries
= 80,
282 .max_ds_entries
= 384,
283 .max_gs_entries
= 256,
287 /* Thread counts and URB limits are placeholders, and may not be accurate. */
288 #define GEN9_FEATURES \
290 .has_hiz_and_separate_stencil = true, \
291 .must_use_separate_stencil = true, \
294 .max_vs_threads = 280, \
295 .max_gs_threads = 256, \
296 .max_wm_threads = 408, \
299 .min_vs_entries = 64, \
300 .max_vs_entries = 1664, \
301 .max_gs_entries = 640, \
304 static const struct brw_device_info brw_device_info_skl_gt1
= {
305 GEN9_FEATURES
, .gt
= 1
308 static const struct brw_device_info brw_device_info_skl_gt2
= {
309 GEN9_FEATURES
, .gt
= 2
312 static const struct brw_device_info brw_device_info_skl_gt3
= {
313 GEN9_FEATURES
, .gt
= 3
316 const struct brw_device_info
*
317 brw_get_device_info(int devid
)
321 #define CHIPSET(id, family, name) case id: return &brw_device_info_##family;
322 #include "pci_ids/i965_pci_ids.h"
324 fprintf(stderr
, "i965_dri.so does not support the 0x%x PCI ID.\n", devid
);