src/mesa/drivers/dri/i965/brw_device_info.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdio.h>
  25 #include <stdlib.h>
  26 #include "brw_device_info.h"
  27
  28 static const struct brw_device_info brw_device_info_i965 = {
  29    .gen = 4,
  30    .has_negative_rhw_bug = true,
  31    .max_vs_threads = 16,
  32    .max_gs_threads = 2,
  33    .max_wm_threads = 8 * 4,
  34    .urb = {
  35       .size = 256,
  36    },
  37 };
  38
  39 static const struct brw_device_info brw_device_info_g4x = {
  40    .gen = 4,
  41    .has_pln = true,
  42    .has_compr4 = true,
  43    .has_surface_tile_offset = true,
  44    .is_g4x = true,
  45    .max_vs_threads = 32,
  46    .max_gs_threads = 2,
  47    .max_wm_threads = 10 * 5,
  48    .urb = {
  49       .size = 384,
  50    },
  51 };
  52
  53 static const struct brw_device_info brw_device_info_ilk = {
  54    .gen = 5,
  55    .has_pln = true,
  56    .has_compr4 = true,
  57    .has_surface_tile_offset = true,
  58    .max_vs_threads = 72,
  59    .max_gs_threads = 32,
  60    .max_wm_threads = 12 * 6,
  61    .urb = {
  62       .size = 1024,
  63    },
  64 };
  65
  66 static const struct brw_device_info brw_device_info_snb_gt1 = {
  67    .gen = 6,
  68    .gt = 1,
  69    .has_hiz_and_separate_stencil = true,
  70    .has_llc = true,
  71    .has_pln = true,
  72    .has_surface_tile_offset = true,
  73    .needs_unlit_centroid_workaround = true,
  74    .max_vs_threads = 24,
  75    .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
  76    .max_wm_threads = 40,
  77    .urb = {
  78       .size = 32,
  79       .min_vs_entries = 24,
  80       .max_vs_entries = 256,
  81       .max_gs_entries = 256,
  82    },
  83 };
  84
  85 static const struct brw_device_info brw_device_info_snb_gt2 = {
  86    .gen = 6,
  87    .gt = 2,
  88    .has_hiz_and_separate_stencil = true,
  89    .has_llc = true,
  90    .has_pln = true,
  91    .has_surface_tile_offset = true,
  92    .needs_unlit_centroid_workaround = true,
  93    .max_vs_threads = 60,
  94    .max_gs_threads = 60,
  95    .max_wm_threads = 80,
  96    .urb = {
  97       .size = 64,
  98       .min_vs_entries = 24,
  99       .max_vs_entries = 256,
 100       .max_gs_entries = 256,
 101    },
 102 };
 103
 104 #define GEN7_FEATURES                               \
 105    .gen = 7,                                        \
 106    .has_hiz_and_separate_stencil = true,            \
 107    .must_use_separate_stencil = true,               \
 108    .has_llc = true,                                 \
 109    .has_pln = true,                                 \
 110    .has_surface_tile_offset = true
 111
 112 static const struct brw_device_info brw_device_info_ivb_gt1 = {
 113    GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
 114    .needs_unlit_centroid_workaround = true,
 115    .max_vs_threads = 36,
 116    .max_gs_threads = 36,
 117    .max_wm_threads = 48,
 118    .urb = {
 119       .size = 128,
 120       .min_vs_entries = 32,
 121       .max_vs_entries = 512,
 122       .max_gs_entries = 192,
 123    },
 124 };
 125
 126 static const struct brw_device_info brw_device_info_ivb_gt2 = {
 127    GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
 128    .needs_unlit_centroid_workaround = true,
 129    .max_vs_threads = 128,
 130    .max_gs_threads = 128,
 131    .max_wm_threads = 172,
 132    .urb = {
 133       .size = 256,
 134       .min_vs_entries = 32,
 135       .max_vs_entries = 704,
 136       .max_gs_entries = 320,
 137    },
 138 };
 139
 140 static const struct brw_device_info brw_device_info_byt = {
 141    GEN7_FEATURES, .is_baytrail = true, .gt = 1,
 142    .needs_unlit_centroid_workaround = true,
 143    .has_llc = false,
 144    .max_vs_threads = 36,
 145    .max_gs_threads = 36,
 146    .max_wm_threads = 48,
 147    .urb = {
 148       .size = 128,
 149       .min_vs_entries = 32,
 150       .max_vs_entries = 512,
 151       .max_gs_entries = 192,
 152    },
 153 };
 154
 155 static const struct brw_device_info brw_device_info_hsw_gt1 = {
 156    GEN7_FEATURES, .is_haswell = true, .gt = 1,
 157    .max_vs_threads = 70,
 158    .max_gs_threads = 70,
 159    .max_wm_threads = 102,
 160    .urb = {
 161       .size = 128,
 162       .min_vs_entries = 32,
 163       .max_vs_entries = 640,
 164       .max_gs_entries = 256,
 165    },
 166 };
 167
 168 static const struct brw_device_info brw_device_info_hsw_gt2 = {
 169    GEN7_FEATURES, .is_haswell = true, .gt = 2,
 170    .max_vs_threads = 280,
 171    .max_gs_threads = 256,
 172    .max_wm_threads = 204,
 173    .urb = {
 174       .size = 256,
 175       .min_vs_entries = 64,
 176       .max_vs_entries = 1664,
 177       .max_gs_entries = 640,
 178    },
 179 };
 180
 181 static const struct brw_device_info brw_device_info_hsw_gt3 = {
 182    GEN7_FEATURES, .is_haswell = true, .gt = 3,
 183    .max_vs_threads = 280,
 184    .max_gs_threads = 256,
 185    .max_wm_threads = 408,
 186    .urb = {
 187       .size = 512,
 188       .min_vs_entries = 64,
 189       .max_vs_entries = 1664,
 190       .max_gs_entries = 640,
 191    },
 192 };
 193
 194 #define GEN8_FEATURES                               \
 195    .gen = 8,                                        \
 196    .has_hiz_and_separate_stencil = true,            \
 197    .must_use_separate_stencil = true,               \
 198    .has_llc = true,                                 \
 199    .has_pln = true,                                 \
 200    .max_vs_threads = 504,                           \
 201    .max_gs_threads = 504,                           \
 202    .max_wm_threads = 384                            \
 203
 204 static const struct brw_device_info brw_device_info_bdw_gt1 = {
 205    GEN8_FEATURES, .gt = 1,
 206    .urb = {
 207       .size = 192,
 208       .min_vs_entries = 64,
 209       .max_vs_entries = 2560,
 210       .max_gs_entries = 960,
 211    }
 212 };
 213
 214 static const struct brw_device_info brw_device_info_bdw_gt2 = {
 215    GEN8_FEATURES, .gt = 2,
 216    .urb = {
 217       .size = 384,
 218       .min_vs_entries = 64,
 219       .max_vs_entries = 2560,
 220       .max_gs_entries = 960,
 221    }
 222 };
 223
 224 static const struct brw_device_info brw_device_info_bdw_gt3 = {
 225    GEN8_FEATURES, .gt = 3,
 226    .urb = {
 227       .size = 384,
 228       .min_vs_entries = 64,
 229       .max_vs_entries = 2560,
 230       .max_gs_entries = 960,
 231    }
 232 };
 233
 234 /* Thread counts and URB limits are placeholders, and may not be accurate.
 235  * These were copied from Haswell GT1, above.
 236  */
 237 static const struct brw_device_info brw_device_info_chv = {
 238    GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
 239    .has_llc = false,
 240    .max_vs_threads = 80,
 241    .max_gs_threads = 80,
 242    .max_wm_threads = 102,
 243    .urb = {
 244       .size = 128,
 245       .min_vs_entries = 64,
 246       .max_vs_entries = 640,
 247       .max_gs_entries = 256,
 248    }
 249 };
 250
 251 /* Thread counts and URB limits are placeholders, and may not be accurate. */
 252 #define GEN9_FEATURES                               \
 253    .gen = 9,                                        \
 254    .has_hiz_and_separate_stencil = true,            \
 255    .must_use_separate_stencil = true,               \
 256    .has_llc = true,                                 \
 257    .has_pln = true,                                 \
 258    .max_vs_threads = 280,                           \
 259    .max_gs_threads = 256,                           \
 260    .max_wm_threads = 408,                           \
 261    .urb = {                                         \
 262       .size = 128,                                  \
 263       .min_vs_entries = 64,                         \
 264       .max_vs_entries = 1664,                       \
 265       .max_gs_entries = 640,                        \
 266    }
 267
 268 static const struct brw_device_info brw_device_info_skl_gt1 = {
 269    GEN9_FEATURES, .gt = 1
 270 };
 271
 272 static const struct brw_device_info brw_device_info_skl_gt2 = {
 273    GEN9_FEATURES, .gt = 2
 274 };
 275
 276 static const struct brw_device_info brw_device_info_skl_gt3 = {
 277    GEN9_FEATURES, .gt = 3
 278 };
 279
 280 const struct brw_device_info *
 281 brw_get_device_info(int devid)
 282 {
 283    switch (devid) {
 284 #undef CHIPSET
 285 #define CHIPSET(id, family, name) case id: return &brw_device_info_##family;
 286 #include "pci_ids/i965_pci_ids.h"
 287    default:
 288       fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
 289       return NULL;
 290    }
 291 }