2 * Copyright © 2013 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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26 #include "brw_device_info.h"
28 static const struct brw_device_info brw_device_info_i965
= {
30 .has_negative_rhw_bug
= true,
33 .max_wm_threads
= 8 * 4,
39 static const struct brw_device_info brw_device_info_g4x
= {
43 .has_surface_tile_offset
= true,
47 .max_wm_threads
= 10 * 5,
53 static const struct brw_device_info brw_device_info_ilk
= {
57 .has_surface_tile_offset
= true,
60 .max_wm_threads
= 12 * 6,
66 static const struct brw_device_info brw_device_info_snb_gt1
= {
69 .has_hiz_and_separate_stencil
= true,
72 .has_surface_tile_offset
= true,
73 .needs_unlit_centroid_workaround
= true,
75 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
80 .max_vs_entries
= 256,
81 .max_gs_entries
= 256,
85 static const struct brw_device_info brw_device_info_snb_gt2
= {
88 .has_hiz_and_separate_stencil
= true,
91 .has_surface_tile_offset
= true,
92 .needs_unlit_centroid_workaround
= true,
99 .max_vs_entries
= 256,
100 .max_gs_entries
= 256,
104 #define GEN7_FEATURES \
106 .has_hiz_and_separate_stencil = true, \
107 .must_use_separate_stencil = true, \
110 .has_surface_tile_offset = true
112 static const struct brw_device_info brw_device_info_ivb_gt1
= {
113 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
114 .needs_unlit_centroid_workaround
= true,
115 .max_vs_threads
= 36,
116 .max_hs_threads
= 36,
117 .max_ds_threads
= 36,
118 .max_gs_threads
= 36,
119 .max_wm_threads
= 48,
120 .max_cs_threads
= 36,
123 .min_vs_entries
= 32,
124 .max_vs_entries
= 512,
125 .max_hs_entries
= 32,
126 .max_ds_entries
= 288,
127 .max_gs_entries
= 192,
131 static const struct brw_device_info brw_device_info_ivb_gt2
= {
132 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
133 .needs_unlit_centroid_workaround
= true,
134 .max_vs_threads
= 128,
135 .max_hs_threads
= 128,
136 .max_ds_threads
= 128,
137 .max_gs_threads
= 128,
138 .max_wm_threads
= 172,
139 .max_cs_threads
= 64,
142 .min_vs_entries
= 32,
143 .max_vs_entries
= 704,
144 .max_hs_entries
= 64,
145 .max_ds_entries
= 448,
146 .max_gs_entries
= 320,
150 static const struct brw_device_info brw_device_info_byt
= {
151 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
152 .needs_unlit_centroid_workaround
= true,
154 .max_vs_threads
= 36,
155 .max_hs_threads
= 36,
156 .max_ds_threads
= 36,
157 .max_gs_threads
= 36,
158 .max_wm_threads
= 48,
159 .max_cs_threads
= 32,
162 .min_vs_entries
= 32,
163 .max_vs_entries
= 512,
164 .max_hs_entries
= 32,
165 .max_ds_entries
= 288,
166 .max_gs_entries
= 192,
170 #define HSW_FEATURES \
172 .is_haswell = true, \
173 .supports_simd16_3src = true
175 static const struct brw_device_info brw_device_info_hsw_gt1
= {
176 HSW_FEATURES
, .gt
= 1,
177 .max_vs_threads
= 70,
178 .max_hs_threads
= 70,
179 .max_ds_threads
= 70,
180 .max_gs_threads
= 70,
181 .max_wm_threads
= 102,
182 .max_cs_threads
= 70,
185 .min_vs_entries
= 32,
186 .max_vs_entries
= 640,
187 .max_hs_entries
= 64,
188 .max_ds_entries
= 384,
189 .max_gs_entries
= 256,
193 static const struct brw_device_info brw_device_info_hsw_gt2
= {
194 HSW_FEATURES
, .gt
= 2,
195 .max_vs_threads
= 280,
196 .max_hs_threads
= 256,
197 .max_ds_threads
= 280,
198 .max_gs_threads
= 256,
199 .max_wm_threads
= 204,
200 .max_cs_threads
= 70,
203 .min_vs_entries
= 64,
204 .max_vs_entries
= 1664,
205 .max_hs_entries
= 128,
206 .max_ds_entries
= 960,
207 .max_gs_entries
= 640,
211 static const struct brw_device_info brw_device_info_hsw_gt3
= {
212 HSW_FEATURES
, .gt
= 3,
213 .max_vs_threads
= 280,
214 .max_hs_threads
= 256,
215 .max_ds_threads
= 280,
216 .max_gs_threads
= 256,
217 .max_wm_threads
= 408,
218 .max_cs_threads
= 70,
221 .min_vs_entries
= 64,
222 .max_vs_entries
= 1664,
223 .max_hs_entries
= 128,
224 .max_ds_entries
= 960,
225 .max_gs_entries
= 640,
229 #define GEN8_FEATURES \
231 .has_hiz_and_separate_stencil = true, \
232 .must_use_separate_stencil = true, \
235 .supports_simd16_3src = true, \
236 .max_vs_threads = 504, \
237 .max_hs_threads = 504, \
238 .max_ds_threads = 504, \
239 .max_gs_threads = 504, \
240 .max_wm_threads = 384
242 static const struct brw_device_info brw_device_info_bdw_gt1
= {
243 GEN8_FEATURES
, .gt
= 1,
244 .max_cs_threads
= 42,
247 .min_vs_entries
= 64,
248 .max_vs_entries
= 2560,
249 .max_hs_entries
= 504,
250 .max_ds_entries
= 1536,
251 .max_gs_entries
= 960,
255 static const struct brw_device_info brw_device_info_bdw_gt2
= {
256 GEN8_FEATURES
, .gt
= 2,
257 .max_cs_threads
= 56,
260 .min_vs_entries
= 64,
261 .max_vs_entries
= 2560,
262 .max_hs_entries
= 504,
263 .max_ds_entries
= 1536,
264 .max_gs_entries
= 960,
268 static const struct brw_device_info brw_device_info_bdw_gt3
= {
269 GEN8_FEATURES
, .gt
= 3,
270 .max_cs_threads
= 56,
273 .min_vs_entries
= 64,
274 .max_vs_entries
= 2560,
275 .max_hs_entries
= 504,
276 .max_ds_entries
= 1536,
277 .max_gs_entries
= 960,
281 static const struct brw_device_info brw_device_info_chv
= {
282 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
284 .max_vs_threads
= 80,
285 .max_hs_threads
= 80,
286 .max_ds_threads
= 80,
287 .max_gs_threads
= 80,
288 .max_wm_threads
= 128,
289 .max_cs_threads
= 28,
292 .min_vs_entries
= 34,
293 .max_vs_entries
= 640,
294 .max_hs_entries
= 80,
295 .max_ds_entries
= 384,
296 .max_gs_entries
= 256,
300 /* Thread counts and URB limits are placeholders, and may not be accurate. */
301 #define GEN9_FEATURES \
303 .has_hiz_and_separate_stencil = true, \
304 .must_use_separate_stencil = true, \
307 .max_vs_threads = 280, \
308 .max_gs_threads = 256, \
309 .max_wm_threads = 408, \
312 .min_vs_entries = 64, \
313 .max_vs_entries = 1664, \
314 .max_gs_entries = 640, \
317 static const struct brw_device_info brw_device_info_skl_early
= {
318 GEN9_FEATURES
, .gt
= 1,
319 .supports_simd16_3src
= false,
322 static const struct brw_device_info brw_device_info_skl_gt1
= {
323 GEN9_FEATURES
, .gt
= 1,
324 .supports_simd16_3src
= true,
327 static const struct brw_device_info brw_device_info_skl_gt2
= {
328 GEN9_FEATURES
, .gt
= 2,
329 .supports_simd16_3src
= true,
332 static const struct brw_device_info brw_device_info_skl_gt3
= {
333 GEN9_FEATURES
, .gt
= 3,
334 .supports_simd16_3src
= true,
337 const struct brw_device_info
*
338 brw_get_device_info(int devid
, int revision
)
340 const struct brw_device_info
*devinfo
;
343 #define CHIPSET(id, family, name) \
344 case id: devinfo = &brw_device_info_##family; break;
345 #include "pci_ids/i965_pci_ids.h"
347 fprintf(stderr
, "i965_dri.so does not support the 0x%x PCI ID.\n", devid
);
351 if (devinfo
->gen
== 9 && (revision
== 2 || revision
== 3 || revision
== -1))
352 return &brw_device_info_skl_early
;
358 brw_get_device_name(int devid
)
362 #define CHIPSET(id, family, name) case id: return name;
363 #include "pci_ids/i965_pci_ids.h"