2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_device_info.h"
28 static const struct brw_device_info brw_device_info_i965
= {
30 .has_negative_rhw_bug
= true,
34 .max_wm_threads
= 8 * 4,
40 static const struct brw_device_info brw_device_info_g4x
= {
44 .has_surface_tile_offset
= true,
49 .max_wm_threads
= 10 * 5,
55 static const struct brw_device_info brw_device_info_ilk
= {
59 .has_surface_tile_offset
= true,
63 .max_wm_threads
= 12 * 6,
69 static const struct brw_device_info brw_device_info_snb_gt1
= {
72 .has_hiz_and_separate_stencil
= true,
75 .has_surface_tile_offset
= true,
76 .needs_unlit_centroid_workaround
= true,
79 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
84 .max_vs_entries
= 256,
85 .max_gs_entries
= 256,
89 static const struct brw_device_info brw_device_info_snb_gt2
= {
92 .has_hiz_and_separate_stencil
= true,
95 .has_surface_tile_offset
= true,
96 .needs_unlit_centroid_workaround
= true,
100 .max_wm_threads
= 80,
103 .min_vs_entries
= 24,
104 .max_vs_entries
= 256,
105 .max_gs_entries
= 256,
109 #define GEN7_FEATURES \
111 .has_hiz_and_separate_stencil = true, \
112 .must_use_separate_stencil = true, \
115 .has_surface_tile_offset = true
117 static const struct brw_device_info brw_device_info_ivb_gt1
= {
118 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
120 .max_vs_threads
= 36,
121 .max_hs_threads
= 36,
122 .max_ds_threads
= 36,
123 .max_gs_threads
= 36,
124 .max_wm_threads
= 48,
125 .max_cs_threads
= 36,
128 .min_vs_entries
= 32,
129 .max_vs_entries
= 512,
130 .max_hs_entries
= 32,
131 .min_ds_entries
= 10,
132 .max_ds_entries
= 288,
133 .max_gs_entries
= 192,
137 static const struct brw_device_info brw_device_info_ivb_gt2
= {
138 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
140 .max_vs_threads
= 128,
141 .max_hs_threads
= 128,
142 .max_ds_threads
= 128,
143 .max_gs_threads
= 128,
144 .max_wm_threads
= 172,
145 .max_cs_threads
= 64,
148 .min_vs_entries
= 32,
149 .max_vs_entries
= 704,
150 .max_hs_entries
= 64,
151 .min_ds_entries
= 10,
152 .max_ds_entries
= 448,
153 .max_gs_entries
= 320,
157 static const struct brw_device_info brw_device_info_byt
= {
158 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
161 .max_vs_threads
= 36,
162 .max_hs_threads
= 36,
163 .max_ds_threads
= 36,
164 .max_gs_threads
= 36,
165 .max_wm_threads
= 48,
166 .max_cs_threads
= 32,
169 .min_vs_entries
= 32,
170 .max_vs_entries
= 512,
171 .max_hs_entries
= 32,
172 .min_ds_entries
= 10,
173 .max_ds_entries
= 288,
174 .max_gs_entries
= 192,
178 #define HSW_FEATURES \
180 .is_haswell = true, \
181 .supports_simd16_3src = true, \
182 .has_resource_streamer = true
184 static const struct brw_device_info brw_device_info_hsw_gt1
= {
185 HSW_FEATURES
, .gt
= 1,
187 .max_vs_threads
= 70,
188 .max_hs_threads
= 70,
189 .max_ds_threads
= 70,
190 .max_gs_threads
= 70,
191 .max_wm_threads
= 102,
192 .max_cs_threads
= 70,
195 .min_vs_entries
= 32,
196 .max_vs_entries
= 640,
197 .max_hs_entries
= 64,
198 .min_ds_entries
= 10,
199 .max_ds_entries
= 384,
200 .max_gs_entries
= 256,
204 static const struct brw_device_info brw_device_info_hsw_gt2
= {
205 HSW_FEATURES
, .gt
= 2,
207 .max_vs_threads
= 280,
208 .max_hs_threads
= 256,
209 .max_ds_threads
= 280,
210 .max_gs_threads
= 256,
211 .max_wm_threads
= 204,
212 .max_cs_threads
= 70,
215 .min_vs_entries
= 64,
216 .max_vs_entries
= 1664,
217 .max_hs_entries
= 128,
218 .min_ds_entries
= 10,
219 .max_ds_entries
= 960,
220 .max_gs_entries
= 640,
224 static const struct brw_device_info brw_device_info_hsw_gt3
= {
225 HSW_FEATURES
, .gt
= 3,
227 .max_vs_threads
= 280,
228 .max_hs_threads
= 256,
229 .max_ds_threads
= 280,
230 .max_gs_threads
= 256,
231 .max_wm_threads
= 408,
232 .max_cs_threads
= 70,
235 .min_vs_entries
= 64,
236 .max_vs_entries
= 1664,
237 .max_hs_entries
= 128,
238 .min_ds_entries
= 10,
239 .max_ds_entries
= 960,
240 .max_gs_entries
= 640,
244 #define GEN8_FEATURES \
246 .has_hiz_and_separate_stencil = true, \
247 .has_resource_streamer = true, \
248 .must_use_separate_stencil = true, \
251 .supports_simd16_3src = true, \
252 .max_vs_threads = 504, \
253 .max_hs_threads = 504, \
254 .max_ds_threads = 504, \
255 .max_gs_threads = 504, \
256 .max_wm_threads = 384
258 static const struct brw_device_info brw_device_info_bdw_gt1
= {
259 GEN8_FEATURES
, .gt
= 1,
261 .max_cs_threads
= 42,
264 .min_vs_entries
= 64,
265 .max_vs_entries
= 2560,
266 .max_hs_entries
= 504,
267 .min_ds_entries
= 34,
268 .max_ds_entries
= 1536,
269 .max_gs_entries
= 960,
273 static const struct brw_device_info brw_device_info_bdw_gt2
= {
274 GEN8_FEATURES
, .gt
= 2,
276 .max_cs_threads
= 56,
279 .min_vs_entries
= 64,
280 .max_vs_entries
= 2560,
281 .max_hs_entries
= 504,
282 .min_ds_entries
= 34,
283 .max_ds_entries
= 1536,
284 .max_gs_entries
= 960,
288 static const struct brw_device_info brw_device_info_bdw_gt3
= {
289 GEN8_FEATURES
, .gt
= 3,
291 .max_cs_threads
= 56,
294 .min_vs_entries
= 64,
295 .max_vs_entries
= 2560,
296 .max_hs_entries
= 504,
297 .min_ds_entries
= 34,
298 .max_ds_entries
= 1536,
299 .max_gs_entries
= 960,
303 static const struct brw_device_info brw_device_info_chv
= {
304 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
307 .max_vs_threads
= 80,
308 .max_hs_threads
= 80,
309 .max_ds_threads
= 80,
310 .max_gs_threads
= 80,
311 .max_wm_threads
= 128,
312 .max_cs_threads
= 6 * 7,
315 .min_vs_entries
= 34,
316 .max_vs_entries
= 640,
317 .max_hs_entries
= 80,
318 .min_ds_entries
= 34,
319 .max_ds_entries
= 384,
320 .max_gs_entries
= 256,
324 #define GEN9_FEATURES \
326 .has_hiz_and_separate_stencil = true, \
327 .has_resource_streamer = true, \
328 .must_use_separate_stencil = true, \
331 .supports_simd16_3src = true, \
332 .max_vs_threads = 336, \
333 .max_gs_threads = 336, \
334 .max_hs_threads = 336, \
335 .max_ds_threads = 336, \
336 .max_wm_threads = 64 * 9, \
337 .max_cs_threads = 56, \
340 .min_vs_entries = 64, \
341 .max_vs_entries = 1856, \
342 .max_hs_entries = 672, \
343 .min_ds_entries = 34, \
344 .max_ds_entries = 1120, \
345 .max_gs_entries = 640, \
348 static const struct brw_device_info brw_device_info_skl_gt1
= {
349 GEN9_FEATURES
, .gt
= 1,
354 static const struct brw_device_info brw_device_info_skl_gt2
= {
355 GEN9_FEATURES
, .gt
= 2,
359 static const struct brw_device_info brw_device_info_skl_gt3
= {
360 GEN9_FEATURES
, .gt
= 3,
364 static const struct brw_device_info brw_device_info_skl_gt4
= {
365 GEN9_FEATURES
, .gt
= 4,
367 /* From the "L3 Allocation and Programming" documentation:
369 * "URB is limited to 1008KB due to programming restrictions. This is not a
370 * restriction of the L3 implementation, but of the FF and other clients.
371 * Therefore, in a GT4 implementation it is possible for the programmed
372 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
373 * only 1008KB of this will be used."
375 .urb
.size
= 1008 / 3,
378 static const struct brw_device_info brw_device_info_bxt
= {
385 .max_vs_threads
= 112,
386 .max_hs_threads
= 112,
387 .max_ds_threads
= 112,
388 .max_gs_threads
= 112,
389 .max_wm_threads
= 64 * 3,
390 .max_cs_threads
= 6 * 6,
393 .min_vs_entries
= 34,
394 .max_vs_entries
= 704,
395 .max_hs_entries
= 256,
396 .max_ds_entries
= 416,
397 .max_gs_entries
= 256,
401 static const struct brw_device_info brw_device_info_bxt_2x6
= {
408 .max_vs_threads
= 56, /* XXX: guess */
409 .max_hs_threads
= 56, /* XXX: guess */
410 .max_ds_threads
= 56,
411 .max_gs_threads
= 56,
412 .max_wm_threads
= 64 * 2,
413 .max_cs_threads
= 6 * 6,
416 .min_vs_entries
= 34,
417 .max_vs_entries
= 352,
418 .max_hs_entries
= 128,
419 .max_ds_entries
= 208,
420 .max_gs_entries
= 128,
424 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
425 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
429 * Both SKL and KBL support a maximum of 64 threads per
430 * Pixel Shader Dispatch (PSD) unit.
432 #define KBL_MAX_THREADS_PER_PSD 64
434 static const struct brw_device_info brw_device_info_kbl_gt1
= {
438 .max_cs_threads
= 7 * 6,
439 .max_wm_threads
= KBL_MAX_THREADS_PER_PSD
* 2,
444 static const struct brw_device_info brw_device_info_kbl_gt1_5
= {
448 .max_cs_threads
= 7 * 6,
449 .max_wm_threads
= KBL_MAX_THREADS_PER_PSD
* 3,
453 static const struct brw_device_info brw_device_info_kbl_gt2
= {
457 .max_wm_threads
= KBL_MAX_THREADS_PER_PSD
* 3,
461 static const struct brw_device_info brw_device_info_kbl_gt3
= {
465 .max_wm_threads
= KBL_MAX_THREADS_PER_PSD
* 6,
469 static const struct brw_device_info brw_device_info_kbl_gt4
= {
473 .max_wm_threads
= KBL_MAX_THREADS_PER_PSD
* 9,
475 * From the "L3 Allocation and Programming" documentation:
477 * "URB is limited to 1008KB due to programming restrictions. This
478 * is not a restriction of the L3 implementation, but of the FF and
479 * other clients. Therefore, in a GT4 implementation it is
480 * possible for the programmed allocation of the L3 data array to
481 * provide 3*384KB=1152KB for URB, but only 1008KB of this
484 .urb
.size
= 1008 / 3,
488 const struct brw_device_info
*
489 brw_get_device_info(int devid
)
491 const struct brw_device_info
*devinfo
;
494 #define CHIPSET(id, family, name) \
495 case id: devinfo = &brw_device_info_##family; break;
496 #include "pci_ids/i965_pci_ids.h"
498 fprintf(stderr
, "i965_dri.so does not support the 0x%x PCI ID.\n", devid
);
506 brw_get_device_name(int devid
)
510 #define CHIPSET(id, family, name) case id: return name;
511 #include "pci_ids/i965_pci_ids.h"