2 * Copyright © 2013 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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26 #include "brw_device_info.h"
28 static const struct brw_device_info brw_device_info_i965
= {
30 .has_negative_rhw_bug
= true,
31 .needs_unlit_centroid_workaround
= true,
34 .max_wm_threads
= 8 * 4,
40 static const struct brw_device_info brw_device_info_g4x
= {
44 .has_surface_tile_offset
= true,
45 .needs_unlit_centroid_workaround
= true,
49 .max_wm_threads
= 10 * 5,
55 static const struct brw_device_info brw_device_info_ilk
= {
59 .has_surface_tile_offset
= true,
60 .needs_unlit_centroid_workaround
= true,
63 .max_wm_threads
= 12 * 6,
69 static const struct brw_device_info brw_device_info_snb_gt1
= {
72 .has_hiz_and_separate_stencil
= true,
75 .has_surface_tile_offset
= true,
76 .needs_unlit_centroid_workaround
= true,
78 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
83 .max_vs_entries
= 256,
84 .max_gs_entries
= 256,
88 static const struct brw_device_info brw_device_info_snb_gt2
= {
91 .has_hiz_and_separate_stencil
= true,
94 .has_surface_tile_offset
= true,
95 .needs_unlit_centroid_workaround
= true,
101 .min_vs_entries
= 24,
102 .max_vs_entries
= 256,
103 .max_gs_entries
= 256,
107 #define GEN7_FEATURES \
109 .has_hiz_and_separate_stencil = true, \
110 .must_use_separate_stencil = true, \
113 .has_surface_tile_offset = true
115 static const struct brw_device_info brw_device_info_ivb_gt1
= {
116 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
117 .needs_unlit_centroid_workaround
= true,
118 .max_vs_threads
= 36,
119 .max_gs_threads
= 36,
120 .max_wm_threads
= 48,
123 .min_vs_entries
= 32,
124 .max_vs_entries
= 512,
125 .max_gs_entries
= 192,
129 static const struct brw_device_info brw_device_info_ivb_gt2
= {
130 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
131 .needs_unlit_centroid_workaround
= true,
132 .max_vs_threads
= 128,
133 .max_gs_threads
= 128,
134 .max_wm_threads
= 172,
137 .min_vs_entries
= 32,
138 .max_vs_entries
= 704,
139 .max_gs_entries
= 320,
143 static const struct brw_device_info brw_device_info_byt
= {
144 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
145 .needs_unlit_centroid_workaround
= true,
147 .max_vs_threads
= 36,
148 .max_gs_threads
= 36,
149 .max_wm_threads
= 48,
152 .min_vs_entries
= 32,
153 .max_vs_entries
= 512,
154 .max_gs_entries
= 192,
158 static const struct brw_device_info brw_device_info_hsw_gt1
= {
159 GEN7_FEATURES
, .is_haswell
= true, .gt
= 1,
160 .max_vs_threads
= 70,
161 .max_gs_threads
= 70,
162 .max_wm_threads
= 102,
165 .min_vs_entries
= 32,
166 .max_vs_entries
= 640,
167 .max_gs_entries
= 256,
171 static const struct brw_device_info brw_device_info_hsw_gt2
= {
172 GEN7_FEATURES
, .is_haswell
= true, .gt
= 2,
173 .max_vs_threads
= 280,
174 .max_gs_threads
= 256,
175 .max_wm_threads
= 204,
178 .min_vs_entries
= 64,
179 .max_vs_entries
= 1664,
180 .max_gs_entries
= 640,
184 static const struct brw_device_info brw_device_info_hsw_gt3
= {
185 GEN7_FEATURES
, .is_haswell
= true, .gt
= 3,
186 .max_vs_threads
= 280,
187 .max_gs_threads
= 256,
188 .max_wm_threads
= 408,
191 .min_vs_entries
= 64,
192 .max_vs_entries
= 1664,
193 .max_gs_entries
= 640,
197 #define GEN8_FEATURES \
199 .has_hiz_and_separate_stencil = true, \
200 .must_use_separate_stencil = true, \
203 .max_vs_threads = 504, \
204 .max_gs_threads = 504, \
205 .max_wm_threads = 384 \
207 static const struct brw_device_info brw_device_info_bdw_gt1 = {
208 GEN8_FEATURES
, .gt
= 1,
211 .min_vs_entries
= 64,
212 .max_vs_entries
= 2560,
213 .max_gs_entries
= 960,
217 static const struct brw_device_info brw_device_info_bdw_gt2
= {
218 GEN8_FEATURES
, .gt
= 2,
221 .min_vs_entries
= 64,
222 .max_vs_entries
= 2560,
223 .max_gs_entries
= 960,
227 static const struct brw_device_info brw_device_info_bdw_gt3
= {
228 GEN8_FEATURES
, .gt
= 3,
231 .min_vs_entries
= 64,
232 .max_vs_entries
= 2560,
233 .max_gs_entries
= 960,
237 /* Thread counts and URB limits are placeholders, and may not be accurate.
238 * These were copied from Haswell GT1, above.
240 static const struct brw_device_info brw_device_info_chv
= {
241 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
243 .max_vs_threads
= 70,
244 .max_gs_threads
= 70,
245 .max_wm_threads
= 102,
248 .min_vs_entries
= 64,
249 .max_vs_entries
= 640,
250 .max_gs_entries
= 256,
254 const struct brw_device_info
*
255 brw_get_device_info(int devid
)
259 #define CHIPSET(id, family, name) case id: return &brw_device_info_##family;
260 #include "pci_ids/i965_pci_ids.h"
262 fprintf(stderr
, "i965_dri.so does not support the 0x%x PCI ID.\n", devid
);