projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Merge remote-tracking branch 'origin/master' into vulkan
[mesa.git] / src / mesa / drivers / dri / i965 / brw_disasm.c
1 /*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23 #include <stdio.h>
24 #include <string.h>
25 #include <stdarg.h>
26
27 #include "brw_context.h"
28 #include "brw_defines.h"
29 #include "brw_reg.h"
30 #include "brw_inst.h"
31
32 const struct opcode_desc opcode_descs[128] = {
33 [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 },
34 [BRW_OPCODE_MOVI] = { .name = "movi", .nsrc = 2, .ndst = 1 },
35 [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 },
36 [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 },
37 [BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 },
38 [BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 },
39 [BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 },
40 [BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 },
41 [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 },
42 [BRW_OPCODE_F32TO16] = { .name = "f32to16", .nsrc = 1, .ndst = 1 },
43 [BRW_OPCODE_F16TO32] = { .name = "f16to32", .nsrc = 1, .ndst = 1 },
44 [BRW_OPCODE_BFREV] = { .name = "bfrev", .nsrc = 1, .ndst = 1 },
45 [BRW_OPCODE_FBH] = { .name = "fbh", .nsrc = 1, .ndst = 1 },
46 [BRW_OPCODE_FBL] = { .name = "fbl", .nsrc = 1, .ndst = 1 },
47 [BRW_OPCODE_CBIT] = { .name = "cbit", .nsrc = 1, .ndst = 1 },
48
49 [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 },
50 [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 },
51 [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 },
52 [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 },
53 [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 },
54 [BRW_OPCODE_MAD] = { .name = "mad", .nsrc = 3, .ndst = 1 },
55 [BRW_OPCODE_LRP] = { .name = "lrp", .nsrc = 3, .ndst = 1 },
56 [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 },
57 [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 },
58 [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 },
59 [BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 },
60 [BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 },
61 [BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 },
62 [BRW_OPCODE_MATH] = { .name = "math", .nsrc = 2, .ndst = 1 },
63
64 [BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 },
65 [BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 },
66 [BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 },
67 [BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 },
68 [BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 },
69 [BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 },
70 [BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 },
71 [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 },
72 [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 },
73 [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 },
74 [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 },
75 [BRW_OPCODE_CSEL] = { .name = "csel", .nsrc = 3, .ndst = 1 },
76 [BRW_OPCODE_BFE] = { .name = "bfe", .nsrc = 3, .ndst = 1 },
77 [BRW_OPCODE_BFI1] = { .name = "bfi1", .nsrc = 2, .ndst = 1 },
78 [BRW_OPCODE_BFI2] = { .name = "bfi2", .nsrc = 3, .ndst = 1 },
79 [BRW_OPCODE_ADDC] = { .name = "addc", .nsrc = 2, .ndst = 1 },
80 [BRW_OPCODE_SUBB] = { .name = "subb", .nsrc = 2, .ndst = 1 },
81
82 [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 },
83 [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 },
84 [BRW_OPCODE_SENDS] = { .name = "sends", .nsrc = 2, .ndst = 1 },
85 [BRW_OPCODE_SENDSC] = { .name = "sendsc", .nsrc = 2, .ndst = 1 },
86 [BRW_OPCODE_ILLEGAL] = { .name = "illegal", .nsrc = 0, .ndst = 0 },
87 [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
88 [BRW_OPCODE_NENOP] = { .name = "nenop", .nsrc = 0, .ndst = 0 },
89 [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 0, .ndst = 0 },
90 [BRW_OPCODE_IF] = { .name = "if", .nsrc = 0, .ndst = 0 },
91 [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 0, .ndst = 0 },
92 [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 0, .ndst = 0 },
93 [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 0, .ndst = 0 },
94 [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 0, .ndst = 0 },
95 [BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 0, .ndst = 0 },
96 [BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 0, .ndst = 0 },
97 // [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 },
98 // [BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 },
99 // [BRW_OPCODE_MREST] = { .name = "mrest", .nsrc = 1, .ndst = 1 },
100 // [BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 },
101 [BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 },
102 [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 },
103 [BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 0, .ndst = 0 },
104 };
105
106 static bool
107 has_jip(const struct brw_device_info *devinfo, enum opcode opcode)
108 {
109 if (devinfo->gen < 6)
110 return false;
111
112 return opcode == BRW_OPCODE_IF ||
113 opcode == BRW_OPCODE_ELSE ||
114 opcode == BRW_OPCODE_ENDIF ||
115 opcode == BRW_OPCODE_WHILE ||
116 opcode == BRW_OPCODE_BREAK ||
117 opcode == BRW_OPCODE_CONTINUE ||
118 opcode == BRW_OPCODE_HALT;
119 }
120
121 static bool
122 has_uip(const struct brw_device_info *devinfo, enum opcode opcode)
123 {
124 if (devinfo->gen < 6)
125 return false;
126
127 return (devinfo->gen >= 7 && opcode == BRW_OPCODE_IF) ||
128 (devinfo->gen >= 8 && opcode == BRW_OPCODE_ELSE) ||
129 opcode == BRW_OPCODE_BREAK ||
130 opcode == BRW_OPCODE_CONTINUE ||
131 opcode == BRW_OPCODE_HALT;
132 }
133
134 static bool
135 has_branch_ctrl(const struct brw_device_info *devinfo, enum opcode opcode)
136 {
137 if (devinfo->gen < 8)
138 return false;
139
140 return opcode == BRW_OPCODE_IF ||
141 opcode == BRW_OPCODE_ELSE;
142 /* opcode == BRW_OPCODE_GOTO; */
143 }
144
145 static bool
146 is_logic_instruction(unsigned opcode)
147 {
148 return opcode == BRW_OPCODE_AND ||
149 opcode == BRW_OPCODE_NOT ||
150 opcode == BRW_OPCODE_OR ||
151 opcode == BRW_OPCODE_XOR;
152 }
153
154 const char *const conditional_modifier[16] = {
155 [BRW_CONDITIONAL_NONE] = "",
156 [BRW_CONDITIONAL_Z] = ".z",
157 [BRW_CONDITIONAL_NZ] = ".nz",
158 [BRW_CONDITIONAL_G] = ".g",
159 [BRW_CONDITIONAL_GE] = ".ge",
160 [BRW_CONDITIONAL_L] = ".l",
161 [BRW_CONDITIONAL_LE] = ".le",
162 [BRW_CONDITIONAL_R] = ".r",
163 [BRW_CONDITIONAL_O] = ".o",
164 [BRW_CONDITIONAL_U] = ".u",
165 };
166
167 static const char *const m_negate[2] = {
168 [0] = "",
169 [1] = "-",
170 };
171
172 static const char *const _abs[2] = {
173 [0] = "",
174 [1] = "(abs)",
175 };
176
177 static const char *const m_bitnot[2] = { "", "~" };
178
179 static const char *const vert_stride[16] = {
180 [0] = "0",
181 [1] = "1",
182 [2] = "2",
183 [3] = "4",
184 [4] = "8",
185 [5] = "16",
186 [6] = "32",
187 [15] = "VxH",
188 };
189
190 static const char *const width[8] = {
191 [0] = "1",
192 [1] = "2",
193 [2] = "4",
194 [3] = "8",
195 [4] = "16",
196 };
197
198 static const char *const horiz_stride[4] = {
199 [0] = "0",
200 [1] = "1",
201 [2] = "2",
202 [3] = "4"
203 };
204
205 static const char *const chan_sel[4] = {
206 [0] = "x",
207 [1] = "y",
208 [2] = "z",
209 [3] = "w",
210 };
211
212 static const char *const debug_ctrl[2] = {
213 [0] = "",
214 [1] = ".breakpoint"
215 };
216
217 static const char *const saturate[2] = {
218 [0] = "",
219 [1] = ".sat"
220 };
221
222 static const char *const cmpt_ctrl[2] = {
223 [0] = "",
224 [1] = "compacted"
225 };
226
227 static const char *const accwr[2] = {
228 [0] = "",
229 [1] = "AccWrEnable"
230 };
231
232 static const char *const branch_ctrl[2] = {
233 [0] = "",
234 [1] = "BranchCtrl"
235 };
236
237 static const char *const wectrl[2] = {
238 [0] = "",
239 [1] = "WE_all"
240 };
241
242 static const char *const exec_size[8] = {
243 [0] = "1",
244 [1] = "2",
245 [2] = "4",
246 [3] = "8",
247 [4] = "16",
248 [5] = "32"
249 };
250
251 static const char *const pred_inv[2] = {
252 [0] = "+",
253 [1] = "-"
254 };
255
256 const char *const pred_ctrl_align16[16] = {
257 [1] = "",
258 [2] = ".x",
259 [3] = ".y",
260 [4] = ".z",
261 [5] = ".w",
262 [6] = ".any4h",
263 [7] = ".all4h",
264 };
265
266 static const char *const pred_ctrl_align1[16] = {
267 [BRW_PREDICATE_NORMAL] = "",
268 [BRW_PREDICATE_ALIGN1_ANYV] = ".anyv",
269 [BRW_PREDICATE_ALIGN1_ALLV] = ".allv",
270 [BRW_PREDICATE_ALIGN1_ANY2H] = ".any2h",
271 [BRW_PREDICATE_ALIGN1_ALL2H] = ".all2h",
272 [BRW_PREDICATE_ALIGN1_ANY4H] = ".any4h",
273 [BRW_PREDICATE_ALIGN1_ALL4H] = ".all4h",
274 [BRW_PREDICATE_ALIGN1_ANY8H] = ".any8h",
275 [BRW_PREDICATE_ALIGN1_ALL8H] = ".all8h",
276 [BRW_PREDICATE_ALIGN1_ANY16H] = ".any16h",
277 [BRW_PREDICATE_ALIGN1_ALL16H] = ".all16h",
278 [BRW_PREDICATE_ALIGN1_ANY32H] = ".any32h",
279 [BRW_PREDICATE_ALIGN1_ALL32H] = ".all32h",
280 };
281
282 static const char *const thread_ctrl[4] = {
283 [BRW_THREAD_NORMAL] = "",
284 [BRW_THREAD_ATOMIC] = "atomic",
285 [BRW_THREAD_SWITCH] = "switch",
286 };
287
288 static const char *const compr_ctrl[4] = {
289 [0] = "",
290 [1] = "sechalf",
291 [2] = "compr",
292 [3] = "compr4",
293 };
294
295 static const char *const dep_ctrl[4] = {
296 [0] = "",
297 [1] = "NoDDClr",
298 [2] = "NoDDChk",
299 [3] = "NoDDClr,NoDDChk",
300 };
301
302 static const char *const mask_ctrl[4] = {
303 [0] = "",
304 [1] = "nomask",
305 };
306
307 static const char *const access_mode[2] = {
308 [0] = "align1",
309 [1] = "align16",
310 };
311
312 static const char * const reg_encoding[] = {
313 [BRW_HW_REG_TYPE_UD] = "UD",
314 [BRW_HW_REG_TYPE_D] = "D",
315 [BRW_HW_REG_TYPE_UW] = "UW",
316 [BRW_HW_REG_TYPE_W] = "W",
317 [BRW_HW_REG_NON_IMM_TYPE_UB] = "UB",
318 [BRW_HW_REG_NON_IMM_TYPE_B] = "B",
319 [GEN7_HW_REG_NON_IMM_TYPE_DF] = "DF",
320 [BRW_HW_REG_TYPE_F] = "F",
321 [GEN8_HW_REG_TYPE_UQ] = "UQ",
322 [GEN8_HW_REG_TYPE_Q] = "Q",
323 [GEN8_HW_REG_NON_IMM_TYPE_HF] = "HF",
324 };
325
326 static const char *const three_source_reg_encoding[] = {
327 [BRW_3SRC_TYPE_F] = "F",
328 [BRW_3SRC_TYPE_D] = "D",
329 [BRW_3SRC_TYPE_UD] = "UD",
330 };
331
332 const int reg_type_size[] = {
333 [BRW_HW_REG_TYPE_UD] = 4,
334 [BRW_HW_REG_TYPE_D] = 4,
335 [BRW_HW_REG_TYPE_UW] = 2,
336 [BRW_HW_REG_TYPE_W] = 2,
337 [BRW_HW_REG_NON_IMM_TYPE_UB] = 1,
338 [BRW_HW_REG_NON_IMM_TYPE_B] = 1,
339 [GEN7_HW_REG_NON_IMM_TYPE_DF] = 8,
340 [BRW_HW_REG_TYPE_F] = 4,
341 [GEN8_HW_REG_TYPE_UQ] = 8,
342 [GEN8_HW_REG_TYPE_Q] = 8,
343 [GEN8_HW_REG_NON_IMM_TYPE_HF] = 2,
344 };
345
346 static const char *const reg_file[4] = {
347 [0] = "A",
348 [1] = "g",
349 [2] = "m",
350 [3] = "imm",
351 };
352
353 static const char *const writemask[16] = {
354 [0x0] = ".",
355 [0x1] = ".x",
356 [0x2] = ".y",
357 [0x3] = ".xy",
358 [0x4] = ".z",
359 [0x5] = ".xz",
360 [0x6] = ".yz",
361 [0x7] = ".xyz",
362 [0x8] = ".w",
363 [0x9] = ".xw",
364 [0xa] = ".yw",
365 [0xb] = ".xyw",
366 [0xc] = ".zw",
367 [0xd] = ".xzw",
368 [0xe] = ".yzw",
369 [0xf] = "",
370 };
371
372 static const char *const end_of_thread[2] = {
373 [0] = "",
374 [1] = "EOT"
375 };
376
377 /* SFIDs on Gen4-5 */
378 static const char *const gen4_sfid[16] = {
379 [BRW_SFID_NULL] = "null",
380 [BRW_SFID_MATH] = "math",
381 [BRW_SFID_SAMPLER] = "sampler",
382 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
383 [BRW_SFID_DATAPORT_READ] = "read",
384 [BRW_SFID_DATAPORT_WRITE] = "write",
385 [BRW_SFID_URB] = "urb",
386 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
387 [BRW_SFID_VME] = "vme",
388 };
389
390 static const char *const gen6_sfid[16] = {
391 [BRW_SFID_NULL] = "null",
392 [BRW_SFID_MATH] = "math",
393 [BRW_SFID_SAMPLER] = "sampler",
394 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
395 [BRW_SFID_URB] = "urb",
396 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
397 [GEN6_SFID_DATAPORT_SAMPLER_CACHE] = "sampler",
398 [GEN6_SFID_DATAPORT_RENDER_CACHE] = "render",
399 [GEN6_SFID_DATAPORT_CONSTANT_CACHE] = "const",
400 [GEN7_SFID_DATAPORT_DATA_CACHE] = "data",
401 [GEN7_SFID_PIXEL_INTERPOLATOR] = "pixel interp",
402 [HSW_SFID_DATAPORT_DATA_CACHE_1] = "dp data 1",
403 [HSW_SFID_CRE] = "cre",
404 };
405
406 static const char *const gen7_gateway_subfuncid[8] = {
407 [BRW_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY] = "open",
408 [BRW_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY] = "close",
409 [BRW_MESSAGE_GATEWAY_SFID_FORWARD_MSG] = "forward msg",
410 [BRW_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP] = "get timestamp",
411 [BRW_MESSAGE_GATEWAY_SFID_BARRIER_MSG] = "barrier msg",
412 [BRW_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE] = "update state",
413 [BRW_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE] = "mmio read/write",
414 };
415
416 static const char *const gen4_dp_read_port_msg_type[4] = {
417 [0b00] = "OWord Block Read",
418 [0b01] = "OWord Dual Block Read",
419 [0b10] = "Media Block Read",
420 [0b11] = "DWord Scattered Read",
421 };
422
423 static const char *const g45_dp_read_port_msg_type[8] = {
424 [0b000] = "OWord Block Read",
425 [0b010] = "OWord Dual Block Read",
426 [0b100] = "Media Block Read",
427 [0b110] = "DWord Scattered Read",
428 [0b001] = "Render Target UNORM Read",
429 [0b011] = "AVC Loop Filter Read",
430 };
431
432 static const char *const dp_write_port_msg_type[8] = {
433 [0b000] = "OWord block write",
434 [0b001] = "OWord dual block write",
435 [0b010] = "media block write",
436 [0b011] = "DWord scattered write",
437 [0b100] = "RT write",
438 [0b101] = "streamed VB write",
439 [0b110] = "RT UNORM write", /* G45+ */
440 [0b111] = "flush render cache",
441 };
442
443 static const char *const dp_rc_msg_type_gen6[16] = {
444 [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read",
445 [GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read",
446 [GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read",
447 [GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read",
448 [GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ] =
449 "OWORD unaligned block read",
450 [GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ] = "DWORD scattered read",
451 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE] = "DWORD atomic write",
452 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE] = "OWORD block write",
453 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE] =
454 "OWORD dual block write",
455 [GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE] = "media block write",
456 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE] =
457 "DWORD scattered write",
458 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write",
459 [GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write",
460 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORM write",
461 };
462
463 static const char *const m_rt_write_subtype[] = {
464 [0b000] = "SIMD16",
465 [0b001] = "SIMD16/RepData",
466 [0b010] = "SIMD8/DualSrcLow",
467 [0b011] = "SIMD8/DualSrcHigh",
468 [0b100] = "SIMD8",
469 [0b101] = "SIMD8/ImageWrite", /* Gen6+ */
470 [0b111] = "SIMD16/RepData-111", /* no idea how this is different than 1 */
471 };
472
473 static const char *const dp_dc0_msg_type_gen7[16] = {
474 [GEN7_DATAPORT_DC_OWORD_BLOCK_READ] = "DC OWORD block read",
475 [GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ] =
476 "DC unaligned OWORD block read",
477 [GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ] = "DC OWORD dual block read",
478 [GEN7_DATAPORT_DC_DWORD_SCATTERED_READ] = "DC DWORD scattered read",
479 [GEN7_DATAPORT_DC_BYTE_SCATTERED_READ] = "DC byte scattered read",
480 [GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ] = "DC untyped surface read",
481 [GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP] = "DC untyped atomic",
482 [GEN7_DATAPORT_DC_MEMORY_FENCE] = "DC mfence",
483 [GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE] = "DC OWORD block write",
484 [GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE] = "DC OWORD dual block write",
485 [GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE] = "DC DWORD scatterd write",
486 [GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE] = "DC byte scattered write",
487 [GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
488 };
489
490 static const char *const dp_dc1_msg_type_hsw[16] = {
491 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ] = "untyped surface read",
492 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP] = "DC untyped atomic op",
493 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2] =
494 "DC untyped 4x2 atomic op",
495 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ] = "DC media block read",
496 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ] = "DC typed surface read",
497 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP] = "DC typed atomic",
498 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2] = "DC typed 4x2 atomic op",
499 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
500 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE] = "DC media block write",
501 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP] = "DC atomic counter op",
502 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2] =
503 "DC 4x2 atomic counter op",
504 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE] = "DC typed surface write",
505 };
506
507 static const char *const aop[16] = {
508 [BRW_AOP_AND] = "and",
509 [BRW_AOP_OR] = "or",
510 [BRW_AOP_XOR] = "xor",
511 [BRW_AOP_MOV] = "mov",
512 [BRW_AOP_INC] = "inc",
513 [BRW_AOP_DEC] = "dec",
514 [BRW_AOP_ADD] = "add",
515 [BRW_AOP_SUB] = "sub",
516 [BRW_AOP_REVSUB] = "revsub",
517 [BRW_AOP_IMAX] = "imax",
518 [BRW_AOP_IMIN] = "imin",
519 [BRW_AOP_UMAX] = "umax",
520 [BRW_AOP_UMIN] = "umin",
521 [BRW_AOP_CMPWR] = "cmpwr",
522 [BRW_AOP_PREDEC] = "predec",
523 };
524
525 static const char * const pixel_interpolator_msg_types[4] = {
526 [GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET] = "per_message_offset",
527 [GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE] = "sample_position",
528 [GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID] = "centroid",
529 [GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET] = "per_slot_offset",
530 };
531
532 static const char *const math_function[16] = {
533 [BRW_MATH_FUNCTION_INV] = "inv",
534 [BRW_MATH_FUNCTION_LOG] = "log",
535 [BRW_MATH_FUNCTION_EXP] = "exp",
536 [BRW_MATH_FUNCTION_SQRT] = "sqrt",
537 [BRW_MATH_FUNCTION_RSQ] = "rsq",
538 [BRW_MATH_FUNCTION_SIN] = "sin",
539 [BRW_MATH_FUNCTION_COS] = "cos",
540 [BRW_MATH_FUNCTION_SINCOS] = "sincos",
541 [BRW_MATH_FUNCTION_FDIV] = "fdiv",
542 [BRW_MATH_FUNCTION_POW] = "pow",
543 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod",
544 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intdiv",
545 [BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod",
546 [GEN8_MATH_FUNCTION_INVM] = "invm",
547 [GEN8_MATH_FUNCTION_RSQRTM] = "rsqrtm",
548 };
549
550 static const char *const math_saturate[2] = {
551 [0] = "",
552 [1] = "sat"
553 };
554
555 static const char *const math_signed[2] = {
556 [0] = "",
557 [1] = "signed"
558 };
559
560 static const char *const math_scalar[2] = {
561 [0] = "",
562 [1] = "scalar"
563 };
564
565 static const char *const math_precision[2] = {
566 [0] = "",
567 [1] = "partial_precision"
568 };
569
570 static const char *const gen5_urb_opcode[] = {
571 [0] = "urb_write",
572 [1] = "ff_sync",
573 };
574
575 static const char *const gen7_urb_opcode[] = {
576 [BRW_URB_OPCODE_WRITE_HWORD] = "write HWord",
577 [BRW_URB_OPCODE_WRITE_OWORD] = "write OWord",
578 [BRW_URB_OPCODE_READ_HWORD] = "read HWord",
579 [BRW_URB_OPCODE_READ_OWORD] = "read OWord",
580 [GEN7_URB_OPCODE_ATOMIC_MOV] = "atomic mov", /* Gen7+ */
581 [GEN7_URB_OPCODE_ATOMIC_INC] = "atomic inc", /* Gen7+ */
582 [GEN8_URB_OPCODE_ATOMIC_ADD] = "atomic add", /* Gen8+ */
583 [GEN8_URB_OPCODE_SIMD8_WRITE] = "SIMD8 write", /* Gen8+ */
584 [GEN8_URB_OPCODE_SIMD8_READ] = "SIMD8 read", /* Gen8+ */
585 /* [9-15] - reserved */
586 };
587
588 static const char *const urb_swizzle[4] = {
589 [BRW_URB_SWIZZLE_NONE] = "",
590 [BRW_URB_SWIZZLE_INTERLEAVE] = "interleave",
591 [BRW_URB_SWIZZLE_TRANSPOSE] = "transpose",
592 };
593
594 static const char *const urb_allocate[2] = {
595 [0] = "",
596 [1] = "allocate"
597 };
598
599 static const char *const urb_used[2] = {
600 [0] = "",
601 [1] = "used"
602 };
603
604 static const char *const urb_complete[2] = {
605 [0] = "",
606 [1] = "complete"
607 };
608
609 static const char *const gen5_sampler_msg_type[] = {
610 [GEN5_SAMPLER_MESSAGE_SAMPLE] = "sample",
611 [GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS] = "sample_b",
612 [GEN5_SAMPLER_MESSAGE_SAMPLE_LOD] = "sample_l",
613 [GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE] = "sample_c",
614 [GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS] = "sample_d",
615 [GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE] = "sample_b_c",
616 [GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE] = "sample_l_c",
617 [GEN5_SAMPLER_MESSAGE_SAMPLE_LD] = "ld",
618 [GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4] = "gather4",
619 [GEN5_SAMPLER_MESSAGE_LOD] = "lod",
620 [GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO] = "resinfo",
621 [GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO] = "sampleinfo",
622 [GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C] = "gather4_c",
623 [GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO] = "gather4_po",
624 [GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C] = "gather4_po_c",
625 [HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE] = "sample_d_c",
626 [GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W] = "ld2dms_w",
627 [GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS] = "ld_mcs",
628 [GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS] = "ld2dms",
629 [GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS] = "ld2dss",
630 };
631
632 static const char *const gen5_sampler_simd_mode[4] = {
633 [BRW_SAMPLER_SIMD_MODE_SIMD4X2] = "SIMD4x2",
634 [BRW_SAMPLER_SIMD_MODE_SIMD8] = "SIMD8",
635 [BRW_SAMPLER_SIMD_MODE_SIMD16] = "SIMD16",
636 [BRW_SAMPLER_SIMD_MODE_SIMD32_64] = "SIMD32/64",
637 };
638
639 static const char *const sampler_target_format[4] = {
640 [0] = "F",
641 [2] = "UD",
642 [3] = "D"
643 };
644
645
646 static int column;
647
648 static int
649 string(FILE *file, const char *string)
650 {
651 fputs(string, file);
652 column += strlen(string);
653 return 0;
654 }
655
656 static int
657 format(FILE *f, const char *format, ...) PRINTFLIKE(2, 3);
658
659 static int
660 format(FILE *f, const char *format, ...)
661 {
662 char buf[1024];
663 va_list args;
664 va_start(args, format);
665
666 vsnprintf(buf, sizeof(buf) - 1, format, args);
667 va_end(args);
668 string(f, buf);
669 return 0;
670 }
671
672 static int
673 newline(FILE *f)
674 {
675 putc('\n', f);
676 column = 0;
677 return 0;
678 }
679
680 static int
681 pad(FILE *f, int c)
682 {
683 do
684 string(f, " ");
685 while (column < c);
686 return 0;
687 }
688
689 static int
690 control(FILE *file, const char *name, const char *const ctrl[],
691 unsigned id, int *space)
692 {
693 if (!ctrl[id]) {
694 fprintf(file, "*** invalid %s value %d ", name, id);
695 return 1;
696 }
697 if (ctrl[id][0]) {
698 if (space && *space)
699 string(file, " ");
700 string(file, ctrl[id]);
701 if (space)
702 *space = 1;
703 }
704 return 0;
705 }
706
707 static int
708 print_opcode(FILE *file, int id)
709 {
710 if (!opcode_descs[id].name) {
711 format(file, "*** invalid opcode value %d ", id);
712 return 1;
713 }
714 string(file, opcode_descs[id].name);
715 return 0;
716 }
717
718 static int
719 reg(FILE *file, unsigned _reg_file, unsigned _reg_nr)
720 {
721 int err = 0;
722
723 /* Clear the Compr4 instruction compression bit. */
724 if (_reg_file == BRW_MESSAGE_REGISTER_FILE)
725 _reg_nr &= ~BRW_MRF_COMPR4;
726
727 if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
728 switch (_reg_nr & 0xf0) {
729 case BRW_ARF_NULL:
730 string(file, "null");
731 break;
732 case BRW_ARF_ADDRESS:
733 format(file, "a%d", _reg_nr & 0x0f);
734 break;
735 case BRW_ARF_ACCUMULATOR:
736 format(file, "acc%d", _reg_nr & 0x0f);
737 break;
738 case BRW_ARF_FLAG:
739 format(file, "f%d", _reg_nr & 0x0f);
740 break;
741 case BRW_ARF_MASK:
742 format(file, "mask%d", _reg_nr & 0x0f);
743 break;
744 case BRW_ARF_MASK_STACK:
745 format(file, "msd%d", _reg_nr & 0x0f);
746 break;
747 case BRW_ARF_STATE:
748 format(file, "sr%d", _reg_nr & 0x0f);
749 break;
750 case BRW_ARF_CONTROL:
751 format(file, "cr%d", _reg_nr & 0x0f);
752 break;
753 case BRW_ARF_NOTIFICATION_COUNT:
754 format(file, "n%d", _reg_nr & 0x0f);
755 break;
756 case BRW_ARF_IP:
757 string(file, "ip");
758 return -1;
759 break;
760 case BRW_ARF_TDR:
761 format(file, "tdr0");
762 return -1;
763 case BRW_ARF_TIMESTAMP:
764 format(file, "tm%d", _reg_nr & 0x0f);
765 break;
766 default:
767 format(file, "ARF%d", _reg_nr);
768 break;
769 }
770 } else {
771 err |= control(file, "src reg file", reg_file, _reg_file, NULL);
772 format(file, "%d", _reg_nr);
773 }
774 return err;
775 }
776
777 static int
778 dest(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
779 {
780 int err = 0;
781
782 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
783 if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
784 err |= reg(file, brw_inst_dst_reg_file(devinfo, inst),
785 brw_inst_dst_da_reg_nr(devinfo, inst));
786 if (err == -1)
787 return 0;
788 if (brw_inst_dst_da1_subreg_nr(devinfo, inst))
789 format(file, ".%ld", brw_inst_dst_da1_subreg_nr(devinfo, inst) /
790 reg_type_size[brw_inst_dst_reg_type(devinfo, inst)]);
791 string(file, "<");
792 err |= control(file, "horiz stride", horiz_stride,
793 brw_inst_dst_hstride(devinfo, inst), NULL);
794 string(file, ">");
795 err |= control(file, "dest reg encoding", reg_encoding,
796 brw_inst_dst_reg_type(devinfo, inst), NULL);
797 } else {
798 string(file, "g[a0");
799 if (brw_inst_dst_ia_subreg_nr(devinfo, inst))
800 format(file, ".%ld", brw_inst_dst_ia_subreg_nr(devinfo, inst) /
801 reg_type_size[brw_inst_dst_reg_type(devinfo, inst)]);
802 if (brw_inst_dst_ia1_addr_imm(devinfo, inst))
803 format(file, " %d", brw_inst_dst_ia1_addr_imm(devinfo, inst));
804 string(file, "]<");
805 err |= control(file, "horiz stride", horiz_stride,
806 brw_inst_dst_hstride(devinfo, inst), NULL);
807 string(file, ">");
808 err |= control(file, "dest reg encoding", reg_encoding,
809 brw_inst_dst_reg_type(devinfo, inst), NULL);
810 }
811 } else {
812 if (brw_inst_dst_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
813 err |= reg(file, brw_inst_dst_reg_file(devinfo, inst),
814 brw_inst_dst_da_reg_nr(devinfo, inst));
815 if (err == -1)
816 return 0;
817 if (brw_inst_dst_da16_subreg_nr(devinfo, inst))
818 format(file, ".%ld", brw_inst_dst_da16_subreg_nr(devinfo, inst) /
819 reg_type_size[brw_inst_dst_reg_type(devinfo, inst)]);
820 string(file, "<1>");
821 err |= control(file, "writemask", writemask,
822 brw_inst_da16_writemask(devinfo, inst), NULL);
823 err |= control(file, "dest reg encoding", reg_encoding,
824 brw_inst_dst_reg_type(devinfo, inst), NULL);
825 } else {
826 err = 1;
827 string(file, "Indirect align16 address mode not supported");
828 }
829 }
830
831 return 0;
832 }
833
834 static int
835 dest_3src(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
836 {
837 int err = 0;
838 uint32_t reg_file;
839
840 if (devinfo->gen == 6 && brw_inst_3src_dst_reg_file(devinfo, inst))
841 reg_file = BRW_MESSAGE_REGISTER_FILE;
842 else
843 reg_file = BRW_GENERAL_REGISTER_FILE;
844
845 err |= reg(file, reg_file, brw_inst_3src_dst_reg_nr(devinfo, inst));
846 if (err == -1)
847 return 0;
848 if (brw_inst_3src_dst_subreg_nr(devinfo, inst))
849 format(file, ".%ld", brw_inst_3src_dst_subreg_nr(devinfo, inst));
850 string(file, "<1>");
851 err |= control(file, "writemask", writemask,
852 brw_inst_3src_dst_writemask(devinfo, inst), NULL);
853 err |= control(file, "dest reg encoding", three_source_reg_encoding,
854 brw_inst_3src_dst_type(devinfo, inst), NULL);
855
856 return 0;
857 }
858
859 static int
860 src_align1_region(FILE *file,
861 unsigned _vert_stride, unsigned _width,
862 unsigned _horiz_stride)
863 {
864 int err = 0;
865 string(file, "<");
866 err |= control(file, "vert stride", vert_stride, _vert_stride, NULL);
867 string(file, ",");
868 err |= control(file, "width", width, _width, NULL);
869 string(file, ",");
870 err |= control(file, "horiz_stride", horiz_stride, _horiz_stride, NULL);
871 string(file, ">");
872 return err;
873 }
874
875 static int
876 src_da1(FILE *file,
877 const struct brw_device_info *devinfo,
878 unsigned opcode,
879 unsigned type, unsigned _reg_file,
880 unsigned _vert_stride, unsigned _width, unsigned _horiz_stride,
881 unsigned reg_num, unsigned sub_reg_num, unsigned __abs,
882 unsigned _negate)
883 {
884 int err = 0;
885
886 if (devinfo->gen >= 8 && is_logic_instruction(opcode))
887 err |= control(file, "bitnot", m_bitnot, _negate, NULL);
888 else
889 err |= control(file, "negate", m_negate, _negate, NULL);
890
891 err |= control(file, "abs", _abs, __abs, NULL);
892
893 err |= reg(file, _reg_file, reg_num);
894 if (err == -1)
895 return 0;
896 if (sub_reg_num)
897 format(file, ".%d", sub_reg_num / reg_type_size[type]); /* use formal style like spec */
898 src_align1_region(file, _vert_stride, _width, _horiz_stride);
899 err |= control(file, "src reg encoding", reg_encoding, type, NULL);
900 return err;
901 }
902
903 static int
904 src_ia1(FILE *file,
905 const struct brw_device_info *devinfo,
906 unsigned opcode,
907 unsigned type,
908 unsigned _reg_file,
909 int _addr_imm,
910 unsigned _addr_subreg_nr,
911 unsigned _negate,
912 unsigned __abs,
913 unsigned _horiz_stride, unsigned _width, unsigned _vert_stride)
914 {
915 int err = 0;
916
917 if (devinfo->gen >= 8 && is_logic_instruction(opcode))
918 err |= control(file, "bitnot", m_bitnot, _negate, NULL);
919 else
920 err |= control(file, "negate", m_negate, _negate, NULL);
921
922 err |= control(file, "abs", _abs, __abs, NULL);
923
924 string(file, "g[a0");
925 if (_addr_subreg_nr)
926 format(file, ".%d", _addr_subreg_nr);
927 if (_addr_imm)
928 format(file, " %d", _addr_imm);
929 string(file, "]");
930 src_align1_region(file, _vert_stride, _width, _horiz_stride);
931 err |= control(file, "src reg encoding", reg_encoding, type, NULL);
932 return err;
933 }
934
935 static int
936 src_swizzle(FILE *file, unsigned swiz)
937 {
938 unsigned x = BRW_GET_SWZ(swiz, BRW_CHANNEL_X);
939 unsigned y = BRW_GET_SWZ(swiz, BRW_CHANNEL_Y);
940 unsigned z = BRW_GET_SWZ(swiz, BRW_CHANNEL_Z);
941 unsigned w = BRW_GET_SWZ(swiz, BRW_CHANNEL_W);
942 int err = 0;
943
944 if (x == y && x == z && x == w) {
945 string(file, ".");
946 err |= control(file, "channel select", chan_sel, x, NULL);
947 } else if (swiz != BRW_SWIZZLE_XYZW) {
948 string(file, ".");
949 err |= control(file, "channel select", chan_sel, x, NULL);
950 err |= control(file, "channel select", chan_sel, y, NULL);
951 err |= control(file, "channel select", chan_sel, z, NULL);
952 err |= control(file, "channel select", chan_sel, w, NULL);
953 }
954 return err;
955 }
956
957 static int
958 src_da16(FILE *file,
959 const struct brw_device_info *devinfo,
960 unsigned opcode,
961 unsigned _reg_type,
962 unsigned _reg_file,
963 unsigned _vert_stride,
964 unsigned _reg_nr,
965 unsigned _subreg_nr,
966 unsigned __abs,
967 unsigned _negate,
968 unsigned swz_x, unsigned swz_y, unsigned swz_z, unsigned swz_w)
969 {
970 int err = 0;
971
972 if (devinfo->gen >= 8 && is_logic_instruction(opcode))
973 err |= control(file, "bitnot", m_bitnot, _negate, NULL);
974 else
975 err |= control(file, "negate", m_negate, _negate, NULL);
976
977 err |= control(file, "abs", _abs, __abs, NULL);
978
979 err |= reg(file, _reg_file, _reg_nr);
980 if (err == -1)
981 return 0;
982 if (_subreg_nr)
983 /* bit4 for subreg number byte addressing. Make this same meaning as
984 in da1 case, so output looks consistent. */
985 format(file, ".%d", 16 / reg_type_size[_reg_type]);
986 string(file, "<");
987 err |= control(file, "vert stride", vert_stride, _vert_stride, NULL);
988 string(file, ",4,1>");
989 err |= src_swizzle(file, BRW_SWIZZLE4(swz_x, swz_y, swz_z, swz_w));
990 err |= control(file, "src da16 reg type", reg_encoding, _reg_type, NULL);
991 return err;
992 }
993
994 static int
995 src0_3src(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
996 {
997 int err = 0;
998 unsigned src0_subreg_nr = brw_inst_3src_src0_subreg_nr(devinfo, inst);
999
1000 err |= control(file, "negate", m_negate,
1001 brw_inst_3src_src0_negate(devinfo, inst), NULL);
1002 err |= control(file, "abs", _abs, brw_inst_3src_src0_abs(devinfo, inst), NULL);
1003
1004 err |= reg(file, BRW_GENERAL_REGISTER_FILE,
1005 brw_inst_3src_src0_reg_nr(devinfo, inst));
1006 if (err == -1)
1007 return 0;
1008 if (src0_subreg_nr || brw_inst_3src_src0_rep_ctrl(devinfo, inst))
1009 format(file, ".%d", src0_subreg_nr);
1010 if (brw_inst_3src_src0_rep_ctrl(devinfo, inst))
1011 string(file, "<0,1,0>");
1012 else {
1013 string(file, "<4,4,1>");
1014 err |= src_swizzle(file, brw_inst_3src_src0_swizzle(devinfo, inst));
1015 }
1016 err |= control(file, "src da16 reg type", three_source_reg_encoding,
1017 brw_inst_3src_src_type(devinfo, inst), NULL);
1018 return err;
1019 }
1020
1021 static int
1022 src1_3src(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
1023 {
1024 int err = 0;
1025 unsigned src1_subreg_nr = brw_inst_3src_src1_subreg_nr(devinfo, inst);
1026
1027 err |= control(file, "negate", m_negate,
1028 brw_inst_3src_src1_negate(devinfo, inst), NULL);
1029 err |= control(file, "abs", _abs, brw_inst_3src_src1_abs(devinfo, inst), NULL);
1030
1031 err |= reg(file, BRW_GENERAL_REGISTER_FILE,
1032 brw_inst_3src_src1_reg_nr(devinfo, inst));
1033 if (err == -1)
1034 return 0;
1035 if (src1_subreg_nr || brw_inst_3src_src1_rep_ctrl(devinfo, inst))
1036 format(file, ".%d", src1_subreg_nr);
1037 if (brw_inst_3src_src1_rep_ctrl(devinfo, inst))
1038 string(file, "<0,1,0>");
1039 else {
1040 string(file, "<4,4,1>");
1041 err |= src_swizzle(file, brw_inst_3src_src1_swizzle(devinfo, inst));
1042 }
1043 err |= control(file, "src da16 reg type", three_source_reg_encoding,
1044 brw_inst_3src_src_type(devinfo, inst), NULL);
1045 return err;
1046 }
1047
1048
1049 static int
1050 src2_3src(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
1051 {
1052 int err = 0;
1053 unsigned src2_subreg_nr = brw_inst_3src_src2_subreg_nr(devinfo, inst);
1054
1055 err |= control(file, "negate", m_negate,
1056 brw_inst_3src_src2_negate(devinfo, inst), NULL);
1057 err |= control(file, "abs", _abs, brw_inst_3src_src2_abs(devinfo, inst), NULL);
1058
1059 err |= reg(file, BRW_GENERAL_REGISTER_FILE,
1060 brw_inst_3src_src2_reg_nr(devinfo, inst));
1061 if (err == -1)
1062 return 0;
1063 if (src2_subreg_nr || brw_inst_3src_src2_rep_ctrl(devinfo, inst))
1064 format(file, ".%d", src2_subreg_nr);
1065 if (brw_inst_3src_src2_rep_ctrl(devinfo, inst))
1066 string(file, "<0,1,0>");
1067 else {
1068 string(file, "<4,4,1>");
1069 err |= src_swizzle(file, brw_inst_3src_src2_swizzle(devinfo, inst));
1070 }
1071 err |= control(file, "src da16 reg type", three_source_reg_encoding,
1072 brw_inst_3src_src_type(devinfo, inst), NULL);
1073 return err;
1074 }
1075
1076 static int
1077 imm(FILE *file, const struct brw_device_info *devinfo, unsigned type, brw_inst *inst)
1078 {
1079 switch (type) {
1080 case BRW_HW_REG_TYPE_UD:
1081 format(file, "0x%08xUD", brw_inst_imm_ud(devinfo, inst));
1082 break;
1083 case BRW_HW_REG_TYPE_D:
1084 format(file, "%dD", brw_inst_imm_d(devinfo, inst));
1085 break;
1086 case BRW_HW_REG_TYPE_UW:
1087 format(file, "0x%04xUW", (uint16_t) brw_inst_imm_ud(devinfo, inst));
1088 break;
1089 case BRW_HW_REG_TYPE_W:
1090 format(file, "%dW", (int16_t) brw_inst_imm_d(devinfo, inst));
1091 break;
1092 case BRW_HW_REG_IMM_TYPE_UV:
1093 format(file, "0x%08xUV", brw_inst_imm_ud(devinfo, inst));
1094 break;
1095 case BRW_HW_REG_IMM_TYPE_VF:
1096 format(file, "[%-gF, %-gF, %-gF, %-gF]VF",
1097 brw_vf_to_float(brw_inst_imm_ud(devinfo, inst)),
1098 brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 8),
1099 brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 16),
1100 brw_vf_to_float(brw_inst_imm_ud(devinfo, inst) >> 24));
1101 break;
1102 case BRW_HW_REG_IMM_TYPE_V:
1103 format(file, "0x%08xV", brw_inst_imm_ud(devinfo, inst));
1104 break;
1105 case BRW_HW_REG_TYPE_F:
1106 format(file, "%-gF", brw_inst_imm_f(devinfo, inst));
1107 break;
1108 case GEN8_HW_REG_IMM_TYPE_DF:
1109 string(file, "Double IMM");
1110 break;
1111 case GEN8_HW_REG_IMM_TYPE_HF:
1112 string(file, "Half Float IMM");
1113 break;
1114 }
1115 return 0;
1116 }
1117
1118 static int
1119 src0(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
1120 {
1121 if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
1122 return imm(file, devinfo, brw_inst_src0_reg_type(devinfo, inst), inst);
1123 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1124 if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1125 return src_da1(file,
1126 devinfo,
1127 brw_inst_opcode(devinfo, inst),
1128 brw_inst_src0_reg_type(devinfo, inst),
1129 brw_inst_src0_reg_file(devinfo, inst),
1130 brw_inst_src0_vstride(devinfo, inst),
1131 brw_inst_src0_width(devinfo, inst),
1132 brw_inst_src0_hstride(devinfo, inst),
1133 brw_inst_src0_da_reg_nr(devinfo, inst),
1134 brw_inst_src0_da1_subreg_nr(devinfo, inst),
1135 brw_inst_src0_abs(devinfo, inst),
1136 brw_inst_src0_negate(devinfo, inst));
1137 } else {
1138 return src_ia1(file,
1139 devinfo,
1140 brw_inst_opcode(devinfo, inst),
1141 brw_inst_src0_reg_type(devinfo, inst),
1142 brw_inst_src0_reg_file(devinfo, inst),
1143 brw_inst_src0_ia1_addr_imm(devinfo, inst),
1144 brw_inst_src0_ia_subreg_nr(devinfo, inst),
1145 brw_inst_src0_negate(devinfo, inst),
1146 brw_inst_src0_abs(devinfo, inst),
1147 brw_inst_src0_hstride(devinfo, inst),
1148 brw_inst_src0_width(devinfo, inst),
1149 brw_inst_src0_vstride(devinfo, inst));
1150 }
1151 } else {
1152 if (brw_inst_src0_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1153 return src_da16(file,
1154 devinfo,
1155 brw_inst_opcode(devinfo, inst),
1156 brw_inst_src0_reg_type(devinfo, inst),
1157 brw_inst_src0_reg_file(devinfo, inst),
1158 brw_inst_src0_vstride(devinfo, inst),
1159 brw_inst_src0_da_reg_nr(devinfo, inst),
1160 brw_inst_src0_da16_subreg_nr(devinfo, inst),
1161 brw_inst_src0_abs(devinfo, inst),
1162 brw_inst_src0_negate(devinfo, inst),
1163 brw_inst_src0_da16_swiz_x(devinfo, inst),
1164 brw_inst_src0_da16_swiz_y(devinfo, inst),
1165 brw_inst_src0_da16_swiz_z(devinfo, inst),
1166 brw_inst_src0_da16_swiz_w(devinfo, inst));
1167 } else {
1168 string(file, "Indirect align16 address mode not supported");
1169 return 1;
1170 }
1171 }
1172 }
1173
1174 static int
1175 src1(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
1176 {
1177 if (brw_inst_src1_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
1178 return imm(file, devinfo, brw_inst_src1_reg_type(devinfo, inst), inst);
1179 } else if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1180 if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1181 return src_da1(file,
1182 devinfo,
1183 brw_inst_opcode(devinfo, inst),
1184 brw_inst_src1_reg_type(devinfo, inst),
1185 brw_inst_src1_reg_file(devinfo, inst),
1186 brw_inst_src1_vstride(devinfo, inst),
1187 brw_inst_src1_width(devinfo, inst),
1188 brw_inst_src1_hstride(devinfo, inst),
1189 brw_inst_src1_da_reg_nr(devinfo, inst),
1190 brw_inst_src1_da1_subreg_nr(devinfo, inst),
1191 brw_inst_src1_abs(devinfo, inst),
1192 brw_inst_src1_negate(devinfo, inst));
1193 } else {
1194 return src_ia1(file,
1195 devinfo,
1196 brw_inst_opcode(devinfo, inst),
1197 brw_inst_src1_reg_type(devinfo, inst),
1198 brw_inst_src1_reg_file(devinfo, inst),
1199 brw_inst_src1_ia1_addr_imm(devinfo, inst),
1200 brw_inst_src1_ia_subreg_nr(devinfo, inst),
1201 brw_inst_src1_negate(devinfo, inst),
1202 brw_inst_src1_abs(devinfo, inst),
1203 brw_inst_src1_hstride(devinfo, inst),
1204 brw_inst_src1_width(devinfo, inst),
1205 brw_inst_src1_vstride(devinfo, inst));
1206 }
1207 } else {
1208 if (brw_inst_src1_address_mode(devinfo, inst) == BRW_ADDRESS_DIRECT) {
1209 return src_da16(file,
1210 devinfo,
1211 brw_inst_opcode(devinfo, inst),
1212 brw_inst_src1_reg_type(devinfo, inst),
1213 brw_inst_src1_reg_file(devinfo, inst),
1214 brw_inst_src1_vstride(devinfo, inst),
1215 brw_inst_src1_da_reg_nr(devinfo, inst),
1216 brw_inst_src1_da16_subreg_nr(devinfo, inst),
1217 brw_inst_src1_abs(devinfo, inst),
1218 brw_inst_src1_negate(devinfo, inst),
1219 brw_inst_src1_da16_swiz_x(devinfo, inst),
1220 brw_inst_src1_da16_swiz_y(devinfo, inst),
1221 brw_inst_src1_da16_swiz_z(devinfo, inst),
1222 brw_inst_src1_da16_swiz_w(devinfo, inst));
1223 } else {
1224 string(file, "Indirect align16 address mode not supported");
1225 return 1;
1226 }
1227 }
1228 }
1229
1230 static int
1231 qtr_ctrl(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
1232 {
1233 int qtr_ctl = brw_inst_qtr_control(devinfo, inst);
1234 int exec_size = 1 << brw_inst_exec_size(devinfo, inst);
1235
1236 if (exec_size == 8) {
1237 switch (qtr_ctl) {
1238 case 0:
1239 string(file, " 1Q");
1240 break;
1241 case 1:
1242 string(file, " 2Q");
1243 break;
1244 case 2:
1245 string(file, " 3Q");
1246 break;
1247 case 3:
1248 string(file, " 4Q");
1249 break;
1250 }
1251 } else if (exec_size == 16) {
1252 if (qtr_ctl < 2)
1253 string(file, " 1H");
1254 else
1255 string(file, " 2H");
1256 }
1257 return 0;
1258 }
1259
1260 #ifdef DEBUG
1261 static __attribute__((__unused__)) int
1262 brw_disassemble_imm(const struct brw_device_info *devinfo,
1263 uint32_t dw3, uint32_t dw2, uint32_t dw1, uint32_t dw0)
1264 {
1265 brw_inst inst;
1266 inst.data[0] = (((uint64_t) dw1) << 32) | ((uint64_t) dw0);
1267 inst.data[1] = (((uint64_t) dw3) << 32) | ((uint64_t) dw2);
1268 return brw_disassemble_inst(stderr, devinfo, &inst, false);
1269 }
1270 #endif
1271
1272 int
1273 brw_disassemble_inst(FILE *file, const struct brw_device_info *devinfo,
1274 brw_inst *inst, bool is_compacted)
1275 {
1276 int err = 0;
1277 int space = 0;
1278
1279 const enum opcode opcode = brw_inst_opcode(devinfo, inst);
1280
1281 if (brw_inst_pred_control(devinfo, inst)) {
1282 string(file, "(");
1283 err |= control(file, "predicate inverse", pred_inv,
1284 brw_inst_pred_inv(devinfo, inst), NULL);
1285 format(file, "f%ld", devinfo->gen >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0);
1286 if (brw_inst_flag_subreg_nr(devinfo, inst))
1287 format(file, ".%ld", brw_inst_flag_subreg_nr(devinfo, inst));
1288 if (brw_inst_access_mode(devinfo, inst) == BRW_ALIGN_1) {
1289 err |= control(file, "predicate control align1", pred_ctrl_align1,
1290 brw_inst_pred_control(devinfo, inst), NULL);
1291 } else {
1292 err |= control(file, "predicate control align16", pred_ctrl_align16,
1293 brw_inst_pred_control(devinfo, inst), NULL);
1294 }
1295 string(file, ") ");
1296 }
1297
1298 err |= print_opcode(file, opcode);
1299 err |= control(file, "saturate", saturate, brw_inst_saturate(devinfo, inst),
1300 NULL);
1301
1302 err |= control(file, "debug control", debug_ctrl,
1303 brw_inst_debug_control(devinfo, inst), NULL);
1304
1305 if (opcode == BRW_OPCODE_MATH) {
1306 string(file, " ");
1307 err |= control(file, "function", math_function,
1308 brw_inst_math_function(devinfo, inst), NULL);
1309 } else if (opcode != BRW_OPCODE_SEND && opcode != BRW_OPCODE_SENDC) {
1310 err |= control(file, "conditional modifier", conditional_modifier,
1311 brw_inst_cond_modifier(devinfo, inst), NULL);
1312
1313 /* If we're using the conditional modifier, print which flags reg is
1314 * used for it. Note that on gen6+, the embedded-condition SEL and
1315 * control flow doesn't update flags.
1316 */
1317 if (brw_inst_cond_modifier(devinfo, inst) &&
1318 (devinfo->gen < 6 || (opcode != BRW_OPCODE_SEL &&
1319 opcode != BRW_OPCODE_IF &&
1320 opcode != BRW_OPCODE_WHILE))) {
1321 format(file, ".f%ld",
1322 devinfo->gen >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0);
1323 if (brw_inst_flag_subreg_nr(devinfo, inst))
1324 format(file, ".%ld", brw_inst_flag_subreg_nr(devinfo, inst));
1325 }
1326 }
1327
1328 if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) {
1329 string(file, "(");
1330 err |= control(file, "execution size", exec_size,
1331 brw_inst_exec_size(devinfo, inst), NULL);
1332 string(file, ")");
1333 }
1334
1335 if (opcode == BRW_OPCODE_SEND && devinfo->gen < 6)
1336 format(file, " %ld", brw_inst_base_mrf(devinfo, inst));
1337
1338 if (has_uip(devinfo, opcode)) {
1339 /* Instructions that have UIP also have JIP. */
1340 pad(file, 16);
1341 format(file, "JIP: %d", brw_inst_jip(devinfo, inst));
1342 pad(file, 32);
1343 format(file, "UIP: %d", brw_inst_uip(devinfo, inst));
1344 } else if (has_jip(devinfo, opcode)) {
1345 pad(file, 16);
1346 if (devinfo->gen >= 7) {
1347 format(file, "JIP: %d", brw_inst_jip(devinfo, inst));
1348 } else {
1349 format(file, "JIP: %d", brw_inst_gen6_jump_count(devinfo, inst));
1350 }
1351 } else if (devinfo->gen < 6 && (opcode == BRW_OPCODE_BREAK ||
1352 opcode == BRW_OPCODE_CONTINUE ||
1353 opcode == BRW_OPCODE_ELSE)) {
1354 pad(file, 16);
1355 format(file, "Jump: %d", brw_inst_gen4_jump_count(devinfo, inst));
1356 pad(file, 32);
1357 format(file, "Pop: %ld", brw_inst_gen4_pop_count(devinfo, inst));
1358 } else if (devinfo->gen < 6 && (opcode == BRW_OPCODE_IF ||
1359 opcode == BRW_OPCODE_IFF ||
1360 opcode == BRW_OPCODE_HALT)) {
1361 pad(file, 16);
1362 format(file, "Jump: %d", brw_inst_gen4_jump_count(devinfo, inst));
1363 } else if (devinfo->gen < 6 && opcode == BRW_OPCODE_ENDIF) {
1364 pad(file, 16);
1365 format(file, "Pop: %ld", brw_inst_gen4_pop_count(devinfo, inst));
1366 } else if (opcode == BRW_OPCODE_JMPI) {
1367 pad(file, 16);
1368 err |= src1(file, devinfo, inst);
1369 } else if (opcode_descs[opcode].nsrc == 3) {
1370 pad(file, 16);
1371 err |= dest_3src(file, devinfo, inst);
1372
1373 pad(file, 32);
1374 err |= src0_3src(file, devinfo, inst);
1375
1376 pad(file, 48);
1377 err |= src1_3src(file, devinfo, inst);
1378
1379 pad(file, 64);
1380 err |= src2_3src(file, devinfo, inst);
1381 } else {
1382 if (opcode_descs[opcode].ndst > 0) {
1383 pad(file, 16);
1384 err |= dest(file, devinfo, inst);
1385 }
1386
1387 if (opcode_descs[opcode].nsrc > 0) {
1388 pad(file, 32);
1389 err |= src0(file, devinfo, inst);
1390 }
1391
1392 if (opcode_descs[opcode].nsrc > 1) {
1393 pad(file, 48);
1394 err |= src1(file, devinfo, inst);
1395 }
1396 }
1397
1398 if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC) {
1399 enum brw_message_target sfid = brw_inst_sfid(devinfo, inst);
1400
1401 if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
1402 /* show the indirect descriptor source */
1403 pad(file, 48);
1404 err |= src1(file, devinfo, inst);
1405 }
1406
1407 newline(file);
1408 pad(file, 16);
1409 space = 0;
1410
1411 fprintf(file, " ");
1412 err |= control(file, "SFID", devinfo->gen >= 6 ? gen6_sfid : gen4_sfid,
1413 sfid, &space);
1414
1415
1416 if (brw_inst_src1_reg_file(devinfo, inst) != BRW_IMMEDIATE_VALUE) {
1417 format(file, " indirect");
1418 } else {
1419 switch (sfid) {
1420 case BRW_SFID_MATH:
1421 err |= control(file, "math function", math_function,
1422 brw_inst_math_msg_function(devinfo, inst), &space);
1423 err |= control(file, "math saturate", math_saturate,
1424 brw_inst_math_msg_saturate(devinfo, inst), &space);
1425 err |= control(file, "math signed", math_signed,
1426 brw_inst_math_msg_signed_int(devinfo, inst), &space);
1427 err |= control(file, "math scalar", math_scalar,
1428 brw_inst_math_msg_data_type(devinfo, inst), &space);
1429 err |= control(file, "math precision", math_precision,
1430 brw_inst_math_msg_precision(devinfo, inst), &space);
1431 break;
1432 case BRW_SFID_SAMPLER:
1433 if (devinfo->gen >= 5) {
1434 err |= control(file, "sampler message", gen5_sampler_msg_type,
1435 brw_inst_sampler_msg_type(devinfo, inst), &space);
1436 err |= control(file, "sampler simd mode", gen5_sampler_simd_mode,
1437 brw_inst_sampler_simd_mode(devinfo, inst), &space);
1438 format(file, " Surface = %ld Sampler = %ld",
1439 brw_inst_binding_table_index(devinfo, inst),
1440 brw_inst_sampler(devinfo, inst));
1441 } else {
1442 format(file, " (%ld, %ld, %ld, ",
1443 brw_inst_binding_table_index(devinfo, inst),
1444 brw_inst_sampler(devinfo, inst),
1445 brw_inst_sampler_msg_type(devinfo, inst));
1446 if (!devinfo->is_g4x) {
1447 err |= control(file, "sampler target format",
1448 sampler_target_format,
1449 brw_inst_sampler_return_format(devinfo, inst), NULL);
1450 }
1451 string(file, ")");
1452 }
1453 break;
1454 case GEN6_SFID_DATAPORT_SAMPLER_CACHE:
1455 /* aka BRW_SFID_DATAPORT_READ on Gen4-5 */
1456 if (devinfo->gen >= 6) {
1457 format(file, " (%ld, %ld, %ld, %ld)",
1458 brw_inst_binding_table_index(devinfo, inst),
1459 brw_inst_dp_msg_control(devinfo, inst),
1460 brw_inst_dp_msg_type(devinfo, inst),
1461 devinfo->gen >= 7 ? 0 : brw_inst_dp_write_commit(devinfo, inst));
1462 } else {
1463 bool is_965 = devinfo->gen == 4 && !devinfo->is_g4x;
1464 err |= control(file, "DP read message type",
1465 is_965 ? gen4_dp_read_port_msg_type :
1466 g45_dp_read_port_msg_type,
1467 brw_inst_dp_read_msg_type(devinfo, inst),
1468 &space);
1469
1470 format(file, " MsgCtrl = 0x%lx",
1471 brw_inst_dp_read_msg_control(devinfo, inst));
1472
1473 format(file, " Surface = %ld", brw_inst_binding_table_index(devinfo, inst));
1474 }
1475 break;
1476
1477 case GEN6_SFID_DATAPORT_RENDER_CACHE: {
1478 /* aka BRW_SFID_DATAPORT_WRITE on Gen4-5 */
1479 unsigned msg_type = brw_inst_dp_write_msg_type(devinfo, inst);
1480
1481 err |= control(file, "DP rc message type",
1482 devinfo->gen >= 6 ? dp_rc_msg_type_gen6
1483 : dp_write_port_msg_type,
1484 msg_type, &space);
1485
1486 bool is_rt_write = msg_type ==
1487 (devinfo->gen >= 6 ? GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
1488 : BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE);
1489
1490 if (is_rt_write) {
1491 err |= control(file, "RT message type", m_rt_write_subtype,
1492 brw_inst_rt_message_type(devinfo, inst), &space);
1493 if (devinfo->gen >= 6 && brw_inst_rt_slot_group(devinfo, inst))
1494 string(file, " Hi");
1495 if (brw_inst_rt_last(devinfo, inst))
1496 string(file, " LastRT");
1497 if (devinfo->gen < 7 && brw_inst_dp_write_commit(devinfo, inst))
1498 string(file, " WriteCommit");
1499 } else {
1500 format(file, " MsgCtrl = 0x%lx",
1501 brw_inst_dp_write_msg_control(devinfo, inst));
1502 }
1503
1504 format(file, " Surface = %ld", brw_inst_binding_table_index(devinfo, inst));
1505 break;
1506 }
1507
1508 case BRW_SFID_URB:
1509 format(file, " %ld", brw_inst_urb_global_offset(devinfo, inst));
1510
1511 space = 1;
1512 if (devinfo->gen >= 7) {
1513 err |= control(file, "urb opcode", gen7_urb_opcode,
1514 brw_inst_urb_opcode(devinfo, inst), &space);
1515 } else if (devinfo->gen >= 5) {
1516 err |= control(file, "urb opcode", gen5_urb_opcode,
1517 brw_inst_urb_opcode(devinfo, inst), &space);
1518 }
1519 err |= control(file, "urb swizzle", urb_swizzle,
1520 brw_inst_urb_swizzle_control(devinfo, inst), &space);
1521 if (devinfo->gen < 7) {
1522 err |= control(file, "urb allocate", urb_allocate,
1523 brw_inst_urb_allocate(devinfo, inst), &space);
1524 err |= control(file, "urb used", urb_used,
1525 brw_inst_urb_used(devinfo, inst), &space);
1526 }
1527 if (devinfo->gen < 8) {
1528 err |= control(file, "urb complete", urb_complete,
1529 brw_inst_urb_complete(devinfo, inst), &space);
1530 }
1531 break;
1532 case BRW_SFID_THREAD_SPAWNER:
1533 break;
1534
1535 case BRW_SFID_MESSAGE_GATEWAY:
1536 format(file, " (%s)",
1537 gen7_gateway_subfuncid[brw_inst_gateway_subfuncid(devinfo, inst)]);
1538 break;
1539
1540 case GEN7_SFID_DATAPORT_DATA_CACHE:
1541 if (devinfo->gen >= 7) {
1542 format(file, " (");
1543
1544 err |= control(file, "DP DC0 message type",
1545 dp_dc0_msg_type_gen7,
1546 brw_inst_dp_msg_type(devinfo, inst), &space);
1547
1548 format(file, ", %ld, ", brw_inst_binding_table_index(devinfo, inst));
1549
1550 switch (brw_inst_dp_msg_type(devinfo, inst)) {
1551 case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
1552 control(file, "atomic op", aop,
1553 brw_inst_imm_ud(devinfo, inst) >> 8 & 0xf, &space);
1554 break;
1555 default:
1556 format(file, "%ld", brw_inst_dp_msg_control(devinfo, inst));
1557 }
1558 format(file, ")");
1559 break;
1560 }
1561 /* FALLTHROUGH */
1562
1563 case HSW_SFID_DATAPORT_DATA_CACHE_1: {
1564 if (devinfo->gen >= 7) {
1565 format(file, " (");
1566
1567 unsigned msg_ctrl = brw_inst_dp_msg_control(devinfo, inst);
1568
1569 err |= control(file, "DP DC1 message type",
1570 dp_dc1_msg_type_hsw,
1571 brw_inst_dp_msg_type(devinfo, inst), &space);
1572
1573 format(file, ", Surface = %ld, ",
1574 brw_inst_binding_table_index(devinfo, inst));
1575
1576 switch (brw_inst_dp_msg_type(devinfo, inst)) {
1577 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP:
1578 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP:
1579 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP:
1580 format(file, "SIMD%d,", (msg_ctrl & (1 << 4)) ? 8 : 16);
1581 /* fallthrough */
1582 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2:
1583 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2:
1584 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2:
1585 control(file, "atomic op", aop, msg_ctrl & 0xf, &space);
1586 break;
1587 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ:
1588 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE:
1589 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ:
1590 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE: {
1591 static const char *simd_modes[] = { "4x2", "16", "8" };
1592 format(file, "SIMD%s, Mask = 0x%x",
1593 simd_modes[msg_ctrl >> 4], msg_ctrl & 0xf);
1594 break;
1595 }
1596 default:
1597 format(file, "0x%x", msg_ctrl);
1598 }
1599 format(file, ")");
1600 break;
1601 }
1602 /* FALLTHROUGH */
1603 }
1604
1605 case GEN7_SFID_PIXEL_INTERPOLATOR:
1606 if (devinfo->gen >= 7) {
1607 format(file, " (%s, %s, 0x%02lx)",
1608 brw_inst_pi_nopersp(devinfo, inst) ? "linear" : "persp",
1609 pixel_interpolator_msg_types[brw_inst_pi_message_type(devinfo, inst)],
1610 brw_inst_pi_message_data(devinfo, inst));
1611 break;
1612 }
1613 /* FALLTHROUGH */
1614
1615 default:
1616 format(file, "unsupported shared function ID %d", sfid);
1617 break;
1618 }
1619
1620 if (space)
1621 string(file, " ");
1622 format(file, "mlen %ld", brw_inst_mlen(devinfo, inst));
1623 format(file, " rlen %ld", brw_inst_rlen(devinfo, inst));
1624 }
1625 }
1626 pad(file, 64);
1627 if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) {
1628 string(file, "{");
1629 space = 1;
1630 err |= control(file, "access mode", access_mode,
1631 brw_inst_access_mode(devinfo, inst), &space);
1632 if (devinfo->gen >= 6) {
1633 err |= control(file, "write enable control", wectrl,
1634 brw_inst_mask_control(devinfo, inst), &space);
1635 } else {
1636 err |= control(file, "mask control", mask_ctrl,
1637 brw_inst_mask_control(devinfo, inst), &space);
1638 }
1639 err |= control(file, "dependency control", dep_ctrl,
1640 ((brw_inst_no_dd_check(devinfo, inst) << 1) |
1641 brw_inst_no_dd_clear(devinfo, inst)), &space);
1642
1643 if (devinfo->gen >= 6)
1644 err |= qtr_ctrl(file, devinfo, inst);
1645 else {
1646 if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_COMPRESSED &&
1647 opcode_descs[opcode].ndst > 0 &&
1648 brw_inst_dst_reg_file(devinfo, inst) == BRW_MESSAGE_REGISTER_FILE &&
1649 brw_inst_dst_da_reg_nr(devinfo, inst) & BRW_MRF_COMPR4) {
1650 format(file, " compr4");
1651 } else {
1652 err |= control(file, "compression control", compr_ctrl,
1653 brw_inst_qtr_control(devinfo, inst), &space);
1654 }
1655 }
1656
1657 err |= control(file, "compaction", cmpt_ctrl, is_compacted, &space);
1658 err |= control(file, "thread control", thread_ctrl,
1659 brw_inst_thread_control(devinfo, inst), &space);
1660 if (has_branch_ctrl(devinfo, opcode)) {
1661 err |= control(file, "branch ctrl", branch_ctrl,
1662 brw_inst_branch_control(devinfo, inst), &space);
1663 } else if (devinfo->gen >= 6) {
1664 err |= control(file, "acc write control", accwr,
1665 brw_inst_acc_wr_control(devinfo, inst), &space);
1666 }
1667 if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC)
1668 err |= control(file, "end of thread", end_of_thread,
1669 brw_inst_eot(devinfo, inst), &space);
1670 if (space)
1671 string(file, " ");
1672 string(file, "}");
1673 }
1674 string(file, ";");
1675 newline(file);
1676 return err;
1677 }