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1621769b9dd4795ada517f76193e7fafae570ef9
[mesa.git] / src / mesa / drivers / dri / i965 / brw_disasm.c
1 /*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23 #include <stdio.h>
24 #include <stdlib.h>
25 #include <string.h>
26 #include <getopt.h>
27 #include <unistd.h>
28 #include <stdarg.h>
29
30 #include "main/mtypes.h"
31
32 #include "brw_context.h"
33 #include "brw_defines.h"
34
35 const struct opcode_desc opcode_descs[128] = {
36 [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 },
37 [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 },
38 [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 },
39 [BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 },
40 [BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 },
41 [BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 },
42 [BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 },
43 [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 },
44
45 [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 },
46 [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 },
47 [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 },
48 [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 },
49 [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 },
50 [BRW_OPCODE_MAD] = { .name = "mad", .nsrc = 3, .ndst = 1 },
51 [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 },
52 [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 },
53 [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 },
54 [BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 },
55 [BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 },
56 [BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 },
57 [BRW_OPCODE_MATH] = { .name = "math", .nsrc = 2, .ndst = 1 },
58
59 [BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 },
60 [BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 },
61 [BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 },
62 [BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 },
63 [BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 },
64 [BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 },
65 [BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 },
66 [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 },
67 [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 },
68 [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 },
69 [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 },
70
71 [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 },
72 [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 },
73 [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
74 [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 0, .ndst = 0 },
75 [BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 },
76 [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 2, .ndst = 1 },
77 [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 2, .ndst = 0 },
78 [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 2, .ndst = 0 },
79 [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 2, .ndst = 0 },
80 [BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 1, .ndst = 0 },
81 [BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 1, .ndst = 0 },
82 [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 },
83 [BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 },
84 [BRW_OPCODE_MRESTORE] = { .name = "mrest", .nsrc = 1, .ndst = 1 },
85 [BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 },
86 [BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 },
87 [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 },
88 [BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 2, .ndst = 0 },
89 };
90 static const struct opcode_desc *opcode = opcode_descs;
91
92 static const char * const conditional_modifier[16] = {
93 [BRW_CONDITIONAL_NONE] = "",
94 [BRW_CONDITIONAL_Z] = ".e",
95 [BRW_CONDITIONAL_NZ] = ".ne",
96 [BRW_CONDITIONAL_G] = ".g",
97 [BRW_CONDITIONAL_GE] = ".ge",
98 [BRW_CONDITIONAL_L] = ".l",
99 [BRW_CONDITIONAL_LE] = ".le",
100 [BRW_CONDITIONAL_R] = ".r",
101 [BRW_CONDITIONAL_O] = ".o",
102 [BRW_CONDITIONAL_U] = ".u",
103 };
104
105 static const char * const negate[2] = {
106 [0] = "",
107 [1] = "-",
108 };
109
110 static const char * const _abs[2] = {
111 [0] = "",
112 [1] = "(abs)",
113 };
114
115 static const char * const vert_stride[16] = {
116 [0] = "0",
117 [1] = "1",
118 [2] = "2",
119 [3] = "4",
120 [4] = "8",
121 [5] = "16",
122 [6] = "32",
123 [15] = "VxH",
124 };
125
126 static const char * const width[8] = {
127 [0] = "1",
128 [1] = "2",
129 [2] = "4",
130 [3] = "8",
131 [4] = "16",
132 };
133
134 static const char * const horiz_stride[4] = {
135 [0] = "0",
136 [1] = "1",
137 [2] = "2",
138 [3] = "4"
139 };
140
141 static const char * const chan_sel[4] = {
142 [0] = "x",
143 [1] = "y",
144 [2] = "z",
145 [3] = "w",
146 };
147
148 static const char * const debug_ctrl[2] = {
149 [0] = "",
150 [1] = ".breakpoint"
151 };
152
153 static const char * const saturate[2] = {
154 [0] = "",
155 [1] = ".sat"
156 };
157
158 static const char * const accwr[2] = {
159 [0] = "",
160 [1] = "AccWrEnable"
161 };
162
163 static const char * const wectrl[2] = {
164 [0] = "WE_normal",
165 [1] = "WE_all"
166 };
167
168 static const char * const exec_size[8] = {
169 [0] = "1",
170 [1] = "2",
171 [2] = "4",
172 [3] = "8",
173 [4] = "16",
174 [5] = "32"
175 };
176
177 static const char * const pred_inv[2] = {
178 [0] = "+",
179 [1] = "-"
180 };
181
182 static const char * const pred_ctrl_align16[16] = {
183 [1] = "",
184 [2] = ".x",
185 [3] = ".y",
186 [4] = ".z",
187 [5] = ".w",
188 [6] = ".any4h",
189 [7] = ".all4h",
190 };
191
192 static const char * const pred_ctrl_align1[16] = {
193 [1] = "",
194 [2] = ".anyv",
195 [3] = ".allv",
196 [4] = ".any2h",
197 [5] = ".all2h",
198 [6] = ".any4h",
199 [7] = ".all4h",
200 [8] = ".any8h",
201 [9] = ".all8h",
202 [10] = ".any16h",
203 [11] = ".all16h",
204 };
205
206 static const char * const thread_ctrl[4] = {
207 [0] = "",
208 [2] = "switch"
209 };
210
211 static const char * const compr_ctrl[4] = {
212 [0] = "",
213 [1] = "sechalf",
214 [2] = "compr",
215 [3] = "compr4",
216 };
217
218 static const char * const dep_ctrl[4] = {
219 [0] = "",
220 [1] = "NoDDClr",
221 [2] = "NoDDChk",
222 [3] = "NoDDClr,NoDDChk",
223 };
224
225 static const char * const mask_ctrl[4] = {
226 [0] = "",
227 [1] = "nomask",
228 };
229
230 static const char * const access_mode[2] = {
231 [0] = "align1",
232 [1] = "align16",
233 };
234
235 static const char * const reg_encoding[8] = {
236 [0] = "UD",
237 [1] = "D",
238 [2] = "UW",
239 [3] = "W",
240 [4] = "UB",
241 [5] = "B",
242 [7] = "F"
243 };
244
245 const int reg_type_size[8] = {
246 [0] = 4,
247 [1] = 4,
248 [2] = 2,
249 [3] = 2,
250 [4] = 1,
251 [5] = 1,
252 [7] = 4
253 };
254
255 static const char * const reg_file[4] = {
256 [0] = "A",
257 [1] = "g",
258 [2] = "m",
259 [3] = "imm",
260 };
261
262 static const char * const writemask[16] = {
263 [0x0] = ".",
264 [0x1] = ".x",
265 [0x2] = ".y",
266 [0x3] = ".xy",
267 [0x4] = ".z",
268 [0x5] = ".xz",
269 [0x6] = ".yz",
270 [0x7] = ".xyz",
271 [0x8] = ".w",
272 [0x9] = ".xw",
273 [0xa] = ".yw",
274 [0xb] = ".xyw",
275 [0xc] = ".zw",
276 [0xd] = ".xzw",
277 [0xe] = ".yzw",
278 [0xf] = "",
279 };
280
281 static const char * const end_of_thread[2] = {
282 [0] = "",
283 [1] = "EOT"
284 };
285
286 static const char * const target_function[16] = {
287 [BRW_SFID_NULL] = "null",
288 [BRW_SFID_MATH] = "math",
289 [BRW_SFID_SAMPLER] = "sampler",
290 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
291 [BRW_SFID_DATAPORT_READ] = "read",
292 [BRW_SFID_DATAPORT_WRITE] = "write",
293 [BRW_SFID_URB] = "urb",
294 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner"
295 };
296
297 static const char * const target_function_gen6[16] = {
298 [BRW_SFID_NULL] = "null",
299 [BRW_SFID_MATH] = "math",
300 [BRW_SFID_SAMPLER] = "sampler",
301 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
302 [BRW_SFID_URB] = "urb",
303 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
304 [GEN6_SFID_DATAPORT_SAMPLER_CACHE] = "sampler",
305 [GEN6_SFID_DATAPORT_RENDER_CACHE] = "render",
306 [GEN6_SFID_DATAPORT_CONSTANT_CACHE] = "const",
307 [GEN7_SFID_DATAPORT_DATA_CACHE] = "data"
308 };
309
310 static const char * const dp_rc_msg_type_gen6[16] = {
311 [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read",
312 [GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read",
313 [GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read",
314 [GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read",
315 [GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ] = "OWORD unaligned block read",
316 [GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ] = "DWORD scattered read",
317 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE] = "DWORD atomic write",
318 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE] = "OWORD block write",
319 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE] = "OWORD dual block write",
320 [GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE] = "media block write",
321 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE] = "DWORD scattered write",
322 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write",
323 [GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write",
324 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORMc write",
325 };
326
327 static const char * const math_function[16] = {
328 [BRW_MATH_FUNCTION_INV] = "inv",
329 [BRW_MATH_FUNCTION_LOG] = "log",
330 [BRW_MATH_FUNCTION_EXP] = "exp",
331 [BRW_MATH_FUNCTION_SQRT] = "sqrt",
332 [BRW_MATH_FUNCTION_RSQ] = "rsq",
333 [BRW_MATH_FUNCTION_SIN] = "sin",
334 [BRW_MATH_FUNCTION_COS] = "cos",
335 [BRW_MATH_FUNCTION_SINCOS] = "sincos",
336 [BRW_MATH_FUNCTION_TAN] = "tan",
337 [BRW_MATH_FUNCTION_POW] = "pow",
338 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod",
339 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intdiv",
340 [BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod",
341 };
342
343 static const char * const math_saturate[2] = {
344 [0] = "",
345 [1] = "sat"
346 };
347
348 static const char * const math_signed[2] = {
349 [0] = "",
350 [1] = "signed"
351 };
352
353 static const char * const math_scalar[2] = {
354 [0] = "",
355 [1] = "scalar"
356 };
357
358 static const char * const math_precision[2] = {
359 [0] = "",
360 [1] = "partial_precision"
361 };
362
363 static const char * const urb_opcode[2] = {
364 [0] = "urb_write",
365 [1] = "ff_sync",
366 };
367
368 static const char * const urb_swizzle[4] = {
369 [BRW_URB_SWIZZLE_NONE] = "",
370 [BRW_URB_SWIZZLE_INTERLEAVE] = "interleave",
371 [BRW_URB_SWIZZLE_TRANSPOSE] = "transpose",
372 };
373
374 static const char * const urb_allocate[2] = {
375 [0] = "",
376 [1] = "allocate"
377 };
378
379 static const char * const urb_used[2] = {
380 [0] = "",
381 [1] = "used"
382 };
383
384 static const char * const urb_complete[2] = {
385 [0] = "",
386 [1] = "complete"
387 };
388
389 static const char * const sampler_target_format[4] = {
390 [0] = "F",
391 [2] = "UD",
392 [3] = "D"
393 };
394
395
396 static int column;
397
398 static int string (FILE *file, const char *string)
399 {
400 fputs (string, file);
401 column += strlen (string);
402 return 0;
403 }
404
405 static int format (FILE *f, const char *format, ...)
406 {
407 char buf[1024];
408 va_list args;
409 va_start (args, format);
410
411 vsnprintf (buf, sizeof (buf) - 1, format, args);
412 va_end (args);
413 string (f, buf);
414 return 0;
415 }
416
417 static int newline (FILE *f)
418 {
419 putc ('\n', f);
420 column = 0;
421 return 0;
422 }
423
424 static int pad (FILE *f, int c)
425 {
426 do
427 string (f, " ");
428 while (column < c);
429 return 0;
430 }
431
432 static int control (FILE *file, const char *name, const char * const ctrl[],
433 GLuint id, int *space)
434 {
435 if (!ctrl[id]) {
436 fprintf (file, "*** invalid %s value %d ",
437 name, id);
438 return 1;
439 }
440 if (ctrl[id][0])
441 {
442 if (space && *space)
443 string (file, " ");
444 string (file, ctrl[id]);
445 if (space)
446 *space = 1;
447 }
448 return 0;
449 }
450
451 static int print_opcode (FILE *file, int id)
452 {
453 if (!opcode[id].name) {
454 format (file, "*** invalid opcode value %d ", id);
455 return 1;
456 }
457 string (file, opcode[id].name);
458 return 0;
459 }
460
461 static int reg (FILE *file, GLuint _reg_file, GLuint _reg_nr)
462 {
463 int err = 0;
464
465 /* Clear the Compr4 instruction compression bit. */
466 if (_reg_file == BRW_MESSAGE_REGISTER_FILE)
467 _reg_nr &= ~(1 << 7);
468
469 if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
470 switch (_reg_nr & 0xf0) {
471 case BRW_ARF_NULL:
472 string (file, "null");
473 return -1;
474 case BRW_ARF_ADDRESS:
475 format (file, "a%d", _reg_nr & 0x0f);
476 break;
477 case BRW_ARF_ACCUMULATOR:
478 format (file, "acc%d", _reg_nr & 0x0f);
479 break;
480 case BRW_ARF_FLAG:
481 format (file, "f%d", _reg_nr & 0x0f);
482 break;
483 case BRW_ARF_MASK:
484 format (file, "mask%d", _reg_nr & 0x0f);
485 break;
486 case BRW_ARF_MASK_STACK:
487 format (file, "msd%d", _reg_nr & 0x0f);
488 break;
489 case BRW_ARF_STATE:
490 format (file, "sr%d", _reg_nr & 0x0f);
491 break;
492 case BRW_ARF_CONTROL:
493 format (file, "cr%d", _reg_nr & 0x0f);
494 break;
495 case BRW_ARF_NOTIFICATION_COUNT:
496 format (file, "n%d", _reg_nr & 0x0f);
497 break;
498 case BRW_ARF_IP:
499 string (file, "ip");
500 return -1;
501 break;
502 default:
503 format (file, "ARF%d", _reg_nr);
504 break;
505 }
506 } else {
507 err |= control (file, "src reg file", reg_file, _reg_file, NULL);
508 format (file, "%d", _reg_nr);
509 }
510 return err;
511 }
512
513 static int dest (FILE *file, struct brw_instruction *inst)
514 {
515 int err = 0;
516
517 if (inst->header.access_mode == BRW_ALIGN_1)
518 {
519 if (inst->bits1.da1.dest_address_mode == BRW_ADDRESS_DIRECT)
520 {
521 err |= reg (file, inst->bits1.da1.dest_reg_file, inst->bits1.da1.dest_reg_nr);
522 if (err == -1)
523 return 0;
524 if (inst->bits1.da1.dest_subreg_nr)
525 format (file, ".%d", inst->bits1.da1.dest_subreg_nr /
526 reg_type_size[inst->bits1.da1.dest_reg_type]);
527 string (file, "<");
528 err |= control (file, "horiz stride", horiz_stride, inst->bits1.da1.dest_horiz_stride, NULL);
529 string (file, ">");
530 err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da1.dest_reg_type, NULL);
531 }
532 else
533 {
534 string (file, "g[a0");
535 if (inst->bits1.ia1.dest_subreg_nr)
536 format (file, ".%d", inst->bits1.ia1.dest_subreg_nr /
537 reg_type_size[inst->bits1.ia1.dest_reg_type]);
538 if (inst->bits1.ia1.dest_indirect_offset)
539 format (file, " %d", inst->bits1.ia1.dest_indirect_offset);
540 string (file, "]<");
541 err |= control (file, "horiz stride", horiz_stride, inst->bits1.ia1.dest_horiz_stride, NULL);
542 string (file, ">");
543 err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.ia1.dest_reg_type, NULL);
544 }
545 }
546 else
547 {
548 if (inst->bits1.da16.dest_address_mode == BRW_ADDRESS_DIRECT)
549 {
550 err |= reg (file, inst->bits1.da16.dest_reg_file, inst->bits1.da16.dest_reg_nr);
551 if (err == -1)
552 return 0;
553 if (inst->bits1.da16.dest_subreg_nr)
554 format (file, ".%d", inst->bits1.da16.dest_subreg_nr /
555 reg_type_size[inst->bits1.da16.dest_reg_type]);
556 string (file, "<1>");
557 err |= control (file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL);
558 err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da16.dest_reg_type, NULL);
559 }
560 else
561 {
562 err = 1;
563 string (file, "Indirect align16 address mode not supported");
564 }
565 }
566
567 return 0;
568 }
569
570 static int dest_3src (FILE *file, struct brw_instruction *inst)
571 {
572 int err = 0;
573 uint32_t reg_file;
574
575 if (inst->bits1.da3src.dest_reg_file)
576 reg_file = BRW_MESSAGE_REGISTER_FILE;
577 else
578 reg_file = BRW_GENERAL_REGISTER_FILE;
579
580 err |= reg (file, reg_file, inst->bits1.da3src.dest_reg_nr);
581 if (err == -1)
582 return 0;
583 if (inst->bits1.da3src.dest_subreg_nr)
584 format (file, ".%d", inst->bits1.da3src.dest_subreg_nr);
585 string (file, "<1>");
586 err |= control (file, "writemask", writemask, inst->bits1.da3src.dest_writemask, NULL);
587 err |= control (file, "dest reg encoding", reg_encoding, BRW_REGISTER_TYPE_F, NULL);
588
589 return 0;
590 }
591
592 static int src_align1_region (FILE *file,
593 GLuint _vert_stride, GLuint _width, GLuint _horiz_stride)
594 {
595 int err = 0;
596 string (file, "<");
597 err |= control (file, "vert stride", vert_stride, _vert_stride, NULL);
598 string (file, ",");
599 err |= control (file, "width", width, _width, NULL);
600 string (file, ",");
601 err |= control (file, "horiz_stride", horiz_stride, _horiz_stride, NULL);
602 string (file, ">");
603 return err;
604 }
605
606 static int src_da1 (FILE *file, GLuint type, GLuint _reg_file,
607 GLuint _vert_stride, GLuint _width, GLuint _horiz_stride,
608 GLuint reg_num, GLuint sub_reg_num, GLuint __abs, GLuint _negate)
609 {
610 int err = 0;
611 err |= control (file, "negate", negate, _negate, NULL);
612 err |= control (file, "abs", _abs, __abs, NULL);
613
614 err |= reg (file, _reg_file, reg_num);
615 if (err == -1)
616 return 0;
617 if (sub_reg_num)
618 format (file, ".%d", sub_reg_num / reg_type_size[type]); /* use formal style like spec */
619 src_align1_region (file, _vert_stride, _width, _horiz_stride);
620 err |= control (file, "src reg encoding", reg_encoding, type, NULL);
621 return err;
622 }
623
624 static int src_ia1 (FILE *file,
625 GLuint type,
626 GLuint _reg_file,
627 GLint _addr_imm,
628 GLuint _addr_subreg_nr,
629 GLuint _negate,
630 GLuint __abs,
631 GLuint _addr_mode,
632 GLuint _horiz_stride,
633 GLuint _width,
634 GLuint _vert_stride)
635 {
636 int err = 0;
637 err |= control (file, "negate", negate, _negate, NULL);
638 err |= control (file, "abs", _abs, __abs, NULL);
639
640 string (file, "g[a0");
641 if (_addr_subreg_nr)
642 format (file, ".%d", _addr_subreg_nr);
643 if (_addr_imm)
644 format (file, " %d", _addr_imm);
645 string (file, "]");
646 src_align1_region (file, _vert_stride, _width, _horiz_stride);
647 err |= control (file, "src reg encoding", reg_encoding, type, NULL);
648 return err;
649 }
650
651 static int src_da16 (FILE *file,
652 GLuint _reg_type,
653 GLuint _reg_file,
654 GLuint _vert_stride,
655 GLuint _reg_nr,
656 GLuint _subreg_nr,
657 GLuint __abs,
658 GLuint _negate,
659 GLuint swz_x,
660 GLuint swz_y,
661 GLuint swz_z,
662 GLuint swz_w)
663 {
664 int err = 0;
665 err |= control (file, "negate", negate, _negate, NULL);
666 err |= control (file, "abs", _abs, __abs, NULL);
667
668 err |= reg (file, _reg_file, _reg_nr);
669 if (err == -1)
670 return 0;
671 if (_subreg_nr)
672 /* bit4 for subreg number byte addressing. Make this same meaning as
673 in da1 case, so output looks consistent. */
674 format (file, ".%d", 16 / reg_type_size[_reg_type]);
675 string (file, "<");
676 err |= control (file, "vert stride", vert_stride, _vert_stride, NULL);
677 string (file, ",4,1>");
678 /*
679 * Three kinds of swizzle display:
680 * identity - nothing printed
681 * 1->all - print the single channel
682 * 1->1 - print the mapping
683 */
684 if (swz_x == BRW_CHANNEL_X &&
685 swz_y == BRW_CHANNEL_Y &&
686 swz_z == BRW_CHANNEL_Z &&
687 swz_w == BRW_CHANNEL_W)
688 {
689 ;
690 }
691 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
692 {
693 string (file, ".");
694 err |= control (file, "channel select", chan_sel, swz_x, NULL);
695 }
696 else
697 {
698 string (file, ".");
699 err |= control (file, "channel select", chan_sel, swz_x, NULL);
700 err |= control (file, "channel select", chan_sel, swz_y, NULL);
701 err |= control (file, "channel select", chan_sel, swz_z, NULL);
702 err |= control (file, "channel select", chan_sel, swz_w, NULL);
703 }
704 err |= control (file, "src da16 reg type", reg_encoding, _reg_type, NULL);
705 return err;
706 }
707
708 static int src0_3src (FILE *file, struct brw_instruction *inst)
709 {
710 int err = 0;
711 GLuint swz_x = (inst->bits2.da3src.src0_swizzle >> 0) & 0x3;
712 GLuint swz_y = (inst->bits2.da3src.src0_swizzle >> 2) & 0x3;
713 GLuint swz_z = (inst->bits2.da3src.src0_swizzle >> 4) & 0x3;
714 GLuint swz_w = (inst->bits2.da3src.src0_swizzle >> 6) & 0x3;
715
716 err |= control (file, "negate", negate, inst->bits1.da3src.src0_negate, NULL);
717 err |= control (file, "abs", _abs, inst->bits1.da3src.src0_abs, NULL);
718
719 err |= reg (file, BRW_GENERAL_REGISTER_FILE, inst->bits2.da3src.src0_reg_nr);
720 if (err == -1)
721 return 0;
722 if (inst->bits2.da3src.src0_subreg_nr)
723 format (file, ".%d", inst->bits2.da3src.src0_subreg_nr);
724 string (file, "<4,1,1>");
725 err |= control (file, "src da16 reg type", reg_encoding,
726 BRW_REGISTER_TYPE_F, NULL);
727 /*
728 * Three kinds of swizzle display:
729 * identity - nothing printed
730 * 1->all - print the single channel
731 * 1->1 - print the mapping
732 */
733 if (swz_x == BRW_CHANNEL_X &&
734 swz_y == BRW_CHANNEL_Y &&
735 swz_z == BRW_CHANNEL_Z &&
736 swz_w == BRW_CHANNEL_W)
737 {
738 ;
739 }
740 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
741 {
742 string (file, ".");
743 err |= control (file, "channel select", chan_sel, swz_x, NULL);
744 }
745 else
746 {
747 string (file, ".");
748 err |= control (file, "channel select", chan_sel, swz_x, NULL);
749 err |= control (file, "channel select", chan_sel, swz_y, NULL);
750 err |= control (file, "channel select", chan_sel, swz_z, NULL);
751 err |= control (file, "channel select", chan_sel, swz_w, NULL);
752 }
753 return err;
754 }
755
756 static int src1_3src (FILE *file, struct brw_instruction *inst)
757 {
758 int err = 0;
759 GLuint swz_x = (inst->bits2.da3src.src1_swizzle >> 0) & 0x3;
760 GLuint swz_y = (inst->bits2.da3src.src1_swizzle >> 2) & 0x3;
761 GLuint swz_z = (inst->bits2.da3src.src1_swizzle >> 4) & 0x3;
762 GLuint swz_w = (inst->bits2.da3src.src1_swizzle >> 6) & 0x3;
763 GLuint src1_subreg_nr = (inst->bits2.da3src.src1_subreg_nr_low |
764 (inst->bits3.da3src.src1_subreg_nr_high << 2));
765
766 err |= control (file, "negate", negate, inst->bits1.da3src.src1_negate,
767 NULL);
768 err |= control (file, "abs", _abs, inst->bits1.da3src.src1_abs, NULL);
769
770 err |= reg (file, BRW_GENERAL_REGISTER_FILE,
771 inst->bits3.da3src.src1_reg_nr);
772 if (err == -1)
773 return 0;
774 if (src1_subreg_nr)
775 format (file, ".%d", src1_subreg_nr);
776 string (file, "<4,1,1>");
777 err |= control (file, "src da16 reg type", reg_encoding,
778 BRW_REGISTER_TYPE_F, NULL);
779 /*
780 * Three kinds of swizzle display:
781 * identity - nothing printed
782 * 1->all - print the single channel
783 * 1->1 - print the mapping
784 */
785 if (swz_x == BRW_CHANNEL_X &&
786 swz_y == BRW_CHANNEL_Y &&
787 swz_z == BRW_CHANNEL_Z &&
788 swz_w == BRW_CHANNEL_W)
789 {
790 ;
791 }
792 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
793 {
794 string (file, ".");
795 err |= control (file, "channel select", chan_sel, swz_x, NULL);
796 }
797 else
798 {
799 string (file, ".");
800 err |= control (file, "channel select", chan_sel, swz_x, NULL);
801 err |= control (file, "channel select", chan_sel, swz_y, NULL);
802 err |= control (file, "channel select", chan_sel, swz_z, NULL);
803 err |= control (file, "channel select", chan_sel, swz_w, NULL);
804 }
805 return err;
806 }
807
808
809 static int src2_3src (FILE *file, struct brw_instruction *inst)
810 {
811 int err = 0;
812 GLuint swz_x = (inst->bits3.da3src.src2_swizzle >> 0) & 0x3;
813 GLuint swz_y = (inst->bits3.da3src.src2_swizzle >> 2) & 0x3;
814 GLuint swz_z = (inst->bits3.da3src.src2_swizzle >> 4) & 0x3;
815 GLuint swz_w = (inst->bits3.da3src.src2_swizzle >> 6) & 0x3;
816
817 err |= control (file, "negate", negate, inst->bits1.da3src.src2_negate,
818 NULL);
819 err |= control (file, "abs", _abs, inst->bits1.da3src.src2_abs, NULL);
820
821 err |= reg (file, BRW_GENERAL_REGISTER_FILE,
822 inst->bits3.da3src.src2_reg_nr);
823 if (err == -1)
824 return 0;
825 if (inst->bits3.da3src.src2_subreg_nr)
826 format (file, ".%d", inst->bits3.da3src.src2_subreg_nr);
827 string (file, "<4,1,1>");
828 err |= control (file, "src da16 reg type", reg_encoding,
829 BRW_REGISTER_TYPE_F, NULL);
830 /*
831 * Three kinds of swizzle display:
832 * identity - nothing printed
833 * 1->all - print the single channel
834 * 1->1 - print the mapping
835 */
836 if (swz_x == BRW_CHANNEL_X &&
837 swz_y == BRW_CHANNEL_Y &&
838 swz_z == BRW_CHANNEL_Z &&
839 swz_w == BRW_CHANNEL_W)
840 {
841 ;
842 }
843 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
844 {
845 string (file, ".");
846 err |= control (file, "channel select", chan_sel, swz_x, NULL);
847 }
848 else
849 {
850 string (file, ".");
851 err |= control (file, "channel select", chan_sel, swz_x, NULL);
852 err |= control (file, "channel select", chan_sel, swz_y, NULL);
853 err |= control (file, "channel select", chan_sel, swz_z, NULL);
854 err |= control (file, "channel select", chan_sel, swz_w, NULL);
855 }
856 return err;
857 }
858
859 static int imm (FILE *file, GLuint type, struct brw_instruction *inst) {
860 switch (type) {
861 case BRW_REGISTER_TYPE_UD:
862 format (file, "0x%08xUD", inst->bits3.ud);
863 break;
864 case BRW_REGISTER_TYPE_D:
865 format (file, "%dD", inst->bits3.d);
866 break;
867 case BRW_REGISTER_TYPE_UW:
868 format (file, "0x%04xUW", (uint16_t) inst->bits3.ud);
869 break;
870 case BRW_REGISTER_TYPE_W:
871 format (file, "%dW", (int16_t) inst->bits3.d);
872 break;
873 case BRW_REGISTER_TYPE_UB:
874 format (file, "0x%02xUB", (int8_t) inst->bits3.ud);
875 break;
876 case BRW_REGISTER_TYPE_VF:
877 format (file, "Vector Float");
878 break;
879 case BRW_REGISTER_TYPE_V:
880 format (file, "0x%08xV", inst->bits3.ud);
881 break;
882 case BRW_REGISTER_TYPE_F:
883 format (file, "%-gF", inst->bits3.f);
884 }
885 return 0;
886 }
887
888 static int src0 (FILE *file, struct brw_instruction *inst)
889 {
890 if (inst->bits1.da1.src0_reg_file == BRW_IMMEDIATE_VALUE)
891 return imm (file, inst->bits1.da1.src0_reg_type,
892 inst);
893 else if (inst->header.access_mode == BRW_ALIGN_1)
894 {
895 if (inst->bits2.da1.src0_address_mode == BRW_ADDRESS_DIRECT)
896 {
897 return src_da1 (file,
898 inst->bits1.da1.src0_reg_type,
899 inst->bits1.da1.src0_reg_file,
900 inst->bits2.da1.src0_vert_stride,
901 inst->bits2.da1.src0_width,
902 inst->bits2.da1.src0_horiz_stride,
903 inst->bits2.da1.src0_reg_nr,
904 inst->bits2.da1.src0_subreg_nr,
905 inst->bits2.da1.src0_abs,
906 inst->bits2.da1.src0_negate);
907 }
908 else
909 {
910 return src_ia1 (file,
911 inst->bits1.ia1.src0_reg_type,
912 inst->bits1.ia1.src0_reg_file,
913 inst->bits2.ia1.src0_indirect_offset,
914 inst->bits2.ia1.src0_subreg_nr,
915 inst->bits2.ia1.src0_negate,
916 inst->bits2.ia1.src0_abs,
917 inst->bits2.ia1.src0_address_mode,
918 inst->bits2.ia1.src0_horiz_stride,
919 inst->bits2.ia1.src0_width,
920 inst->bits2.ia1.src0_vert_stride);
921 }
922 }
923 else
924 {
925 if (inst->bits2.da16.src0_address_mode == BRW_ADDRESS_DIRECT)
926 {
927 return src_da16 (file,
928 inst->bits1.da16.src0_reg_type,
929 inst->bits1.da16.src0_reg_file,
930 inst->bits2.da16.src0_vert_stride,
931 inst->bits2.da16.src0_reg_nr,
932 inst->bits2.da16.src0_subreg_nr,
933 inst->bits2.da16.src0_abs,
934 inst->bits2.da16.src0_negate,
935 inst->bits2.da16.src0_swz_x,
936 inst->bits2.da16.src0_swz_y,
937 inst->bits2.da16.src0_swz_z,
938 inst->bits2.da16.src0_swz_w);
939 }
940 else
941 {
942 string (file, "Indirect align16 address mode not supported");
943 return 1;
944 }
945 }
946 }
947
948 static int src1 (FILE *file, struct brw_instruction *inst)
949 {
950 if (inst->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE)
951 return imm (file, inst->bits1.da1.src1_reg_type,
952 inst);
953 else if (inst->header.access_mode == BRW_ALIGN_1)
954 {
955 if (inst->bits3.da1.src1_address_mode == BRW_ADDRESS_DIRECT)
956 {
957 return src_da1 (file,
958 inst->bits1.da1.src1_reg_type,
959 inst->bits1.da1.src1_reg_file,
960 inst->bits3.da1.src1_vert_stride,
961 inst->bits3.da1.src1_width,
962 inst->bits3.da1.src1_horiz_stride,
963 inst->bits3.da1.src1_reg_nr,
964 inst->bits3.da1.src1_subreg_nr,
965 inst->bits3.da1.src1_abs,
966 inst->bits3.da1.src1_negate);
967 }
968 else
969 {
970 return src_ia1 (file,
971 inst->bits1.ia1.src1_reg_type,
972 inst->bits1.ia1.src1_reg_file,
973 inst->bits3.ia1.src1_indirect_offset,
974 inst->bits3.ia1.src1_subreg_nr,
975 inst->bits3.ia1.src1_negate,
976 inst->bits3.ia1.src1_abs,
977 inst->bits3.ia1.src1_address_mode,
978 inst->bits3.ia1.src1_horiz_stride,
979 inst->bits3.ia1.src1_width,
980 inst->bits3.ia1.src1_vert_stride);
981 }
982 }
983 else
984 {
985 if (inst->bits3.da16.src1_address_mode == BRW_ADDRESS_DIRECT)
986 {
987 return src_da16 (file,
988 inst->bits1.da16.src1_reg_type,
989 inst->bits1.da16.src1_reg_file,
990 inst->bits3.da16.src1_vert_stride,
991 inst->bits3.da16.src1_reg_nr,
992 inst->bits3.da16.src1_subreg_nr,
993 inst->bits3.da16.src1_abs,
994 inst->bits3.da16.src1_negate,
995 inst->bits3.da16.src1_swz_x,
996 inst->bits3.da16.src1_swz_y,
997 inst->bits3.da16.src1_swz_z,
998 inst->bits3.da16.src1_swz_w);
999 }
1000 else
1001 {
1002 string (file, "Indirect align16 address mode not supported");
1003 return 1;
1004 }
1005 }
1006 }
1007
1008 int esize[6] = {
1009 [0] = 1,
1010 [1] = 2,
1011 [2] = 4,
1012 [3] = 8,
1013 [4] = 16,
1014 [5] = 32,
1015 };
1016
1017 static int qtr_ctrl(FILE *file, struct brw_instruction *inst)
1018 {
1019 int qtr_ctl = inst->header.compression_control;
1020 int exec_size = esize[inst->header.execution_size];
1021
1022 if (exec_size == 8) {
1023 switch (qtr_ctl) {
1024 case 0:
1025 string (file, " 1Q");
1026 break;
1027 case 1:
1028 string (file, " 2Q");
1029 break;
1030 case 2:
1031 string (file, " 3Q");
1032 break;
1033 case 3:
1034 string (file, " 4Q");
1035 break;
1036 }
1037 } else if (exec_size == 16){
1038 if (qtr_ctl < 2)
1039 string (file, " 1H");
1040 else
1041 string (file, " 2H");
1042 }
1043 return 0;
1044 }
1045
1046 int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
1047 {
1048 int err = 0;
1049 int space = 0;
1050
1051 if (inst->header.predicate_control) {
1052 string (file, "(");
1053 err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL);
1054 format (file, "f%d", gen >= 7 ? inst->bits2.da1.flag_reg_nr : 0);
1055 if (inst->bits2.da1.flag_subreg_nr)
1056 format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
1057 if (inst->header.access_mode == BRW_ALIGN_1)
1058 err |= control (file, "predicate control align1", pred_ctrl_align1,
1059 inst->header.predicate_control, NULL);
1060 else
1061 err |= control (file, "predicate control align16", pred_ctrl_align16,
1062 inst->header.predicate_control, NULL);
1063 string (file, ") ");
1064 }
1065
1066 err |= print_opcode (file, inst->header.opcode);
1067 err |= control (file, "saturate", saturate, inst->header.saturate, NULL);
1068 err |= control (file, "debug control", debug_ctrl, inst->header.debug_control, NULL);
1069
1070 if (inst->header.opcode == BRW_OPCODE_MATH) {
1071 string (file, " ");
1072 err |= control (file, "function", math_function,
1073 inst->header.destreg__conditionalmod, NULL);
1074 } else if (inst->header.opcode != BRW_OPCODE_SEND &&
1075 inst->header.opcode != BRW_OPCODE_SENDC) {
1076 err |= control (file, "conditional modifier", conditional_modifier,
1077 inst->header.destreg__conditionalmod, NULL);
1078
1079 /* If we're using the conditional modifier, print which flags reg is
1080 * used for it. Note that on gen6+, the embedded-condition SEL and
1081 * control flow doesn't update flags.
1082 */
1083 if (inst->header.destreg__conditionalmod &&
1084 (gen < 6 || (inst->header.opcode != BRW_OPCODE_SEL &&
1085 inst->header.opcode != BRW_OPCODE_IF &&
1086 inst->header.opcode != BRW_OPCODE_WHILE))) {
1087 format (file, ".f%d", gen >= 7 ? inst->bits2.da1.flag_reg_nr : 0);
1088 if (inst->bits2.da1.flag_subreg_nr)
1089 format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
1090 }
1091 }
1092
1093 if (inst->header.opcode != BRW_OPCODE_NOP) {
1094 string (file, "(");
1095 err |= control (file, "execution size", exec_size, inst->header.execution_size, NULL);
1096 string (file, ")");
1097 }
1098
1099 if (inst->header.opcode == BRW_OPCODE_SEND && gen < 6)
1100 format (file, " %d", inst->header.destreg__conditionalmod);
1101
1102 if (opcode[inst->header.opcode].nsrc == 3) {
1103 pad (file, 16);
1104 err |= dest_3src (file, inst);
1105
1106 pad (file, 32);
1107 err |= src0_3src (file, inst);
1108
1109 pad (file, 48);
1110 err |= src1_3src (file, inst);
1111
1112 pad (file, 64);
1113 err |= src2_3src (file, inst);
1114 } else {
1115 if (opcode[inst->header.opcode].ndst > 0) {
1116 pad (file, 16);
1117 err |= dest (file, inst);
1118 } else if (gen == 7 && (inst->header.opcode == BRW_OPCODE_ELSE ||
1119 inst->header.opcode == BRW_OPCODE_ENDIF ||
1120 inst->header.opcode == BRW_OPCODE_WHILE)) {
1121 format (file, " %d", inst->bits3.break_cont.jip);
1122 } else if (gen == 6 && (inst->header.opcode == BRW_OPCODE_IF ||
1123 inst->header.opcode == BRW_OPCODE_ELSE ||
1124 inst->header.opcode == BRW_OPCODE_ENDIF ||
1125 inst->header.opcode == BRW_OPCODE_WHILE)) {
1126 format (file, " %d", inst->bits1.branch_gen6.jump_count);
1127 } else if ((gen >= 6 && (inst->header.opcode == BRW_OPCODE_BREAK ||
1128 inst->header.opcode == BRW_OPCODE_CONTINUE ||
1129 inst->header.opcode == BRW_OPCODE_HALT)) ||
1130 (gen == 7 && inst->header.opcode == BRW_OPCODE_IF)) {
1131 format (file, " %d %d", inst->bits3.break_cont.uip, inst->bits3.break_cont.jip);
1132 } else if (inst->header.opcode == BRW_OPCODE_JMPI) {
1133 format (file, " %d", inst->bits3.d);
1134 }
1135
1136 if (opcode[inst->header.opcode].nsrc > 0) {
1137 pad (file, 32);
1138 err |= src0 (file, inst);
1139 }
1140 if (opcode[inst->header.opcode].nsrc > 1) {
1141 pad (file, 48);
1142 err |= src1 (file, inst);
1143 }
1144 }
1145
1146 if (inst->header.opcode == BRW_OPCODE_SEND ||
1147 inst->header.opcode == BRW_OPCODE_SENDC) {
1148 enum brw_message_target target;
1149
1150 if (gen >= 6)
1151 target = inst->header.destreg__conditionalmod;
1152 else if (gen == 5)
1153 target = inst->bits2.send_gen5.sfid;
1154 else
1155 target = inst->bits3.generic.msg_target;
1156
1157 newline (file);
1158 pad (file, 16);
1159 space = 0;
1160
1161 if (gen >= 6) {
1162 err |= control (file, "target function", target_function_gen6,
1163 target, &space);
1164 } else {
1165 err |= control (file, "target function", target_function,
1166 target, &space);
1167 }
1168
1169 switch (target) {
1170 case BRW_SFID_MATH:
1171 err |= control (file, "math function", math_function,
1172 inst->bits3.math.function, &space);
1173 err |= control (file, "math saturate", math_saturate,
1174 inst->bits3.math.saturate, &space);
1175 err |= control (file, "math signed", math_signed,
1176 inst->bits3.math.int_type, &space);
1177 err |= control (file, "math scalar", math_scalar,
1178 inst->bits3.math.data_type, &space);
1179 err |= control (file, "math precision", math_precision,
1180 inst->bits3.math.precision, &space);
1181 break;
1182 case BRW_SFID_SAMPLER:
1183 if (gen >= 7) {
1184 format (file, " (%d, %d, %d, %d)",
1185 inst->bits3.sampler_gen7.binding_table_index,
1186 inst->bits3.sampler_gen7.sampler,
1187 inst->bits3.sampler_gen7.msg_type,
1188 inst->bits3.sampler_gen7.simd_mode);
1189 } else if (gen >= 5) {
1190 format (file, " (%d, %d, %d, %d)",
1191 inst->bits3.sampler_gen5.binding_table_index,
1192 inst->bits3.sampler_gen5.sampler,
1193 inst->bits3.sampler_gen5.msg_type,
1194 inst->bits3.sampler_gen5.simd_mode);
1195 } else if (0 /* FINISHME: is_g4x */) {
1196 format (file, " (%d, %d)",
1197 inst->bits3.sampler_g4x.binding_table_index,
1198 inst->bits3.sampler_g4x.sampler);
1199 } else {
1200 format (file, " (%d, %d, ",
1201 inst->bits3.sampler.binding_table_index,
1202 inst->bits3.sampler.sampler);
1203 err |= control (file, "sampler target format",
1204 sampler_target_format,
1205 inst->bits3.sampler.return_format, NULL);
1206 string (file, ")");
1207 }
1208 break;
1209 case BRW_SFID_DATAPORT_READ:
1210 if (gen >= 6) {
1211 format (file, " (%d, %d, %d, %d)",
1212 inst->bits3.gen6_dp.binding_table_index,
1213 inst->bits3.gen6_dp.msg_control,
1214 inst->bits3.gen6_dp.msg_type,
1215 inst->bits3.gen6_dp.send_commit_msg);
1216 } else if (gen >= 5 /* FINISHME: || is_g4x */) {
1217 format (file, " (%d, %d, %d)",
1218 inst->bits3.dp_read_gen5.binding_table_index,
1219 inst->bits3.dp_read_gen5.msg_control,
1220 inst->bits3.dp_read_gen5.msg_type);
1221 } else {
1222 format (file, " (%d, %d, %d)",
1223 inst->bits3.dp_read.binding_table_index,
1224 inst->bits3.dp_read.msg_control,
1225 inst->bits3.dp_read.msg_type);
1226 }
1227 break;
1228
1229 case BRW_SFID_DATAPORT_WRITE:
1230 if (gen >= 7) {
1231 format (file, " (");
1232
1233 err |= control (file, "DP rc message type",
1234 dp_rc_msg_type_gen6,
1235 inst->bits3.gen7_dp.msg_type, &space);
1236
1237 format (file, ", %d, %d, %d)",
1238 inst->bits3.gen7_dp.binding_table_index,
1239 inst->bits3.gen7_dp.msg_control,
1240 inst->bits3.gen7_dp.msg_type);
1241 } else if (gen == 6) {
1242 format (file, " (");
1243
1244 err |= control (file, "DP rc message type",
1245 dp_rc_msg_type_gen6,
1246 inst->bits3.gen6_dp.msg_type, &space);
1247
1248 format (file, ", %d, %d, %d, %d)",
1249 inst->bits3.gen6_dp.binding_table_index,
1250 inst->bits3.gen6_dp.msg_control,
1251 inst->bits3.gen6_dp.msg_type,
1252 inst->bits3.gen6_dp.send_commit_msg);
1253 } else {
1254 format (file, " (%d, %d, %d, %d)",
1255 inst->bits3.dp_write.binding_table_index,
1256 (inst->bits3.dp_write.last_render_target << 3) |
1257 inst->bits3.dp_write.msg_control,
1258 inst->bits3.dp_write.msg_type,
1259 inst->bits3.dp_write.send_commit_msg);
1260 }
1261 break;
1262
1263 case BRW_SFID_URB:
1264 if (gen >= 5) {
1265 format (file, " %d", inst->bits3.urb_gen5.offset);
1266 } else {
1267 format (file, " %d", inst->bits3.urb.offset);
1268 }
1269
1270 space = 1;
1271 if (gen >= 5) {
1272 err |= control (file, "urb opcode", urb_opcode,
1273 inst->bits3.urb_gen5.opcode, &space);
1274 }
1275 err |= control (file, "urb swizzle", urb_swizzle,
1276 inst->bits3.urb.swizzle_control, &space);
1277 err |= control (file, "urb allocate", urb_allocate,
1278 inst->bits3.urb.allocate, &space);
1279 err |= control (file, "urb used", urb_used,
1280 inst->bits3.urb.used, &space);
1281 err |= control (file, "urb complete", urb_complete,
1282 inst->bits3.urb.complete, &space);
1283 break;
1284 case BRW_SFID_THREAD_SPAWNER:
1285 break;
1286 case GEN7_SFID_DATAPORT_DATA_CACHE:
1287 format (file, " (%d, %d, %d)",
1288 inst->bits3.gen7_dp.binding_table_index,
1289 inst->bits3.gen7_dp.msg_control,
1290 inst->bits3.gen7_dp.msg_type);
1291 break;
1292
1293
1294 default:
1295 format (file, "unsupported target %d", target);
1296 break;
1297 }
1298 if (space)
1299 string (file, " ");
1300 if (gen >= 5) {
1301 format (file, "mlen %d",
1302 inst->bits3.generic_gen5.msg_length);
1303 format (file, " rlen %d",
1304 inst->bits3.generic_gen5.response_length);
1305 } else {
1306 format (file, "mlen %d",
1307 inst->bits3.generic.msg_length);
1308 format (file, " rlen %d",
1309 inst->bits3.generic.response_length);
1310 }
1311 }
1312 pad (file, 64);
1313 if (inst->header.opcode != BRW_OPCODE_NOP) {
1314 string (file, "{");
1315 space = 1;
1316 err |= control(file, "access mode", access_mode, inst->header.access_mode, &space);
1317 if (gen >= 6)
1318 err |= control (file, "write enable control", wectrl, inst->header.mask_control, &space);
1319 else
1320 err |= control (file, "mask control", mask_ctrl, inst->header.mask_control, &space);
1321 err |= control (file, "dependency control", dep_ctrl, inst->header.dependency_control, &space);
1322
1323 if (gen >= 6)
1324 err |= qtr_ctrl (file, inst);
1325 else {
1326 if (inst->header.compression_control == BRW_COMPRESSION_COMPRESSED &&
1327 opcode[inst->header.opcode].ndst > 0 &&
1328 inst->bits1.da1.dest_reg_file == BRW_MESSAGE_REGISTER_FILE &&
1329 inst->bits1.da1.dest_reg_nr & (1 << 7)) {
1330 format (file, " compr4");
1331 } else {
1332 err |= control (file, "compression control", compr_ctrl,
1333 inst->header.compression_control, &space);
1334 }
1335 }
1336
1337 err |= control (file, "thread control", thread_ctrl, inst->header.thread_control, &space);
1338 if (gen >= 6)
1339 err |= control (file, "acc write control", accwr, inst->header.acc_wr_control, &space);
1340 if (inst->header.opcode == BRW_OPCODE_SEND ||
1341 inst->header.opcode == BRW_OPCODE_SENDC)
1342 err |= control (file, "end of thread", end_of_thread,
1343 inst->bits3.generic.end_of_thread, &space);
1344 if (space)
1345 string (file, " ");
1346 string (file, "}");
1347 }
1348 string (file, ";");
1349 newline (file);
1350 return err;
1351 }