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i965: Fix dump_prog_cache to handle compacted instructions.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_disasm.c
1 /*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23 #include <stdio.h>
24 #include <stdlib.h>
25 #include <string.h>
26 #include <getopt.h>
27 #include <unistd.h>
28 #include <stdarg.h>
29
30 #include "main/mtypes.h"
31
32 #include "brw_context.h"
33 #include "brw_defines.h"
34
35 const struct opcode_desc opcode_descs[128] = {
36 [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 },
37 [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 },
38 [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 },
39 [BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 },
40 [BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 },
41 [BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 },
42 [BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 },
43 [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 },
44 [BRW_OPCODE_F32TO16] = { .name = "f32to16", .nsrc = 1, .ndst = 1 },
45 [BRW_OPCODE_F16TO32] = { .name = "f16to32", .nsrc = 1, .ndst = 1 },
46 [BRW_OPCODE_BFREV] = { .name = "bfrev", .nsrc = 1, .ndst = 1},
47 [BRW_OPCODE_FBH] = { .name = "fbh", .nsrc = 1, .ndst = 1},
48 [BRW_OPCODE_FBL] = { .name = "fbl", .nsrc = 1, .ndst = 1},
49 [BRW_OPCODE_CBIT] = { .name = "cbit", .nsrc = 1, .ndst = 1},
50
51 [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 },
52 [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 },
53 [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 },
54 [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 },
55 [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 },
56 [BRW_OPCODE_MAD] = { .name = "mad", .nsrc = 3, .ndst = 1 },
57 [BRW_OPCODE_LRP] = { .name = "lrp", .nsrc = 3, .ndst = 1 },
58 [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 },
59 [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 },
60 [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 },
61 [BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 },
62 [BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 },
63 [BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 },
64 [BRW_OPCODE_MATH] = { .name = "math", .nsrc = 2, .ndst = 1 },
65
66 [BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 },
67 [BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 },
68 [BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 },
69 [BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 },
70 [BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 },
71 [BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 },
72 [BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 },
73 [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 },
74 [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 },
75 [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 },
76 [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 },
77 [BRW_OPCODE_BFE] = { .name = "bfe", .nsrc = 3, .ndst = 1},
78 [BRW_OPCODE_BFI1] = { .name = "bfi1", .nsrc = 2, .ndst = 1},
79 [BRW_OPCODE_BFI2] = { .name = "bfi2", .nsrc = 3, .ndst = 1},
80 [BRW_OPCODE_ADDC] = { .name = "addc", .nsrc = 2, .ndst = 1},
81 [BRW_OPCODE_SUBB] = { .name = "subb", .nsrc = 2, .ndst = 1},
82
83 [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 },
84 [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 },
85 [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
86 [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 0, .ndst = 0 },
87 [BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 },
88 [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 2, .ndst = 1 },
89 [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 2, .ndst = 0 },
90 [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 2, .ndst = 0 },
91 [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 2, .ndst = 0 },
92 [BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 1, .ndst = 0 },
93 [BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 1, .ndst = 0 },
94 [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 },
95 [BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 },
96 [BRW_OPCODE_MRESTORE] = { .name = "mrest", .nsrc = 1, .ndst = 1 },
97 [BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 },
98 [BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 },
99 [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 },
100 [BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 2, .ndst = 0 },
101 };
102 static const struct opcode_desc *opcode = opcode_descs;
103
104 const char * const conditional_modifier[16] = {
105 [BRW_CONDITIONAL_NONE] = "",
106 [BRW_CONDITIONAL_Z] = ".e",
107 [BRW_CONDITIONAL_NZ] = ".ne",
108 [BRW_CONDITIONAL_G] = ".g",
109 [BRW_CONDITIONAL_GE] = ".ge",
110 [BRW_CONDITIONAL_L] = ".l",
111 [BRW_CONDITIONAL_LE] = ".le",
112 [BRW_CONDITIONAL_R] = ".r",
113 [BRW_CONDITIONAL_O] = ".o",
114 [BRW_CONDITIONAL_U] = ".u",
115 };
116
117 static const char * const negate[2] = {
118 [0] = "",
119 [1] = "-",
120 };
121
122 static const char * const _abs[2] = {
123 [0] = "",
124 [1] = "(abs)",
125 };
126
127 static const char * const vert_stride[16] = {
128 [0] = "0",
129 [1] = "1",
130 [2] = "2",
131 [3] = "4",
132 [4] = "8",
133 [5] = "16",
134 [6] = "32",
135 [15] = "VxH",
136 };
137
138 static const char * const width[8] = {
139 [0] = "1",
140 [1] = "2",
141 [2] = "4",
142 [3] = "8",
143 [4] = "16",
144 };
145
146 static const char * const horiz_stride[4] = {
147 [0] = "0",
148 [1] = "1",
149 [2] = "2",
150 [3] = "4"
151 };
152
153 static const char * const chan_sel[4] = {
154 [0] = "x",
155 [1] = "y",
156 [2] = "z",
157 [3] = "w",
158 };
159
160 static const char * const debug_ctrl[2] = {
161 [0] = "",
162 [1] = ".breakpoint"
163 };
164
165 static const char * const saturate[2] = {
166 [0] = "",
167 [1] = ".sat"
168 };
169
170 static const char * const cmpt_ctrl[2] = {
171 [0] = "",
172 [1] = "compacted"
173 };
174
175 static const char * const accwr[2] = {
176 [0] = "",
177 [1] = "AccWrEnable"
178 };
179
180 static const char * const wectrl[2] = {
181 [0] = "WE_normal",
182 [1] = "WE_all"
183 };
184
185 static const char * const exec_size[8] = {
186 [0] = "1",
187 [1] = "2",
188 [2] = "4",
189 [3] = "8",
190 [4] = "16",
191 [5] = "32"
192 };
193
194 static const char * const pred_inv[2] = {
195 [0] = "+",
196 [1] = "-"
197 };
198
199 static const char * const pred_ctrl_align16[16] = {
200 [1] = "",
201 [2] = ".x",
202 [3] = ".y",
203 [4] = ".z",
204 [5] = ".w",
205 [6] = ".any4h",
206 [7] = ".all4h",
207 };
208
209 static const char * const pred_ctrl_align1[16] = {
210 [1] = "",
211 [2] = ".anyv",
212 [3] = ".allv",
213 [4] = ".any2h",
214 [5] = ".all2h",
215 [6] = ".any4h",
216 [7] = ".all4h",
217 [8] = ".any8h",
218 [9] = ".all8h",
219 [10] = ".any16h",
220 [11] = ".all16h",
221 };
222
223 static const char * const thread_ctrl[4] = {
224 [0] = "",
225 [2] = "switch"
226 };
227
228 static const char * const compr_ctrl[4] = {
229 [0] = "",
230 [1] = "sechalf",
231 [2] = "compr",
232 [3] = "compr4",
233 };
234
235 static const char * const dep_ctrl[4] = {
236 [0] = "",
237 [1] = "NoDDClr",
238 [2] = "NoDDChk",
239 [3] = "NoDDClr,NoDDChk",
240 };
241
242 static const char * const mask_ctrl[4] = {
243 [0] = "",
244 [1] = "nomask",
245 };
246
247 static const char * const access_mode[2] = {
248 [0] = "align1",
249 [1] = "align16",
250 };
251
252 static const char * const reg_encoding[8] = {
253 [0] = "UD",
254 [1] = "D",
255 [2] = "UW",
256 [3] = "W",
257 [4] = "UB",
258 [5] = "B",
259 [7] = "F"
260 };
261
262 const char * const three_source_reg_encoding[] = {
263 [BRW_3SRC_TYPE_F] = "F",
264 [BRW_3SRC_TYPE_D] = "D",
265 [BRW_3SRC_TYPE_UD] = "UD",
266 };
267
268 const int reg_type_size[8] = {
269 [0] = 4,
270 [1] = 4,
271 [2] = 2,
272 [3] = 2,
273 [4] = 1,
274 [5] = 1,
275 [7] = 4
276 };
277
278 static const char * const reg_file[4] = {
279 [0] = "A",
280 [1] = "g",
281 [2] = "m",
282 [3] = "imm",
283 };
284
285 static const char * const writemask[16] = {
286 [0x0] = ".",
287 [0x1] = ".x",
288 [0x2] = ".y",
289 [0x3] = ".xy",
290 [0x4] = ".z",
291 [0x5] = ".xz",
292 [0x6] = ".yz",
293 [0x7] = ".xyz",
294 [0x8] = ".w",
295 [0x9] = ".xw",
296 [0xa] = ".yw",
297 [0xb] = ".xyw",
298 [0xc] = ".zw",
299 [0xd] = ".xzw",
300 [0xe] = ".yzw",
301 [0xf] = "",
302 };
303
304 static const char * const end_of_thread[2] = {
305 [0] = "",
306 [1] = "EOT"
307 };
308
309 static const char * const target_function[16] = {
310 [BRW_SFID_NULL] = "null",
311 [BRW_SFID_MATH] = "math",
312 [BRW_SFID_SAMPLER] = "sampler",
313 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
314 [BRW_SFID_DATAPORT_READ] = "read",
315 [BRW_SFID_DATAPORT_WRITE] = "write",
316 [BRW_SFID_URB] = "urb",
317 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
318 [BRW_SFID_VME] = "vme",
319 };
320
321 static const char * const target_function_gen6[16] = {
322 [BRW_SFID_NULL] = "null",
323 [BRW_SFID_MATH] = "math",
324 [BRW_SFID_SAMPLER] = "sampler",
325 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
326 [BRW_SFID_URB] = "urb",
327 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
328 [GEN6_SFID_DATAPORT_SAMPLER_CACHE] = "sampler",
329 [GEN6_SFID_DATAPORT_RENDER_CACHE] = "render",
330 [GEN6_SFID_DATAPORT_CONSTANT_CACHE] = "const",
331 [GEN7_SFID_DATAPORT_DATA_CACHE] = "data",
332 [GEN7_SFID_PIXEL_INTERPOLATOR] = "pixel interp",
333 [HSW_SFID_DATAPORT_DATA_CACHE_1] = "dp data 1",
334 [HSW_SFID_CRE] = "cre",
335 };
336
337 static const char * const dp_rc_msg_type_gen6[16] = {
338 [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read",
339 [GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read",
340 [GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read",
341 [GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read",
342 [GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ] = "OWORD unaligned block read",
343 [GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ] = "DWORD scattered read",
344 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE] = "DWORD atomic write",
345 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE] = "OWORD block write",
346 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE] = "OWORD dual block write",
347 [GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE] = "media block write",
348 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE] = "DWORD scattered write",
349 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write",
350 [GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write",
351 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORMc write",
352 };
353
354 static const char *const dp_dc0_msg_type_gen7[16] = {
355 [GEN7_DATAPORT_DC_OWORD_BLOCK_READ] = "DC OWORD block read",
356 [GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ] = "DC unaligned OWORD block read",
357 [GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ] = "DC OWORD dual block read",
358 [GEN7_DATAPORT_DC_DWORD_SCATTERED_READ] = "DC DWORD scattered read",
359 [GEN7_DATAPORT_DC_BYTE_SCATTERED_READ] = "DC byte scattered read",
360 [GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP] = "DC untyped atomic",
361 [GEN7_DATAPORT_DC_MEMORY_FENCE] = "DC mfence",
362 [GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE] = "DC OWORD block write",
363 [GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE] = "DC OWORD dual block write",
364 [GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE] = "DC DWORD scatterd write",
365 [GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE] = "DC byte scattered write",
366 [GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
367 };
368
369 static const char *const dp_dc1_msg_type_hsw[16] = {
370 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ] = "untyped surface read",
371 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP] = "DC untyped atomic op",
372 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2] = "DC untyped 4x2 atomic op",
373 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ] = "DC media block read",
374 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ] = "DC typed surface read",
375 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP] = "DC typed atomic",
376 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2] = "DC typed 4x2 atomic op",
377 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
378 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE] = "DC media block write",
379 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP] = "DC atomic counter op",
380 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2] = "DC 4x2 atomic counter op",
381 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE] = "DC typed surface write",
382 };
383
384 static const char * const aop[16] = {
385 [BRW_AOP_AND] = "and",
386 [BRW_AOP_OR] = "or",
387 [BRW_AOP_XOR] = "xor",
388 [BRW_AOP_MOV] = "mov",
389 [BRW_AOP_INC] = "inc",
390 [BRW_AOP_DEC] = "dec",
391 [BRW_AOP_ADD] = "add",
392 [BRW_AOP_SUB] = "sub",
393 [BRW_AOP_REVSUB] = "revsub",
394 [BRW_AOP_IMAX] = "imax",
395 [BRW_AOP_IMIN] = "imin",
396 [BRW_AOP_UMAX] = "umax",
397 [BRW_AOP_UMIN] = "umin",
398 [BRW_AOP_CMPWR] = "cmpwr",
399 [BRW_AOP_PREDEC] = "predec",
400 };
401
402 static const char * const math_function[16] = {
403 [BRW_MATH_FUNCTION_INV] = "inv",
404 [BRW_MATH_FUNCTION_LOG] = "log",
405 [BRW_MATH_FUNCTION_EXP] = "exp",
406 [BRW_MATH_FUNCTION_SQRT] = "sqrt",
407 [BRW_MATH_FUNCTION_RSQ] = "rsq",
408 [BRW_MATH_FUNCTION_SIN] = "sin",
409 [BRW_MATH_FUNCTION_COS] = "cos",
410 [BRW_MATH_FUNCTION_SINCOS] = "sincos",
411 [BRW_MATH_FUNCTION_FDIV] = "fdiv",
412 [BRW_MATH_FUNCTION_POW] = "pow",
413 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod",
414 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intdiv",
415 [BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod",
416 };
417
418 static const char * const math_saturate[2] = {
419 [0] = "",
420 [1] = "sat"
421 };
422
423 static const char * const math_signed[2] = {
424 [0] = "",
425 [1] = "signed"
426 };
427
428 static const char * const math_scalar[2] = {
429 [0] = "",
430 [1] = "scalar"
431 };
432
433 static const char * const math_precision[2] = {
434 [0] = "",
435 [1] = "partial_precision"
436 };
437
438 static const char * const urb_opcode[2] = {
439 [0] = "urb_write",
440 [1] = "ff_sync",
441 };
442
443 static const char * const urb_swizzle[4] = {
444 [BRW_URB_SWIZZLE_NONE] = "",
445 [BRW_URB_SWIZZLE_INTERLEAVE] = "interleave",
446 [BRW_URB_SWIZZLE_TRANSPOSE] = "transpose",
447 };
448
449 static const char * const urb_allocate[2] = {
450 [0] = "",
451 [1] = "allocate"
452 };
453
454 static const char * const urb_used[2] = {
455 [0] = "",
456 [1] = "used"
457 };
458
459 static const char * const urb_complete[2] = {
460 [0] = "",
461 [1] = "complete"
462 };
463
464 static const char * const sampler_target_format[4] = {
465 [0] = "F",
466 [2] = "UD",
467 [3] = "D"
468 };
469
470
471 static int column;
472
473 static int string (FILE *file, const char *string)
474 {
475 fputs (string, file);
476 column += strlen (string);
477 return 0;
478 }
479
480 static int format (FILE *f, const char *format, ...)
481 {
482 char buf[1024];
483 va_list args;
484 va_start (args, format);
485
486 vsnprintf (buf, sizeof (buf) - 1, format, args);
487 va_end (args);
488 string (f, buf);
489 return 0;
490 }
491
492 static int newline (FILE *f)
493 {
494 putc ('\n', f);
495 column = 0;
496 return 0;
497 }
498
499 static int pad (FILE *f, int c)
500 {
501 do
502 string (f, " ");
503 while (column < c);
504 return 0;
505 }
506
507 static int control (FILE *file, const char *name, const char * const ctrl[],
508 unsigned id, int *space)
509 {
510 if (!ctrl[id]) {
511 fprintf (file, "*** invalid %s value %d ",
512 name, id);
513 return 1;
514 }
515 if (ctrl[id][0])
516 {
517 if (space && *space)
518 string (file, " ");
519 string (file, ctrl[id]);
520 if (space)
521 *space = 1;
522 }
523 return 0;
524 }
525
526 static int print_opcode (FILE *file, int id)
527 {
528 if (!opcode[id].name) {
529 format (file, "*** invalid opcode value %d ", id);
530 return 1;
531 }
532 string (file, opcode[id].name);
533 return 0;
534 }
535
536 static int reg (FILE *file, unsigned _reg_file, unsigned _reg_nr)
537 {
538 int err = 0;
539
540 /* Clear the Compr4 instruction compression bit. */
541 if (_reg_file == BRW_MESSAGE_REGISTER_FILE)
542 _reg_nr &= ~(1 << 7);
543
544 if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
545 switch (_reg_nr & 0xf0) {
546 case BRW_ARF_NULL:
547 string (file, "null");
548 return -1;
549 case BRW_ARF_ADDRESS:
550 format (file, "a%d", _reg_nr & 0x0f);
551 break;
552 case BRW_ARF_ACCUMULATOR:
553 format (file, "acc%d", _reg_nr & 0x0f);
554 break;
555 case BRW_ARF_FLAG:
556 format (file, "f%d", _reg_nr & 0x0f);
557 break;
558 case BRW_ARF_MASK:
559 format (file, "mask%d", _reg_nr & 0x0f);
560 break;
561 case BRW_ARF_MASK_STACK:
562 format (file, "msd%d", _reg_nr & 0x0f);
563 break;
564 case BRW_ARF_STATE:
565 format (file, "sr%d", _reg_nr & 0x0f);
566 break;
567 case BRW_ARF_CONTROL:
568 format (file, "cr%d", _reg_nr & 0x0f);
569 break;
570 case BRW_ARF_NOTIFICATION_COUNT:
571 format (file, "n%d", _reg_nr & 0x0f);
572 break;
573 case BRW_ARF_IP:
574 string (file, "ip");
575 return -1;
576 break;
577 default:
578 format (file, "ARF%d", _reg_nr);
579 break;
580 }
581 } else {
582 err |= control (file, "src reg file", reg_file, _reg_file, NULL);
583 format (file, "%d", _reg_nr);
584 }
585 return err;
586 }
587
588 static int dest (FILE *file, struct brw_instruction *inst)
589 {
590 int err = 0;
591
592 if (inst->header.access_mode == BRW_ALIGN_1)
593 {
594 if (inst->bits1.da1.dest_address_mode == BRW_ADDRESS_DIRECT)
595 {
596 err |= reg (file, inst->bits1.da1.dest_reg_file, inst->bits1.da1.dest_reg_nr);
597 if (err == -1)
598 return 0;
599 if (inst->bits1.da1.dest_subreg_nr)
600 format (file, ".%d", inst->bits1.da1.dest_subreg_nr /
601 reg_type_size[inst->bits1.da1.dest_reg_type]);
602 string (file, "<");
603 err |= control (file, "horiz stride", horiz_stride, inst->bits1.da1.dest_horiz_stride, NULL);
604 string (file, ">");
605 err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da1.dest_reg_type, NULL);
606 }
607 else
608 {
609 string (file, "g[a0");
610 if (inst->bits1.ia1.dest_subreg_nr)
611 format (file, ".%d", inst->bits1.ia1.dest_subreg_nr /
612 reg_type_size[inst->bits1.ia1.dest_reg_type]);
613 if (inst->bits1.ia1.dest_indirect_offset)
614 format (file, " %d", inst->bits1.ia1.dest_indirect_offset);
615 string (file, "]<");
616 err |= control (file, "horiz stride", horiz_stride, inst->bits1.ia1.dest_horiz_stride, NULL);
617 string (file, ">");
618 err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.ia1.dest_reg_type, NULL);
619 }
620 }
621 else
622 {
623 if (inst->bits1.da16.dest_address_mode == BRW_ADDRESS_DIRECT)
624 {
625 err |= reg (file, inst->bits1.da16.dest_reg_file, inst->bits1.da16.dest_reg_nr);
626 if (err == -1)
627 return 0;
628 if (inst->bits1.da16.dest_subreg_nr)
629 format (file, ".%d", inst->bits1.da16.dest_subreg_nr /
630 reg_type_size[inst->bits1.da16.dest_reg_type]);
631 string (file, "<1>");
632 err |= control (file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL);
633 err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da16.dest_reg_type, NULL);
634 }
635 else
636 {
637 err = 1;
638 string (file, "Indirect align16 address mode not supported");
639 }
640 }
641
642 return 0;
643 }
644
645 static int dest_3src (FILE *file, struct brw_instruction *inst)
646 {
647 int err = 0;
648 uint32_t reg_file;
649
650 if (inst->bits1.da3src.dest_reg_file)
651 reg_file = BRW_MESSAGE_REGISTER_FILE;
652 else
653 reg_file = BRW_GENERAL_REGISTER_FILE;
654
655 err |= reg (file, reg_file, inst->bits1.da3src.dest_reg_nr);
656 if (err == -1)
657 return 0;
658 if (inst->bits1.da3src.dest_subreg_nr)
659 format (file, ".%d", inst->bits1.da3src.dest_subreg_nr);
660 string (file, "<1>");
661 err |= control (file, "writemask", writemask, inst->bits1.da3src.dest_writemask, NULL);
662 err |= control (file, "dest reg encoding", three_source_reg_encoding,
663 inst->bits1.da3src.dst_type, NULL);
664
665 return 0;
666 }
667
668 static int src_align1_region (FILE *file,
669 unsigned _vert_stride, unsigned _width, unsigned _horiz_stride)
670 {
671 int err = 0;
672 string (file, "<");
673 err |= control (file, "vert stride", vert_stride, _vert_stride, NULL);
674 string (file, ",");
675 err |= control (file, "width", width, _width, NULL);
676 string (file, ",");
677 err |= control (file, "horiz_stride", horiz_stride, _horiz_stride, NULL);
678 string (file, ">");
679 return err;
680 }
681
682 static int src_da1 (FILE *file, unsigned type, unsigned _reg_file,
683 unsigned _vert_stride, unsigned _width, unsigned _horiz_stride,
684 unsigned reg_num, unsigned sub_reg_num, unsigned __abs, unsigned _negate)
685 {
686 int err = 0;
687 err |= control (file, "negate", negate, _negate, NULL);
688 err |= control (file, "abs", _abs, __abs, NULL);
689
690 err |= reg (file, _reg_file, reg_num);
691 if (err == -1)
692 return 0;
693 if (sub_reg_num)
694 format (file, ".%d", sub_reg_num / reg_type_size[type]); /* use formal style like spec */
695 src_align1_region (file, _vert_stride, _width, _horiz_stride);
696 err |= control (file, "src reg encoding", reg_encoding, type, NULL);
697 return err;
698 }
699
700 static int src_ia1 (FILE *file,
701 unsigned type,
702 unsigned _reg_file,
703 int _addr_imm,
704 unsigned _addr_subreg_nr,
705 unsigned _negate,
706 unsigned __abs,
707 unsigned _addr_mode,
708 unsigned _horiz_stride,
709 unsigned _width,
710 unsigned _vert_stride)
711 {
712 int err = 0;
713 err |= control (file, "negate", negate, _negate, NULL);
714 err |= control (file, "abs", _abs, __abs, NULL);
715
716 string (file, "g[a0");
717 if (_addr_subreg_nr)
718 format (file, ".%d", _addr_subreg_nr);
719 if (_addr_imm)
720 format (file, " %d", _addr_imm);
721 string (file, "]");
722 src_align1_region (file, _vert_stride, _width, _horiz_stride);
723 err |= control (file, "src reg encoding", reg_encoding, type, NULL);
724 return err;
725 }
726
727 static int src_da16 (FILE *file,
728 unsigned _reg_type,
729 unsigned _reg_file,
730 unsigned _vert_stride,
731 unsigned _reg_nr,
732 unsigned _subreg_nr,
733 unsigned __abs,
734 unsigned _negate,
735 unsigned swz_x,
736 unsigned swz_y,
737 unsigned swz_z,
738 unsigned swz_w)
739 {
740 int err = 0;
741 err |= control (file, "negate", negate, _negate, NULL);
742 err |= control (file, "abs", _abs, __abs, NULL);
743
744 err |= reg (file, _reg_file, _reg_nr);
745 if (err == -1)
746 return 0;
747 if (_subreg_nr)
748 /* bit4 for subreg number byte addressing. Make this same meaning as
749 in da1 case, so output looks consistent. */
750 format (file, ".%d", 16 / reg_type_size[_reg_type]);
751 string (file, "<");
752 err |= control (file, "vert stride", vert_stride, _vert_stride, NULL);
753 string (file, ",4,1>");
754 /*
755 * Three kinds of swizzle display:
756 * identity - nothing printed
757 * 1->all - print the single channel
758 * 1->1 - print the mapping
759 */
760 if (swz_x == BRW_CHANNEL_X &&
761 swz_y == BRW_CHANNEL_Y &&
762 swz_z == BRW_CHANNEL_Z &&
763 swz_w == BRW_CHANNEL_W)
764 {
765 ;
766 }
767 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
768 {
769 string (file, ".");
770 err |= control (file, "channel select", chan_sel, swz_x, NULL);
771 }
772 else
773 {
774 string (file, ".");
775 err |= control (file, "channel select", chan_sel, swz_x, NULL);
776 err |= control (file, "channel select", chan_sel, swz_y, NULL);
777 err |= control (file, "channel select", chan_sel, swz_z, NULL);
778 err |= control (file, "channel select", chan_sel, swz_w, NULL);
779 }
780 err |= control (file, "src da16 reg type", reg_encoding, _reg_type, NULL);
781 return err;
782 }
783
784 static int src0_3src (FILE *file, struct brw_instruction *inst)
785 {
786 int err = 0;
787 unsigned swz_x = (inst->bits2.da3src.src0_swizzle >> 0) & 0x3;
788 unsigned swz_y = (inst->bits2.da3src.src0_swizzle >> 2) & 0x3;
789 unsigned swz_z = (inst->bits2.da3src.src0_swizzle >> 4) & 0x3;
790 unsigned swz_w = (inst->bits2.da3src.src0_swizzle >> 6) & 0x3;
791
792 err |= control (file, "negate", negate, inst->bits1.da3src.src0_negate, NULL);
793 err |= control (file, "abs", _abs, inst->bits1.da3src.src0_abs, NULL);
794
795 err |= reg (file, BRW_GENERAL_REGISTER_FILE, inst->bits2.da3src.src0_reg_nr);
796 if (err == -1)
797 return 0;
798 if (inst->bits2.da3src.src0_subreg_nr)
799 format (file, ".%d", inst->bits2.da3src.src0_subreg_nr);
800 if (inst->bits2.da3src.src0_rep_ctrl)
801 string (file, "<0,1,0>");
802 else
803 string (file, "<4,4,1>");
804 err |= control (file, "src da16 reg type", three_source_reg_encoding,
805 inst->bits1.da3src.src_type, NULL);
806 /*
807 * Three kinds of swizzle display:
808 * identity - nothing printed
809 * 1->all - print the single channel
810 * 1->1 - print the mapping
811 */
812 if (swz_x == BRW_CHANNEL_X &&
813 swz_y == BRW_CHANNEL_Y &&
814 swz_z == BRW_CHANNEL_Z &&
815 swz_w == BRW_CHANNEL_W)
816 {
817 ;
818 }
819 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
820 {
821 string (file, ".");
822 err |= control (file, "channel select", chan_sel, swz_x, NULL);
823 }
824 else
825 {
826 string (file, ".");
827 err |= control (file, "channel select", chan_sel, swz_x, NULL);
828 err |= control (file, "channel select", chan_sel, swz_y, NULL);
829 err |= control (file, "channel select", chan_sel, swz_z, NULL);
830 err |= control (file, "channel select", chan_sel, swz_w, NULL);
831 }
832 return err;
833 }
834
835 static int src1_3src (FILE *file, struct brw_instruction *inst)
836 {
837 int err = 0;
838 unsigned swz_x = (inst->bits2.da3src.src1_swizzle >> 0) & 0x3;
839 unsigned swz_y = (inst->bits2.da3src.src1_swizzle >> 2) & 0x3;
840 unsigned swz_z = (inst->bits2.da3src.src1_swizzle >> 4) & 0x3;
841 unsigned swz_w = (inst->bits2.da3src.src1_swizzle >> 6) & 0x3;
842 unsigned src1_subreg_nr = (inst->bits2.da3src.src1_subreg_nr_low |
843 (inst->bits3.da3src.src1_subreg_nr_high << 2));
844
845 err |= control (file, "negate", negate, inst->bits1.da3src.src1_negate,
846 NULL);
847 err |= control (file, "abs", _abs, inst->bits1.da3src.src1_abs, NULL);
848
849 err |= reg (file, BRW_GENERAL_REGISTER_FILE,
850 inst->bits3.da3src.src1_reg_nr);
851 if (err == -1)
852 return 0;
853 if (src1_subreg_nr)
854 format (file, ".%d", src1_subreg_nr);
855 if (inst->bits2.da3src.src1_rep_ctrl)
856 string (file, "<0,1,0>");
857 else
858 string (file, "<4,4,1>");
859 err |= control (file, "src da16 reg type", three_source_reg_encoding,
860 inst->bits1.da3src.src_type, NULL);
861 /*
862 * Three kinds of swizzle display:
863 * identity - nothing printed
864 * 1->all - print the single channel
865 * 1->1 - print the mapping
866 */
867 if (swz_x == BRW_CHANNEL_X &&
868 swz_y == BRW_CHANNEL_Y &&
869 swz_z == BRW_CHANNEL_Z &&
870 swz_w == BRW_CHANNEL_W)
871 {
872 ;
873 }
874 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
875 {
876 string (file, ".");
877 err |= control (file, "channel select", chan_sel, swz_x, NULL);
878 }
879 else
880 {
881 string (file, ".");
882 err |= control (file, "channel select", chan_sel, swz_x, NULL);
883 err |= control (file, "channel select", chan_sel, swz_y, NULL);
884 err |= control (file, "channel select", chan_sel, swz_z, NULL);
885 err |= control (file, "channel select", chan_sel, swz_w, NULL);
886 }
887 return err;
888 }
889
890
891 static int src2_3src (FILE *file, struct brw_instruction *inst)
892 {
893 int err = 0;
894 unsigned swz_x = (inst->bits3.da3src.src2_swizzle >> 0) & 0x3;
895 unsigned swz_y = (inst->bits3.da3src.src2_swizzle >> 2) & 0x3;
896 unsigned swz_z = (inst->bits3.da3src.src2_swizzle >> 4) & 0x3;
897 unsigned swz_w = (inst->bits3.da3src.src2_swizzle >> 6) & 0x3;
898
899 err |= control (file, "negate", negate, inst->bits1.da3src.src2_negate,
900 NULL);
901 err |= control (file, "abs", _abs, inst->bits1.da3src.src2_abs, NULL);
902
903 err |= reg (file, BRW_GENERAL_REGISTER_FILE,
904 inst->bits3.da3src.src2_reg_nr);
905 if (err == -1)
906 return 0;
907 if (inst->bits3.da3src.src2_subreg_nr)
908 format (file, ".%d", inst->bits3.da3src.src2_subreg_nr);
909 if (inst->bits3.da3src.src2_rep_ctrl)
910 string (file, "<0,1,0>");
911 else
912 string (file, "<4,4,1>");
913 err |= control (file, "src da16 reg type", three_source_reg_encoding,
914 inst->bits1.da3src.src_type, NULL);
915 /*
916 * Three kinds of swizzle display:
917 * identity - nothing printed
918 * 1->all - print the single channel
919 * 1->1 - print the mapping
920 */
921 if (swz_x == BRW_CHANNEL_X &&
922 swz_y == BRW_CHANNEL_Y &&
923 swz_z == BRW_CHANNEL_Z &&
924 swz_w == BRW_CHANNEL_W)
925 {
926 ;
927 }
928 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
929 {
930 string (file, ".");
931 err |= control (file, "channel select", chan_sel, swz_x, NULL);
932 }
933 else
934 {
935 string (file, ".");
936 err |= control (file, "channel select", chan_sel, swz_x, NULL);
937 err |= control (file, "channel select", chan_sel, swz_y, NULL);
938 err |= control (file, "channel select", chan_sel, swz_z, NULL);
939 err |= control (file, "channel select", chan_sel, swz_w, NULL);
940 }
941 return err;
942 }
943
944 static int imm (FILE *file, unsigned type, struct brw_instruction *inst) {
945 switch (type) {
946 case BRW_HW_REG_TYPE_UD:
947 format (file, "0x%08xUD", inst->bits3.ud);
948 break;
949 case BRW_HW_REG_TYPE_D:
950 format (file, "%dD", inst->bits3.d);
951 break;
952 case BRW_HW_REG_TYPE_UW:
953 format (file, "0x%04xUW", (uint16_t) inst->bits3.ud);
954 break;
955 case BRW_HW_REG_TYPE_W:
956 format (file, "%dW", (int16_t) inst->bits3.d);
957 break;
958 case BRW_HW_REG_IMM_TYPE_UV:
959 format (file, "0x%08xUV", inst->bits3.ud);
960 break;
961 case BRW_HW_REG_IMM_TYPE_VF:
962 format (file, "Vector Float");
963 break;
964 case BRW_HW_REG_IMM_TYPE_V:
965 format (file, "0x%08xV", inst->bits3.ud);
966 break;
967 case BRW_HW_REG_TYPE_F:
968 format (file, "%-gF", inst->bits3.f);
969 }
970 return 0;
971 }
972
973 static int src0 (FILE *file, struct brw_instruction *inst)
974 {
975 if (inst->bits1.da1.src0_reg_file == BRW_IMMEDIATE_VALUE)
976 return imm (file, inst->bits1.da1.src0_reg_type,
977 inst);
978 else if (inst->header.access_mode == BRW_ALIGN_1)
979 {
980 if (inst->bits2.da1.src0_address_mode == BRW_ADDRESS_DIRECT)
981 {
982 return src_da1 (file,
983 inst->bits1.da1.src0_reg_type,
984 inst->bits1.da1.src0_reg_file,
985 inst->bits2.da1.src0_vert_stride,
986 inst->bits2.da1.src0_width,
987 inst->bits2.da1.src0_horiz_stride,
988 inst->bits2.da1.src0_reg_nr,
989 inst->bits2.da1.src0_subreg_nr,
990 inst->bits2.da1.src0_abs,
991 inst->bits2.da1.src0_negate);
992 }
993 else
994 {
995 return src_ia1 (file,
996 inst->bits1.ia1.src0_reg_type,
997 inst->bits1.ia1.src0_reg_file,
998 inst->bits2.ia1.src0_indirect_offset,
999 inst->bits2.ia1.src0_subreg_nr,
1000 inst->bits2.ia1.src0_negate,
1001 inst->bits2.ia1.src0_abs,
1002 inst->bits2.ia1.src0_address_mode,
1003 inst->bits2.ia1.src0_horiz_stride,
1004 inst->bits2.ia1.src0_width,
1005 inst->bits2.ia1.src0_vert_stride);
1006 }
1007 }
1008 else
1009 {
1010 if (inst->bits2.da16.src0_address_mode == BRW_ADDRESS_DIRECT)
1011 {
1012 return src_da16 (file,
1013 inst->bits1.da16.src0_reg_type,
1014 inst->bits1.da16.src0_reg_file,
1015 inst->bits2.da16.src0_vert_stride,
1016 inst->bits2.da16.src0_reg_nr,
1017 inst->bits2.da16.src0_subreg_nr,
1018 inst->bits2.da16.src0_abs,
1019 inst->bits2.da16.src0_negate,
1020 inst->bits2.da16.src0_swz_x,
1021 inst->bits2.da16.src0_swz_y,
1022 inst->bits2.da16.src0_swz_z,
1023 inst->bits2.da16.src0_swz_w);
1024 }
1025 else
1026 {
1027 string (file, "Indirect align16 address mode not supported");
1028 return 1;
1029 }
1030 }
1031 }
1032
1033 static int src1 (FILE *file, struct brw_instruction *inst)
1034 {
1035 if (inst->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE)
1036 return imm (file, inst->bits1.da1.src1_reg_type,
1037 inst);
1038 else if (inst->header.access_mode == BRW_ALIGN_1)
1039 {
1040 if (inst->bits3.da1.src1_address_mode == BRW_ADDRESS_DIRECT)
1041 {
1042 return src_da1 (file,
1043 inst->bits1.da1.src1_reg_type,
1044 inst->bits1.da1.src1_reg_file,
1045 inst->bits3.da1.src1_vert_stride,
1046 inst->bits3.da1.src1_width,
1047 inst->bits3.da1.src1_horiz_stride,
1048 inst->bits3.da1.src1_reg_nr,
1049 inst->bits3.da1.src1_subreg_nr,
1050 inst->bits3.da1.src1_abs,
1051 inst->bits3.da1.src1_negate);
1052 }
1053 else
1054 {
1055 return src_ia1 (file,
1056 inst->bits1.ia1.src1_reg_type,
1057 inst->bits1.ia1.src1_reg_file,
1058 inst->bits3.ia1.src1_indirect_offset,
1059 inst->bits3.ia1.src1_subreg_nr,
1060 inst->bits3.ia1.src1_negate,
1061 inst->bits3.ia1.src1_abs,
1062 inst->bits3.ia1.src1_address_mode,
1063 inst->bits3.ia1.src1_horiz_stride,
1064 inst->bits3.ia1.src1_width,
1065 inst->bits3.ia1.src1_vert_stride);
1066 }
1067 }
1068 else
1069 {
1070 if (inst->bits3.da16.src1_address_mode == BRW_ADDRESS_DIRECT)
1071 {
1072 return src_da16 (file,
1073 inst->bits1.da16.src1_reg_type,
1074 inst->bits1.da16.src1_reg_file,
1075 inst->bits3.da16.src1_vert_stride,
1076 inst->bits3.da16.src1_reg_nr,
1077 inst->bits3.da16.src1_subreg_nr,
1078 inst->bits3.da16.src1_abs,
1079 inst->bits3.da16.src1_negate,
1080 inst->bits3.da16.src1_swz_x,
1081 inst->bits3.da16.src1_swz_y,
1082 inst->bits3.da16.src1_swz_z,
1083 inst->bits3.da16.src1_swz_w);
1084 }
1085 else
1086 {
1087 string (file, "Indirect align16 address mode not supported");
1088 return 1;
1089 }
1090 }
1091 }
1092
1093 static int qtr_ctrl(FILE *file, struct brw_instruction *inst)
1094 {
1095 int qtr_ctl = inst->header.compression_control;
1096 int exec_size = 1 << inst->header.execution_size;
1097
1098 if (exec_size == 8) {
1099 switch (qtr_ctl) {
1100 case 0:
1101 string (file, " 1Q");
1102 break;
1103 case 1:
1104 string (file, " 2Q");
1105 break;
1106 case 2:
1107 string (file, " 3Q");
1108 break;
1109 case 3:
1110 string (file, " 4Q");
1111 break;
1112 }
1113 } else if (exec_size == 16){
1114 if (qtr_ctl < 2)
1115 string (file, " 1H");
1116 else
1117 string (file, " 2H");
1118 }
1119 return 0;
1120 }
1121
1122 int brw_disasm (FILE *file, struct brw_instruction *inst, int gen, bool is_compacted)
1123 {
1124 int err = 0;
1125 int space = 0;
1126
1127 if (inst->header.predicate_control) {
1128 string (file, "(");
1129 err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL);
1130 format (file, "f%d", gen >= 7 ? inst->bits2.da1.flag_reg_nr : 0);
1131 if (inst->bits2.da1.flag_subreg_nr)
1132 format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
1133 if (inst->header.access_mode == BRW_ALIGN_1)
1134 err |= control (file, "predicate control align1", pred_ctrl_align1,
1135 inst->header.predicate_control, NULL);
1136 else
1137 err |= control (file, "predicate control align16", pred_ctrl_align16,
1138 inst->header.predicate_control, NULL);
1139 string (file, ") ");
1140 }
1141
1142 err |= print_opcode (file, inst->header.opcode);
1143 err |= control (file, "saturate", saturate, inst->header.saturate, NULL);
1144
1145 err |= control (file, "debug control", debug_ctrl, inst->header.debug_control, NULL);
1146
1147 if (inst->header.opcode == BRW_OPCODE_MATH) {
1148 string (file, " ");
1149 err |= control (file, "function", math_function,
1150 inst->header.destreg__conditionalmod, NULL);
1151 } else if (inst->header.opcode != BRW_OPCODE_SEND &&
1152 inst->header.opcode != BRW_OPCODE_SENDC) {
1153 err |= control (file, "conditional modifier", conditional_modifier,
1154 inst->header.destreg__conditionalmod, NULL);
1155
1156 /* If we're using the conditional modifier, print which flags reg is
1157 * used for it. Note that on gen6+, the embedded-condition SEL and
1158 * control flow doesn't update flags.
1159 */
1160 if (inst->header.destreg__conditionalmod &&
1161 (gen < 6 || (inst->header.opcode != BRW_OPCODE_SEL &&
1162 inst->header.opcode != BRW_OPCODE_IF &&
1163 inst->header.opcode != BRW_OPCODE_WHILE))) {
1164 format (file, ".f%d", gen >= 7 ? inst->bits2.da1.flag_reg_nr : 0);
1165 if (inst->bits2.da1.flag_subreg_nr)
1166 format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
1167 }
1168 }
1169
1170 if (inst->header.opcode != BRW_OPCODE_NOP) {
1171 string (file, "(");
1172 err |= control (file, "execution size", exec_size, inst->header.execution_size, NULL);
1173 string (file, ")");
1174 }
1175
1176 if (inst->header.opcode == BRW_OPCODE_SEND && gen < 6)
1177 format (file, " %d", inst->header.destreg__conditionalmod);
1178
1179 if (opcode[inst->header.opcode].nsrc == 3) {
1180 pad (file, 16);
1181 err |= dest_3src (file, inst);
1182
1183 pad (file, 32);
1184 err |= src0_3src (file, inst);
1185
1186 pad (file, 48);
1187 err |= src1_3src (file, inst);
1188
1189 pad (file, 64);
1190 err |= src2_3src (file, inst);
1191 } else {
1192 if (opcode[inst->header.opcode].ndst > 0) {
1193 pad (file, 16);
1194 err |= dest (file, inst);
1195 } else if (gen == 7 && (inst->header.opcode == BRW_OPCODE_ELSE ||
1196 inst->header.opcode == BRW_OPCODE_ENDIF ||
1197 inst->header.opcode == BRW_OPCODE_WHILE)) {
1198 format (file, " %d", inst->bits3.break_cont.jip);
1199 } else if (gen == 6 && (inst->header.opcode == BRW_OPCODE_IF ||
1200 inst->header.opcode == BRW_OPCODE_ELSE ||
1201 inst->header.opcode == BRW_OPCODE_ENDIF ||
1202 inst->header.opcode == BRW_OPCODE_WHILE)) {
1203 format (file, " %d", inst->bits1.branch_gen6.jump_count);
1204 } else if ((gen >= 6 && (inst->header.opcode == BRW_OPCODE_BREAK ||
1205 inst->header.opcode == BRW_OPCODE_CONTINUE ||
1206 inst->header.opcode == BRW_OPCODE_HALT)) ||
1207 (gen == 7 && inst->header.opcode == BRW_OPCODE_IF)) {
1208 format (file, " %d %d", inst->bits3.break_cont.uip, inst->bits3.break_cont.jip);
1209 } else if (inst->header.opcode == BRW_OPCODE_JMPI) {
1210 format (file, " %d", inst->bits3.d);
1211 }
1212
1213 if (opcode[inst->header.opcode].nsrc > 0) {
1214 pad (file, 32);
1215 err |= src0 (file, inst);
1216 }
1217 if (opcode[inst->header.opcode].nsrc > 1) {
1218 pad (file, 48);
1219 err |= src1 (file, inst);
1220 }
1221 }
1222
1223 if (inst->header.opcode == BRW_OPCODE_SEND ||
1224 inst->header.opcode == BRW_OPCODE_SENDC) {
1225 enum brw_message_target target;
1226
1227 if (gen >= 6)
1228 target = inst->header.destreg__conditionalmod;
1229 else if (gen == 5)
1230 target = inst->bits2.send_gen5.sfid;
1231 else
1232 target = inst->bits3.generic.msg_target;
1233
1234 newline (file);
1235 pad (file, 16);
1236 space = 0;
1237
1238 fprintf (file, " ");
1239 if (gen >= 6) {
1240 err |= control (file, "target function", target_function_gen6,
1241 target, &space);
1242 } else {
1243 err |= control (file, "target function", target_function,
1244 target, &space);
1245 }
1246
1247 switch (target) {
1248 case BRW_SFID_MATH:
1249 err |= control (file, "math function", math_function,
1250 inst->bits3.math.function, &space);
1251 err |= control (file, "math saturate", math_saturate,
1252 inst->bits3.math.saturate, &space);
1253 err |= control (file, "math signed", math_signed,
1254 inst->bits3.math.int_type, &space);
1255 err |= control (file, "math scalar", math_scalar,
1256 inst->bits3.math.data_type, &space);
1257 err |= control (file, "math precision", math_precision,
1258 inst->bits3.math.precision, &space);
1259 break;
1260 case BRW_SFID_SAMPLER:
1261 if (gen >= 7) {
1262 format (file, " (%d, %d, %d, %d)",
1263 inst->bits3.sampler_gen7.binding_table_index,
1264 inst->bits3.sampler_gen7.sampler,
1265 inst->bits3.sampler_gen7.msg_type,
1266 inst->bits3.sampler_gen7.simd_mode);
1267 } else if (gen >= 5) {
1268 format (file, " (%d, %d, %d, %d)",
1269 inst->bits3.sampler_gen5.binding_table_index,
1270 inst->bits3.sampler_gen5.sampler,
1271 inst->bits3.sampler_gen5.msg_type,
1272 inst->bits3.sampler_gen5.simd_mode);
1273 } else if (0 /* FINISHME: is_g4x */) {
1274 format (file, " (%d, %d)",
1275 inst->bits3.sampler_g4x.binding_table_index,
1276 inst->bits3.sampler_g4x.sampler);
1277 } else {
1278 format (file, " (%d, %d, ",
1279 inst->bits3.sampler.binding_table_index,
1280 inst->bits3.sampler.sampler);
1281 err |= control (file, "sampler target format",
1282 sampler_target_format,
1283 inst->bits3.sampler.return_format, NULL);
1284 string (file, ")");
1285 }
1286 break;
1287 case BRW_SFID_DATAPORT_READ:
1288 if (gen >= 6) {
1289 format (file, " (%d, %d, %d, %d)",
1290 inst->bits3.gen6_dp.binding_table_index,
1291 inst->bits3.gen6_dp.msg_control,
1292 inst->bits3.gen6_dp.msg_type,
1293 inst->bits3.gen6_dp.send_commit_msg);
1294 } else if (gen >= 5 /* FINISHME: || is_g4x */) {
1295 format (file, " (%d, %d, %d)",
1296 inst->bits3.dp_read_gen5.binding_table_index,
1297 inst->bits3.dp_read_gen5.msg_control,
1298 inst->bits3.dp_read_gen5.msg_type);
1299 } else {
1300 format (file, " (%d, %d, %d)",
1301 inst->bits3.dp_read.binding_table_index,
1302 inst->bits3.dp_read.msg_control,
1303 inst->bits3.dp_read.msg_type);
1304 }
1305 break;
1306
1307 case BRW_SFID_DATAPORT_WRITE:
1308 if (gen >= 7) {
1309 format (file, " (");
1310
1311 err |= control (file, "DP rc message type",
1312 dp_rc_msg_type_gen6,
1313 inst->bits3.gen7_dp.msg_type, &space);
1314
1315 format (file, ", %d, %d, %d)",
1316 inst->bits3.gen7_dp.binding_table_index,
1317 inst->bits3.gen7_dp.msg_control,
1318 inst->bits3.gen7_dp.msg_type);
1319 } else if (gen == 6) {
1320 format (file, " (");
1321
1322 err |= control (file, "DP rc message type",
1323 dp_rc_msg_type_gen6,
1324 inst->bits3.gen6_dp.msg_type, &space);
1325
1326 format (file, ", %d, %d, %d, %d)",
1327 inst->bits3.gen6_dp.binding_table_index,
1328 inst->bits3.gen6_dp.msg_control,
1329 inst->bits3.gen6_dp.msg_type,
1330 inst->bits3.gen6_dp.send_commit_msg);
1331 } else {
1332 format (file, " (%d, %d, %d, %d)",
1333 inst->bits3.dp_write.binding_table_index,
1334 (inst->bits3.dp_write.last_render_target << 3) |
1335 inst->bits3.dp_write.msg_control,
1336 inst->bits3.dp_write.msg_type,
1337 inst->bits3.dp_write.send_commit_msg);
1338 }
1339 break;
1340
1341 case BRW_SFID_URB:
1342 if (gen >= 5) {
1343 format (file, " %d", inst->bits3.urb_gen5.offset);
1344 } else {
1345 format (file, " %d", inst->bits3.urb.offset);
1346 }
1347
1348 space = 1;
1349 if (gen >= 5) {
1350 err |= control (file, "urb opcode", urb_opcode,
1351 inst->bits3.urb_gen5.opcode, &space);
1352 }
1353 err |= control (file, "urb swizzle", urb_swizzle,
1354 inst->bits3.urb.swizzle_control, &space);
1355 err |= control (file, "urb allocate", urb_allocate,
1356 inst->bits3.urb.allocate, &space);
1357 err |= control (file, "urb used", urb_used,
1358 inst->bits3.urb.used, &space);
1359 err |= control (file, "urb complete", urb_complete,
1360 inst->bits3.urb.complete, &space);
1361 break;
1362 case BRW_SFID_THREAD_SPAWNER:
1363 break;
1364 case GEN7_SFID_DATAPORT_DATA_CACHE:
1365 if (gen >= 7) {
1366 format (file, " (");
1367
1368 err |= control (file, "DP DC0 message type",
1369 dp_dc0_msg_type_gen7,
1370 inst->bits3.gen7_dp.msg_type, &space);
1371
1372 format (file, ", %d, ", inst->bits3.gen7_dp.binding_table_index);
1373
1374 switch (inst->bits3.gen7_dp.msg_type) {
1375 case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
1376 control (file, "atomic op", aop, inst->bits3.ud >> 8 & 0xf,
1377 &space);
1378 break;
1379 default:
1380 format (file, "%d", inst->bits3.gen7_dp.msg_control);
1381 }
1382 format (file, ")");
1383 break;
1384 }
1385 /* FALLTHROUGH */
1386
1387 case HSW_SFID_DATAPORT_DATA_CACHE_1:
1388 if (gen >= 7) {
1389 format (file, " (");
1390
1391 err |= control (file, "DP DC1 message type",
1392 dp_dc1_msg_type_hsw,
1393 inst->bits3.gen7_dp.msg_type, &space);
1394
1395 format (file, ", %d, ",
1396 inst->bits3.gen7_dp.binding_table_index);
1397
1398 switch (inst->bits3.gen7_dp.msg_type) {
1399 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP:
1400 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2:
1401 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP:
1402 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2:
1403 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP:
1404 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2:
1405 control (file, "atomic op", aop,
1406 inst->bits3.ud >> 8 & 0xf, &space);
1407 break;
1408 default:
1409 format (file, "%d", inst->bits3.gen7_dp.msg_control);
1410 }
1411 format (file, ")");
1412 break;
1413 }
1414 /* FALLTHROUGH */
1415
1416 default:
1417 format (file, "unsupported target %d", target);
1418 break;
1419 }
1420 if (space)
1421 string (file, " ");
1422 if (gen >= 5) {
1423 format (file, "mlen %d",
1424 inst->bits3.generic_gen5.msg_length);
1425 format (file, " rlen %d",
1426 inst->bits3.generic_gen5.response_length);
1427 } else {
1428 format (file, "mlen %d",
1429 inst->bits3.generic.msg_length);
1430 format (file, " rlen %d",
1431 inst->bits3.generic.response_length);
1432 }
1433 }
1434 pad (file, 64);
1435 if (inst->header.opcode != BRW_OPCODE_NOP) {
1436 string (file, "{");
1437 space = 1;
1438 err |= control(file, "access mode", access_mode, inst->header.access_mode, &space);
1439 if (gen >= 6)
1440 err |= control (file, "write enable control", wectrl, inst->header.mask_control, &space);
1441 else
1442 err |= control (file, "mask control", mask_ctrl, inst->header.mask_control, &space);
1443 err |= control (file, "dependency control", dep_ctrl, inst->header.dependency_control, &space);
1444
1445 if (gen >= 6)
1446 err |= qtr_ctrl (file, inst);
1447 else {
1448 if (inst->header.compression_control == BRW_COMPRESSION_COMPRESSED &&
1449 opcode[inst->header.opcode].ndst > 0 &&
1450 inst->bits1.da1.dest_reg_file == BRW_MESSAGE_REGISTER_FILE &&
1451 inst->bits1.da1.dest_reg_nr & (1 << 7)) {
1452 format (file, " compr4");
1453 } else {
1454 err |= control (file, "compression control", compr_ctrl,
1455 inst->header.compression_control, &space);
1456 }
1457 }
1458
1459 err |= control (file, "compaction control", cmpt_ctrl, is_compacted, &space);
1460 err |= control (file, "thread control", thread_ctrl, inst->header.thread_control, &space);
1461 if (gen >= 6)
1462 err |= control (file, "acc write control", accwr, inst->header.acc_wr_control, &space);
1463 if (inst->header.opcode == BRW_OPCODE_SEND ||
1464 inst->header.opcode == BRW_OPCODE_SENDC)
1465 err |= control (file, "end of thread", end_of_thread,
1466 inst->bits3.generic.end_of_thread, &space);
1467 if (space)
1468 string (file, " ");
1469 string (file, "}");
1470 }
1471 string (file, ";");
1472 newline (file);
1473 return err;
1474 }