2 * Copyright © 2008 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
30 #include "main/mtypes.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
35 const struct opcode_desc opcode_descs
[128] = {
36 [BRW_OPCODE_MOV
] = { .name
= "mov", .nsrc
= 1, .ndst
= 1 },
37 [BRW_OPCODE_FRC
] = { .name
= "frc", .nsrc
= 1, .ndst
= 1 },
38 [BRW_OPCODE_RNDU
] = { .name
= "rndu", .nsrc
= 1, .ndst
= 1 },
39 [BRW_OPCODE_RNDD
] = { .name
= "rndd", .nsrc
= 1, .ndst
= 1 },
40 [BRW_OPCODE_RNDE
] = { .name
= "rnde", .nsrc
= 1, .ndst
= 1 },
41 [BRW_OPCODE_RNDZ
] = { .name
= "rndz", .nsrc
= 1, .ndst
= 1 },
42 [BRW_OPCODE_NOT
] = { .name
= "not", .nsrc
= 1, .ndst
= 1 },
43 [BRW_OPCODE_LZD
] = { .name
= "lzd", .nsrc
= 1, .ndst
= 1 },
45 [BRW_OPCODE_MUL
] = { .name
= "mul", .nsrc
= 2, .ndst
= 1 },
46 [BRW_OPCODE_MAC
] = { .name
= "mac", .nsrc
= 2, .ndst
= 1 },
47 [BRW_OPCODE_MACH
] = { .name
= "mach", .nsrc
= 2, .ndst
= 1 },
48 [BRW_OPCODE_LINE
] = { .name
= "line", .nsrc
= 2, .ndst
= 1 },
49 [BRW_OPCODE_PLN
] = { .name
= "pln", .nsrc
= 2, .ndst
= 1 },
50 [BRW_OPCODE_MAD
] = { .name
= "mad", .nsrc
= 3, .ndst
= 1 },
51 [BRW_OPCODE_SAD2
] = { .name
= "sad2", .nsrc
= 2, .ndst
= 1 },
52 [BRW_OPCODE_SADA2
] = { .name
= "sada2", .nsrc
= 2, .ndst
= 1 },
53 [BRW_OPCODE_DP4
] = { .name
= "dp4", .nsrc
= 2, .ndst
= 1 },
54 [BRW_OPCODE_DPH
] = { .name
= "dph", .nsrc
= 2, .ndst
= 1 },
55 [BRW_OPCODE_DP3
] = { .name
= "dp3", .nsrc
= 2, .ndst
= 1 },
56 [BRW_OPCODE_DP2
] = { .name
= "dp2", .nsrc
= 2, .ndst
= 1 },
57 [BRW_OPCODE_MATH
] = { .name
= "math", .nsrc
= 2, .ndst
= 1 },
59 [BRW_OPCODE_AVG
] = { .name
= "avg", .nsrc
= 2, .ndst
= 1 },
60 [BRW_OPCODE_ADD
] = { .name
= "add", .nsrc
= 2, .ndst
= 1 },
61 [BRW_OPCODE_SEL
] = { .name
= "sel", .nsrc
= 2, .ndst
= 1 },
62 [BRW_OPCODE_AND
] = { .name
= "and", .nsrc
= 2, .ndst
= 1 },
63 [BRW_OPCODE_OR
] = { .name
= "or", .nsrc
= 2, .ndst
= 1 },
64 [BRW_OPCODE_XOR
] = { .name
= "xor", .nsrc
= 2, .ndst
= 1 },
65 [BRW_OPCODE_SHR
] = { .name
= "shr", .nsrc
= 2, .ndst
= 1 },
66 [BRW_OPCODE_SHL
] = { .name
= "shl", .nsrc
= 2, .ndst
= 1 },
67 [BRW_OPCODE_ASR
] = { .name
= "asr", .nsrc
= 2, .ndst
= 1 },
68 [BRW_OPCODE_CMP
] = { .name
= "cmp", .nsrc
= 2, .ndst
= 1 },
69 [BRW_OPCODE_CMPN
] = { .name
= "cmpn", .nsrc
= 2, .ndst
= 1 },
71 [BRW_OPCODE_SEND
] = { .name
= "send", .nsrc
= 1, .ndst
= 1 },
72 [BRW_OPCODE_SENDC
] = { .name
= "sendc", .nsrc
= 1, .ndst
= 1 },
73 [BRW_OPCODE_NOP
] = { .name
= "nop", .nsrc
= 0, .ndst
= 0 },
74 [BRW_OPCODE_JMPI
] = { .name
= "jmpi", .nsrc
= 0, .ndst
= 0 },
75 [BRW_OPCODE_IF
] = { .name
= "if", .nsrc
= 2, .ndst
= 0 },
76 [BRW_OPCODE_IFF
] = { .name
= "iff", .nsrc
= 2, .ndst
= 1 },
77 [BRW_OPCODE_WHILE
] = { .name
= "while", .nsrc
= 2, .ndst
= 0 },
78 [BRW_OPCODE_ELSE
] = { .name
= "else", .nsrc
= 2, .ndst
= 0 },
79 [BRW_OPCODE_BREAK
] = { .name
= "break", .nsrc
= 2, .ndst
= 0 },
80 [BRW_OPCODE_CONTINUE
] = { .name
= "cont", .nsrc
= 1, .ndst
= 0 },
81 [BRW_OPCODE_HALT
] = { .name
= "halt", .nsrc
= 1, .ndst
= 0 },
82 [BRW_OPCODE_MSAVE
] = { .name
= "msave", .nsrc
= 1, .ndst
= 1 },
83 [BRW_OPCODE_PUSH
] = { .name
= "push", .nsrc
= 1, .ndst
= 1 },
84 [BRW_OPCODE_MRESTORE
] = { .name
= "mrest", .nsrc
= 1, .ndst
= 1 },
85 [BRW_OPCODE_POP
] = { .name
= "pop", .nsrc
= 2, .ndst
= 0 },
86 [BRW_OPCODE_WAIT
] = { .name
= "wait", .nsrc
= 1, .ndst
= 0 },
87 [BRW_OPCODE_DO
] = { .name
= "do", .nsrc
= 0, .ndst
= 0 },
88 [BRW_OPCODE_ENDIF
] = { .name
= "endif", .nsrc
= 2, .ndst
= 0 },
90 static const struct opcode_desc
*opcode
= opcode_descs
;
92 static const char * const conditional_modifier
[16] = {
93 [BRW_CONDITIONAL_NONE
] = "",
94 [BRW_CONDITIONAL_Z
] = ".e",
95 [BRW_CONDITIONAL_NZ
] = ".ne",
96 [BRW_CONDITIONAL_G
] = ".g",
97 [BRW_CONDITIONAL_GE
] = ".ge",
98 [BRW_CONDITIONAL_L
] = ".l",
99 [BRW_CONDITIONAL_LE
] = ".le",
100 [BRW_CONDITIONAL_R
] = ".r",
101 [BRW_CONDITIONAL_O
] = ".o",
102 [BRW_CONDITIONAL_U
] = ".u",
105 static const char * const negate
[2] = {
110 static const char * const _abs
[2] = {
115 static const char * const vert_stride
[16] = {
126 static const char * const width
[8] = {
134 static const char * const horiz_stride
[4] = {
141 static const char * const chan_sel
[4] = {
148 static const char * const debug_ctrl
[2] = {
153 static const char * const saturate
[2] = {
158 static const char * const accwr
[2] = {
163 static const char * const wectrl
[2] = {
168 static const char * const exec_size
[8] = {
177 static const char * const pred_inv
[2] = {
182 static const char * const pred_ctrl_align16
[16] = {
192 static const char * const pred_ctrl_align1
[16] = {
206 static const char * const thread_ctrl
[4] = {
211 static const char * const compr_ctrl
[4] = {
218 static const char * const dep_ctrl
[4] = {
222 [3] = "NoDDClr,NoDDChk",
225 static const char * const mask_ctrl
[4] = {
230 static const char * const access_mode
[2] = {
235 static const char * const reg_encoding
[8] = {
245 const int reg_type_size
[8] = {
255 static const char * const reg_file
[4] = {
262 static const char * const writemask
[16] = {
281 static const char * const end_of_thread
[2] = {
286 static const char * const target_function
[16] = {
287 [BRW_SFID_NULL
] = "null",
288 [BRW_SFID_MATH
] = "math",
289 [BRW_SFID_SAMPLER
] = "sampler",
290 [BRW_SFID_MESSAGE_GATEWAY
] = "gateway",
291 [BRW_SFID_DATAPORT_READ
] = "read",
292 [BRW_SFID_DATAPORT_WRITE
] = "write",
293 [BRW_SFID_URB
] = "urb",
294 [BRW_SFID_THREAD_SPAWNER
] = "thread_spawner"
297 static const char * const target_function_gen6
[16] = {
298 [BRW_SFID_NULL
] = "null",
299 [BRW_SFID_MATH
] = "math",
300 [BRW_SFID_SAMPLER
] = "sampler",
301 [BRW_SFID_MESSAGE_GATEWAY
] = "gateway",
302 [BRW_SFID_URB
] = "urb",
303 [BRW_SFID_THREAD_SPAWNER
] = "thread_spawner",
304 [GEN6_SFID_DATAPORT_SAMPLER_CACHE
] = "sampler",
305 [GEN6_SFID_DATAPORT_RENDER_CACHE
] = "render",
306 [GEN6_SFID_DATAPORT_CONSTANT_CACHE
] = "const",
307 [GEN7_SFID_DATAPORT_DATA_CACHE
] = "data"
310 static const char * const dp_rc_msg_type_gen6
[16] = {
311 [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
] = "OWORD block read",
312 [GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ
] = "RT UNORM read",
313 [GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
] = "OWORD dual block read",
314 [GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ
] = "media block read",
315 [GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ
] = "OWORD unaligned block read",
316 [GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
] = "DWORD scattered read",
317 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE
] = "DWORD atomic write",
318 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE
] = "OWORD block write",
319 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
] = "OWORD dual block write",
320 [GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE
] = "media block write",
321 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE
] = "DWORD scattered write",
322 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
] = "RT write",
323 [GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE
] = "streamed VB write",
324 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE
] = "RT UNORMc write",
327 static const char * const math_function
[16] = {
328 [BRW_MATH_FUNCTION_INV
] = "inv",
329 [BRW_MATH_FUNCTION_LOG
] = "log",
330 [BRW_MATH_FUNCTION_EXP
] = "exp",
331 [BRW_MATH_FUNCTION_SQRT
] = "sqrt",
332 [BRW_MATH_FUNCTION_RSQ
] = "rsq",
333 [BRW_MATH_FUNCTION_SIN
] = "sin",
334 [BRW_MATH_FUNCTION_COS
] = "cos",
335 [BRW_MATH_FUNCTION_SINCOS
] = "sincos",
336 [BRW_MATH_FUNCTION_TAN
] = "tan",
337 [BRW_MATH_FUNCTION_POW
] = "pow",
338 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
] = "intdivmod",
339 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
] = "intdiv",
340 [BRW_MATH_FUNCTION_INT_DIV_REMAINDER
] = "intmod",
343 static const char * const math_saturate
[2] = {
348 static const char * const math_signed
[2] = {
353 static const char * const math_scalar
[2] = {
358 static const char * const math_precision
[2] = {
360 [1] = "partial_precision"
363 static const char * const urb_opcode
[2] = {
368 static const char * const urb_swizzle
[4] = {
369 [BRW_URB_SWIZZLE_NONE
] = "",
370 [BRW_URB_SWIZZLE_INTERLEAVE
] = "interleave",
371 [BRW_URB_SWIZZLE_TRANSPOSE
] = "transpose",
374 static const char * const urb_allocate
[2] = {
379 static const char * const urb_used
[2] = {
384 static const char * const urb_complete
[2] = {
389 static const char * const sampler_target_format
[4] = {
398 static int string (FILE *file
, const char *string
)
400 fputs (string
, file
);
401 column
+= strlen (string
);
405 static int format (FILE *f
, const char *format
, ...)
409 va_start (args
, format
);
411 vsnprintf (buf
, sizeof (buf
) - 1, format
, args
);
417 static int newline (FILE *f
)
424 static int pad (FILE *f
, int c
)
432 static int control (FILE *file
, const char *name
, const char * const ctrl
[],
433 GLuint id
, int *space
)
436 fprintf (file
, "*** invalid %s value %d ",
444 string (file
, ctrl
[id
]);
451 static int print_opcode (FILE *file
, int id
)
453 if (!opcode
[id
].name
) {
454 format (file
, "*** invalid opcode value %d ", id
);
457 string (file
, opcode
[id
].name
);
461 static int reg (FILE *file
, GLuint _reg_file
, GLuint _reg_nr
)
465 /* Clear the Compr4 instruction compression bit. */
466 if (_reg_file
== BRW_MESSAGE_REGISTER_FILE
)
467 _reg_nr
&= ~(1 << 7);
469 if (_reg_file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
470 switch (_reg_nr
& 0xf0) {
472 string (file
, "null");
474 case BRW_ARF_ADDRESS
:
475 format (file
, "a%d", _reg_nr
& 0x0f);
477 case BRW_ARF_ACCUMULATOR
:
478 format (file
, "acc%d", _reg_nr
& 0x0f);
481 format (file
, "f%d", _reg_nr
& 0x0f);
484 format (file
, "mask%d", _reg_nr
& 0x0f);
486 case BRW_ARF_MASK_STACK
:
487 format (file
, "msd%d", _reg_nr
& 0x0f);
490 format (file
, "sr%d", _reg_nr
& 0x0f);
492 case BRW_ARF_CONTROL
:
493 format (file
, "cr%d", _reg_nr
& 0x0f);
495 case BRW_ARF_NOTIFICATION_COUNT
:
496 format (file
, "n%d", _reg_nr
& 0x0f);
503 format (file
, "ARF%d", _reg_nr
);
507 err
|= control (file
, "src reg file", reg_file
, _reg_file
, NULL
);
508 format (file
, "%d", _reg_nr
);
513 static int dest (FILE *file
, struct brw_instruction
*inst
)
517 if (inst
->header
.access_mode
== BRW_ALIGN_1
)
519 if (inst
->bits1
.da1
.dest_address_mode
== BRW_ADDRESS_DIRECT
)
521 err
|= reg (file
, inst
->bits1
.da1
.dest_reg_file
, inst
->bits1
.da1
.dest_reg_nr
);
524 if (inst
->bits1
.da1
.dest_subreg_nr
)
525 format (file
, ".%d", inst
->bits1
.da1
.dest_subreg_nr
/
526 reg_type_size
[inst
->bits1
.da1
.dest_reg_type
]);
527 format (file
, "<%d>", inst
->bits1
.da1
.dest_horiz_stride
);
528 err
|= control (file
, "dest reg encoding", reg_encoding
, inst
->bits1
.da1
.dest_reg_type
, NULL
);
532 string (file
, "g[a0");
533 if (inst
->bits1
.ia1
.dest_subreg_nr
)
534 format (file
, ".%d", inst
->bits1
.ia1
.dest_subreg_nr
/
535 reg_type_size
[inst
->bits1
.ia1
.dest_reg_type
]);
536 if (inst
->bits1
.ia1
.dest_indirect_offset
)
537 format (file
, " %d", inst
->bits1
.ia1
.dest_indirect_offset
);
539 format (file
, "<%d>", inst
->bits1
.ia1
.dest_horiz_stride
);
540 err
|= control (file
, "dest reg encoding", reg_encoding
, inst
->bits1
.ia1
.dest_reg_type
, NULL
);
545 if (inst
->bits1
.da16
.dest_address_mode
== BRW_ADDRESS_DIRECT
)
547 err
|= reg (file
, inst
->bits1
.da16
.dest_reg_file
, inst
->bits1
.da16
.dest_reg_nr
);
550 if (inst
->bits1
.da16
.dest_subreg_nr
)
551 format (file
, ".%d", inst
->bits1
.da16
.dest_subreg_nr
/
552 reg_type_size
[inst
->bits1
.da16
.dest_reg_type
]);
553 string (file
, "<1>");
554 err
|= control (file
, "writemask", writemask
, inst
->bits1
.da16
.dest_writemask
, NULL
);
555 err
|= control (file
, "dest reg encoding", reg_encoding
, inst
->bits1
.da16
.dest_reg_type
, NULL
);
560 string (file
, "Indirect align16 address mode not supported");
567 static int dest_3src (FILE *file
, struct brw_instruction
*inst
)
572 if (inst
->bits1
.da3src
.dest_reg_file
)
573 reg_file
= BRW_MESSAGE_REGISTER_FILE
;
575 reg_file
= BRW_GENERAL_REGISTER_FILE
;
577 err
|= reg (file
, reg_file
, inst
->bits1
.da3src
.dest_reg_nr
);
580 if (inst
->bits1
.da3src
.dest_subreg_nr
)
581 format (file
, ".%d", inst
->bits1
.da3src
.dest_subreg_nr
);
582 string (file
, "<1>");
583 err
|= control (file
, "writemask", writemask
, inst
->bits1
.da3src
.dest_writemask
, NULL
);
584 err
|= control (file
, "dest reg encoding", reg_encoding
, BRW_REGISTER_TYPE_F
, NULL
);
589 static int src_align1_region (FILE *file
,
590 GLuint _vert_stride
, GLuint _width
, GLuint _horiz_stride
)
594 err
|= control (file
, "vert stride", vert_stride
, _vert_stride
, NULL
);
596 err
|= control (file
, "width", width
, _width
, NULL
);
598 err
|= control (file
, "horiz_stride", horiz_stride
, _horiz_stride
, NULL
);
603 static int src_da1 (FILE *file
, GLuint type
, GLuint _reg_file
,
604 GLuint _vert_stride
, GLuint _width
, GLuint _horiz_stride
,
605 GLuint reg_num
, GLuint sub_reg_num
, GLuint __abs
, GLuint _negate
)
608 err
|= control (file
, "negate", negate
, _negate
, NULL
);
609 err
|= control (file
, "abs", _abs
, __abs
, NULL
);
611 err
|= reg (file
, _reg_file
, reg_num
);
615 format (file
, ".%d", sub_reg_num
/ reg_type_size
[type
]); /* use formal style like spec */
616 src_align1_region (file
, _vert_stride
, _width
, _horiz_stride
);
617 err
|= control (file
, "src reg encoding", reg_encoding
, type
, NULL
);
621 static int src_ia1 (FILE *file
,
625 GLuint _addr_subreg_nr
,
629 GLuint _horiz_stride
,
634 err
|= control (file
, "negate", negate
, _negate
, NULL
);
635 err
|= control (file
, "abs", _abs
, __abs
, NULL
);
637 string (file
, "g[a0");
639 format (file
, ".%d", _addr_subreg_nr
);
641 format (file
, " %d", _addr_imm
);
643 src_align1_region (file
, _vert_stride
, _width
, _horiz_stride
);
644 err
|= control (file
, "src reg encoding", reg_encoding
, type
, NULL
);
648 static int src_da16 (FILE *file
,
662 err
|= control (file
, "negate", negate
, _negate
, NULL
);
663 err
|= control (file
, "abs", _abs
, __abs
, NULL
);
665 err
|= reg (file
, _reg_file
, _reg_nr
);
669 /* bit4 for subreg number byte addressing. Make this same meaning as
670 in da1 case, so output looks consistent. */
671 format (file
, ".%d", 16 / reg_type_size
[_reg_type
]);
673 err
|= control (file
, "vert stride", vert_stride
, _vert_stride
, NULL
);
674 string (file
, ",4,1>");
676 * Three kinds of swizzle display:
677 * identity - nothing printed
678 * 1->all - print the single channel
679 * 1->1 - print the mapping
681 if (swz_x
== BRW_CHANNEL_X
&&
682 swz_y
== BRW_CHANNEL_Y
&&
683 swz_z
== BRW_CHANNEL_Z
&&
684 swz_w
== BRW_CHANNEL_W
)
688 else if (swz_x
== swz_y
&& swz_x
== swz_z
&& swz_x
== swz_w
)
691 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
696 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
697 err
|= control (file
, "channel select", chan_sel
, swz_y
, NULL
);
698 err
|= control (file
, "channel select", chan_sel
, swz_z
, NULL
);
699 err
|= control (file
, "channel select", chan_sel
, swz_w
, NULL
);
701 err
|= control (file
, "src da16 reg type", reg_encoding
, _reg_type
, NULL
);
705 static int src0_3src (FILE *file
, struct brw_instruction
*inst
)
708 GLuint swz_x
= (inst
->bits2
.da3src
.src0_swizzle
>> 0) & 0x3;
709 GLuint swz_y
= (inst
->bits2
.da3src
.src0_swizzle
>> 2) & 0x3;
710 GLuint swz_z
= (inst
->bits2
.da3src
.src0_swizzle
>> 4) & 0x3;
711 GLuint swz_w
= (inst
->bits2
.da3src
.src0_swizzle
>> 6) & 0x3;
713 err
|= control (file
, "negate", negate
, inst
->bits1
.da3src
.src0_negate
, NULL
);
714 err
|= control (file
, "abs", _abs
, inst
->bits1
.da3src
.src0_abs
, NULL
);
716 err
|= reg (file
, BRW_GENERAL_REGISTER_FILE
, inst
->bits2
.da3src
.src0_reg_nr
);
719 if (inst
->bits2
.da3src
.src0_subreg_nr
)
720 format (file
, ".%d", inst
->bits2
.da3src
.src0_subreg_nr
);
721 string (file
, "<4,1,1>");
722 err
|= control (file
, "src da16 reg type", reg_encoding
,
723 BRW_REGISTER_TYPE_F
, NULL
);
725 * Three kinds of swizzle display:
726 * identity - nothing printed
727 * 1->all - print the single channel
728 * 1->1 - print the mapping
730 if (swz_x
== BRW_CHANNEL_X
&&
731 swz_y
== BRW_CHANNEL_Y
&&
732 swz_z
== BRW_CHANNEL_Z
&&
733 swz_w
== BRW_CHANNEL_W
)
737 else if (swz_x
== swz_y
&& swz_x
== swz_z
&& swz_x
== swz_w
)
740 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
745 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
746 err
|= control (file
, "channel select", chan_sel
, swz_y
, NULL
);
747 err
|= control (file
, "channel select", chan_sel
, swz_z
, NULL
);
748 err
|= control (file
, "channel select", chan_sel
, swz_w
, NULL
);
753 static int src1_3src (FILE *file
, struct brw_instruction
*inst
)
756 GLuint swz_x
= (inst
->bits2
.da3src
.src1_swizzle
>> 0) & 0x3;
757 GLuint swz_y
= (inst
->bits2
.da3src
.src1_swizzle
>> 2) & 0x3;
758 GLuint swz_z
= (inst
->bits2
.da3src
.src1_swizzle
>> 4) & 0x3;
759 GLuint swz_w
= (inst
->bits2
.da3src
.src1_swizzle
>> 6) & 0x3;
760 GLuint src1_subreg_nr
= (inst
->bits2
.da3src
.src1_subreg_nr_low
|
761 (inst
->bits3
.da3src
.src1_subreg_nr_high
<< 2));
763 err
|= control (file
, "negate", negate
, inst
->bits1
.da3src
.src1_negate
,
765 err
|= control (file
, "abs", _abs
, inst
->bits1
.da3src
.src1_abs
, NULL
);
767 err
|= reg (file
, BRW_GENERAL_REGISTER_FILE
,
768 inst
->bits3
.da3src
.src1_reg_nr
);
772 format (file
, ".%d", src1_subreg_nr
);
773 string (file
, "<4,1,1>");
774 err
|= control (file
, "src da16 reg type", reg_encoding
,
775 BRW_REGISTER_TYPE_F
, NULL
);
777 * Three kinds of swizzle display:
778 * identity - nothing printed
779 * 1->all - print the single channel
780 * 1->1 - print the mapping
782 if (swz_x
== BRW_CHANNEL_X
&&
783 swz_y
== BRW_CHANNEL_Y
&&
784 swz_z
== BRW_CHANNEL_Z
&&
785 swz_w
== BRW_CHANNEL_W
)
789 else if (swz_x
== swz_y
&& swz_x
== swz_z
&& swz_x
== swz_w
)
792 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
797 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
798 err
|= control (file
, "channel select", chan_sel
, swz_y
, NULL
);
799 err
|= control (file
, "channel select", chan_sel
, swz_z
, NULL
);
800 err
|= control (file
, "channel select", chan_sel
, swz_w
, NULL
);
806 static int src2_3src (FILE *file
, struct brw_instruction
*inst
)
809 GLuint swz_x
= (inst
->bits3
.da3src
.src2_swizzle
>> 0) & 0x3;
810 GLuint swz_y
= (inst
->bits3
.da3src
.src2_swizzle
>> 2) & 0x3;
811 GLuint swz_z
= (inst
->bits3
.da3src
.src2_swizzle
>> 4) & 0x3;
812 GLuint swz_w
= (inst
->bits3
.da3src
.src2_swizzle
>> 6) & 0x3;
814 err
|= control (file
, "negate", negate
, inst
->bits1
.da3src
.src2_negate
,
816 err
|= control (file
, "abs", _abs
, inst
->bits1
.da3src
.src2_abs
, NULL
);
818 err
|= reg (file
, BRW_GENERAL_REGISTER_FILE
,
819 inst
->bits3
.da3src
.src2_reg_nr
);
822 if (inst
->bits3
.da3src
.src2_subreg_nr
)
823 format (file
, ".%d", inst
->bits3
.da3src
.src2_subreg_nr
);
824 string (file
, "<4,1,1>");
825 err
|= control (file
, "src da16 reg type", reg_encoding
,
826 BRW_REGISTER_TYPE_F
, NULL
);
828 * Three kinds of swizzle display:
829 * identity - nothing printed
830 * 1->all - print the single channel
831 * 1->1 - print the mapping
833 if (swz_x
== BRW_CHANNEL_X
&&
834 swz_y
== BRW_CHANNEL_Y
&&
835 swz_z
== BRW_CHANNEL_Z
&&
836 swz_w
== BRW_CHANNEL_W
)
840 else if (swz_x
== swz_y
&& swz_x
== swz_z
&& swz_x
== swz_w
)
843 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
848 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
849 err
|= control (file
, "channel select", chan_sel
, swz_y
, NULL
);
850 err
|= control (file
, "channel select", chan_sel
, swz_z
, NULL
);
851 err
|= control (file
, "channel select", chan_sel
, swz_w
, NULL
);
856 static int imm (FILE *file
, GLuint type
, struct brw_instruction
*inst
) {
858 case BRW_REGISTER_TYPE_UD
:
859 format (file
, "0x%08xUD", inst
->bits3
.ud
);
861 case BRW_REGISTER_TYPE_D
:
862 format (file
, "%dD", inst
->bits3
.d
);
864 case BRW_REGISTER_TYPE_UW
:
865 format (file
, "0x%04xUW", (uint16_t) inst
->bits3
.ud
);
867 case BRW_REGISTER_TYPE_W
:
868 format (file
, "%dW", (int16_t) inst
->bits3
.d
);
870 case BRW_REGISTER_TYPE_UB
:
871 format (file
, "0x%02xUB", (int8_t) inst
->bits3
.ud
);
873 case BRW_REGISTER_TYPE_VF
:
874 format (file
, "Vector Float");
876 case BRW_REGISTER_TYPE_V
:
877 format (file
, "0x%08xV", inst
->bits3
.ud
);
879 case BRW_REGISTER_TYPE_F
:
880 format (file
, "%-gF", inst
->bits3
.f
);
885 static int src0 (FILE *file
, struct brw_instruction
*inst
)
887 if (inst
->bits1
.da1
.src0_reg_file
== BRW_IMMEDIATE_VALUE
)
888 return imm (file
, inst
->bits1
.da1
.src0_reg_type
,
890 else if (inst
->header
.access_mode
== BRW_ALIGN_1
)
892 if (inst
->bits2
.da1
.src0_address_mode
== BRW_ADDRESS_DIRECT
)
894 return src_da1 (file
,
895 inst
->bits1
.da1
.src0_reg_type
,
896 inst
->bits1
.da1
.src0_reg_file
,
897 inst
->bits2
.da1
.src0_vert_stride
,
898 inst
->bits2
.da1
.src0_width
,
899 inst
->bits2
.da1
.src0_horiz_stride
,
900 inst
->bits2
.da1
.src0_reg_nr
,
901 inst
->bits2
.da1
.src0_subreg_nr
,
902 inst
->bits2
.da1
.src0_abs
,
903 inst
->bits2
.da1
.src0_negate
);
907 return src_ia1 (file
,
908 inst
->bits1
.ia1
.src0_reg_type
,
909 inst
->bits1
.ia1
.src0_reg_file
,
910 inst
->bits2
.ia1
.src0_indirect_offset
,
911 inst
->bits2
.ia1
.src0_subreg_nr
,
912 inst
->bits2
.ia1
.src0_negate
,
913 inst
->bits2
.ia1
.src0_abs
,
914 inst
->bits2
.ia1
.src0_address_mode
,
915 inst
->bits2
.ia1
.src0_horiz_stride
,
916 inst
->bits2
.ia1
.src0_width
,
917 inst
->bits2
.ia1
.src0_vert_stride
);
922 if (inst
->bits2
.da16
.src0_address_mode
== BRW_ADDRESS_DIRECT
)
924 return src_da16 (file
,
925 inst
->bits1
.da16
.src0_reg_type
,
926 inst
->bits1
.da16
.src0_reg_file
,
927 inst
->bits2
.da16
.src0_vert_stride
,
928 inst
->bits2
.da16
.src0_reg_nr
,
929 inst
->bits2
.da16
.src0_subreg_nr
,
930 inst
->bits2
.da16
.src0_abs
,
931 inst
->bits2
.da16
.src0_negate
,
932 inst
->bits2
.da16
.src0_swz_x
,
933 inst
->bits2
.da16
.src0_swz_y
,
934 inst
->bits2
.da16
.src0_swz_z
,
935 inst
->bits2
.da16
.src0_swz_w
);
939 string (file
, "Indirect align16 address mode not supported");
945 static int src1 (FILE *file
, struct brw_instruction
*inst
)
947 if (inst
->bits1
.da1
.src1_reg_file
== BRW_IMMEDIATE_VALUE
)
948 return imm (file
, inst
->bits1
.da1
.src1_reg_type
,
950 else if (inst
->header
.access_mode
== BRW_ALIGN_1
)
952 if (inst
->bits3
.da1
.src1_address_mode
== BRW_ADDRESS_DIRECT
)
954 return src_da1 (file
,
955 inst
->bits1
.da1
.src1_reg_type
,
956 inst
->bits1
.da1
.src1_reg_file
,
957 inst
->bits3
.da1
.src1_vert_stride
,
958 inst
->bits3
.da1
.src1_width
,
959 inst
->bits3
.da1
.src1_horiz_stride
,
960 inst
->bits3
.da1
.src1_reg_nr
,
961 inst
->bits3
.da1
.src1_subreg_nr
,
962 inst
->bits3
.da1
.src1_abs
,
963 inst
->bits3
.da1
.src1_negate
);
967 return src_ia1 (file
,
968 inst
->bits1
.ia1
.src1_reg_type
,
969 inst
->bits1
.ia1
.src1_reg_file
,
970 inst
->bits3
.ia1
.src1_indirect_offset
,
971 inst
->bits3
.ia1
.src1_subreg_nr
,
972 inst
->bits3
.ia1
.src1_negate
,
973 inst
->bits3
.ia1
.src1_abs
,
974 inst
->bits3
.ia1
.src1_address_mode
,
975 inst
->bits3
.ia1
.src1_horiz_stride
,
976 inst
->bits3
.ia1
.src1_width
,
977 inst
->bits3
.ia1
.src1_vert_stride
);
982 if (inst
->bits3
.da16
.src1_address_mode
== BRW_ADDRESS_DIRECT
)
984 return src_da16 (file
,
985 inst
->bits1
.da16
.src1_reg_type
,
986 inst
->bits1
.da16
.src1_reg_file
,
987 inst
->bits3
.da16
.src1_vert_stride
,
988 inst
->bits3
.da16
.src1_reg_nr
,
989 inst
->bits3
.da16
.src1_subreg_nr
,
990 inst
->bits3
.da16
.src1_abs
,
991 inst
->bits3
.da16
.src1_negate
,
992 inst
->bits3
.da16
.src1_swz_x
,
993 inst
->bits3
.da16
.src1_swz_y
,
994 inst
->bits3
.da16
.src1_swz_z
,
995 inst
->bits3
.da16
.src1_swz_w
);
999 string (file
, "Indirect align16 address mode not supported");
1014 static int qtr_ctrl(FILE *file
, struct brw_instruction
*inst
)
1016 int qtr_ctl
= inst
->header
.compression_control
;
1017 int exec_size
= esize
[inst
->header
.execution_size
];
1019 if (exec_size
== 8) {
1022 string (file
, " 1Q");
1025 string (file
, " 2Q");
1028 string (file
, " 3Q");
1031 string (file
, " 4Q");
1034 } else if (exec_size
== 16){
1036 string (file
, " 1H");
1038 string (file
, " 2H");
1043 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
)
1048 if (inst
->header
.predicate_control
) {
1050 err
|= control (file
, "predicate inverse", pred_inv
, inst
->header
.predicate_inverse
, NULL
);
1051 string (file
, "f0");
1052 if (inst
->bits2
.da1
.flag_subreg_nr
)
1053 format (file
, ".%d", inst
->bits2
.da1
.flag_subreg_nr
);
1054 if (inst
->header
.access_mode
== BRW_ALIGN_1
)
1055 err
|= control (file
, "predicate control align1", pred_ctrl_align1
,
1056 inst
->header
.predicate_control
, NULL
);
1058 err
|= control (file
, "predicate control align16", pred_ctrl_align16
,
1059 inst
->header
.predicate_control
, NULL
);
1060 string (file
, ") ");
1063 err
|= print_opcode (file
, inst
->header
.opcode
);
1064 err
|= control (file
, "saturate", saturate
, inst
->header
.saturate
, NULL
);
1065 err
|= control (file
, "debug control", debug_ctrl
, inst
->header
.debug_control
, NULL
);
1067 if (inst
->header
.opcode
== BRW_OPCODE_MATH
) {
1069 err
|= control (file
, "function", math_function
,
1070 inst
->header
.destreg__conditionalmod
, NULL
);
1071 } else if (inst
->header
.opcode
!= BRW_OPCODE_SEND
&&
1072 inst
->header
.opcode
!= BRW_OPCODE_SENDC
)
1073 err
|= control (file
, "conditional modifier", conditional_modifier
,
1074 inst
->header
.destreg__conditionalmod
, NULL
);
1076 if (inst
->header
.opcode
!= BRW_OPCODE_NOP
) {
1078 err
|= control (file
, "execution size", exec_size
, inst
->header
.execution_size
, NULL
);
1082 if (inst
->header
.opcode
== BRW_OPCODE_SEND
&& gen
< 6)
1083 format (file
, " %d", inst
->header
.destreg__conditionalmod
);
1085 if (opcode
[inst
->header
.opcode
].nsrc
== 3) {
1087 err
|= dest_3src (file
, inst
);
1090 err
|= src0_3src (file
, inst
);
1093 err
|= src1_3src (file
, inst
);
1096 err
|= src2_3src (file
, inst
);
1098 if (opcode
[inst
->header
.opcode
].ndst
> 0) {
1100 err
|= dest (file
, inst
);
1101 } else if (gen
>= 6 && (inst
->header
.opcode
== BRW_OPCODE_IF
||
1102 inst
->header
.opcode
== BRW_OPCODE_ELSE
||
1103 inst
->header
.opcode
== BRW_OPCODE_ENDIF
||
1104 inst
->header
.opcode
== BRW_OPCODE_WHILE
)) {
1105 format (file
, " %d", inst
->bits1
.branch_gen6
.jump_count
);
1106 } else if (gen
>= 6 && (inst
->header
.opcode
== BRW_OPCODE_BREAK
||
1107 inst
->header
.opcode
== BRW_OPCODE_CONTINUE
||
1108 inst
->header
.opcode
== BRW_OPCODE_HALT
)) {
1109 format (file
, " %d %d", inst
->bits3
.break_cont
.uip
, inst
->bits3
.break_cont
.jip
);
1110 } else if (inst
->header
.opcode
== BRW_OPCODE_JMPI
) {
1111 format (file
, " %d", inst
->bits3
.d
);
1114 if (opcode
[inst
->header
.opcode
].nsrc
> 0) {
1116 err
|= src0 (file
, inst
);
1118 if (opcode
[inst
->header
.opcode
].nsrc
> 1) {
1120 err
|= src1 (file
, inst
);
1124 if (inst
->header
.opcode
== BRW_OPCODE_SEND
||
1125 inst
->header
.opcode
== BRW_OPCODE_SENDC
) {
1126 enum brw_message_target target
;
1129 target
= inst
->header
.destreg__conditionalmod
;
1131 target
= inst
->bits2
.send_gen5
.sfid
;
1133 target
= inst
->bits3
.generic
.msg_target
;
1140 err
|= control (file
, "target function", target_function_gen6
,
1143 err
|= control (file
, "target function", target_function
,
1149 err
|= control (file
, "math function", math_function
,
1150 inst
->bits3
.math
.function
, &space
);
1151 err
|= control (file
, "math saturate", math_saturate
,
1152 inst
->bits3
.math
.saturate
, &space
);
1153 err
|= control (file
, "math signed", math_signed
,
1154 inst
->bits3
.math
.int_type
, &space
);
1155 err
|= control (file
, "math scalar", math_scalar
,
1156 inst
->bits3
.math
.data_type
, &space
);
1157 err
|= control (file
, "math precision", math_precision
,
1158 inst
->bits3
.math
.precision
, &space
);
1160 case BRW_SFID_SAMPLER
:
1162 format (file
, " (%d, %d, %d, %d)",
1163 inst
->bits3
.sampler_gen7
.binding_table_index
,
1164 inst
->bits3
.sampler_gen7
.sampler
,
1165 inst
->bits3
.sampler_gen7
.msg_type
,
1166 inst
->bits3
.sampler_gen7
.simd_mode
);
1167 } else if (gen
>= 5) {
1168 format (file
, " (%d, %d, %d, %d)",
1169 inst
->bits3
.sampler_gen5
.binding_table_index
,
1170 inst
->bits3
.sampler_gen5
.sampler
,
1171 inst
->bits3
.sampler_gen5
.msg_type
,
1172 inst
->bits3
.sampler_gen5
.simd_mode
);
1173 } else if (0 /* FINISHME: is_g4x */) {
1174 format (file
, " (%d, %d)",
1175 inst
->bits3
.sampler_g4x
.binding_table_index
,
1176 inst
->bits3
.sampler_g4x
.sampler
);
1178 format (file
, " (%d, %d, ",
1179 inst
->bits3
.sampler
.binding_table_index
,
1180 inst
->bits3
.sampler
.sampler
);
1181 err
|= control (file
, "sampler target format",
1182 sampler_target_format
,
1183 inst
->bits3
.sampler
.return_format
, NULL
);
1187 case BRW_SFID_DATAPORT_READ
:
1189 format (file
, " (%d, %d, %d, %d)",
1190 inst
->bits3
.gen6_dp
.binding_table_index
,
1191 inst
->bits3
.gen6_dp
.msg_control
,
1192 inst
->bits3
.gen6_dp
.msg_type
,
1193 inst
->bits3
.gen6_dp
.send_commit_msg
);
1194 } else if (gen
>= 5 /* FINISHME: || is_g4x */) {
1195 format (file
, " (%d, %d, %d)",
1196 inst
->bits3
.dp_read_gen5
.binding_table_index
,
1197 inst
->bits3
.dp_read_gen5
.msg_control
,
1198 inst
->bits3
.dp_read_gen5
.msg_type
);
1200 format (file
, " (%d, %d, %d)",
1201 inst
->bits3
.dp_read
.binding_table_index
,
1202 inst
->bits3
.dp_read
.msg_control
,
1203 inst
->bits3
.dp_read
.msg_type
);
1207 case BRW_SFID_DATAPORT_WRITE
:
1209 format (file
, " (");
1211 err
|= control (file
, "DP rc message type",
1212 dp_rc_msg_type_gen6
,
1213 inst
->bits3
.gen7_dp
.msg_type
, &space
);
1215 format (file
, ", %d, %d, %d)",
1216 inst
->bits3
.gen7_dp
.binding_table_index
,
1217 inst
->bits3
.gen7_dp
.msg_control
,
1218 inst
->bits3
.gen7_dp
.msg_type
);
1219 } else if (gen
== 6) {
1220 format (file
, " (");
1222 err
|= control (file
, "DP rc message type",
1223 dp_rc_msg_type_gen6
,
1224 inst
->bits3
.gen6_dp
.msg_type
, &space
);
1226 format (file
, ", %d, %d, %d, %d)",
1227 inst
->bits3
.gen6_dp
.binding_table_index
,
1228 inst
->bits3
.gen6_dp
.msg_control
,
1229 inst
->bits3
.gen6_dp
.msg_type
,
1230 inst
->bits3
.gen6_dp
.send_commit_msg
);
1232 format (file
, " (%d, %d, %d, %d)",
1233 inst
->bits3
.dp_write
.binding_table_index
,
1234 (inst
->bits3
.dp_write
.last_render_target
<< 3) |
1235 inst
->bits3
.dp_write
.msg_control
,
1236 inst
->bits3
.dp_write
.msg_type
,
1237 inst
->bits3
.dp_write
.send_commit_msg
);
1243 format (file
, " %d", inst
->bits3
.urb_gen5
.offset
);
1245 format (file
, " %d", inst
->bits3
.urb
.offset
);
1250 err
|= control (file
, "urb opcode", urb_opcode
,
1251 inst
->bits3
.urb_gen5
.opcode
, &space
);
1253 err
|= control (file
, "urb swizzle", urb_swizzle
,
1254 inst
->bits3
.urb
.swizzle_control
, &space
);
1255 err
|= control (file
, "urb allocate", urb_allocate
,
1256 inst
->bits3
.urb
.allocate
, &space
);
1257 err
|= control (file
, "urb used", urb_used
,
1258 inst
->bits3
.urb
.used
, &space
);
1259 err
|= control (file
, "urb complete", urb_complete
,
1260 inst
->bits3
.urb
.complete
, &space
);
1262 case BRW_SFID_THREAD_SPAWNER
:
1264 case GEN7_SFID_DATAPORT_DATA_CACHE
:
1265 format (file
, " (%d, %d, %d)",
1266 inst
->bits3
.gen7_dp
.binding_table_index
,
1267 inst
->bits3
.gen7_dp
.msg_control
,
1268 inst
->bits3
.gen7_dp
.msg_type
);
1273 format (file
, "unsupported target %d", target
);
1279 format (file
, "mlen %d",
1280 inst
->bits3
.generic_gen5
.msg_length
);
1281 format (file
, " rlen %d",
1282 inst
->bits3
.generic_gen5
.response_length
);
1284 format (file
, "mlen %d",
1285 inst
->bits3
.generic
.msg_length
);
1286 format (file
, " rlen %d",
1287 inst
->bits3
.generic
.response_length
);
1291 if (inst
->header
.opcode
!= BRW_OPCODE_NOP
) {
1294 err
|= control(file
, "access mode", access_mode
, inst
->header
.access_mode
, &space
);
1296 err
|= control (file
, "write enable control", wectrl
, inst
->header
.mask_control
, &space
);
1298 err
|= control (file
, "mask control", mask_ctrl
, inst
->header
.mask_control
, &space
);
1299 err
|= control (file
, "dependency control", dep_ctrl
, inst
->header
.dependency_control
, &space
);
1302 err
|= qtr_ctrl (file
, inst
);
1304 if (inst
->header
.compression_control
== BRW_COMPRESSION_COMPRESSED
&&
1305 opcode
[inst
->header
.opcode
].ndst
> 0 &&
1306 inst
->bits1
.da1
.dest_reg_file
== BRW_MESSAGE_REGISTER_FILE
&&
1307 inst
->bits1
.da1
.dest_reg_nr
& (1 << 7)) {
1308 format (file
, " compr4");
1310 err
|= control (file
, "compression control", compr_ctrl
,
1311 inst
->header
.compression_control
, &space
);
1315 err
|= control (file
, "thread control", thread_ctrl
, inst
->header
.thread_control
, &space
);
1317 err
|= control (file
, "acc write control", accwr
, inst
->header
.acc_wr_control
, &space
);
1318 if (inst
->header
.opcode
== BRW_OPCODE_SEND
||
1319 inst
->header
.opcode
== BRW_OPCODE_SENDC
)
1320 err
|= control (file
, "end of thread", end_of_thread
,
1321 inst
->bits3
.generic
.end_of_thread
, &space
);