2 * Copyright © 2008 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
30 #include "main/mtypes.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
40 [BRW_OPCODE_MOV
] = { .name
= "mov", .nsrc
= 1, .ndst
= 1 },
41 [BRW_OPCODE_FRC
] = { .name
= "frc", .nsrc
= 1, .ndst
= 1 },
42 [BRW_OPCODE_RNDU
] = { .name
= "rndu", .nsrc
= 1, .ndst
= 1 },
43 [BRW_OPCODE_RNDD
] = { .name
= "rndd", .nsrc
= 1, .ndst
= 1 },
44 [BRW_OPCODE_RNDE
] = { .name
= "rnde", .nsrc
= 1, .ndst
= 1 },
45 [BRW_OPCODE_RNDZ
] = { .name
= "rndz", .nsrc
= 1, .ndst
= 1 },
46 [BRW_OPCODE_NOT
] = { .name
= "not", .nsrc
= 1, .ndst
= 1 },
47 [BRW_OPCODE_LZD
] = { .name
= "lzd", .nsrc
= 1, .ndst
= 1 },
49 [BRW_OPCODE_MUL
] = { .name
= "mul", .nsrc
= 2, .ndst
= 1 },
50 [BRW_OPCODE_MAC
] = { .name
= "mac", .nsrc
= 2, .ndst
= 1 },
51 [BRW_OPCODE_MACH
] = { .name
= "mach", .nsrc
= 2, .ndst
= 1 },
52 [BRW_OPCODE_LINE
] = { .name
= "line", .nsrc
= 2, .ndst
= 1 },
53 [BRW_OPCODE_PLN
] = { .name
= "pln", .nsrc
= 2, .ndst
= 1 },
54 [BRW_OPCODE_SAD2
] = { .name
= "sad2", .nsrc
= 2, .ndst
= 1 },
55 [BRW_OPCODE_SADA2
] = { .name
= "sada2", .nsrc
= 2, .ndst
= 1 },
56 [BRW_OPCODE_DP4
] = { .name
= "dp4", .nsrc
= 2, .ndst
= 1 },
57 [BRW_OPCODE_DPH
] = { .name
= "dph", .nsrc
= 2, .ndst
= 1 },
58 [BRW_OPCODE_DP3
] = { .name
= "dp3", .nsrc
= 2, .ndst
= 1 },
59 [BRW_OPCODE_DP2
] = { .name
= "dp2", .nsrc
= 2, .ndst
= 1 },
60 [BRW_OPCODE_MATH
] = { .name
= "math", .nsrc
= 2, .ndst
= 1 },
62 [BRW_OPCODE_AVG
] = { .name
= "avg", .nsrc
= 2, .ndst
= 1 },
63 [BRW_OPCODE_ADD
] = { .name
= "add", .nsrc
= 2, .ndst
= 1 },
64 [BRW_OPCODE_SEL
] = { .name
= "sel", .nsrc
= 2, .ndst
= 1 },
65 [BRW_OPCODE_AND
] = { .name
= "and", .nsrc
= 2, .ndst
= 1 },
66 [BRW_OPCODE_OR
] = { .name
= "or", .nsrc
= 2, .ndst
= 1 },
67 [BRW_OPCODE_XOR
] = { .name
= "xor", .nsrc
= 2, .ndst
= 1 },
68 [BRW_OPCODE_SHR
] = { .name
= "shr", .nsrc
= 2, .ndst
= 1 },
69 [BRW_OPCODE_SHL
] = { .name
= "shl", .nsrc
= 2, .ndst
= 1 },
70 [BRW_OPCODE_ASR
] = { .name
= "asr", .nsrc
= 2, .ndst
= 1 },
71 [BRW_OPCODE_CMP
] = { .name
= "cmp", .nsrc
= 2, .ndst
= 1 },
72 [BRW_OPCODE_CMPN
] = { .name
= "cmpn", .nsrc
= 2, .ndst
= 1 },
74 [BRW_OPCODE_SEND
] = { .name
= "send", .nsrc
= 1, .ndst
= 1 },
75 [BRW_OPCODE_SENDC
] = { .name
= "sendc", .nsrc
= 1, .ndst
= 1 },
76 [BRW_OPCODE_NOP
] = { .name
= "nop", .nsrc
= 0, .ndst
= 0 },
77 [BRW_OPCODE_JMPI
] = { .name
= "jmpi", .nsrc
= 1, .ndst
= 0 },
78 [BRW_OPCODE_IF
] = { .name
= "if", .nsrc
= 2, .ndst
= 0 },
79 [BRW_OPCODE_IFF
] = { .name
= "iff", .nsrc
= 2, .ndst
= 1 },
80 [BRW_OPCODE_WHILE
] = { .name
= "while", .nsrc
= 2, .ndst
= 0 },
81 [BRW_OPCODE_ELSE
] = { .name
= "else", .nsrc
= 2, .ndst
= 0 },
82 [BRW_OPCODE_BREAK
] = { .name
= "break", .nsrc
= 2, .ndst
= 0 },
83 [BRW_OPCODE_CONTINUE
] = { .name
= "cont", .nsrc
= 1, .ndst
= 0 },
84 [BRW_OPCODE_HALT
] = { .name
= "halt", .nsrc
= 1, .ndst
= 0 },
85 [BRW_OPCODE_MSAVE
] = { .name
= "msave", .nsrc
= 1, .ndst
= 1 },
86 [BRW_OPCODE_PUSH
] = { .name
= "push", .nsrc
= 1, .ndst
= 1 },
87 [BRW_OPCODE_MRESTORE
] = { .name
= "mrest", .nsrc
= 1, .ndst
= 1 },
88 [BRW_OPCODE_POP
] = { .name
= "pop", .nsrc
= 2, .ndst
= 0 },
89 [BRW_OPCODE_WAIT
] = { .name
= "wait", .nsrc
= 1, .ndst
= 0 },
90 [BRW_OPCODE_DO
] = { .name
= "do", .nsrc
= 0, .ndst
= 0 },
91 [BRW_OPCODE_ENDIF
] = { .name
= "endif", .nsrc
= 2, .ndst
= 0 },
94 char *conditional_modifier
[16] = {
95 [BRW_CONDITIONAL_NONE
] = "",
96 [BRW_CONDITIONAL_Z
] = ".e",
97 [BRW_CONDITIONAL_NZ
] = ".ne",
98 [BRW_CONDITIONAL_G
] = ".g",
99 [BRW_CONDITIONAL_GE
] = ".ge",
100 [BRW_CONDITIONAL_L
] = ".l",
101 [BRW_CONDITIONAL_LE
] = ".le",
102 [BRW_CONDITIONAL_R
] = ".r",
103 [BRW_CONDITIONAL_O
] = ".o",
104 [BRW_CONDITIONAL_U
] = ".u",
117 char *vert_stride
[16] = {
136 char *horiz_stride
[4] = {
143 char *chan_sel
[4] = {
150 char *dest_condmod
[16] = {
153 char *debug_ctrl
[2] = {
158 char *saturate
[2] = {
173 char *exec_size
[8] = {
182 char *pred_inv
[2] = {
187 char *pred_ctrl_align16
[16] = {
197 char *pred_ctrl_align1
[16] = {
211 char *thread_ctrl
[4] = {
216 char *compr_ctrl
[4] = {
223 char *dep_ctrl
[4] = {
227 [3] = "NoDDClr,NoDDChk",
230 char *mask_ctrl
[4] = {
235 char *access_mode
[2] = {
240 char *reg_encoding
[8] = {
250 int reg_type_size
[8] = {
260 char *imm_encoding
[8] = {
270 char *reg_file
[4] = {
277 char *writemask
[16] = {
296 char *end_of_thread
[2] = {
301 char *target_function
[16] = {
302 [BRW_SFID_NULL
] = "null",
303 [BRW_SFID_MATH
] = "math",
304 [BRW_SFID_SAMPLER
] = "sampler",
305 [BRW_SFID_MESSAGE_GATEWAY
] = "gateway",
306 [BRW_SFID_DATAPORT_READ
] = "read",
307 [BRW_SFID_DATAPORT_WRITE
] = "write",
308 [BRW_SFID_URB
] = "urb",
309 [BRW_SFID_THREAD_SPAWNER
] = "thread_spawner"
312 char *target_function_gen6
[16] = {
313 [BRW_SFID_NULL
] = "null",
314 [BRW_SFID_MATH
] = "math",
315 [BRW_SFID_SAMPLER
] = "sampler",
316 [BRW_SFID_MESSAGE_GATEWAY
] = "gateway",
317 [BRW_SFID_URB
] = "urb",
318 [BRW_SFID_THREAD_SPAWNER
] = "thread_spawner",
319 [GEN6_SFID_DATAPORT_SAMPLER_CACHE
] = "sampler",
320 [GEN6_SFID_DATAPORT_RENDER_CACHE
] = "render",
321 [GEN6_SFID_DATAPORT_CONSTANT_CACHE
] = "const",
322 [GEN7_SFID_DATAPORT_DATA_CACHE
] = "data"
325 char *dp_rc_msg_type_gen6
[16] = {
326 [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
] = "OWORD block read",
327 [GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ
] = "RT UNORM read",
328 [GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
] = "OWORD dual block read",
329 [GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ
] = "media block read",
330 [GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ
] = "OWORD unaligned block read",
331 [GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
] = "DWORD scattered read",
332 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE
] = "DWORD atomic write",
333 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE
] = "OWORD block write",
334 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
] = "OWORD dual block write",
335 [GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE
] = "media block write",
336 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE
] = "DWORD scattered write",
337 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
] = "RT write",
338 [GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE
] = "streamed VB write",
339 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE
] = "RT UNORMc write",
342 char *math_function
[16] = {
343 [BRW_MATH_FUNCTION_INV
] = "inv",
344 [BRW_MATH_FUNCTION_LOG
] = "log",
345 [BRW_MATH_FUNCTION_EXP
] = "exp",
346 [BRW_MATH_FUNCTION_SQRT
] = "sqrt",
347 [BRW_MATH_FUNCTION_RSQ
] = "rsq",
348 [BRW_MATH_FUNCTION_SIN
] = "sin",
349 [BRW_MATH_FUNCTION_COS
] = "cos",
350 [BRW_MATH_FUNCTION_SINCOS
] = "sincos",
351 [BRW_MATH_FUNCTION_TAN
] = "tan",
352 [BRW_MATH_FUNCTION_POW
] = "pow",
353 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
] = "intdivmod",
354 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
] = "intdiv",
355 [BRW_MATH_FUNCTION_INT_DIV_REMAINDER
] = "intmod",
358 char *math_saturate
[2] = {
363 char *math_signed
[2] = {
368 char *math_scalar
[2] = {
373 char *math_precision
[2] = {
375 [1] = "partial_precision"
378 char *urb_opcode
[2] = {
383 char *urb_swizzle
[4] = {
384 [BRW_URB_SWIZZLE_NONE
] = "",
385 [BRW_URB_SWIZZLE_INTERLEAVE
] = "interleave",
386 [BRW_URB_SWIZZLE_TRANSPOSE
] = "transpose",
389 char *urb_allocate
[2] = {
394 char *urb_used
[2] = {
399 char *urb_complete
[2] = {
404 char *sampler_target_format
[4] = {
413 static int string (FILE *file
, char *string
)
415 fputs (string
, file
);
416 column
+= strlen (string
);
420 static int format (FILE *f
, char *format
, ...)
424 va_start (args
, format
);
426 vsnprintf (buf
, sizeof (buf
) - 1, format
, args
);
432 static int newline (FILE *f
)
439 static int pad (FILE *f
, int c
)
447 static int control (FILE *file
, char *name
, char *ctrl
[], GLuint id
, int *space
)
450 fprintf (file
, "*** invalid %s value %d ",
458 string (file
, ctrl
[id
]);
465 static int print_opcode (FILE *file
, int id
)
467 if (!opcode
[id
].name
) {
468 format (file
, "*** invalid opcode value %d ", id
);
471 string (file
, opcode
[id
].name
);
475 static int reg (FILE *file
, GLuint _reg_file
, GLuint _reg_nr
)
479 /* Clear the Compr4 instruction compression bit. */
480 if (_reg_file
== BRW_MESSAGE_REGISTER_FILE
)
481 _reg_nr
&= ~(1 << 7);
483 if (_reg_file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
484 switch (_reg_nr
& 0xf0) {
486 string (file
, "null");
488 case BRW_ARF_ADDRESS
:
489 format (file
, "a%d", _reg_nr
& 0x0f);
491 case BRW_ARF_ACCUMULATOR
:
492 format (file
, "acc%d", _reg_nr
& 0x0f);
495 format (file
, "f%d", _reg_nr
& 0x0f);
498 format (file
, "mask%d", _reg_nr
& 0x0f);
500 case BRW_ARF_MASK_STACK
:
501 format (file
, "msd%d", _reg_nr
& 0x0f);
504 format (file
, "sr%d", _reg_nr
& 0x0f);
506 case BRW_ARF_CONTROL
:
507 format (file
, "cr%d", _reg_nr
& 0x0f);
509 case BRW_ARF_NOTIFICATION_COUNT
:
510 format (file
, "n%d", _reg_nr
& 0x0f);
517 format (file
, "ARF%d", _reg_nr
);
521 err
|= control (file
, "src reg file", reg_file
, _reg_file
, NULL
);
522 format (file
, "%d", _reg_nr
);
527 static int dest (FILE *file
, struct brw_instruction
*inst
)
531 if (inst
->header
.access_mode
== BRW_ALIGN_1
)
533 if (inst
->bits1
.da1
.dest_address_mode
== BRW_ADDRESS_DIRECT
)
535 err
|= reg (file
, inst
->bits1
.da1
.dest_reg_file
, inst
->bits1
.da1
.dest_reg_nr
);
538 if (inst
->bits1
.da1
.dest_subreg_nr
)
539 format (file
, ".%d", inst
->bits1
.da1
.dest_subreg_nr
/
540 reg_type_size
[inst
->bits1
.da1
.dest_reg_type
]);
541 format (file
, "<%d>", inst
->bits1
.da1
.dest_horiz_stride
);
542 err
|= control (file
, "dest reg encoding", reg_encoding
, inst
->bits1
.da1
.dest_reg_type
, NULL
);
546 string (file
, "g[a0");
547 if (inst
->bits1
.ia1
.dest_subreg_nr
)
548 format (file
, ".%d", inst
->bits1
.ia1
.dest_subreg_nr
/
549 reg_type_size
[inst
->bits1
.ia1
.dest_reg_type
]);
550 if (inst
->bits1
.ia1
.dest_indirect_offset
)
551 format (file
, " %d", inst
->bits1
.ia1
.dest_indirect_offset
);
553 format (file
, "<%d>", inst
->bits1
.ia1
.dest_horiz_stride
);
554 err
|= control (file
, "dest reg encoding", reg_encoding
, inst
->bits1
.ia1
.dest_reg_type
, NULL
);
559 if (inst
->bits1
.da16
.dest_address_mode
== BRW_ADDRESS_DIRECT
)
561 err
|= reg (file
, inst
->bits1
.da16
.dest_reg_file
, inst
->bits1
.da16
.dest_reg_nr
);
564 if (inst
->bits1
.da16
.dest_subreg_nr
)
565 format (file
, ".%d", inst
->bits1
.da16
.dest_subreg_nr
/
566 reg_type_size
[inst
->bits1
.da16
.dest_reg_type
]);
567 string (file
, "<1>");
568 err
|= control (file
, "writemask", writemask
, inst
->bits1
.da16
.dest_writemask
, NULL
);
569 err
|= control (file
, "dest reg encoding", reg_encoding
, inst
->bits1
.da16
.dest_reg_type
, NULL
);
574 string (file
, "Indirect align16 address mode not supported");
581 static int src_align1_region (FILE *file
,
582 GLuint _vert_stride
, GLuint _width
, GLuint _horiz_stride
)
586 err
|= control (file
, "vert stride", vert_stride
, _vert_stride
, NULL
);
588 err
|= control (file
, "width", width
, _width
, NULL
);
590 err
|= control (file
, "horiz_stride", horiz_stride
, _horiz_stride
, NULL
);
595 static int src_da1 (FILE *file
, GLuint type
, GLuint _reg_file
,
596 GLuint _vert_stride
, GLuint _width
, GLuint _horiz_stride
,
597 GLuint reg_num
, GLuint sub_reg_num
, GLuint __abs
, GLuint _negate
)
600 err
|= control (file
, "negate", negate
, _negate
, NULL
);
601 err
|= control (file
, "abs", _abs
, __abs
, NULL
);
603 err
|= reg (file
, _reg_file
, reg_num
);
607 format (file
, ".%d", sub_reg_num
/ reg_type_size
[type
]); /* use formal style like spec */
608 src_align1_region (file
, _vert_stride
, _width
, _horiz_stride
);
609 err
|= control (file
, "src reg encoding", reg_encoding
, type
, NULL
);
613 static int src_ia1 (FILE *file
,
617 GLuint _addr_subreg_nr
,
621 GLuint _horiz_stride
,
626 err
|= control (file
, "negate", negate
, _negate
, NULL
);
627 err
|= control (file
, "abs", _abs
, __abs
, NULL
);
629 string (file
, "g[a0");
631 format (file
, ".%d", _addr_subreg_nr
);
633 format (file
, " %d", _addr_imm
);
635 src_align1_region (file
, _vert_stride
, _width
, _horiz_stride
);
636 err
|= control (file
, "src reg encoding", reg_encoding
, type
, NULL
);
640 static int src_da16 (FILE *file
,
654 err
|= control (file
, "negate", negate
, _negate
, NULL
);
655 err
|= control (file
, "abs", _abs
, __abs
, NULL
);
657 err
|= reg (file
, _reg_file
, _reg_nr
);
661 /* bit4 for subreg number byte addressing. Make this same meaning as
662 in da1 case, so output looks consistent. */
663 format (file
, ".%d", 16 / reg_type_size
[_reg_type
]);
665 err
|= control (file
, "vert stride", vert_stride
, _vert_stride
, NULL
);
666 string (file
, ",4,1>");
668 * Three kinds of swizzle display:
669 * identity - nothing printed
670 * 1->all - print the single channel
671 * 1->1 - print the mapping
673 if (swz_x
== BRW_CHANNEL_X
&&
674 swz_y
== BRW_CHANNEL_Y
&&
675 swz_z
== BRW_CHANNEL_Z
&&
676 swz_w
== BRW_CHANNEL_W
)
680 else if (swz_x
== swz_y
&& swz_x
== swz_z
&& swz_x
== swz_w
)
683 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
688 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
689 err
|= control (file
, "channel select", chan_sel
, swz_y
, NULL
);
690 err
|= control (file
, "channel select", chan_sel
, swz_z
, NULL
);
691 err
|= control (file
, "channel select", chan_sel
, swz_w
, NULL
);
693 err
|= control (file
, "src da16 reg type", reg_encoding
, _reg_type
, NULL
);
698 static int imm (FILE *file
, GLuint type
, struct brw_instruction
*inst
) {
700 case BRW_REGISTER_TYPE_UD
:
701 format (file
, "0x%08xUD", inst
->bits3
.ud
);
703 case BRW_REGISTER_TYPE_D
:
704 format (file
, "%dD", inst
->bits3
.d
);
706 case BRW_REGISTER_TYPE_UW
:
707 format (file
, "0x%04xUW", (uint16_t) inst
->bits3
.ud
);
709 case BRW_REGISTER_TYPE_W
:
710 format (file
, "%dW", (int16_t) inst
->bits3
.d
);
712 case BRW_REGISTER_TYPE_UB
:
713 format (file
, "0x%02xUB", (int8_t) inst
->bits3
.ud
);
715 case BRW_REGISTER_TYPE_VF
:
716 format (file
, "Vector Float");
718 case BRW_REGISTER_TYPE_V
:
719 format (file
, "0x%08xV", inst
->bits3
.ud
);
721 case BRW_REGISTER_TYPE_F
:
722 format (file
, "%-gF", inst
->bits3
.f
);
727 static int src0 (FILE *file
, struct brw_instruction
*inst
)
729 if (inst
->bits1
.da1
.src0_reg_file
== BRW_IMMEDIATE_VALUE
)
730 return imm (file
, inst
->bits1
.da1
.src0_reg_type
,
732 else if (inst
->header
.access_mode
== BRW_ALIGN_1
)
734 if (inst
->bits2
.da1
.src0_address_mode
== BRW_ADDRESS_DIRECT
)
736 return src_da1 (file
,
737 inst
->bits1
.da1
.src0_reg_type
,
738 inst
->bits1
.da1
.src0_reg_file
,
739 inst
->bits2
.da1
.src0_vert_stride
,
740 inst
->bits2
.da1
.src0_width
,
741 inst
->bits2
.da1
.src0_horiz_stride
,
742 inst
->bits2
.da1
.src0_reg_nr
,
743 inst
->bits2
.da1
.src0_subreg_nr
,
744 inst
->bits2
.da1
.src0_abs
,
745 inst
->bits2
.da1
.src0_negate
);
749 return src_ia1 (file
,
750 inst
->bits1
.ia1
.src0_reg_type
,
751 inst
->bits1
.ia1
.src0_reg_file
,
752 inst
->bits2
.ia1
.src0_indirect_offset
,
753 inst
->bits2
.ia1
.src0_subreg_nr
,
754 inst
->bits2
.ia1
.src0_negate
,
755 inst
->bits2
.ia1
.src0_abs
,
756 inst
->bits2
.ia1
.src0_address_mode
,
757 inst
->bits2
.ia1
.src0_horiz_stride
,
758 inst
->bits2
.ia1
.src0_width
,
759 inst
->bits2
.ia1
.src0_vert_stride
);
764 if (inst
->bits2
.da16
.src0_address_mode
== BRW_ADDRESS_DIRECT
)
766 return src_da16 (file
,
767 inst
->bits1
.da16
.src0_reg_type
,
768 inst
->bits1
.da16
.src0_reg_file
,
769 inst
->bits2
.da16
.src0_vert_stride
,
770 inst
->bits2
.da16
.src0_reg_nr
,
771 inst
->bits2
.da16
.src0_subreg_nr
,
772 inst
->bits2
.da16
.src0_abs
,
773 inst
->bits2
.da16
.src0_negate
,
774 inst
->bits2
.da16
.src0_swz_x
,
775 inst
->bits2
.da16
.src0_swz_y
,
776 inst
->bits2
.da16
.src0_swz_z
,
777 inst
->bits2
.da16
.src0_swz_w
);
781 string (file
, "Indirect align16 address mode not supported");
787 static int src1 (FILE *file
, struct brw_instruction
*inst
)
789 if (inst
->bits1
.da1
.src1_reg_file
== BRW_IMMEDIATE_VALUE
)
790 return imm (file
, inst
->bits1
.da1
.src1_reg_type
,
792 else if (inst
->header
.access_mode
== BRW_ALIGN_1
)
794 if (inst
->bits3
.da1
.src1_address_mode
== BRW_ADDRESS_DIRECT
)
796 return src_da1 (file
,
797 inst
->bits1
.da1
.src1_reg_type
,
798 inst
->bits1
.da1
.src1_reg_file
,
799 inst
->bits3
.da1
.src1_vert_stride
,
800 inst
->bits3
.da1
.src1_width
,
801 inst
->bits3
.da1
.src1_horiz_stride
,
802 inst
->bits3
.da1
.src1_reg_nr
,
803 inst
->bits3
.da1
.src1_subreg_nr
,
804 inst
->bits3
.da1
.src1_abs
,
805 inst
->bits3
.da1
.src1_negate
);
809 return src_ia1 (file
,
810 inst
->bits1
.ia1
.src1_reg_type
,
811 inst
->bits1
.ia1
.src1_reg_file
,
812 inst
->bits3
.ia1
.src1_indirect_offset
,
813 inst
->bits3
.ia1
.src1_subreg_nr
,
814 inst
->bits3
.ia1
.src1_negate
,
815 inst
->bits3
.ia1
.src1_abs
,
816 inst
->bits3
.ia1
.src1_address_mode
,
817 inst
->bits3
.ia1
.src1_horiz_stride
,
818 inst
->bits3
.ia1
.src1_width
,
819 inst
->bits3
.ia1
.src1_vert_stride
);
824 if (inst
->bits3
.da16
.src1_address_mode
== BRW_ADDRESS_DIRECT
)
826 return src_da16 (file
,
827 inst
->bits1
.da16
.src1_reg_type
,
828 inst
->bits1
.da16
.src1_reg_file
,
829 inst
->bits3
.da16
.src1_vert_stride
,
830 inst
->bits3
.da16
.src1_reg_nr
,
831 inst
->bits3
.da16
.src1_subreg_nr
,
832 inst
->bits3
.da16
.src1_abs
,
833 inst
->bits3
.da16
.src1_negate
,
834 inst
->bits3
.da16
.src1_swz_x
,
835 inst
->bits3
.da16
.src1_swz_y
,
836 inst
->bits3
.da16
.src1_swz_z
,
837 inst
->bits3
.da16
.src1_swz_w
);
841 string (file
, "Indirect align16 address mode not supported");
856 static int qtr_ctrl(FILE *file
, struct brw_instruction
*inst
)
858 int qtr_ctl
= inst
->header
.compression_control
;
859 int exec_size
= esize
[inst
->header
.execution_size
];
861 if (exec_size
== 8) {
864 string (file
, " 1Q");
867 string (file
, " 2Q");
870 string (file
, " 3Q");
873 string (file
, " 4Q");
876 } else if (exec_size
== 16){
878 string (file
, " 1H");
880 string (file
, " 2H");
885 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
)
890 if (inst
->header
.predicate_control
) {
892 err
|= control (file
, "predicate inverse", pred_inv
, inst
->header
.predicate_inverse
, NULL
);
894 if (inst
->bits2
.da1
.flag_reg_nr
)
895 format (file
, ".%d", inst
->bits2
.da1
.flag_reg_nr
);
896 if (inst
->header
.access_mode
== BRW_ALIGN_1
)
897 err
|= control (file
, "predicate control align1", pred_ctrl_align1
,
898 inst
->header
.predicate_control
, NULL
);
900 err
|= control (file
, "predicate control align16", pred_ctrl_align16
,
901 inst
->header
.predicate_control
, NULL
);
905 err
|= print_opcode (file
, inst
->header
.opcode
);
906 err
|= control (file
, "saturate", saturate
, inst
->header
.saturate
, NULL
);
907 err
|= control (file
, "debug control", debug_ctrl
, inst
->header
.debug_control
, NULL
);
909 if (inst
->header
.opcode
== BRW_OPCODE_MATH
) {
911 err
|= control (file
, "function", math_function
,
912 inst
->header
.destreg__conditionalmod
, NULL
);
913 } else if (inst
->header
.opcode
!= BRW_OPCODE_SEND
&&
914 inst
->header
.opcode
!= BRW_OPCODE_SENDC
)
915 err
|= control (file
, "conditional modifier", conditional_modifier
,
916 inst
->header
.destreg__conditionalmod
, NULL
);
918 if (inst
->header
.opcode
!= BRW_OPCODE_NOP
) {
920 err
|= control (file
, "execution size", exec_size
, inst
->header
.execution_size
, NULL
);
924 if (inst
->header
.opcode
== BRW_OPCODE_SEND
&& gen
< 6)
925 format (file
, " %d", inst
->header
.destreg__conditionalmod
);
927 if (opcode
[inst
->header
.opcode
].ndst
> 0) {
929 err
|= dest (file
, inst
);
930 } else if (gen
>= 6 && (inst
->header
.opcode
== BRW_OPCODE_IF
||
931 inst
->header
.opcode
== BRW_OPCODE_ELSE
||
932 inst
->header
.opcode
== BRW_OPCODE_ENDIF
||
933 inst
->header
.opcode
== BRW_OPCODE_WHILE
)) {
934 format (file
, " %d", inst
->bits1
.branch_gen6
.jump_count
);
937 if (opcode
[inst
->header
.opcode
].nsrc
> 0) {
939 err
|= src0 (file
, inst
);
941 if (opcode
[inst
->header
.opcode
].nsrc
> 1) {
943 err
|= src1 (file
, inst
);
946 if (inst
->header
.opcode
== BRW_OPCODE_SEND
||
947 inst
->header
.opcode
== BRW_OPCODE_SENDC
) {
948 enum brw_message_target target
;
951 target
= inst
->header
.destreg__conditionalmod
;
953 target
= inst
->bits2
.send_gen5
.sfid
;
955 target
= inst
->bits3
.generic
.msg_target
;
962 err
|= control (file
, "target function", target_function_gen6
,
965 err
|= control (file
, "target function", target_function
,
971 err
|= control (file
, "math function", math_function
,
972 inst
->bits3
.math
.function
, &space
);
973 err
|= control (file
, "math saturate", math_saturate
,
974 inst
->bits3
.math
.saturate
, &space
);
975 err
|= control (file
, "math signed", math_signed
,
976 inst
->bits3
.math
.int_type
, &space
);
977 err
|= control (file
, "math scalar", math_scalar
,
978 inst
->bits3
.math
.data_type
, &space
);
979 err
|= control (file
, "math precision", math_precision
,
980 inst
->bits3
.math
.precision
, &space
);
982 case BRW_SFID_SAMPLER
:
984 format (file
, " (%d, %d, %d, %d)",
985 inst
->bits3
.sampler_gen5
.binding_table_index
,
986 inst
->bits3
.sampler_gen5
.sampler
,
987 inst
->bits3
.sampler_gen5
.msg_type
,
988 inst
->bits3
.sampler_gen5
.simd_mode
);
989 } else if (0 /* FINISHME: is_g4x */) {
990 format (file
, " (%d, %d)",
991 inst
->bits3
.sampler_g4x
.binding_table_index
,
992 inst
->bits3
.sampler_g4x
.sampler
);
994 format (file
, " (%d, %d, ",
995 inst
->bits3
.sampler
.binding_table_index
,
996 inst
->bits3
.sampler
.sampler
);
997 err
|= control (file
, "sampler target format",
998 sampler_target_format
,
999 inst
->bits3
.sampler
.return_format
, NULL
);
1003 case BRW_SFID_DATAPORT_READ
:
1005 format (file
, " (%d, %d, %d, %d)",
1006 inst
->bits3
.gen6_dp
.binding_table_index
,
1007 inst
->bits3
.gen6_dp
.msg_control
,
1008 inst
->bits3
.gen6_dp
.msg_type
,
1009 inst
->bits3
.gen6_dp
.send_commit_msg
);
1010 } else if (gen
>= 5 /* FINISHME: || is_g4x */) {
1011 format (file
, " (%d, %d, %d)",
1012 inst
->bits3
.dp_read_gen5
.binding_table_index
,
1013 inst
->bits3
.dp_read_gen5
.msg_control
,
1014 inst
->bits3
.dp_read_gen5
.msg_type
);
1016 format (file
, " (%d, %d, %d)",
1017 inst
->bits3
.dp_read
.binding_table_index
,
1018 inst
->bits3
.dp_read
.msg_control
,
1019 inst
->bits3
.dp_read
.msg_type
);
1023 case BRW_SFID_DATAPORT_WRITE
:
1025 format (file
, " (");
1027 err
|= control (file
, "DP rc message type",
1028 dp_rc_msg_type_gen6
,
1029 inst
->bits3
.gen6_dp
.msg_type
, &space
);
1031 format (file
, ", %d, %d, %d, %d)",
1032 inst
->bits3
.gen6_dp
.binding_table_index
,
1033 inst
->bits3
.gen6_dp
.msg_control
,
1034 inst
->bits3
.gen6_dp
.msg_type
,
1035 inst
->bits3
.gen6_dp
.send_commit_msg
);
1037 format (file
, " (%d, %d, %d, %d)",
1038 inst
->bits3
.dp_write
.binding_table_index
,
1039 (inst
->bits3
.dp_write
.last_render_target
<< 3) |
1040 inst
->bits3
.dp_write
.msg_control
,
1041 inst
->bits3
.dp_write
.msg_type
,
1042 inst
->bits3
.dp_write
.send_commit_msg
);
1048 format (file
, " %d", inst
->bits3
.urb_gen5
.offset
);
1050 format (file
, " %d", inst
->bits3
.urb
.offset
);
1055 err
|= control (file
, "urb opcode", urb_opcode
,
1056 inst
->bits3
.urb_gen5
.opcode
, &space
);
1058 err
|= control (file
, "urb swizzle", urb_swizzle
,
1059 inst
->bits3
.urb
.swizzle_control
, &space
);
1060 err
|= control (file
, "urb allocate", urb_allocate
,
1061 inst
->bits3
.urb
.allocate
, &space
);
1062 err
|= control (file
, "urb used", urb_used
,
1063 inst
->bits3
.urb
.used
, &space
);
1064 err
|= control (file
, "urb complete", urb_complete
,
1065 inst
->bits3
.urb
.complete
, &space
);
1067 case BRW_SFID_THREAD_SPAWNER
:
1069 case GEN7_SFID_DATAPORT_DATA_CACHE
:
1070 format (file
, " (%d, %d, %d)",
1071 inst
->bits3
.gen7_dp
.binding_table_index
,
1072 inst
->bits3
.gen7_dp
.msg_control
,
1073 inst
->bits3
.gen7_dp
.msg_type
);
1078 format (file
, "unsupported target %d", target
);
1084 format (file
, "mlen %d",
1085 inst
->bits3
.generic_gen5
.msg_length
);
1086 format (file
, " rlen %d",
1087 inst
->bits3
.generic_gen5
.response_length
);
1089 format (file
, "mlen %d",
1090 inst
->bits3
.generic
.msg_length
);
1091 format (file
, " rlen %d",
1092 inst
->bits3
.generic
.response_length
);
1096 if (inst
->header
.opcode
!= BRW_OPCODE_NOP
) {
1099 err
|= control(file
, "access mode", access_mode
, inst
->header
.access_mode
, &space
);
1101 err
|= control (file
, "write enable control", wectrl
, inst
->header
.mask_control
, &space
);
1103 err
|= control (file
, "mask control", mask_ctrl
, inst
->header
.mask_control
, &space
);
1104 err
|= control (file
, "dependency control", dep_ctrl
, inst
->header
.dependency_control
, &space
);
1107 err
|= qtr_ctrl (file
, inst
);
1109 if (inst
->header
.compression_control
== BRW_COMPRESSION_COMPRESSED
&&
1110 opcode
[inst
->header
.opcode
].ndst
> 0 &&
1111 inst
->bits1
.da1
.dest_reg_file
== BRW_MESSAGE_REGISTER_FILE
&&
1112 inst
->bits1
.da1
.dest_reg_nr
& (1 << 7)) {
1113 format (file
, " compr4");
1115 err
|= control (file
, "compression control", compr_ctrl
,
1116 inst
->header
.compression_control
, &space
);
1120 err
|= control (file
, "thread control", thread_ctrl
, inst
->header
.thread_control
, &space
);
1122 err
|= control (file
, "acc write control", accwr
, inst
->header
.acc_wr_control
, &space
);
1123 if (inst
->header
.opcode
== BRW_OPCODE_SEND
||
1124 inst
->header
.opcode
== BRW_OPCODE_SENDC
)
1125 err
|= control (file
, "end of thread", end_of_thread
,
1126 inst
->bits3
.generic
.end_of_thread
, &space
);