2 * Copyright © 2008 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
30 #include "brw_context.h"
31 #include "brw_defines.h"
35 const struct opcode_desc opcode_descs
[128] = {
36 [BRW_OPCODE_MOV
] = { .name
= "mov", .nsrc
= 1, .ndst
= 1 },
37 [BRW_OPCODE_FRC
] = { .name
= "frc", .nsrc
= 1, .ndst
= 1 },
38 [BRW_OPCODE_RNDU
] = { .name
= "rndu", .nsrc
= 1, .ndst
= 1 },
39 [BRW_OPCODE_RNDD
] = { .name
= "rndd", .nsrc
= 1, .ndst
= 1 },
40 [BRW_OPCODE_RNDE
] = { .name
= "rnde", .nsrc
= 1, .ndst
= 1 },
41 [BRW_OPCODE_RNDZ
] = { .name
= "rndz", .nsrc
= 1, .ndst
= 1 },
42 [BRW_OPCODE_NOT
] = { .name
= "not", .nsrc
= 1, .ndst
= 1 },
43 [BRW_OPCODE_LZD
] = { .name
= "lzd", .nsrc
= 1, .ndst
= 1 },
44 [BRW_OPCODE_F32TO16
] = { .name
= "f32to16", .nsrc
= 1, .ndst
= 1 },
45 [BRW_OPCODE_F16TO32
] = { .name
= "f16to32", .nsrc
= 1, .ndst
= 1 },
46 [BRW_OPCODE_BFREV
] = { .name
= "bfrev", .nsrc
= 1, .ndst
= 1 },
47 [BRW_OPCODE_FBH
] = { .name
= "fbh", .nsrc
= 1, .ndst
= 1 },
48 [BRW_OPCODE_FBL
] = { .name
= "fbl", .nsrc
= 1, .ndst
= 1 },
49 [BRW_OPCODE_CBIT
] = { .name
= "cbit", .nsrc
= 1, .ndst
= 1 },
51 [BRW_OPCODE_MUL
] = { .name
= "mul", .nsrc
= 2, .ndst
= 1 },
52 [BRW_OPCODE_MAC
] = { .name
= "mac", .nsrc
= 2, .ndst
= 1 },
53 [BRW_OPCODE_MACH
] = { .name
= "mach", .nsrc
= 2, .ndst
= 1 },
54 [BRW_OPCODE_LINE
] = { .name
= "line", .nsrc
= 2, .ndst
= 1 },
55 [BRW_OPCODE_PLN
] = { .name
= "pln", .nsrc
= 2, .ndst
= 1 },
56 [BRW_OPCODE_MAD
] = { .name
= "mad", .nsrc
= 3, .ndst
= 1 },
57 [BRW_OPCODE_LRP
] = { .name
= "lrp", .nsrc
= 3, .ndst
= 1 },
58 [BRW_OPCODE_SAD2
] = { .name
= "sad2", .nsrc
= 2, .ndst
= 1 },
59 [BRW_OPCODE_SADA2
] = { .name
= "sada2", .nsrc
= 2, .ndst
= 1 },
60 [BRW_OPCODE_DP4
] = { .name
= "dp4", .nsrc
= 2, .ndst
= 1 },
61 [BRW_OPCODE_DPH
] = { .name
= "dph", .nsrc
= 2, .ndst
= 1 },
62 [BRW_OPCODE_DP3
] = { .name
= "dp3", .nsrc
= 2, .ndst
= 1 },
63 [BRW_OPCODE_DP2
] = { .name
= "dp2", .nsrc
= 2, .ndst
= 1 },
64 [BRW_OPCODE_MATH
] = { .name
= "math", .nsrc
= 2, .ndst
= 1 },
66 [BRW_OPCODE_AVG
] = { .name
= "avg", .nsrc
= 2, .ndst
= 1 },
67 [BRW_OPCODE_ADD
] = { .name
= "add", .nsrc
= 2, .ndst
= 1 },
68 [BRW_OPCODE_SEL
] = { .name
= "sel", .nsrc
= 2, .ndst
= 1 },
69 [BRW_OPCODE_AND
] = { .name
= "and", .nsrc
= 2, .ndst
= 1 },
70 [BRW_OPCODE_OR
] = { .name
= "or", .nsrc
= 2, .ndst
= 1 },
71 [BRW_OPCODE_XOR
] = { .name
= "xor", .nsrc
= 2, .ndst
= 1 },
72 [BRW_OPCODE_SHR
] = { .name
= "shr", .nsrc
= 2, .ndst
= 1 },
73 [BRW_OPCODE_SHL
] = { .name
= "shl", .nsrc
= 2, .ndst
= 1 },
74 [BRW_OPCODE_ASR
] = { .name
= "asr", .nsrc
= 2, .ndst
= 1 },
75 [BRW_OPCODE_CMP
] = { .name
= "cmp", .nsrc
= 2, .ndst
= 1 },
76 [BRW_OPCODE_CMPN
] = { .name
= "cmpn", .nsrc
= 2, .ndst
= 1 },
77 [BRW_OPCODE_CSEL
] = { .name
= "csel", .nsrc
= 3, .ndst
= 1 },
78 [BRW_OPCODE_BFE
] = { .name
= "bfe", .nsrc
= 3, .ndst
= 1 },
79 [BRW_OPCODE_BFI1
] = { .name
= "bfi1", .nsrc
= 2, .ndst
= 1 },
80 [BRW_OPCODE_BFI2
] = { .name
= "bfi2", .nsrc
= 3, .ndst
= 1 },
81 [BRW_OPCODE_ADDC
] = { .name
= "addc", .nsrc
= 2, .ndst
= 1 },
82 [BRW_OPCODE_SUBB
] = { .name
= "subb", .nsrc
= 2, .ndst
= 1 },
84 [BRW_OPCODE_SEND
] = { .name
= "send", .nsrc
= 1, .ndst
= 1 },
85 [BRW_OPCODE_SENDC
] = { .name
= "sendc", .nsrc
= 1, .ndst
= 1 },
86 [BRW_OPCODE_NOP
] = { .name
= "nop", .nsrc
= 0, .ndst
= 0 },
87 [BRW_OPCODE_JMPI
] = { .name
= "jmpi", .nsrc
= 0, .ndst
= 0 },
88 [BRW_OPCODE_IF
] = { .name
= "if", .nsrc
= 2, .ndst
= 0 },
89 [BRW_OPCODE_IFF
] = { .name
= "iff", .nsrc
= 2, .ndst
= 1 },
90 [BRW_OPCODE_WHILE
] = { .name
= "while", .nsrc
= 2, .ndst
= 0 },
91 [BRW_OPCODE_ELSE
] = { .name
= "else", .nsrc
= 2, .ndst
= 0 },
92 [BRW_OPCODE_BREAK
] = { .name
= "break", .nsrc
= 2, .ndst
= 0 },
93 [BRW_OPCODE_CONTINUE
] = { .name
= "cont", .nsrc
= 1, .ndst
= 0 },
94 [BRW_OPCODE_HALT
] = { .name
= "halt", .nsrc
= 1, .ndst
= 0 },
95 [BRW_OPCODE_MSAVE
] = { .name
= "msave", .nsrc
= 1, .ndst
= 1 },
96 [BRW_OPCODE_PUSH
] = { .name
= "push", .nsrc
= 1, .ndst
= 1 },
97 [BRW_OPCODE_MRESTORE
] = { .name
= "mrest", .nsrc
= 1, .ndst
= 1 },
98 [BRW_OPCODE_POP
] = { .name
= "pop", .nsrc
= 2, .ndst
= 0 },
99 [BRW_OPCODE_WAIT
] = { .name
= "wait", .nsrc
= 1, .ndst
= 0 },
100 [BRW_OPCODE_DO
] = { .name
= "do", .nsrc
= 0, .ndst
= 0 },
101 [BRW_OPCODE_ENDIF
] = { .name
= "endif", .nsrc
= 2, .ndst
= 0 },
105 has_jip(struct brw_context
*brw
, enum opcode opcode
)
110 return opcode
== BRW_OPCODE_IF
||
111 opcode
== BRW_OPCODE_ELSE
||
112 opcode
== BRW_OPCODE_ENDIF
||
113 opcode
== BRW_OPCODE_WHILE
||
114 opcode
== BRW_OPCODE_BREAK
||
115 opcode
== BRW_OPCODE_CONTINUE
||
116 opcode
== BRW_OPCODE_HALT
;
120 has_uip(struct brw_context
*brw
, enum opcode opcode
)
125 return (brw
->gen
>= 7 && opcode
== BRW_OPCODE_IF
) ||
126 (brw
->gen
>= 8 && opcode
== BRW_OPCODE_ELSE
) ||
127 opcode
== BRW_OPCODE_BREAK
||
128 opcode
== BRW_OPCODE_CONTINUE
||
129 opcode
== BRW_OPCODE_HALT
;
133 is_logic_instruction(unsigned opcode
)
135 return opcode
== BRW_OPCODE_AND
||
136 opcode
== BRW_OPCODE_NOT
||
137 opcode
== BRW_OPCODE_OR
||
138 opcode
== BRW_OPCODE_XOR
;
141 const char *const conditional_modifier
[16] = {
142 [BRW_CONDITIONAL_NONE
] = "",
143 [BRW_CONDITIONAL_Z
] = ".z",
144 [BRW_CONDITIONAL_NZ
] = ".nz",
145 [BRW_CONDITIONAL_G
] = ".g",
146 [BRW_CONDITIONAL_GE
] = ".ge",
147 [BRW_CONDITIONAL_L
] = ".l",
148 [BRW_CONDITIONAL_LE
] = ".le",
149 [BRW_CONDITIONAL_R
] = ".r",
150 [BRW_CONDITIONAL_O
] = ".o",
151 [BRW_CONDITIONAL_U
] = ".u",
154 static const char *const m_negate
[2] = {
159 static const char *const _abs
[2] = {
164 static const char *const m_bitnot
[2] = { "", "~" };
166 static const char *const vert_stride
[16] = {
177 static const char *const width
[8] = {
185 static const char *const horiz_stride
[4] = {
192 static const char *const chan_sel
[4] = {
199 static const char *const debug_ctrl
[2] = {
204 static const char *const saturate
[2] = {
209 static const char *const cmpt_ctrl
[2] = {
214 static const char *const accwr
[2] = {
219 static const char *const wectrl
[2] = {
224 static const char *const exec_size
[8] = {
233 static const char *const pred_inv
[2] = {
238 static const char *const pred_ctrl_align16
[16] = {
248 static const char *const pred_ctrl_align1
[16] = {
249 [BRW_PREDICATE_NORMAL
] = "",
250 [BRW_PREDICATE_ALIGN1_ANYV
] = ".anyv",
251 [BRW_PREDICATE_ALIGN1_ALLV
] = ".allv",
252 [BRW_PREDICATE_ALIGN1_ANY2H
] = ".any2h",
253 [BRW_PREDICATE_ALIGN1_ALL2H
] = ".all2h",
254 [BRW_PREDICATE_ALIGN1_ANY4H
] = ".any4h",
255 [BRW_PREDICATE_ALIGN1_ALL4H
] = ".all4h",
256 [BRW_PREDICATE_ALIGN1_ANY8H
] = ".any8h",
257 [BRW_PREDICATE_ALIGN1_ALL8H
] = ".all8h",
258 [BRW_PREDICATE_ALIGN1_ANY16H
] = ".any16h",
259 [BRW_PREDICATE_ALIGN1_ALL16H
] = ".all16h",
260 [BRW_PREDICATE_ALIGN1_ANY32H
] = ".any32h",
261 [BRW_PREDICATE_ALIGN1_ANY32H
] = ".all32h",
264 static const char *const thread_ctrl
[4] = {
265 [BRW_THREAD_NORMAL
] = "",
266 [BRW_THREAD_ATOMIC
] = "atomic",
267 [BRW_THREAD_SWITCH
] = "switch",
270 static const char *const compr_ctrl
[4] = {
277 static const char *const dep_ctrl
[4] = {
281 [3] = "NoDDClr,NoDDChk",
284 static const char *const mask_ctrl
[4] = {
289 static const char *const access_mode
[2] = {
294 static const char * const reg_encoding
[] = {
295 [BRW_HW_REG_TYPE_UD
] = "UD",
296 [BRW_HW_REG_TYPE_D
] = "D",
297 [BRW_HW_REG_TYPE_UW
] = "UW",
298 [BRW_HW_REG_TYPE_W
] = "W",
299 [BRW_HW_REG_NON_IMM_TYPE_UB
] = "UB",
300 [BRW_HW_REG_NON_IMM_TYPE_B
] = "B",
301 [GEN7_HW_REG_NON_IMM_TYPE_DF
] = "DF",
302 [BRW_HW_REG_TYPE_F
] = "F",
303 [GEN8_HW_REG_TYPE_UQ
] = "UQ",
304 [GEN8_HW_REG_TYPE_Q
] = "Q",
305 [GEN8_HW_REG_NON_IMM_TYPE_HF
] = "HF",
308 static const char *const three_source_reg_encoding
[] = {
309 [BRW_3SRC_TYPE_F
] = "F",
310 [BRW_3SRC_TYPE_D
] = "D",
311 [BRW_3SRC_TYPE_UD
] = "UD",
314 const int reg_type_size
[] = {
315 [BRW_HW_REG_TYPE_UD
] = 4,
316 [BRW_HW_REG_TYPE_D
] = 4,
317 [BRW_HW_REG_TYPE_UW
] = 2,
318 [BRW_HW_REG_TYPE_W
] = 2,
319 [BRW_HW_REG_NON_IMM_TYPE_UB
] = 1,
320 [BRW_HW_REG_NON_IMM_TYPE_B
] = 1,
321 [GEN7_HW_REG_NON_IMM_TYPE_DF
] = 8,
322 [BRW_HW_REG_TYPE_F
] = 4,
323 [GEN8_HW_REG_TYPE_UQ
] = 8,
324 [GEN8_HW_REG_TYPE_Q
] = 8,
325 [GEN8_HW_REG_NON_IMM_TYPE_HF
] = 2,
328 static const char *const reg_file
[4] = {
335 static const char *const writemask
[16] = {
354 static const char *const end_of_thread
[2] = {
359 /* SFIDs on Gen4-5 */
360 static const char *const gen4_sfid
[16] = {
361 [BRW_SFID_NULL
] = "null",
362 [BRW_SFID_MATH
] = "math",
363 [BRW_SFID_SAMPLER
] = "sampler",
364 [BRW_SFID_MESSAGE_GATEWAY
] = "gateway",
365 [BRW_SFID_DATAPORT_READ
] = "read",
366 [BRW_SFID_DATAPORT_WRITE
] = "write",
367 [BRW_SFID_URB
] = "urb",
368 [BRW_SFID_THREAD_SPAWNER
] = "thread_spawner",
369 [BRW_SFID_VME
] = "vme",
372 static const char *const gen6_sfid
[16] = {
373 [BRW_SFID_NULL
] = "null",
374 [BRW_SFID_MATH
] = "math",
375 [BRW_SFID_SAMPLER
] = "sampler",
376 [BRW_SFID_MESSAGE_GATEWAY
] = "gateway",
377 [BRW_SFID_URB
] = "urb",
378 [BRW_SFID_THREAD_SPAWNER
] = "thread_spawner",
379 [GEN6_SFID_DATAPORT_SAMPLER_CACHE
] = "sampler",
380 [GEN6_SFID_DATAPORT_RENDER_CACHE
] = "render",
381 [GEN6_SFID_DATAPORT_CONSTANT_CACHE
] = "const",
382 [GEN7_SFID_DATAPORT_DATA_CACHE
] = "data",
383 [GEN7_SFID_PIXEL_INTERPOLATOR
] = "pixel interp",
384 [HSW_SFID_DATAPORT_DATA_CACHE_1
] = "dp data 1",
385 [HSW_SFID_CRE
] = "cre",
388 static const char *const dp_write_port_msg_type
[8] = {
389 [0b000] = "OWord block write",
390 [0b001] = "OWord dual block write",
391 [0b010] = "media block write",
392 [0b011] = "DWord scattered write",
393 [0b100] = "RT write",
394 [0b101] = "streamed VB write",
395 [0b110] = "RT UNORM write", /* G45+ */
396 [0b111] = "flush render cache",
399 static const char *const dp_rc_msg_type_gen6
[16] = {
400 [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
] = "OWORD block read",
401 [GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ
] = "RT UNORM read",
402 [GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
] = "OWORD dual block read",
403 [GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ
] = "media block read",
404 [GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ
] =
405 "OWORD unaligned block read",
406 [GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
] = "DWORD scattered read",
407 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE
] = "DWORD atomic write",
408 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE
] = "OWORD block write",
409 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
] =
410 "OWORD dual block write",
411 [GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE
] = "media block write",
412 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE
] =
413 "DWORD scattered write",
414 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
] = "RT write",
415 [GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE
] = "streamed VB write",
416 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE
] = "RT UNORM write",
419 static const char *const m_rt_write_subtype
[] = {
421 [0b001] = "SIMD16/RepData",
422 [0b010] = "SIMD8/DualSrcLow",
423 [0b011] = "SIMD8/DualSrcHigh",
425 [0b101] = "SIMD8/ImageWrite", /* Gen6+ */
426 [0b111] = "SIMD16/RepData-111", /* no idea how this is different than 1 */
429 static const char *const dp_dc0_msg_type_gen7
[16] = {
430 [GEN7_DATAPORT_DC_OWORD_BLOCK_READ
] = "DC OWORD block read",
431 [GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ
] =
432 "DC unaligned OWORD block read",
433 [GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ
] = "DC OWORD dual block read",
434 [GEN7_DATAPORT_DC_DWORD_SCATTERED_READ
] = "DC DWORD scattered read",
435 [GEN7_DATAPORT_DC_BYTE_SCATTERED_READ
] = "DC byte scattered read",
436 [GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP
] = "DC untyped atomic",
437 [GEN7_DATAPORT_DC_MEMORY_FENCE
] = "DC mfence",
438 [GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE
] = "DC OWORD block write",
439 [GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE
] = "DC OWORD dual block write",
440 [GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE
] = "DC DWORD scatterd write",
441 [GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE
] = "DC byte scattered write",
442 [GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE
] = "DC untyped surface write",
445 static const char *const dp_dc1_msg_type_hsw
[16] = {
446 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ
] = "untyped surface read",
447 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP
] = "DC untyped atomic op",
448 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2
] =
449 "DC untyped 4x2 atomic op",
450 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ
] = "DC media block read",
451 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ
] = "DC typed surface read",
452 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP
] = "DC typed atomic",
453 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2
] = "DC typed 4x2 atomic op",
454 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE
] = "DC untyped surface write",
455 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE
] = "DC media block write",
456 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP
] = "DC atomic counter op",
457 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2
] =
458 "DC 4x2 atomic counter op",
459 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE
] = "DC typed surface write",
462 static const char *const aop
[16] = {
463 [BRW_AOP_AND
] = "and",
465 [BRW_AOP_XOR
] = "xor",
466 [BRW_AOP_MOV
] = "mov",
467 [BRW_AOP_INC
] = "inc",
468 [BRW_AOP_DEC
] = "dec",
469 [BRW_AOP_ADD
] = "add",
470 [BRW_AOP_SUB
] = "sub",
471 [BRW_AOP_REVSUB
] = "revsub",
472 [BRW_AOP_IMAX
] = "imax",
473 [BRW_AOP_IMIN
] = "imin",
474 [BRW_AOP_UMAX
] = "umax",
475 [BRW_AOP_UMIN
] = "umin",
476 [BRW_AOP_CMPWR
] = "cmpwr",
477 [BRW_AOP_PREDEC
] = "predec",
480 static const char * const pixel_interpolator_msg_types
[4] = {
481 [GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
] = "per_message_offset",
482 [GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
] = "sample_position",
483 [GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID
] = "centroid",
484 [GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
] = "per_slot_offset",
487 static const char *const math_function
[16] = {
488 [BRW_MATH_FUNCTION_INV
] = "inv",
489 [BRW_MATH_FUNCTION_LOG
] = "log",
490 [BRW_MATH_FUNCTION_EXP
] = "exp",
491 [BRW_MATH_FUNCTION_SQRT
] = "sqrt",
492 [BRW_MATH_FUNCTION_RSQ
] = "rsq",
493 [BRW_MATH_FUNCTION_SIN
] = "sin",
494 [BRW_MATH_FUNCTION_COS
] = "cos",
495 [BRW_MATH_FUNCTION_SINCOS
] = "sincos",
496 [BRW_MATH_FUNCTION_FDIV
] = "fdiv",
497 [BRW_MATH_FUNCTION_POW
] = "pow",
498 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
] = "intdivmod",
499 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
] = "intdiv",
500 [BRW_MATH_FUNCTION_INT_DIV_REMAINDER
] = "intmod",
501 [GEN8_MATH_FUNCTION_INVM
] = "invm",
502 [GEN8_MATH_FUNCTION_RSQRTM
] = "rsqrtm",
505 static const char *const math_saturate
[2] = {
510 static const char *const math_signed
[2] = {
515 static const char *const math_scalar
[2] = {
520 static const char *const math_precision
[2] = {
522 [1] = "partial_precision"
525 static const char *const gen5_urb_opcode
[] = {
530 static const char *const gen7_urb_opcode
[] = {
535 [4] = "atomic mov", /* Gen7+ */
536 [5] = "atomic inc", /* Gen7+ */
537 [6] = "atomic add", /* Gen8+ */
538 [7] = "SIMD8 write", /* Gen8+ */
539 [8] = "SIMD8 read", /* Gen8+ */
540 /* [9-15] - reserved */
543 static const char *const urb_swizzle
[4] = {
544 [BRW_URB_SWIZZLE_NONE
] = "",
545 [BRW_URB_SWIZZLE_INTERLEAVE
] = "interleave",
546 [BRW_URB_SWIZZLE_TRANSPOSE
] = "transpose",
549 static const char *const urb_allocate
[2] = {
554 static const char *const urb_used
[2] = {
559 static const char *const urb_complete
[2] = {
564 static const char *const sampler_target_format
[4] = {
574 string(FILE *file
, const char *string
)
577 column
+= strlen(string
);
582 format(FILE *f
, const char *format
, ...)
586 va_start(args
, format
);
588 vsnprintf(buf
, sizeof(buf
) - 1, format
, args
);
612 control(FILE *file
, const char *name
, const char *const ctrl
[],
613 unsigned id
, int *space
)
616 fprintf(file
, "*** invalid %s value %d ", name
, id
);
622 string(file
, ctrl
[id
]);
630 print_opcode(FILE *file
, int id
)
632 if (!opcode_descs
[id
].name
) {
633 format(file
, "*** invalid opcode value %d ", id
);
636 string(file
, opcode_descs
[id
].name
);
641 reg(FILE *file
, unsigned _reg_file
, unsigned _reg_nr
)
645 /* Clear the Compr4 instruction compression bit. */
646 if (_reg_file
== BRW_MESSAGE_REGISTER_FILE
)
647 _reg_nr
&= ~(1 << 7);
649 if (_reg_file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
650 switch (_reg_nr
& 0xf0) {
652 string(file
, "null");
654 case BRW_ARF_ADDRESS
:
655 format(file
, "a%d", _reg_nr
& 0x0f);
657 case BRW_ARF_ACCUMULATOR
:
658 format(file
, "acc%d", _reg_nr
& 0x0f);
661 format(file
, "f%d", _reg_nr
& 0x0f);
664 format(file
, "mask%d", _reg_nr
& 0x0f);
666 case BRW_ARF_MASK_STACK
:
667 format(file
, "msd%d", _reg_nr
& 0x0f);
670 format(file
, "sr%d", _reg_nr
& 0x0f);
672 case BRW_ARF_CONTROL
:
673 format(file
, "cr%d", _reg_nr
& 0x0f);
675 case BRW_ARF_NOTIFICATION_COUNT
:
676 format(file
, "n%d", _reg_nr
& 0x0f);
683 format(file
, "ARF%d", _reg_nr
);
687 err
|= control(file
, "src reg file", reg_file
, _reg_file
, NULL
);
688 format(file
, "%d", _reg_nr
);
694 dest(FILE *file
, struct brw_context
*brw
, brw_inst
*inst
)
698 if (brw_inst_access_mode(brw
, inst
) == BRW_ALIGN_1
) {
699 if (brw_inst_dst_address_mode(brw
, inst
) == BRW_ADDRESS_DIRECT
) {
700 err
|= reg(file
, brw_inst_dst_reg_file(brw
, inst
),
701 brw_inst_dst_da_reg_nr(brw
, inst
));
704 if (brw_inst_dst_da1_subreg_nr(brw
, inst
))
705 format(file
, ".%d", brw_inst_dst_da1_subreg_nr(brw
, inst
) /
706 reg_type_size
[brw_inst_dst_reg_type(brw
, inst
)]);
708 err
|= control(file
, "horiz stride", horiz_stride
,
709 brw_inst_dst_hstride(brw
, inst
), NULL
);
711 err
|= control(file
, "dest reg encoding", reg_encoding
,
712 brw_inst_dst_reg_type(brw
, inst
), NULL
);
714 string(file
, "g[a0");
715 if (brw_inst_dst_ia_subreg_nr(brw
, inst
))
716 format(file
, ".%d", brw_inst_dst_ia_subreg_nr(brw
, inst
) /
717 reg_type_size
[brw_inst_dst_reg_type(brw
, inst
)]);
718 if (brw_inst_dst_ia1_addr_imm(brw
, inst
))
719 format(file
, " %d", brw_inst_dst_ia1_addr_imm(brw
, inst
));
721 err
|= control(file
, "horiz stride", horiz_stride
,
722 brw_inst_dst_hstride(brw
, inst
), NULL
);
724 err
|= control(file
, "dest reg encoding", reg_encoding
,
725 brw_inst_dst_reg_type(brw
, inst
), NULL
);
728 if (brw_inst_dst_address_mode(brw
, inst
) == BRW_ADDRESS_DIRECT
) {
729 err
|= reg(file
, brw_inst_dst_reg_file(brw
, inst
),
730 brw_inst_dst_da_reg_nr(brw
, inst
));
733 if (brw_inst_dst_da16_subreg_nr(brw
, inst
))
734 format(file
, ".%d", brw_inst_dst_da16_subreg_nr(brw
, inst
) /
735 reg_type_size
[brw_inst_dst_reg_type(brw
, inst
)]);
737 err
|= control(file
, "writemask", writemask
,
738 brw_inst_da16_writemask(brw
, inst
), NULL
);
739 err
|= control(file
, "dest reg encoding", reg_encoding
,
740 brw_inst_dst_reg_type(brw
, inst
), NULL
);
743 string(file
, "Indirect align16 address mode not supported");
751 dest_3src(FILE *file
, struct brw_context
*brw
, brw_inst
*inst
)
756 if (brw
->gen
== 6 && brw_inst_3src_dst_reg_file(brw
, inst
))
757 reg_file
= BRW_MESSAGE_REGISTER_FILE
;
759 reg_file
= BRW_GENERAL_REGISTER_FILE
;
761 err
|= reg(file
, reg_file
, brw_inst_3src_dst_reg_nr(brw
, inst
));
764 if (brw_inst_3src_dst_subreg_nr(brw
, inst
))
765 format(file
, ".%d", brw_inst_3src_dst_subreg_nr(brw
, inst
));
767 err
|= control(file
, "writemask", writemask
,
768 brw_inst_3src_dst_writemask(brw
, inst
), NULL
);
769 err
|= control(file
, "dest reg encoding", three_source_reg_encoding
,
770 brw_inst_3src_dst_type(brw
, inst
), NULL
);
776 src_align1_region(FILE *file
,
777 unsigned _vert_stride
, unsigned _width
,
778 unsigned _horiz_stride
)
782 err
|= control(file
, "vert stride", vert_stride
, _vert_stride
, NULL
);
784 err
|= control(file
, "width", width
, _width
, NULL
);
786 err
|= control(file
, "horiz_stride", horiz_stride
, _horiz_stride
, NULL
);
793 const struct brw_context
*brw
,
795 unsigned type
, unsigned _reg_file
,
796 unsigned _vert_stride
, unsigned _width
, unsigned _horiz_stride
,
797 unsigned reg_num
, unsigned sub_reg_num
, unsigned __abs
,
802 if (brw
->gen
>= 8 && is_logic_instruction(opcode
))
803 err
|= control(file
, "bitnot", m_bitnot
, _negate
, NULL
);
805 err
|= control(file
, "negate", m_negate
, _negate
, NULL
);
807 err
|= control(file
, "abs", _abs
, __abs
, NULL
);
809 err
|= reg(file
, _reg_file
, reg_num
);
813 format(file
, ".%d", sub_reg_num
/ reg_type_size
[type
]); /* use formal style like spec */
814 src_align1_region(file
, _vert_stride
, _width
, _horiz_stride
);
815 err
|= control(file
, "src reg encoding", reg_encoding
, type
, NULL
);
821 const struct brw_context
*brw
,
826 unsigned _addr_subreg_nr
,
830 unsigned _horiz_stride
, unsigned _width
, unsigned _vert_stride
)
834 if (brw
->gen
>= 8 && is_logic_instruction(opcode
))
835 err
|= control(file
, "bitnot", m_bitnot
, _negate
, NULL
);
837 err
|= control(file
, "negate", m_negate
, _negate
, NULL
);
839 err
|= control(file
, "abs", _abs
, __abs
, NULL
);
841 string(file
, "g[a0");
843 format(file
, ".%d", _addr_subreg_nr
);
845 format(file
, " %d", _addr_imm
);
847 src_align1_region(file
, _vert_stride
, _width
, _horiz_stride
);
848 err
|= control(file
, "src reg encoding", reg_encoding
, type
, NULL
);
853 src_swizzle(FILE *file
, unsigned swiz
)
855 unsigned x
= BRW_GET_SWZ(swiz
, BRW_CHANNEL_X
);
856 unsigned y
= BRW_GET_SWZ(swiz
, BRW_CHANNEL_Y
);
857 unsigned z
= BRW_GET_SWZ(swiz
, BRW_CHANNEL_Z
);
858 unsigned w
= BRW_GET_SWZ(swiz
, BRW_CHANNEL_W
);
861 if (x
== y
&& x
== z
&& x
== w
) {
863 err
|= control(file
, "channel select", chan_sel
, x
, NULL
);
864 } else if (swiz
!= BRW_SWIZZLE_XYZW
) {
866 err
|= control(file
, "channel select", chan_sel
, x
, NULL
);
867 err
|= control(file
, "channel select", chan_sel
, y
, NULL
);
868 err
|= control(file
, "channel select", chan_sel
, z
, NULL
);
869 err
|= control(file
, "channel select", chan_sel
, w
, NULL
);
876 const struct brw_context
*brw
,
880 unsigned _vert_stride
,
885 unsigned swz_x
, unsigned swz_y
, unsigned swz_z
, unsigned swz_w
)
889 if (brw
->gen
>= 8 && is_logic_instruction(opcode
))
890 err
|= control(file
, "bitnot", m_bitnot
, _negate
, NULL
);
892 err
|= control(file
, "negate", m_negate
, _negate
, NULL
);
894 err
|= control(file
, "abs", _abs
, __abs
, NULL
);
896 err
|= reg(file
, _reg_file
, _reg_nr
);
900 /* bit4 for subreg number byte addressing. Make this same meaning as
901 in da1 case, so output looks consistent. */
902 format(file
, ".%d", 16 / reg_type_size
[_reg_type
]);
904 err
|= control(file
, "vert stride", vert_stride
, _vert_stride
, NULL
);
905 string(file
, ",4,1>");
906 err
|= src_swizzle(file
, BRW_SWIZZLE4(swz_x
, swz_y
, swz_z
, swz_w
));
907 err
|= control(file
, "src da16 reg type", reg_encoding
, _reg_type
, NULL
);
912 src0_3src(FILE *file
, struct brw_context
*brw
, brw_inst
*inst
)
915 unsigned src0_subreg_nr
= brw_inst_3src_src0_subreg_nr(brw
, inst
);
917 err
|= control(file
, "negate", m_negate
,
918 brw_inst_3src_src0_negate(brw
, inst
), NULL
);
919 err
|= control(file
, "abs", _abs
, brw_inst_3src_src0_abs(brw
, inst
), NULL
);
921 err
|= reg(file
, BRW_GENERAL_REGISTER_FILE
,
922 brw_inst_3src_src0_reg_nr(brw
, inst
));
926 format(file
, ".%d", src0_subreg_nr
);
927 if (brw_inst_3src_src0_rep_ctrl(brw
, inst
))
928 string(file
, "<0,1,0>");
930 string(file
, "<4,4,1>");
931 err
|= control(file
, "src da16 reg type", three_source_reg_encoding
,
932 brw_inst_3src_src_type(brw
, inst
), NULL
);
933 err
|= src_swizzle(file
, brw_inst_3src_src0_swizzle(brw
, inst
));
938 src1_3src(FILE *file
, struct brw_context
*brw
, brw_inst
*inst
)
941 unsigned src1_subreg_nr
= brw_inst_3src_src1_subreg_nr(brw
, inst
);
943 err
|= control(file
, "negate", m_negate
,
944 brw_inst_3src_src1_negate(brw
, inst
), NULL
);
945 err
|= control(file
, "abs", _abs
, brw_inst_3src_src1_abs(brw
, inst
), NULL
);
947 err
|= reg(file
, BRW_GENERAL_REGISTER_FILE
,
948 brw_inst_3src_src1_reg_nr(brw
, inst
));
952 format(file
, ".%d", src1_subreg_nr
);
953 if (brw_inst_3src_src1_rep_ctrl(brw
, inst
))
954 string(file
, "<0,1,0>");
956 string(file
, "<4,4,1>");
957 err
|= control(file
, "src da16 reg type", three_source_reg_encoding
,
958 brw_inst_3src_src_type(brw
, inst
), NULL
);
959 err
|= src_swizzle(file
, brw_inst_3src_src1_swizzle(brw
, inst
));
965 src2_3src(FILE *file
, struct brw_context
*brw
, brw_inst
*inst
)
968 unsigned src2_subreg_nr
= brw_inst_3src_src2_subreg_nr(brw
, inst
);
970 err
|= control(file
, "negate", m_negate
,
971 brw_inst_3src_src2_negate(brw
, inst
), NULL
);
972 err
|= control(file
, "abs", _abs
, brw_inst_3src_src2_abs(brw
, inst
), NULL
);
974 err
|= reg(file
, BRW_GENERAL_REGISTER_FILE
,
975 brw_inst_3src_src2_reg_nr(brw
, inst
));
979 format(file
, ".%d", src2_subreg_nr
);
980 if (brw_inst_3src_src2_rep_ctrl(brw
, inst
))
981 string(file
, "<0,1,0>");
983 string(file
, "<4,4,1>");
984 err
|= control(file
, "src da16 reg type", three_source_reg_encoding
,
985 brw_inst_3src_src_type(brw
, inst
), NULL
);
986 err
|= src_swizzle(file
, brw_inst_3src_src2_swizzle(brw
, inst
));
991 imm(FILE *file
, struct brw_context
*brw
, unsigned type
, brw_inst
*inst
)
994 case BRW_HW_REG_TYPE_UD
:
995 format(file
, "0x%08xUD", brw_inst_imm_ud(brw
, inst
));
997 case BRW_HW_REG_TYPE_D
:
998 format(file
, "%dD", brw_inst_imm_d(brw
, inst
));
1000 case BRW_HW_REG_TYPE_UW
:
1001 format(file
, "0x%04xUW", (uint16_t) brw_inst_imm_ud(brw
, inst
));
1003 case BRW_HW_REG_TYPE_W
:
1004 format(file
, "%dW", (int16_t) brw_inst_imm_d(brw
, inst
));
1006 case BRW_HW_REG_IMM_TYPE_UV
:
1007 format(file
, "0x%08xUV", brw_inst_imm_ud(brw
, inst
));
1009 case BRW_HW_REG_IMM_TYPE_VF
:
1010 format(file
, "Vector Float");
1012 case BRW_HW_REG_IMM_TYPE_V
:
1013 format(file
, "0x%08xV", brw_inst_imm_ud(brw
, inst
));
1015 case BRW_HW_REG_TYPE_F
:
1016 format(file
, "%-gF", brw_inst_imm_f(brw
, inst
));
1018 case GEN8_HW_REG_IMM_TYPE_DF
:
1019 string(file
, "Double IMM");
1021 case GEN8_HW_REG_IMM_TYPE_HF
:
1022 string(file
, "Half Float IMM");
1029 src0(FILE *file
, struct brw_context
*brw
, brw_inst
*inst
)
1031 if (brw_inst_src0_reg_file(brw
, inst
) == BRW_IMMEDIATE_VALUE
) {
1032 return imm(file
, brw
, brw_inst_src0_reg_type(brw
, inst
), inst
);
1033 } else if (brw_inst_access_mode(brw
, inst
) == BRW_ALIGN_1
) {
1034 if (brw_inst_src0_address_mode(brw
, inst
) == BRW_ADDRESS_DIRECT
) {
1035 return src_da1(file
,
1037 brw_inst_opcode(brw
, inst
),
1038 brw_inst_src0_reg_type(brw
, inst
),
1039 brw_inst_src0_reg_file(brw
, inst
),
1040 brw_inst_src0_vstride(brw
, inst
),
1041 brw_inst_src0_width(brw
, inst
),
1042 brw_inst_src0_hstride(brw
, inst
),
1043 brw_inst_src0_da_reg_nr(brw
, inst
),
1044 brw_inst_src0_da1_subreg_nr(brw
, inst
),
1045 brw_inst_src0_abs(brw
, inst
),
1046 brw_inst_src0_negate(brw
, inst
));
1048 return src_ia1(file
,
1050 brw_inst_opcode(brw
, inst
),
1051 brw_inst_src0_reg_type(brw
, inst
),
1052 brw_inst_src0_reg_file(brw
, inst
),
1053 brw_inst_src0_ia1_addr_imm(brw
, inst
),
1054 brw_inst_src0_ia_subreg_nr(brw
, inst
),
1055 brw_inst_src0_negate(brw
, inst
),
1056 brw_inst_src0_abs(brw
, inst
),
1057 brw_inst_src0_address_mode(brw
, inst
),
1058 brw_inst_src0_hstride(brw
, inst
),
1059 brw_inst_src0_width(brw
, inst
),
1060 brw_inst_src0_vstride(brw
, inst
));
1063 if (brw_inst_src0_address_mode(brw
, inst
) == BRW_ADDRESS_DIRECT
) {
1064 return src_da16(file
,
1066 brw_inst_opcode(brw
, inst
),
1067 brw_inst_src0_reg_type(brw
, inst
),
1068 brw_inst_src0_reg_file(brw
, inst
),
1069 brw_inst_src0_vstride(brw
, inst
),
1070 brw_inst_src0_da_reg_nr(brw
, inst
),
1071 brw_inst_src0_da16_subreg_nr(brw
, inst
),
1072 brw_inst_src0_abs(brw
, inst
),
1073 brw_inst_src0_negate(brw
, inst
),
1074 brw_inst_src0_da16_swiz_x(brw
, inst
),
1075 brw_inst_src0_da16_swiz_y(brw
, inst
),
1076 brw_inst_src0_da16_swiz_z(brw
, inst
),
1077 brw_inst_src0_da16_swiz_w(brw
, inst
));
1079 string(file
, "Indirect align16 address mode not supported");
1086 src1(FILE *file
, struct brw_context
*brw
, brw_inst
*inst
)
1088 if (brw_inst_src1_reg_file(brw
, inst
) == BRW_IMMEDIATE_VALUE
) {
1089 return imm(file
, brw
, brw_inst_src1_reg_type(brw
, inst
), inst
);
1090 } else if (brw_inst_access_mode(brw
, inst
) == BRW_ALIGN_1
) {
1091 if (brw_inst_src1_address_mode(brw
, inst
) == BRW_ADDRESS_DIRECT
) {
1092 return src_da1(file
,
1094 brw_inst_opcode(brw
, inst
),
1095 brw_inst_src1_reg_type(brw
, inst
),
1096 brw_inst_src1_reg_file(brw
, inst
),
1097 brw_inst_src1_vstride(brw
, inst
),
1098 brw_inst_src1_width(brw
, inst
),
1099 brw_inst_src1_hstride(brw
, inst
),
1100 brw_inst_src1_da_reg_nr(brw
, inst
),
1101 brw_inst_src1_da1_subreg_nr(brw
, inst
),
1102 brw_inst_src1_abs(brw
, inst
),
1103 brw_inst_src1_negate(brw
, inst
));
1105 return src_ia1(file
,
1107 brw_inst_opcode(brw
, inst
),
1108 brw_inst_src1_reg_type(brw
, inst
),
1109 brw_inst_src1_reg_file(brw
, inst
),
1110 brw_inst_src1_ia1_addr_imm(brw
, inst
),
1111 brw_inst_src1_ia_subreg_nr(brw
, inst
),
1112 brw_inst_src1_negate(brw
, inst
),
1113 brw_inst_src1_abs(brw
, inst
),
1114 brw_inst_src1_address_mode(brw
, inst
),
1115 brw_inst_src1_hstride(brw
, inst
),
1116 brw_inst_src1_width(brw
, inst
),
1117 brw_inst_src1_vstride(brw
, inst
));
1120 if (brw_inst_src1_address_mode(brw
, inst
) == BRW_ADDRESS_DIRECT
) {
1121 return src_da16(file
,
1123 brw_inst_opcode(brw
, inst
),
1124 brw_inst_src1_reg_type(brw
, inst
),
1125 brw_inst_src1_reg_file(brw
, inst
),
1126 brw_inst_src1_vstride(brw
, inst
),
1127 brw_inst_src1_da_reg_nr(brw
, inst
),
1128 brw_inst_src1_da16_subreg_nr(brw
, inst
),
1129 brw_inst_src1_abs(brw
, inst
),
1130 brw_inst_src1_negate(brw
, inst
),
1131 brw_inst_src1_da16_swiz_x(brw
, inst
),
1132 brw_inst_src1_da16_swiz_y(brw
, inst
),
1133 brw_inst_src1_da16_swiz_z(brw
, inst
),
1134 brw_inst_src1_da16_swiz_w(brw
, inst
));
1136 string(file
, "Indirect align16 address mode not supported");
1143 qtr_ctrl(FILE *file
, struct brw_context
*brw
, brw_inst
*inst
)
1145 int qtr_ctl
= brw_inst_qtr_control(brw
, inst
);
1146 int exec_size
= 1 << brw_inst_exec_size(brw
, inst
);
1148 if (exec_size
== 8) {
1151 string(file
, " 1Q");
1154 string(file
, " 2Q");
1157 string(file
, " 3Q");
1160 string(file
, " 4Q");
1163 } else if (exec_size
== 16) {
1165 string(file
, " 1H");
1167 string(file
, " 2H");
1173 brw_disassemble_inst(FILE *file
, struct brw_context
*brw
, brw_inst
*inst
,
1179 const enum opcode opcode
= brw_inst_opcode(brw
, inst
);
1181 if (brw_inst_pred_control(brw
, inst
)) {
1183 err
|= control(file
, "predicate inverse", pred_inv
,
1184 brw_inst_pred_inv(brw
, inst
), NULL
);
1185 format(file
, "f%d", brw
->gen
>= 7 ? brw_inst_flag_reg_nr(brw
, inst
) : 0);
1186 if (brw_inst_flag_subreg_nr(brw
, inst
))
1187 format(file
, ".%d", brw_inst_flag_subreg_nr(brw
, inst
));
1188 if (brw_inst_access_mode(brw
, inst
) == BRW_ALIGN_1
) {
1189 err
|= control(file
, "predicate control align1", pred_ctrl_align1
,
1190 brw_inst_pred_control(brw
, inst
), NULL
);
1192 err
|= control(file
, "predicate control align16", pred_ctrl_align16
,
1193 brw_inst_pred_control(brw
, inst
), NULL
);
1198 err
|= print_opcode(file
, opcode
);
1199 err
|= control(file
, "saturate", saturate
, brw_inst_saturate(brw
, inst
),
1202 err
|= control(file
, "debug control", debug_ctrl
,
1203 brw_inst_debug_control(brw
, inst
), NULL
);
1205 if (opcode
== BRW_OPCODE_MATH
) {
1207 err
|= control(file
, "function", math_function
,
1208 brw_inst_math_function(brw
, inst
), NULL
);
1209 } else if (opcode
!= BRW_OPCODE_SEND
&& opcode
!= BRW_OPCODE_SENDC
) {
1210 err
|= control(file
, "conditional modifier", conditional_modifier
,
1211 brw_inst_cond_modifier(brw
, inst
), NULL
);
1213 /* If we're using the conditional modifier, print which flags reg is
1214 * used for it. Note that on gen6+, the embedded-condition SEL and
1215 * control flow doesn't update flags.
1217 if (brw_inst_cond_modifier(brw
, inst
) &&
1218 (brw
->gen
< 6 || (opcode
!= BRW_OPCODE_SEL
&&
1219 opcode
!= BRW_OPCODE_IF
&&
1220 opcode
!= BRW_OPCODE_WHILE
))) {
1221 format(file
, ".f%d",
1222 brw
->gen
>= 7 ? brw_inst_flag_reg_nr(brw
, inst
) : 0);
1223 if (brw_inst_flag_subreg_nr(brw
, inst
))
1224 format(file
, ".%d", brw_inst_flag_subreg_nr(brw
, inst
));
1228 if (opcode
!= BRW_OPCODE_NOP
) {
1230 err
|= control(file
, "execution size", exec_size
,
1231 brw_inst_exec_size(brw
, inst
), NULL
);
1235 if (opcode
== BRW_OPCODE_SEND
&& brw
->gen
< 6)
1236 format(file
, " %d", brw_inst_base_mrf(brw
, inst
));
1238 if (has_uip(brw
, opcode
)) {
1239 /* Instructions that have UIP also have JIP. */
1241 format(file
, "JIP: %d", brw_inst_jip(brw
, inst
));
1243 format(file
, "UIP: %d", brw_inst_uip(brw
, inst
));
1244 } else if (has_jip(brw
, opcode
)) {
1246 if (brw
->gen
>= 7) {
1247 format(file
, "JIP: %d", brw_inst_jip(brw
, inst
));
1249 format(file
, "JIP: %d", brw_inst_gen6_jump_count(brw
, inst
));
1251 } else if (brw
->gen
< 6 && (opcode
== BRW_OPCODE_BREAK
||
1252 opcode
== BRW_OPCODE_CONTINUE
||
1253 opcode
== BRW_OPCODE_ELSE
)) {
1255 format(file
, "Jump: %d", brw_inst_gen4_jump_count(brw
, inst
));
1257 format(file
, "Pop: %d", brw_inst_gen4_pop_count(brw
, inst
));
1258 } else if (brw
->gen
< 6 && (opcode
== BRW_OPCODE_IF
||
1259 opcode
== BRW_OPCODE_IFF
||
1260 opcode
== BRW_OPCODE_HALT
)) {
1262 format(file
, "Jump: %d", brw_inst_gen4_pop_count(brw
, inst
));
1263 } else if (brw
->gen
< 6 && opcode
== BRW_OPCODE_ENDIF
) {
1265 format(file
, "Pop: %d", brw_inst_gen4_pop_count(brw
, inst
));
1266 } else if (opcode
== BRW_OPCODE_JMPI
) {
1268 err
|= src1(file
, brw
, inst
);
1269 } else if (opcode_descs
[opcode
].nsrc
== 3) {
1271 err
|= dest_3src(file
, brw
, inst
);
1274 err
|= src0_3src(file
, brw
, inst
);
1277 err
|= src1_3src(file
, brw
, inst
);
1280 err
|= src2_3src(file
, brw
, inst
);
1282 if (opcode_descs
[opcode
].ndst
> 0) {
1284 err
|= dest(file
, brw
, inst
);
1287 if (opcode_descs
[opcode
].nsrc
> 0) {
1289 err
|= src0(file
, brw
, inst
);
1292 if (opcode_descs
[opcode
].nsrc
> 1) {
1294 err
|= src1(file
, brw
, inst
);
1298 if (opcode
== BRW_OPCODE_SEND
|| opcode
== BRW_OPCODE_SENDC
) {
1299 enum brw_message_target sfid
= brw_inst_sfid(brw
, inst
);
1301 if (brw_inst_src1_reg_file(brw
, inst
) != BRW_IMMEDIATE_VALUE
) {
1302 /* show the indirect descriptor source */
1304 err
|= src1(file
, brw
, inst
);
1312 err
|= control(file
, "SFID", brw
->gen
>= 6 ? gen6_sfid
: gen4_sfid
,
1316 if (brw_inst_src1_reg_file(brw
, inst
) != BRW_IMMEDIATE_VALUE
) {
1317 format(file
, " indirect");
1321 err
|= control(file
, "math function", math_function
,
1322 brw_inst_math_msg_function(brw
, inst
), &space
);
1323 err
|= control(file
, "math saturate", math_saturate
,
1324 brw_inst_math_msg_saturate(brw
, inst
), &space
);
1325 err
|= control(file
, "math signed", math_signed
,
1326 brw_inst_math_msg_signed_int(brw
, inst
), &space
);
1327 err
|= control(file
, "math scalar", math_scalar
,
1328 brw_inst_math_msg_data_type(brw
, inst
), &space
);
1329 err
|= control(file
, "math precision", math_precision
,
1330 brw_inst_math_msg_precision(brw
, inst
), &space
);
1332 case BRW_SFID_SAMPLER
:
1333 if (brw
->gen
>= 5) {
1334 format(file
, " (%d, %d, %d, %d)",
1335 brw_inst_binding_table_index(brw
, inst
),
1336 brw_inst_sampler(brw
, inst
),
1337 brw_inst_sampler_msg_type(brw
, inst
),
1338 brw_inst_sampler_simd_mode(brw
, inst
));
1340 format(file
, " (%d, %d, %d, ",
1341 brw_inst_binding_table_index(brw
, inst
),
1342 brw_inst_sampler(brw
, inst
),
1343 brw_inst_sampler_msg_type(brw
, inst
));
1345 err
|= control(file
, "sampler target format",
1346 sampler_target_format
,
1347 brw_inst_sampler_return_format(brw
, inst
), NULL
);
1352 case GEN6_SFID_DATAPORT_SAMPLER_CACHE
:
1353 /* aka BRW_SFID_DATAPORT_READ on Gen4-5 */
1354 if (brw
->gen
>= 6) {
1355 format(file
, " (%d, %d, %d, %d)",
1356 brw_inst_binding_table_index(brw
, inst
),
1357 brw_inst_dp_msg_control(brw
, inst
),
1358 brw_inst_dp_msg_type(brw
, inst
),
1359 brw
->gen
>= 7 ? 0 : brw_inst_dp_write_commit(brw
, inst
));
1361 format(file
, " (%d, %d, %d)",
1362 brw_inst_binding_table_index(brw
, inst
),
1363 brw_inst_dp_read_msg_control(brw
, inst
),
1364 brw_inst_dp_read_msg_type(brw
, inst
));
1368 case GEN6_SFID_DATAPORT_RENDER_CACHE
: {
1369 /* aka BRW_SFID_DATAPORT_WRITE on Gen4-5 */
1370 unsigned msg_type
= brw_inst_dp_write_msg_type(brw
, inst
);
1372 err
|= control(file
, "DP rc message type",
1373 brw
->gen
>= 6 ? dp_rc_msg_type_gen6
1374 : dp_write_port_msg_type
,
1377 bool is_rt_write
= msg_type
==
1378 (brw
->gen
>= 6 ? GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
1379 : BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
);
1382 err
|= control(file
, "RT message type", m_rt_write_subtype
,
1383 brw_inst_rt_message_type(brw
, inst
), &space
);
1384 if (brw
->gen
>= 6 && brw_inst_rt_slot_group(brw
, inst
))
1385 string(file
, " Hi");
1386 if (brw_inst_rt_last(brw
, inst
))
1387 string(file
, " LastRT");
1388 if (brw
->gen
< 7 && brw_inst_dp_write_commit(brw
, inst
))
1389 string(file
, " WriteCommit");
1391 format(file
, " MsgCtrl = 0x%x",
1392 brw_inst_dp_write_msg_control(brw
, inst
));
1395 format(file
, " Surface = %d", brw_inst_binding_table_index(brw
, inst
));
1400 format(file
, " %d", brw_inst_urb_global_offset(brw
, inst
));
1403 if (brw
->gen
>= 7) {
1404 err
|= control(file
, "urb opcode", gen7_urb_opcode
,
1405 brw_inst_urb_opcode(brw
, inst
), &space
);
1406 } else if (brw
->gen
>= 5) {
1407 err
|= control(file
, "urb opcode", gen5_urb_opcode
,
1408 brw_inst_urb_opcode(brw
, inst
), &space
);
1410 err
|= control(file
, "urb swizzle", urb_swizzle
,
1411 brw_inst_urb_swizzle_control(brw
, inst
), &space
);
1413 err
|= control(file
, "urb allocate", urb_allocate
,
1414 brw_inst_urb_allocate(brw
, inst
), &space
);
1415 err
|= control(file
, "urb used", urb_used
,
1416 brw_inst_urb_used(brw
, inst
), &space
);
1419 err
|= control(file
, "urb complete", urb_complete
,
1420 brw_inst_urb_complete(brw
, inst
), &space
);
1423 case BRW_SFID_THREAD_SPAWNER
:
1425 case GEN7_SFID_DATAPORT_DATA_CACHE
:
1426 if (brw
->gen
>= 7) {
1429 err
|= control(file
, "DP DC0 message type",
1430 dp_dc0_msg_type_gen7
,
1431 brw_inst_dp_msg_type(brw
, inst
), &space
);
1433 format(file
, ", %d, ", brw_inst_binding_table_index(brw
, inst
));
1435 switch (brw_inst_dp_msg_type(brw
, inst
)) {
1436 case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP
:
1437 control(file
, "atomic op", aop
,
1438 brw_inst_imm_ud(brw
, inst
) >> 8 & 0xf, &space
);
1441 format(file
, "%d", brw_inst_dp_msg_control(brw
, inst
));
1448 case HSW_SFID_DATAPORT_DATA_CACHE_1
: {
1449 if (brw
->gen
>= 7) {
1452 unsigned msg_ctrl
= brw_inst_dp_msg_control(brw
, inst
);
1454 err
|= control(file
, "DP DC1 message type",
1455 dp_dc1_msg_type_hsw
,
1456 brw_inst_dp_msg_type(brw
, inst
), &space
);
1458 format(file
, ", Surface = %d, ",
1459 brw_inst_binding_table_index(brw
, inst
));
1461 switch (brw_inst_dp_msg_type(brw
, inst
)) {
1462 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP
:
1463 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP
:
1464 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP
:
1465 format(file
, "SIMD%d,", (msg_ctrl
& (1 << 4)) ? 8 : 16);
1467 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2
:
1468 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2
:
1469 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2
:
1470 control(file
, "atomic op", aop
, msg_ctrl
& 0xf, &space
);
1472 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ
:
1473 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE
:
1474 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ
:
1475 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE
: {
1476 static const char *simd_modes
[] = { "4x2", "16", "8" };
1477 format(file
, "SIMD%s, Mask = 0x%x",
1478 simd_modes
[msg_ctrl
>> 4], msg_ctrl
& 0xf);
1482 format(file
, "0x%x", msg_ctrl
);
1490 case GEN7_SFID_PIXEL_INTERPOLATOR
:
1491 if (brw
->gen
>= 7) {
1492 format(file
, " (%s, %s, 0x%02x)",
1493 brw_inst_pi_nopersp(brw
, inst
) ? "linear" : "persp",
1494 pixel_interpolator_msg_types
[brw_inst_pi_message_type(brw
, inst
)],
1495 brw_inst_pi_message_data(brw
, inst
));
1501 format(file
, "unsupported shared function ID %d", sfid
);
1507 format(file
, "mlen %d", brw_inst_mlen(brw
, inst
));
1508 format(file
, " rlen %d", brw_inst_rlen(brw
, inst
));
1512 if (opcode
!= BRW_OPCODE_NOP
) {
1515 err
|= control(file
, "access mode", access_mode
,
1516 brw_inst_access_mode(brw
, inst
), &space
);
1517 if (brw
->gen
>= 6) {
1518 err
|= control(file
, "write enable control", wectrl
,
1519 brw_inst_mask_control(brw
, inst
), &space
);
1521 err
|= control(file
, "mask control", mask_ctrl
,
1522 brw_inst_mask_control(brw
, inst
), &space
);
1524 err
|= control(file
, "dependency control", dep_ctrl
,
1525 ((brw_inst_no_dd_check(brw
, inst
) << 1) |
1526 brw_inst_no_dd_clear(brw
, inst
)), &space
);
1529 err
|= qtr_ctrl(file
, brw
, inst
);
1531 if (brw_inst_qtr_control(brw
, inst
) == BRW_COMPRESSION_COMPRESSED
&&
1532 opcode_descs
[opcode
].ndst
> 0 &&
1533 brw_inst_dst_reg_file(brw
, inst
) == BRW_MESSAGE_REGISTER_FILE
&&
1534 brw_inst_dst_da_reg_nr(brw
, inst
) & (1 << 7)) {
1535 format(file
, " compr4");
1537 err
|= control(file
, "compression control", compr_ctrl
,
1538 brw_inst_qtr_control(brw
, inst
), &space
);
1542 err
|= control(file
, "compaction", cmpt_ctrl
, is_compacted
, &space
);
1543 err
|= control(file
, "thread control", thread_ctrl
,
1544 brw_inst_thread_control(brw
, inst
), &space
);
1546 err
|= control(file
, "acc write control", accwr
,
1547 brw_inst_acc_wr_control(brw
, inst
), &space
);
1548 if (opcode
== BRW_OPCODE_SEND
|| opcode
== BRW_OPCODE_SENDC
)
1549 err
|= control(file
, "end of thread", end_of_thread
,
1550 brw_inst_eot(brw
, inst
), &space
);