2 * Copyright © 2008 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
30 #include "main/mtypes.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
35 const struct opcode_desc opcode_descs
[128] = {
36 [BRW_OPCODE_MOV
] = { .name
= "mov", .nsrc
= 1, .ndst
= 1 },
37 [BRW_OPCODE_FRC
] = { .name
= "frc", .nsrc
= 1, .ndst
= 1 },
38 [BRW_OPCODE_RNDU
] = { .name
= "rndu", .nsrc
= 1, .ndst
= 1 },
39 [BRW_OPCODE_RNDD
] = { .name
= "rndd", .nsrc
= 1, .ndst
= 1 },
40 [BRW_OPCODE_RNDE
] = { .name
= "rnde", .nsrc
= 1, .ndst
= 1 },
41 [BRW_OPCODE_RNDZ
] = { .name
= "rndz", .nsrc
= 1, .ndst
= 1 },
42 [BRW_OPCODE_NOT
] = { .name
= "not", .nsrc
= 1, .ndst
= 1 },
43 [BRW_OPCODE_LZD
] = { .name
= "lzd", .nsrc
= 1, .ndst
= 1 },
44 [BRW_OPCODE_F32TO16
] = { .name
= "f32to16", .nsrc
= 1, .ndst
= 1 },
45 [BRW_OPCODE_F16TO32
] = { .name
= "f16to32", .nsrc
= 1, .ndst
= 1 },
46 [BRW_OPCODE_BFREV
] = { .name
= "bfrev", .nsrc
= 1, .ndst
= 1},
47 [BRW_OPCODE_FBH
] = { .name
= "fbh", .nsrc
= 1, .ndst
= 1},
48 [BRW_OPCODE_FBL
] = { .name
= "fbl", .nsrc
= 1, .ndst
= 1},
49 [BRW_OPCODE_CBIT
] = { .name
= "cbit", .nsrc
= 1, .ndst
= 1},
51 [BRW_OPCODE_MUL
] = { .name
= "mul", .nsrc
= 2, .ndst
= 1 },
52 [BRW_OPCODE_MAC
] = { .name
= "mac", .nsrc
= 2, .ndst
= 1 },
53 [BRW_OPCODE_MACH
] = { .name
= "mach", .nsrc
= 2, .ndst
= 1 },
54 [BRW_OPCODE_LINE
] = { .name
= "line", .nsrc
= 2, .ndst
= 1 },
55 [BRW_OPCODE_PLN
] = { .name
= "pln", .nsrc
= 2, .ndst
= 1 },
56 [BRW_OPCODE_MAD
] = { .name
= "mad", .nsrc
= 3, .ndst
= 1 },
57 [BRW_OPCODE_LRP
] = { .name
= "lrp", .nsrc
= 3, .ndst
= 1 },
58 [BRW_OPCODE_SAD2
] = { .name
= "sad2", .nsrc
= 2, .ndst
= 1 },
59 [BRW_OPCODE_SADA2
] = { .name
= "sada2", .nsrc
= 2, .ndst
= 1 },
60 [BRW_OPCODE_DP4
] = { .name
= "dp4", .nsrc
= 2, .ndst
= 1 },
61 [BRW_OPCODE_DPH
] = { .name
= "dph", .nsrc
= 2, .ndst
= 1 },
62 [BRW_OPCODE_DP3
] = { .name
= "dp3", .nsrc
= 2, .ndst
= 1 },
63 [BRW_OPCODE_DP2
] = { .name
= "dp2", .nsrc
= 2, .ndst
= 1 },
64 [BRW_OPCODE_MATH
] = { .name
= "math", .nsrc
= 2, .ndst
= 1 },
66 [BRW_OPCODE_AVG
] = { .name
= "avg", .nsrc
= 2, .ndst
= 1 },
67 [BRW_OPCODE_ADD
] = { .name
= "add", .nsrc
= 2, .ndst
= 1 },
68 [BRW_OPCODE_SEL
] = { .name
= "sel", .nsrc
= 2, .ndst
= 1 },
69 [BRW_OPCODE_AND
] = { .name
= "and", .nsrc
= 2, .ndst
= 1 },
70 [BRW_OPCODE_OR
] = { .name
= "or", .nsrc
= 2, .ndst
= 1 },
71 [BRW_OPCODE_XOR
] = { .name
= "xor", .nsrc
= 2, .ndst
= 1 },
72 [BRW_OPCODE_SHR
] = { .name
= "shr", .nsrc
= 2, .ndst
= 1 },
73 [BRW_OPCODE_SHL
] = { .name
= "shl", .nsrc
= 2, .ndst
= 1 },
74 [BRW_OPCODE_ASR
] = { .name
= "asr", .nsrc
= 2, .ndst
= 1 },
75 [BRW_OPCODE_CMP
] = { .name
= "cmp", .nsrc
= 2, .ndst
= 1 },
76 [BRW_OPCODE_CMPN
] = { .name
= "cmpn", .nsrc
= 2, .ndst
= 1 },
77 [BRW_OPCODE_BFE
] = { .name
= "bfe", .nsrc
= 3, .ndst
= 1},
78 [BRW_OPCODE_BFI1
] = { .name
= "bfi1", .nsrc
= 2, .ndst
= 1},
79 [BRW_OPCODE_BFI2
] = { .name
= "bfi2", .nsrc
= 3, .ndst
= 1},
80 [BRW_OPCODE_ADDC
] = { .name
= "addc", .nsrc
= 2, .ndst
= 1},
81 [BRW_OPCODE_SUBB
] = { .name
= "subb", .nsrc
= 2, .ndst
= 1},
83 [BRW_OPCODE_SEND
] = { .name
= "send", .nsrc
= 1, .ndst
= 1 },
84 [BRW_OPCODE_SENDC
] = { .name
= "sendc", .nsrc
= 1, .ndst
= 1 },
85 [BRW_OPCODE_NOP
] = { .name
= "nop", .nsrc
= 0, .ndst
= 0 },
86 [BRW_OPCODE_JMPI
] = { .name
= "jmpi", .nsrc
= 0, .ndst
= 0 },
87 [BRW_OPCODE_IF
] = { .name
= "if", .nsrc
= 2, .ndst
= 0 },
88 [BRW_OPCODE_IFF
] = { .name
= "iff", .nsrc
= 2, .ndst
= 1 },
89 [BRW_OPCODE_WHILE
] = { .name
= "while", .nsrc
= 2, .ndst
= 0 },
90 [BRW_OPCODE_ELSE
] = { .name
= "else", .nsrc
= 2, .ndst
= 0 },
91 [BRW_OPCODE_BREAK
] = { .name
= "break", .nsrc
= 2, .ndst
= 0 },
92 [BRW_OPCODE_CONTINUE
] = { .name
= "cont", .nsrc
= 1, .ndst
= 0 },
93 [BRW_OPCODE_HALT
] = { .name
= "halt", .nsrc
= 1, .ndst
= 0 },
94 [BRW_OPCODE_MSAVE
] = { .name
= "msave", .nsrc
= 1, .ndst
= 1 },
95 [BRW_OPCODE_PUSH
] = { .name
= "push", .nsrc
= 1, .ndst
= 1 },
96 [BRW_OPCODE_MRESTORE
] = { .name
= "mrest", .nsrc
= 1, .ndst
= 1 },
97 [BRW_OPCODE_POP
] = { .name
= "pop", .nsrc
= 2, .ndst
= 0 },
98 [BRW_OPCODE_WAIT
] = { .name
= "wait", .nsrc
= 1, .ndst
= 0 },
99 [BRW_OPCODE_DO
] = { .name
= "do", .nsrc
= 0, .ndst
= 0 },
100 [BRW_OPCODE_ENDIF
] = { .name
= "endif", .nsrc
= 2, .ndst
= 0 },
102 static const struct opcode_desc
*opcode
= opcode_descs
;
104 const char * const conditional_modifier
[16] = {
105 [BRW_CONDITIONAL_NONE
] = "",
106 [BRW_CONDITIONAL_Z
] = ".e",
107 [BRW_CONDITIONAL_NZ
] = ".ne",
108 [BRW_CONDITIONAL_G
] = ".g",
109 [BRW_CONDITIONAL_GE
] = ".ge",
110 [BRW_CONDITIONAL_L
] = ".l",
111 [BRW_CONDITIONAL_LE
] = ".le",
112 [BRW_CONDITIONAL_R
] = ".r",
113 [BRW_CONDITIONAL_O
] = ".o",
114 [BRW_CONDITIONAL_U
] = ".u",
117 static const char * const negate
[2] = {
122 static const char * const _abs
[2] = {
127 static const char * const vert_stride
[16] = {
138 static const char * const width
[8] = {
146 static const char * const horiz_stride
[4] = {
153 static const char * const chan_sel
[4] = {
160 static const char * const debug_ctrl
[2] = {
165 static const char * const saturate
[2] = {
170 static const char * const accwr
[2] = {
175 static const char * const wectrl
[2] = {
180 static const char * const exec_size
[8] = {
189 static const char * const pred_inv
[2] = {
194 static const char * const pred_ctrl_align16
[16] = {
204 static const char * const pred_ctrl_align1
[16] = {
218 static const char * const thread_ctrl
[4] = {
223 static const char * const compr_ctrl
[4] = {
230 static const char * const dep_ctrl
[4] = {
234 [3] = "NoDDClr,NoDDChk",
237 static const char * const mask_ctrl
[4] = {
242 static const char * const access_mode
[2] = {
247 static const char * const reg_encoding
[8] = {
257 const char * const three_source_reg_encoding
[] = {
258 [BRW_3SRC_TYPE_F
] = "F",
259 [BRW_3SRC_TYPE_D
] = "D",
260 [BRW_3SRC_TYPE_UD
] = "UD",
263 const int reg_type_size
[8] = {
273 static const char * const reg_file
[4] = {
280 static const char * const writemask
[16] = {
299 static const char * const end_of_thread
[2] = {
304 static const char * const target_function
[16] = {
305 [BRW_SFID_NULL
] = "null",
306 [BRW_SFID_MATH
] = "math",
307 [BRW_SFID_SAMPLER
] = "sampler",
308 [BRW_SFID_MESSAGE_GATEWAY
] = "gateway",
309 [BRW_SFID_DATAPORT_READ
] = "read",
310 [BRW_SFID_DATAPORT_WRITE
] = "write",
311 [BRW_SFID_URB
] = "urb",
312 [BRW_SFID_THREAD_SPAWNER
] = "thread_spawner"
315 static const char * const target_function_gen6
[16] = {
316 [BRW_SFID_NULL
] = "null",
317 [BRW_SFID_MATH
] = "math",
318 [BRW_SFID_SAMPLER
] = "sampler",
319 [BRW_SFID_MESSAGE_GATEWAY
] = "gateway",
320 [BRW_SFID_URB
] = "urb",
321 [BRW_SFID_THREAD_SPAWNER
] = "thread_spawner",
322 [GEN6_SFID_DATAPORT_SAMPLER_CACHE
] = "sampler",
323 [GEN6_SFID_DATAPORT_RENDER_CACHE
] = "render",
324 [GEN6_SFID_DATAPORT_CONSTANT_CACHE
] = "const",
325 [GEN7_SFID_DATAPORT_DATA_CACHE
] = "data"
328 static const char * const dp_rc_msg_type_gen6
[16] = {
329 [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
] = "OWORD block read",
330 [GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ
] = "RT UNORM read",
331 [GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
] = "OWORD dual block read",
332 [GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ
] = "media block read",
333 [GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ
] = "OWORD unaligned block read",
334 [GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
] = "DWORD scattered read",
335 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE
] = "DWORD atomic write",
336 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE
] = "OWORD block write",
337 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
] = "OWORD dual block write",
338 [GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE
] = "media block write",
339 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE
] = "DWORD scattered write",
340 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
] = "RT write",
341 [GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE
] = "streamed VB write",
342 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE
] = "RT UNORMc write",
345 static const char * const math_function
[16] = {
346 [BRW_MATH_FUNCTION_INV
] = "inv",
347 [BRW_MATH_FUNCTION_LOG
] = "log",
348 [BRW_MATH_FUNCTION_EXP
] = "exp",
349 [BRW_MATH_FUNCTION_SQRT
] = "sqrt",
350 [BRW_MATH_FUNCTION_RSQ
] = "rsq",
351 [BRW_MATH_FUNCTION_SIN
] = "sin",
352 [BRW_MATH_FUNCTION_COS
] = "cos",
353 [BRW_MATH_FUNCTION_SINCOS
] = "sincos",
354 [BRW_MATH_FUNCTION_FDIV
] = "fdiv",
355 [BRW_MATH_FUNCTION_POW
] = "pow",
356 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
] = "intdivmod",
357 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
] = "intdiv",
358 [BRW_MATH_FUNCTION_INT_DIV_REMAINDER
] = "intmod",
361 static const char * const math_saturate
[2] = {
366 static const char * const math_signed
[2] = {
371 static const char * const math_scalar
[2] = {
376 static const char * const math_precision
[2] = {
378 [1] = "partial_precision"
381 static const char * const urb_opcode
[2] = {
386 static const char * const urb_swizzle
[4] = {
387 [BRW_URB_SWIZZLE_NONE
] = "",
388 [BRW_URB_SWIZZLE_INTERLEAVE
] = "interleave",
389 [BRW_URB_SWIZZLE_TRANSPOSE
] = "transpose",
392 static const char * const urb_allocate
[2] = {
397 static const char * const urb_used
[2] = {
402 static const char * const urb_complete
[2] = {
407 static const char * const sampler_target_format
[4] = {
416 static int string (FILE *file
, const char *string
)
418 fputs (string
, file
);
419 column
+= strlen (string
);
423 static int format (FILE *f
, const char *format
, ...)
427 va_start (args
, format
);
429 vsnprintf (buf
, sizeof (buf
) - 1, format
, args
);
435 static int newline (FILE *f
)
442 static int pad (FILE *f
, int c
)
450 static int control (FILE *file
, const char *name
, const char * const ctrl
[],
451 unsigned id
, int *space
)
454 fprintf (file
, "*** invalid %s value %d ",
462 string (file
, ctrl
[id
]);
469 static int print_opcode (FILE *file
, int id
)
471 if (!opcode
[id
].name
) {
472 format (file
, "*** invalid opcode value %d ", id
);
475 string (file
, opcode
[id
].name
);
479 static int reg (FILE *file
, unsigned _reg_file
, unsigned _reg_nr
)
483 /* Clear the Compr4 instruction compression bit. */
484 if (_reg_file
== BRW_MESSAGE_REGISTER_FILE
)
485 _reg_nr
&= ~(1 << 7);
487 if (_reg_file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
488 switch (_reg_nr
& 0xf0) {
490 string (file
, "null");
492 case BRW_ARF_ADDRESS
:
493 format (file
, "a%d", _reg_nr
& 0x0f);
495 case BRW_ARF_ACCUMULATOR
:
496 format (file
, "acc%d", _reg_nr
& 0x0f);
499 format (file
, "f%d", _reg_nr
& 0x0f);
502 format (file
, "mask%d", _reg_nr
& 0x0f);
504 case BRW_ARF_MASK_STACK
:
505 format (file
, "msd%d", _reg_nr
& 0x0f);
508 format (file
, "sr%d", _reg_nr
& 0x0f);
510 case BRW_ARF_CONTROL
:
511 format (file
, "cr%d", _reg_nr
& 0x0f);
513 case BRW_ARF_NOTIFICATION_COUNT
:
514 format (file
, "n%d", _reg_nr
& 0x0f);
521 format (file
, "ARF%d", _reg_nr
);
525 err
|= control (file
, "src reg file", reg_file
, _reg_file
, NULL
);
526 format (file
, "%d", _reg_nr
);
531 static int dest (FILE *file
, struct brw_instruction
*inst
)
535 if (inst
->header
.access_mode
== BRW_ALIGN_1
)
537 if (inst
->bits1
.da1
.dest_address_mode
== BRW_ADDRESS_DIRECT
)
539 err
|= reg (file
, inst
->bits1
.da1
.dest_reg_file
, inst
->bits1
.da1
.dest_reg_nr
);
542 if (inst
->bits1
.da1
.dest_subreg_nr
)
543 format (file
, ".%d", inst
->bits1
.da1
.dest_subreg_nr
/
544 reg_type_size
[inst
->bits1
.da1
.dest_reg_type
]);
546 err
|= control (file
, "horiz stride", horiz_stride
, inst
->bits1
.da1
.dest_horiz_stride
, NULL
);
548 err
|= control (file
, "dest reg encoding", reg_encoding
, inst
->bits1
.da1
.dest_reg_type
, NULL
);
552 string (file
, "g[a0");
553 if (inst
->bits1
.ia1
.dest_subreg_nr
)
554 format (file
, ".%d", inst
->bits1
.ia1
.dest_subreg_nr
/
555 reg_type_size
[inst
->bits1
.ia1
.dest_reg_type
]);
556 if (inst
->bits1
.ia1
.dest_indirect_offset
)
557 format (file
, " %d", inst
->bits1
.ia1
.dest_indirect_offset
);
559 err
|= control (file
, "horiz stride", horiz_stride
, inst
->bits1
.ia1
.dest_horiz_stride
, NULL
);
561 err
|= control (file
, "dest reg encoding", reg_encoding
, inst
->bits1
.ia1
.dest_reg_type
, NULL
);
566 if (inst
->bits1
.da16
.dest_address_mode
== BRW_ADDRESS_DIRECT
)
568 err
|= reg (file
, inst
->bits1
.da16
.dest_reg_file
, inst
->bits1
.da16
.dest_reg_nr
);
571 if (inst
->bits1
.da16
.dest_subreg_nr
)
572 format (file
, ".%d", inst
->bits1
.da16
.dest_subreg_nr
/
573 reg_type_size
[inst
->bits1
.da16
.dest_reg_type
]);
574 string (file
, "<1>");
575 err
|= control (file
, "writemask", writemask
, inst
->bits1
.da16
.dest_writemask
, NULL
);
576 err
|= control (file
, "dest reg encoding", reg_encoding
, inst
->bits1
.da16
.dest_reg_type
, NULL
);
581 string (file
, "Indirect align16 address mode not supported");
588 static int dest_3src (FILE *file
, struct brw_instruction
*inst
)
593 if (inst
->bits1
.da3src
.dest_reg_file
)
594 reg_file
= BRW_MESSAGE_REGISTER_FILE
;
596 reg_file
= BRW_GENERAL_REGISTER_FILE
;
598 err
|= reg (file
, reg_file
, inst
->bits1
.da3src
.dest_reg_nr
);
601 if (inst
->bits1
.da3src
.dest_subreg_nr
)
602 format (file
, ".%d", inst
->bits1
.da3src
.dest_subreg_nr
);
603 string (file
, "<1>");
604 err
|= control (file
, "writemask", writemask
, inst
->bits1
.da3src
.dest_writemask
, NULL
);
605 err
|= control (file
, "dest reg encoding", three_source_reg_encoding
,
606 inst
->bits1
.da3src
.dst_type
, NULL
);
611 static int src_align1_region (FILE *file
,
612 unsigned _vert_stride
, unsigned _width
, unsigned _horiz_stride
)
616 err
|= control (file
, "vert stride", vert_stride
, _vert_stride
, NULL
);
618 err
|= control (file
, "width", width
, _width
, NULL
);
620 err
|= control (file
, "horiz_stride", horiz_stride
, _horiz_stride
, NULL
);
625 static int src_da1 (FILE *file
, unsigned type
, unsigned _reg_file
,
626 unsigned _vert_stride
, unsigned _width
, unsigned _horiz_stride
,
627 unsigned reg_num
, unsigned sub_reg_num
, unsigned __abs
, unsigned _negate
)
630 err
|= control (file
, "negate", negate
, _negate
, NULL
);
631 err
|= control (file
, "abs", _abs
, __abs
, NULL
);
633 err
|= reg (file
, _reg_file
, reg_num
);
637 format (file
, ".%d", sub_reg_num
/ reg_type_size
[type
]); /* use formal style like spec */
638 src_align1_region (file
, _vert_stride
, _width
, _horiz_stride
);
639 err
|= control (file
, "src reg encoding", reg_encoding
, type
, NULL
);
643 static int src_ia1 (FILE *file
,
647 unsigned _addr_subreg_nr
,
651 unsigned _horiz_stride
,
653 unsigned _vert_stride
)
656 err
|= control (file
, "negate", negate
, _negate
, NULL
);
657 err
|= control (file
, "abs", _abs
, __abs
, NULL
);
659 string (file
, "g[a0");
661 format (file
, ".%d", _addr_subreg_nr
);
663 format (file
, " %d", _addr_imm
);
665 src_align1_region (file
, _vert_stride
, _width
, _horiz_stride
);
666 err
|= control (file
, "src reg encoding", reg_encoding
, type
, NULL
);
670 static int src_da16 (FILE *file
,
673 unsigned _vert_stride
,
684 err
|= control (file
, "negate", negate
, _negate
, NULL
);
685 err
|= control (file
, "abs", _abs
, __abs
, NULL
);
687 err
|= reg (file
, _reg_file
, _reg_nr
);
691 /* bit4 for subreg number byte addressing. Make this same meaning as
692 in da1 case, so output looks consistent. */
693 format (file
, ".%d", 16 / reg_type_size
[_reg_type
]);
695 err
|= control (file
, "vert stride", vert_stride
, _vert_stride
, NULL
);
696 string (file
, ",4,1>");
698 * Three kinds of swizzle display:
699 * identity - nothing printed
700 * 1->all - print the single channel
701 * 1->1 - print the mapping
703 if (swz_x
== BRW_CHANNEL_X
&&
704 swz_y
== BRW_CHANNEL_Y
&&
705 swz_z
== BRW_CHANNEL_Z
&&
706 swz_w
== BRW_CHANNEL_W
)
710 else if (swz_x
== swz_y
&& swz_x
== swz_z
&& swz_x
== swz_w
)
713 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
718 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
719 err
|= control (file
, "channel select", chan_sel
, swz_y
, NULL
);
720 err
|= control (file
, "channel select", chan_sel
, swz_z
, NULL
);
721 err
|= control (file
, "channel select", chan_sel
, swz_w
, NULL
);
723 err
|= control (file
, "src da16 reg type", reg_encoding
, _reg_type
, NULL
);
727 static int src0_3src (FILE *file
, struct brw_instruction
*inst
)
730 unsigned swz_x
= (inst
->bits2
.da3src
.src0_swizzle
>> 0) & 0x3;
731 unsigned swz_y
= (inst
->bits2
.da3src
.src0_swizzle
>> 2) & 0x3;
732 unsigned swz_z
= (inst
->bits2
.da3src
.src0_swizzle
>> 4) & 0x3;
733 unsigned swz_w
= (inst
->bits2
.da3src
.src0_swizzle
>> 6) & 0x3;
735 err
|= control (file
, "negate", negate
, inst
->bits1
.da3src
.src0_negate
, NULL
);
736 err
|= control (file
, "abs", _abs
, inst
->bits1
.da3src
.src0_abs
, NULL
);
738 err
|= reg (file
, BRW_GENERAL_REGISTER_FILE
, inst
->bits2
.da3src
.src0_reg_nr
);
741 if (inst
->bits2
.da3src
.src0_subreg_nr
)
742 format (file
, ".%d", inst
->bits2
.da3src
.src0_subreg_nr
);
743 if (inst
->bits2
.da3src
.src0_rep_ctrl
)
744 string (file
, "<0,1,0>");
746 string (file
, "<4,4,1>");
747 err
|= control (file
, "src da16 reg type", three_source_reg_encoding
,
748 inst
->bits1
.da3src
.src_type
, NULL
);
750 * Three kinds of swizzle display:
751 * identity - nothing printed
752 * 1->all - print the single channel
753 * 1->1 - print the mapping
755 if (swz_x
== BRW_CHANNEL_X
&&
756 swz_y
== BRW_CHANNEL_Y
&&
757 swz_z
== BRW_CHANNEL_Z
&&
758 swz_w
== BRW_CHANNEL_W
)
762 else if (swz_x
== swz_y
&& swz_x
== swz_z
&& swz_x
== swz_w
)
765 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
770 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
771 err
|= control (file
, "channel select", chan_sel
, swz_y
, NULL
);
772 err
|= control (file
, "channel select", chan_sel
, swz_z
, NULL
);
773 err
|= control (file
, "channel select", chan_sel
, swz_w
, NULL
);
778 static int src1_3src (FILE *file
, struct brw_instruction
*inst
)
781 unsigned swz_x
= (inst
->bits2
.da3src
.src1_swizzle
>> 0) & 0x3;
782 unsigned swz_y
= (inst
->bits2
.da3src
.src1_swizzle
>> 2) & 0x3;
783 unsigned swz_z
= (inst
->bits2
.da3src
.src1_swizzle
>> 4) & 0x3;
784 unsigned swz_w
= (inst
->bits2
.da3src
.src1_swizzle
>> 6) & 0x3;
785 unsigned src1_subreg_nr
= (inst
->bits2
.da3src
.src1_subreg_nr_low
|
786 (inst
->bits3
.da3src
.src1_subreg_nr_high
<< 2));
788 err
|= control (file
, "negate", negate
, inst
->bits1
.da3src
.src1_negate
,
790 err
|= control (file
, "abs", _abs
, inst
->bits1
.da3src
.src1_abs
, NULL
);
792 err
|= reg (file
, BRW_GENERAL_REGISTER_FILE
,
793 inst
->bits3
.da3src
.src1_reg_nr
);
797 format (file
, ".%d", src1_subreg_nr
);
798 if (inst
->bits2
.da3src
.src1_rep_ctrl
)
799 string (file
, "<0,1,0>");
801 string (file
, "<4,4,1>");
802 err
|= control (file
, "src da16 reg type", three_source_reg_encoding
,
803 inst
->bits1
.da3src
.src_type
, NULL
);
805 * Three kinds of swizzle display:
806 * identity - nothing printed
807 * 1->all - print the single channel
808 * 1->1 - print the mapping
810 if (swz_x
== BRW_CHANNEL_X
&&
811 swz_y
== BRW_CHANNEL_Y
&&
812 swz_z
== BRW_CHANNEL_Z
&&
813 swz_w
== BRW_CHANNEL_W
)
817 else if (swz_x
== swz_y
&& swz_x
== swz_z
&& swz_x
== swz_w
)
820 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
825 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
826 err
|= control (file
, "channel select", chan_sel
, swz_y
, NULL
);
827 err
|= control (file
, "channel select", chan_sel
, swz_z
, NULL
);
828 err
|= control (file
, "channel select", chan_sel
, swz_w
, NULL
);
834 static int src2_3src (FILE *file
, struct brw_instruction
*inst
)
837 unsigned swz_x
= (inst
->bits3
.da3src
.src2_swizzle
>> 0) & 0x3;
838 unsigned swz_y
= (inst
->bits3
.da3src
.src2_swizzle
>> 2) & 0x3;
839 unsigned swz_z
= (inst
->bits3
.da3src
.src2_swizzle
>> 4) & 0x3;
840 unsigned swz_w
= (inst
->bits3
.da3src
.src2_swizzle
>> 6) & 0x3;
842 err
|= control (file
, "negate", negate
, inst
->bits1
.da3src
.src2_negate
,
844 err
|= control (file
, "abs", _abs
, inst
->bits1
.da3src
.src2_abs
, NULL
);
846 err
|= reg (file
, BRW_GENERAL_REGISTER_FILE
,
847 inst
->bits3
.da3src
.src2_reg_nr
);
850 if (inst
->bits3
.da3src
.src2_subreg_nr
)
851 format (file
, ".%d", inst
->bits3
.da3src
.src2_subreg_nr
);
852 if (inst
->bits3
.da3src
.src2_rep_ctrl
)
853 string (file
, "<0,1,0>");
855 string (file
, "<4,4,1>");
856 err
|= control (file
, "src da16 reg type", three_source_reg_encoding
,
857 inst
->bits1
.da3src
.src_type
, NULL
);
859 * Three kinds of swizzle display:
860 * identity - nothing printed
861 * 1->all - print the single channel
862 * 1->1 - print the mapping
864 if (swz_x
== BRW_CHANNEL_X
&&
865 swz_y
== BRW_CHANNEL_Y
&&
866 swz_z
== BRW_CHANNEL_Z
&&
867 swz_w
== BRW_CHANNEL_W
)
871 else if (swz_x
== swz_y
&& swz_x
== swz_z
&& swz_x
== swz_w
)
874 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
879 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
880 err
|= control (file
, "channel select", chan_sel
, swz_y
, NULL
);
881 err
|= control (file
, "channel select", chan_sel
, swz_z
, NULL
);
882 err
|= control (file
, "channel select", chan_sel
, swz_w
, NULL
);
887 static int imm (FILE *file
, unsigned type
, struct brw_instruction
*inst
) {
889 case BRW_HW_REG_TYPE_UD
:
890 format (file
, "0x%08xUD", inst
->bits3
.ud
);
892 case BRW_HW_REG_TYPE_D
:
893 format (file
, "%dD", inst
->bits3
.d
);
895 case BRW_HW_REG_TYPE_UW
:
896 format (file
, "0x%04xUW", (uint16_t) inst
->bits3
.ud
);
898 case BRW_HW_REG_TYPE_W
:
899 format (file
, "%dW", (int16_t) inst
->bits3
.d
);
901 case BRW_HW_REG_IMM_TYPE_UV
:
902 format (file
, "0x%08xUV", inst
->bits3
.ud
);
904 case BRW_HW_REG_IMM_TYPE_VF
:
905 format (file
, "Vector Float");
907 case BRW_HW_REG_IMM_TYPE_V
:
908 format (file
, "0x%08xV", inst
->bits3
.ud
);
910 case BRW_HW_REG_TYPE_F
:
911 format (file
, "%-gF", inst
->bits3
.f
);
916 static int src0 (FILE *file
, struct brw_instruction
*inst
)
918 if (inst
->bits1
.da1
.src0_reg_file
== BRW_IMMEDIATE_VALUE
)
919 return imm (file
, inst
->bits1
.da1
.src0_reg_type
,
921 else if (inst
->header
.access_mode
== BRW_ALIGN_1
)
923 if (inst
->bits2
.da1
.src0_address_mode
== BRW_ADDRESS_DIRECT
)
925 return src_da1 (file
,
926 inst
->bits1
.da1
.src0_reg_type
,
927 inst
->bits1
.da1
.src0_reg_file
,
928 inst
->bits2
.da1
.src0_vert_stride
,
929 inst
->bits2
.da1
.src0_width
,
930 inst
->bits2
.da1
.src0_horiz_stride
,
931 inst
->bits2
.da1
.src0_reg_nr
,
932 inst
->bits2
.da1
.src0_subreg_nr
,
933 inst
->bits2
.da1
.src0_abs
,
934 inst
->bits2
.da1
.src0_negate
);
938 return src_ia1 (file
,
939 inst
->bits1
.ia1
.src0_reg_type
,
940 inst
->bits1
.ia1
.src0_reg_file
,
941 inst
->bits2
.ia1
.src0_indirect_offset
,
942 inst
->bits2
.ia1
.src0_subreg_nr
,
943 inst
->bits2
.ia1
.src0_negate
,
944 inst
->bits2
.ia1
.src0_abs
,
945 inst
->bits2
.ia1
.src0_address_mode
,
946 inst
->bits2
.ia1
.src0_horiz_stride
,
947 inst
->bits2
.ia1
.src0_width
,
948 inst
->bits2
.ia1
.src0_vert_stride
);
953 if (inst
->bits2
.da16
.src0_address_mode
== BRW_ADDRESS_DIRECT
)
955 return src_da16 (file
,
956 inst
->bits1
.da16
.src0_reg_type
,
957 inst
->bits1
.da16
.src0_reg_file
,
958 inst
->bits2
.da16
.src0_vert_stride
,
959 inst
->bits2
.da16
.src0_reg_nr
,
960 inst
->bits2
.da16
.src0_subreg_nr
,
961 inst
->bits2
.da16
.src0_abs
,
962 inst
->bits2
.da16
.src0_negate
,
963 inst
->bits2
.da16
.src0_swz_x
,
964 inst
->bits2
.da16
.src0_swz_y
,
965 inst
->bits2
.da16
.src0_swz_z
,
966 inst
->bits2
.da16
.src0_swz_w
);
970 string (file
, "Indirect align16 address mode not supported");
976 static int src1 (FILE *file
, struct brw_instruction
*inst
)
978 if (inst
->bits1
.da1
.src1_reg_file
== BRW_IMMEDIATE_VALUE
)
979 return imm (file
, inst
->bits1
.da1
.src1_reg_type
,
981 else if (inst
->header
.access_mode
== BRW_ALIGN_1
)
983 if (inst
->bits3
.da1
.src1_address_mode
== BRW_ADDRESS_DIRECT
)
985 return src_da1 (file
,
986 inst
->bits1
.da1
.src1_reg_type
,
987 inst
->bits1
.da1
.src1_reg_file
,
988 inst
->bits3
.da1
.src1_vert_stride
,
989 inst
->bits3
.da1
.src1_width
,
990 inst
->bits3
.da1
.src1_horiz_stride
,
991 inst
->bits3
.da1
.src1_reg_nr
,
992 inst
->bits3
.da1
.src1_subreg_nr
,
993 inst
->bits3
.da1
.src1_abs
,
994 inst
->bits3
.da1
.src1_negate
);
998 return src_ia1 (file
,
999 inst
->bits1
.ia1
.src1_reg_type
,
1000 inst
->bits1
.ia1
.src1_reg_file
,
1001 inst
->bits3
.ia1
.src1_indirect_offset
,
1002 inst
->bits3
.ia1
.src1_subreg_nr
,
1003 inst
->bits3
.ia1
.src1_negate
,
1004 inst
->bits3
.ia1
.src1_abs
,
1005 inst
->bits3
.ia1
.src1_address_mode
,
1006 inst
->bits3
.ia1
.src1_horiz_stride
,
1007 inst
->bits3
.ia1
.src1_width
,
1008 inst
->bits3
.ia1
.src1_vert_stride
);
1013 if (inst
->bits3
.da16
.src1_address_mode
== BRW_ADDRESS_DIRECT
)
1015 return src_da16 (file
,
1016 inst
->bits1
.da16
.src1_reg_type
,
1017 inst
->bits1
.da16
.src1_reg_file
,
1018 inst
->bits3
.da16
.src1_vert_stride
,
1019 inst
->bits3
.da16
.src1_reg_nr
,
1020 inst
->bits3
.da16
.src1_subreg_nr
,
1021 inst
->bits3
.da16
.src1_abs
,
1022 inst
->bits3
.da16
.src1_negate
,
1023 inst
->bits3
.da16
.src1_swz_x
,
1024 inst
->bits3
.da16
.src1_swz_y
,
1025 inst
->bits3
.da16
.src1_swz_z
,
1026 inst
->bits3
.da16
.src1_swz_w
);
1030 string (file
, "Indirect align16 address mode not supported");
1045 static int qtr_ctrl(FILE *file
, struct brw_instruction
*inst
)
1047 int qtr_ctl
= inst
->header
.compression_control
;
1048 int exec_size
= esize
[inst
->header
.execution_size
];
1050 if (exec_size
== 8) {
1053 string (file
, " 1Q");
1056 string (file
, " 2Q");
1059 string (file
, " 3Q");
1062 string (file
, " 4Q");
1065 } else if (exec_size
== 16){
1067 string (file
, " 1H");
1069 string (file
, " 2H");
1074 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
)
1079 if (inst
->header
.predicate_control
) {
1081 err
|= control (file
, "predicate inverse", pred_inv
, inst
->header
.predicate_inverse
, NULL
);
1082 format (file
, "f%d", gen
>= 7 ? inst
->bits2
.da1
.flag_reg_nr
: 0);
1083 if (inst
->bits2
.da1
.flag_subreg_nr
)
1084 format (file
, ".%d", inst
->bits2
.da1
.flag_subreg_nr
);
1085 if (inst
->header
.access_mode
== BRW_ALIGN_1
)
1086 err
|= control (file
, "predicate control align1", pred_ctrl_align1
,
1087 inst
->header
.predicate_control
, NULL
);
1089 err
|= control (file
, "predicate control align16", pred_ctrl_align16
,
1090 inst
->header
.predicate_control
, NULL
);
1091 string (file
, ") ");
1094 err
|= print_opcode (file
, inst
->header
.opcode
);
1095 err
|= control (file
, "saturate", saturate
, inst
->header
.saturate
, NULL
);
1096 err
|= control (file
, "debug control", debug_ctrl
, inst
->header
.debug_control
, NULL
);
1098 if (inst
->header
.opcode
== BRW_OPCODE_MATH
) {
1100 err
|= control (file
, "function", math_function
,
1101 inst
->header
.destreg__conditionalmod
, NULL
);
1102 } else if (inst
->header
.opcode
!= BRW_OPCODE_SEND
&&
1103 inst
->header
.opcode
!= BRW_OPCODE_SENDC
) {
1104 err
|= control (file
, "conditional modifier", conditional_modifier
,
1105 inst
->header
.destreg__conditionalmod
, NULL
);
1107 /* If we're using the conditional modifier, print which flags reg is
1108 * used for it. Note that on gen6+, the embedded-condition SEL and
1109 * control flow doesn't update flags.
1111 if (inst
->header
.destreg__conditionalmod
&&
1112 (gen
< 6 || (inst
->header
.opcode
!= BRW_OPCODE_SEL
&&
1113 inst
->header
.opcode
!= BRW_OPCODE_IF
&&
1114 inst
->header
.opcode
!= BRW_OPCODE_WHILE
))) {
1115 format (file
, ".f%d", gen
>= 7 ? inst
->bits2
.da1
.flag_reg_nr
: 0);
1116 if (inst
->bits2
.da1
.flag_subreg_nr
)
1117 format (file
, ".%d", inst
->bits2
.da1
.flag_subreg_nr
);
1121 if (inst
->header
.opcode
!= BRW_OPCODE_NOP
) {
1123 err
|= control (file
, "execution size", exec_size
, inst
->header
.execution_size
, NULL
);
1127 if (inst
->header
.opcode
== BRW_OPCODE_SEND
&& gen
< 6)
1128 format (file
, " %d", inst
->header
.destreg__conditionalmod
);
1130 if (opcode
[inst
->header
.opcode
].nsrc
== 3) {
1132 err
|= dest_3src (file
, inst
);
1135 err
|= src0_3src (file
, inst
);
1138 err
|= src1_3src (file
, inst
);
1141 err
|= src2_3src (file
, inst
);
1143 if (opcode
[inst
->header
.opcode
].ndst
> 0) {
1145 err
|= dest (file
, inst
);
1146 } else if (gen
== 7 && (inst
->header
.opcode
== BRW_OPCODE_ELSE
||
1147 inst
->header
.opcode
== BRW_OPCODE_ENDIF
||
1148 inst
->header
.opcode
== BRW_OPCODE_WHILE
)) {
1149 format (file
, " %d", inst
->bits3
.break_cont
.jip
);
1150 } else if (gen
== 6 && (inst
->header
.opcode
== BRW_OPCODE_IF
||
1151 inst
->header
.opcode
== BRW_OPCODE_ELSE
||
1152 inst
->header
.opcode
== BRW_OPCODE_ENDIF
||
1153 inst
->header
.opcode
== BRW_OPCODE_WHILE
)) {
1154 format (file
, " %d", inst
->bits1
.branch_gen6
.jump_count
);
1155 } else if ((gen
>= 6 && (inst
->header
.opcode
== BRW_OPCODE_BREAK
||
1156 inst
->header
.opcode
== BRW_OPCODE_CONTINUE
||
1157 inst
->header
.opcode
== BRW_OPCODE_HALT
)) ||
1158 (gen
== 7 && inst
->header
.opcode
== BRW_OPCODE_IF
)) {
1159 format (file
, " %d %d", inst
->bits3
.break_cont
.uip
, inst
->bits3
.break_cont
.jip
);
1160 } else if (inst
->header
.opcode
== BRW_OPCODE_JMPI
) {
1161 format (file
, " %d", inst
->bits3
.d
);
1164 if (opcode
[inst
->header
.opcode
].nsrc
> 0) {
1166 err
|= src0 (file
, inst
);
1168 if (opcode
[inst
->header
.opcode
].nsrc
> 1) {
1170 err
|= src1 (file
, inst
);
1174 if (inst
->header
.opcode
== BRW_OPCODE_SEND
||
1175 inst
->header
.opcode
== BRW_OPCODE_SENDC
) {
1176 enum brw_message_target target
;
1179 target
= inst
->header
.destreg__conditionalmod
;
1181 target
= inst
->bits2
.send_gen5
.sfid
;
1183 target
= inst
->bits3
.generic
.msg_target
;
1190 err
|= control (file
, "target function", target_function_gen6
,
1193 err
|= control (file
, "target function", target_function
,
1199 err
|= control (file
, "math function", math_function
,
1200 inst
->bits3
.math
.function
, &space
);
1201 err
|= control (file
, "math saturate", math_saturate
,
1202 inst
->bits3
.math
.saturate
, &space
);
1203 err
|= control (file
, "math signed", math_signed
,
1204 inst
->bits3
.math
.int_type
, &space
);
1205 err
|= control (file
, "math scalar", math_scalar
,
1206 inst
->bits3
.math
.data_type
, &space
);
1207 err
|= control (file
, "math precision", math_precision
,
1208 inst
->bits3
.math
.precision
, &space
);
1210 case BRW_SFID_SAMPLER
:
1212 format (file
, " (%d, %d, %d, %d)",
1213 inst
->bits3
.sampler_gen7
.binding_table_index
,
1214 inst
->bits3
.sampler_gen7
.sampler
,
1215 inst
->bits3
.sampler_gen7
.msg_type
,
1216 inst
->bits3
.sampler_gen7
.simd_mode
);
1217 } else if (gen
>= 5) {
1218 format (file
, " (%d, %d, %d, %d)",
1219 inst
->bits3
.sampler_gen5
.binding_table_index
,
1220 inst
->bits3
.sampler_gen5
.sampler
,
1221 inst
->bits3
.sampler_gen5
.msg_type
,
1222 inst
->bits3
.sampler_gen5
.simd_mode
);
1223 } else if (0 /* FINISHME: is_g4x */) {
1224 format (file
, " (%d, %d)",
1225 inst
->bits3
.sampler_g4x
.binding_table_index
,
1226 inst
->bits3
.sampler_g4x
.sampler
);
1228 format (file
, " (%d, %d, ",
1229 inst
->bits3
.sampler
.binding_table_index
,
1230 inst
->bits3
.sampler
.sampler
);
1231 err
|= control (file
, "sampler target format",
1232 sampler_target_format
,
1233 inst
->bits3
.sampler
.return_format
, NULL
);
1237 case BRW_SFID_DATAPORT_READ
:
1239 format (file
, " (%d, %d, %d, %d)",
1240 inst
->bits3
.gen6_dp
.binding_table_index
,
1241 inst
->bits3
.gen6_dp
.msg_control
,
1242 inst
->bits3
.gen6_dp
.msg_type
,
1243 inst
->bits3
.gen6_dp
.send_commit_msg
);
1244 } else if (gen
>= 5 /* FINISHME: || is_g4x */) {
1245 format (file
, " (%d, %d, %d)",
1246 inst
->bits3
.dp_read_gen5
.binding_table_index
,
1247 inst
->bits3
.dp_read_gen5
.msg_control
,
1248 inst
->bits3
.dp_read_gen5
.msg_type
);
1250 format (file
, " (%d, %d, %d)",
1251 inst
->bits3
.dp_read
.binding_table_index
,
1252 inst
->bits3
.dp_read
.msg_control
,
1253 inst
->bits3
.dp_read
.msg_type
);
1257 case BRW_SFID_DATAPORT_WRITE
:
1259 format (file
, " (");
1261 err
|= control (file
, "DP rc message type",
1262 dp_rc_msg_type_gen6
,
1263 inst
->bits3
.gen7_dp
.msg_type
, &space
);
1265 format (file
, ", %d, %d, %d)",
1266 inst
->bits3
.gen7_dp
.binding_table_index
,
1267 inst
->bits3
.gen7_dp
.msg_control
,
1268 inst
->bits3
.gen7_dp
.msg_type
);
1269 } else if (gen
== 6) {
1270 format (file
, " (");
1272 err
|= control (file
, "DP rc message type",
1273 dp_rc_msg_type_gen6
,
1274 inst
->bits3
.gen6_dp
.msg_type
, &space
);
1276 format (file
, ", %d, %d, %d, %d)",
1277 inst
->bits3
.gen6_dp
.binding_table_index
,
1278 inst
->bits3
.gen6_dp
.msg_control
,
1279 inst
->bits3
.gen6_dp
.msg_type
,
1280 inst
->bits3
.gen6_dp
.send_commit_msg
);
1282 format (file
, " (%d, %d, %d, %d)",
1283 inst
->bits3
.dp_write
.binding_table_index
,
1284 (inst
->bits3
.dp_write
.last_render_target
<< 3) |
1285 inst
->bits3
.dp_write
.msg_control
,
1286 inst
->bits3
.dp_write
.msg_type
,
1287 inst
->bits3
.dp_write
.send_commit_msg
);
1293 format (file
, " %d", inst
->bits3
.urb_gen5
.offset
);
1295 format (file
, " %d", inst
->bits3
.urb
.offset
);
1300 err
|= control (file
, "urb opcode", urb_opcode
,
1301 inst
->bits3
.urb_gen5
.opcode
, &space
);
1303 err
|= control (file
, "urb swizzle", urb_swizzle
,
1304 inst
->bits3
.urb
.swizzle_control
, &space
);
1305 err
|= control (file
, "urb allocate", urb_allocate
,
1306 inst
->bits3
.urb
.allocate
, &space
);
1307 err
|= control (file
, "urb used", urb_used
,
1308 inst
->bits3
.urb
.used
, &space
);
1309 err
|= control (file
, "urb complete", urb_complete
,
1310 inst
->bits3
.urb
.complete
, &space
);
1312 case BRW_SFID_THREAD_SPAWNER
:
1314 case GEN7_SFID_DATAPORT_DATA_CACHE
:
1315 format (file
, " (%d, %d, %d)",
1316 inst
->bits3
.gen7_dp
.binding_table_index
,
1317 inst
->bits3
.gen7_dp
.msg_control
,
1318 inst
->bits3
.gen7_dp
.msg_type
);
1323 format (file
, "unsupported target %d", target
);
1329 format (file
, "mlen %d",
1330 inst
->bits3
.generic_gen5
.msg_length
);
1331 format (file
, " rlen %d",
1332 inst
->bits3
.generic_gen5
.response_length
);
1334 format (file
, "mlen %d",
1335 inst
->bits3
.generic
.msg_length
);
1336 format (file
, " rlen %d",
1337 inst
->bits3
.generic
.response_length
);
1341 if (inst
->header
.opcode
!= BRW_OPCODE_NOP
) {
1344 err
|= control(file
, "access mode", access_mode
, inst
->header
.access_mode
, &space
);
1346 err
|= control (file
, "write enable control", wectrl
, inst
->header
.mask_control
, &space
);
1348 err
|= control (file
, "mask control", mask_ctrl
, inst
->header
.mask_control
, &space
);
1349 err
|= control (file
, "dependency control", dep_ctrl
, inst
->header
.dependency_control
, &space
);
1352 err
|= qtr_ctrl (file
, inst
);
1354 if (inst
->header
.compression_control
== BRW_COMPRESSION_COMPRESSED
&&
1355 opcode
[inst
->header
.opcode
].ndst
> 0 &&
1356 inst
->bits1
.da1
.dest_reg_file
== BRW_MESSAGE_REGISTER_FILE
&&
1357 inst
->bits1
.da1
.dest_reg_nr
& (1 << 7)) {
1358 format (file
, " compr4");
1360 err
|= control (file
, "compression control", compr_ctrl
,
1361 inst
->header
.compression_control
, &space
);
1365 err
|= control (file
, "thread control", thread_ctrl
, inst
->header
.thread_control
, &space
);
1367 err
|= control (file
, "acc write control", accwr
, inst
->header
.acc_wr_control
, &space
);
1368 if (inst
->header
.opcode
== BRW_OPCODE_SEND
||
1369 inst
->header
.opcode
== BRW_OPCODE_SENDC
)
1370 err
|= control (file
, "end of thread", end_of_thread
,
1371 inst
->bits3
.generic
.end_of_thread
, &space
);