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b211a0f70d9436484566b325607ca626bb65f731
[mesa.git] / src / mesa / drivers / dri / i965 / brw_disasm.c
1 /*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23 #include <stdio.h>
24 #include <stdlib.h>
25 #include <string.h>
26 #include <getopt.h>
27 #include <unistd.h>
28 #include <stdarg.h>
29
30 #include "brw_context.h"
31 #include "brw_defines.h"
32 #include "brw_reg.h"
33 #include "brw_inst.h"
34
35 const struct opcode_desc opcode_descs[128] = {
36 [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 },
37 [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 },
38 [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 },
39 [BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 },
40 [BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 },
41 [BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 },
42 [BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 },
43 [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 },
44 [BRW_OPCODE_F32TO16] = { .name = "f32to16", .nsrc = 1, .ndst = 1 },
45 [BRW_OPCODE_F16TO32] = { .name = "f16to32", .nsrc = 1, .ndst = 1 },
46 [BRW_OPCODE_BFREV] = { .name = "bfrev", .nsrc = 1, .ndst = 1 },
47 [BRW_OPCODE_FBH] = { .name = "fbh", .nsrc = 1, .ndst = 1 },
48 [BRW_OPCODE_FBL] = { .name = "fbl", .nsrc = 1, .ndst = 1 },
49 [BRW_OPCODE_CBIT] = { .name = "cbit", .nsrc = 1, .ndst = 1 },
50
51 [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 },
52 [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 },
53 [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 },
54 [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 },
55 [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 },
56 [BRW_OPCODE_MAD] = { .name = "mad", .nsrc = 3, .ndst = 1 },
57 [BRW_OPCODE_LRP] = { .name = "lrp", .nsrc = 3, .ndst = 1 },
58 [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 },
59 [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 },
60 [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 },
61 [BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 },
62 [BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 },
63 [BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 },
64 [BRW_OPCODE_MATH] = { .name = "math", .nsrc = 2, .ndst = 1 },
65
66 [BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 },
67 [BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 },
68 [BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 },
69 [BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 },
70 [BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 },
71 [BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 },
72 [BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 },
73 [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 },
74 [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 },
75 [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 },
76 [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 },
77 [BRW_OPCODE_CSEL] = { .name = "csel", .nsrc = 3, .ndst = 1 },
78 [BRW_OPCODE_BFE] = { .name = "bfe", .nsrc = 3, .ndst = 1 },
79 [BRW_OPCODE_BFI1] = { .name = "bfi1", .nsrc = 2, .ndst = 1 },
80 [BRW_OPCODE_BFI2] = { .name = "bfi2", .nsrc = 3, .ndst = 1 },
81 [BRW_OPCODE_ADDC] = { .name = "addc", .nsrc = 2, .ndst = 1 },
82 [BRW_OPCODE_SUBB] = { .name = "subb", .nsrc = 2, .ndst = 1 },
83
84 [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 },
85 [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 },
86 [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
87 [BRW_OPCODE_NENOP] = { .name = "nenop", .nsrc = 0, .ndst = 0 },
88 [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 0, .ndst = 0 },
89 [BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 },
90 [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 2, .ndst = 1 },
91 [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 2, .ndst = 0 },
92 [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 2, .ndst = 0 },
93 [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 2, .ndst = 0 },
94 [BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 1, .ndst = 0 },
95 [BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 1, .ndst = 0 },
96 [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 },
97 [BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 },
98 [BRW_OPCODE_MRESTORE] = { .name = "mrest", .nsrc = 1, .ndst = 1 },
99 [BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 },
100 [BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 },
101 [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 },
102 [BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 2, .ndst = 0 },
103 };
104
105 static bool
106 has_jip(struct brw_context *brw, enum opcode opcode)
107 {
108 if (brw->gen < 6)
109 return false;
110
111 return opcode == BRW_OPCODE_IF ||
112 opcode == BRW_OPCODE_ELSE ||
113 opcode == BRW_OPCODE_ENDIF ||
114 opcode == BRW_OPCODE_WHILE ||
115 opcode == BRW_OPCODE_BREAK ||
116 opcode == BRW_OPCODE_CONTINUE ||
117 opcode == BRW_OPCODE_HALT;
118 }
119
120 static bool
121 has_uip(struct brw_context *brw, enum opcode opcode)
122 {
123 if (brw->gen < 6)
124 return false;
125
126 return (brw->gen >= 7 && opcode == BRW_OPCODE_IF) ||
127 (brw->gen >= 8 && opcode == BRW_OPCODE_ELSE) ||
128 opcode == BRW_OPCODE_BREAK ||
129 opcode == BRW_OPCODE_CONTINUE ||
130 opcode == BRW_OPCODE_HALT;
131 }
132
133 static bool
134 has_branch_ctrl(struct brw_context *brw, enum opcode opcode)
135 {
136 if (brw->gen < 8)
137 return false;
138
139 return opcode == BRW_OPCODE_IF ||
140 opcode == BRW_OPCODE_ELSE ||
141 opcode == BRW_OPCODE_GOTO;
142 }
143
144 static bool
145 is_logic_instruction(unsigned opcode)
146 {
147 return opcode == BRW_OPCODE_AND ||
148 opcode == BRW_OPCODE_NOT ||
149 opcode == BRW_OPCODE_OR ||
150 opcode == BRW_OPCODE_XOR;
151 }
152
153 const char *const conditional_modifier[16] = {
154 [BRW_CONDITIONAL_NONE] = "",
155 [BRW_CONDITIONAL_Z] = ".z",
156 [BRW_CONDITIONAL_NZ] = ".nz",
157 [BRW_CONDITIONAL_G] = ".g",
158 [BRW_CONDITIONAL_GE] = ".ge",
159 [BRW_CONDITIONAL_L] = ".l",
160 [BRW_CONDITIONAL_LE] = ".le",
161 [BRW_CONDITIONAL_R] = ".r",
162 [BRW_CONDITIONAL_O] = ".o",
163 [BRW_CONDITIONAL_U] = ".u",
164 };
165
166 static const char *const m_negate[2] = {
167 [0] = "",
168 [1] = "-",
169 };
170
171 static const char *const _abs[2] = {
172 [0] = "",
173 [1] = "(abs)",
174 };
175
176 static const char *const m_bitnot[2] = { "", "~" };
177
178 static const char *const vert_stride[16] = {
179 [0] = "0",
180 [1] = "1",
181 [2] = "2",
182 [3] = "4",
183 [4] = "8",
184 [5] = "16",
185 [6] = "32",
186 [15] = "VxH",
187 };
188
189 static const char *const width[8] = {
190 [0] = "1",
191 [1] = "2",
192 [2] = "4",
193 [3] = "8",
194 [4] = "16",
195 };
196
197 static const char *const horiz_stride[4] = {
198 [0] = "0",
199 [1] = "1",
200 [2] = "2",
201 [3] = "4"
202 };
203
204 static const char *const chan_sel[4] = {
205 [0] = "x",
206 [1] = "y",
207 [2] = "z",
208 [3] = "w",
209 };
210
211 static const char *const debug_ctrl[2] = {
212 [0] = "",
213 [1] = ".breakpoint"
214 };
215
216 static const char *const saturate[2] = {
217 [0] = "",
218 [1] = ".sat"
219 };
220
221 static const char *const cmpt_ctrl[2] = {
222 [0] = "",
223 [1] = "compacted"
224 };
225
226 static const char *const accwr[2] = {
227 [0] = "",
228 [1] = "AccWrEnable"
229 };
230
231 static const char *const branch_ctrl[2] = {
232 [0] = "",
233 [1] = "BranchCtrl"
234 };
235
236 static const char *const wectrl[2] = {
237 [0] = "",
238 [1] = "WE_all"
239 };
240
241 static const char *const exec_size[8] = {
242 [0] = "1",
243 [1] = "2",
244 [2] = "4",
245 [3] = "8",
246 [4] = "16",
247 [5] = "32"
248 };
249
250 static const char *const pred_inv[2] = {
251 [0] = "+",
252 [1] = "-"
253 };
254
255 static const char *const pred_ctrl_align16[16] = {
256 [1] = "",
257 [2] = ".x",
258 [3] = ".y",
259 [4] = ".z",
260 [5] = ".w",
261 [6] = ".any4h",
262 [7] = ".all4h",
263 };
264
265 static const char *const pred_ctrl_align1[16] = {
266 [BRW_PREDICATE_NORMAL] = "",
267 [BRW_PREDICATE_ALIGN1_ANYV] = ".anyv",
268 [BRW_PREDICATE_ALIGN1_ALLV] = ".allv",
269 [BRW_PREDICATE_ALIGN1_ANY2H] = ".any2h",
270 [BRW_PREDICATE_ALIGN1_ALL2H] = ".all2h",
271 [BRW_PREDICATE_ALIGN1_ANY4H] = ".any4h",
272 [BRW_PREDICATE_ALIGN1_ALL4H] = ".all4h",
273 [BRW_PREDICATE_ALIGN1_ANY8H] = ".any8h",
274 [BRW_PREDICATE_ALIGN1_ALL8H] = ".all8h",
275 [BRW_PREDICATE_ALIGN1_ANY16H] = ".any16h",
276 [BRW_PREDICATE_ALIGN1_ALL16H] = ".all16h",
277 [BRW_PREDICATE_ALIGN1_ANY32H] = ".any32h",
278 [BRW_PREDICATE_ALIGN1_ANY32H] = ".all32h",
279 };
280
281 static const char *const thread_ctrl[4] = {
282 [BRW_THREAD_NORMAL] = "",
283 [BRW_THREAD_ATOMIC] = "atomic",
284 [BRW_THREAD_SWITCH] = "switch",
285 };
286
287 static const char *const compr_ctrl[4] = {
288 [0] = "",
289 [1] = "sechalf",
290 [2] = "compr",
291 [3] = "compr4",
292 };
293
294 static const char *const dep_ctrl[4] = {
295 [0] = "",
296 [1] = "NoDDClr",
297 [2] = "NoDDChk",
298 [3] = "NoDDClr,NoDDChk",
299 };
300
301 static const char *const mask_ctrl[4] = {
302 [0] = "",
303 [1] = "nomask",
304 };
305
306 static const char *const access_mode[2] = {
307 [0] = "align1",
308 [1] = "align16",
309 };
310
311 static const char * const reg_encoding[] = {
312 [BRW_HW_REG_TYPE_UD] = "UD",
313 [BRW_HW_REG_TYPE_D] = "D",
314 [BRW_HW_REG_TYPE_UW] = "UW",
315 [BRW_HW_REG_TYPE_W] = "W",
316 [BRW_HW_REG_NON_IMM_TYPE_UB] = "UB",
317 [BRW_HW_REG_NON_IMM_TYPE_B] = "B",
318 [GEN7_HW_REG_NON_IMM_TYPE_DF] = "DF",
319 [BRW_HW_REG_TYPE_F] = "F",
320 [GEN8_HW_REG_TYPE_UQ] = "UQ",
321 [GEN8_HW_REG_TYPE_Q] = "Q",
322 [GEN8_HW_REG_NON_IMM_TYPE_HF] = "HF",
323 };
324
325 static const char *const three_source_reg_encoding[] = {
326 [BRW_3SRC_TYPE_F] = "F",
327 [BRW_3SRC_TYPE_D] = "D",
328 [BRW_3SRC_TYPE_UD] = "UD",
329 };
330
331 const int reg_type_size[] = {
332 [BRW_HW_REG_TYPE_UD] = 4,
333 [BRW_HW_REG_TYPE_D] = 4,
334 [BRW_HW_REG_TYPE_UW] = 2,
335 [BRW_HW_REG_TYPE_W] = 2,
336 [BRW_HW_REG_NON_IMM_TYPE_UB] = 1,
337 [BRW_HW_REG_NON_IMM_TYPE_B] = 1,
338 [GEN7_HW_REG_NON_IMM_TYPE_DF] = 8,
339 [BRW_HW_REG_TYPE_F] = 4,
340 [GEN8_HW_REG_TYPE_UQ] = 8,
341 [GEN8_HW_REG_TYPE_Q] = 8,
342 [GEN8_HW_REG_NON_IMM_TYPE_HF] = 2,
343 };
344
345 static const char *const reg_file[4] = {
346 [0] = "A",
347 [1] = "g",
348 [2] = "m",
349 [3] = "imm",
350 };
351
352 static const char *const writemask[16] = {
353 [0x0] = ".",
354 [0x1] = ".x",
355 [0x2] = ".y",
356 [0x3] = ".xy",
357 [0x4] = ".z",
358 [0x5] = ".xz",
359 [0x6] = ".yz",
360 [0x7] = ".xyz",
361 [0x8] = ".w",
362 [0x9] = ".xw",
363 [0xa] = ".yw",
364 [0xb] = ".xyw",
365 [0xc] = ".zw",
366 [0xd] = ".xzw",
367 [0xe] = ".yzw",
368 [0xf] = "",
369 };
370
371 static const char *const end_of_thread[2] = {
372 [0] = "",
373 [1] = "EOT"
374 };
375
376 /* SFIDs on Gen4-5 */
377 static const char *const gen4_sfid[16] = {
378 [BRW_SFID_NULL] = "null",
379 [BRW_SFID_MATH] = "math",
380 [BRW_SFID_SAMPLER] = "sampler",
381 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
382 [BRW_SFID_DATAPORT_READ] = "read",
383 [BRW_SFID_DATAPORT_WRITE] = "write",
384 [BRW_SFID_URB] = "urb",
385 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
386 [BRW_SFID_VME] = "vme",
387 };
388
389 static const char *const gen6_sfid[16] = {
390 [BRW_SFID_NULL] = "null",
391 [BRW_SFID_MATH] = "math",
392 [BRW_SFID_SAMPLER] = "sampler",
393 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
394 [BRW_SFID_URB] = "urb",
395 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
396 [GEN6_SFID_DATAPORT_SAMPLER_CACHE] = "sampler",
397 [GEN6_SFID_DATAPORT_RENDER_CACHE] = "render",
398 [GEN6_SFID_DATAPORT_CONSTANT_CACHE] = "const",
399 [GEN7_SFID_DATAPORT_DATA_CACHE] = "data",
400 [GEN7_SFID_PIXEL_INTERPOLATOR] = "pixel interp",
401 [HSW_SFID_DATAPORT_DATA_CACHE_1] = "dp data 1",
402 [HSW_SFID_CRE] = "cre",
403 };
404
405 static const char *const dp_write_port_msg_type[8] = {
406 [0b000] = "OWord block write",
407 [0b001] = "OWord dual block write",
408 [0b010] = "media block write",
409 [0b011] = "DWord scattered write",
410 [0b100] = "RT write",
411 [0b101] = "streamed VB write",
412 [0b110] = "RT UNORM write", /* G45+ */
413 [0b111] = "flush render cache",
414 };
415
416 static const char *const dp_rc_msg_type_gen6[16] = {
417 [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read",
418 [GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read",
419 [GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read",
420 [GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read",
421 [GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ] =
422 "OWORD unaligned block read",
423 [GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ] = "DWORD scattered read",
424 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE] = "DWORD atomic write",
425 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE] = "OWORD block write",
426 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE] =
427 "OWORD dual block write",
428 [GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE] = "media block write",
429 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE] =
430 "DWORD scattered write",
431 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write",
432 [GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write",
433 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORM write",
434 };
435
436 static const char *const m_rt_write_subtype[] = {
437 [0b000] = "SIMD16",
438 [0b001] = "SIMD16/RepData",
439 [0b010] = "SIMD8/DualSrcLow",
440 [0b011] = "SIMD8/DualSrcHigh",
441 [0b100] = "SIMD8",
442 [0b101] = "SIMD8/ImageWrite", /* Gen6+ */
443 [0b111] = "SIMD16/RepData-111", /* no idea how this is different than 1 */
444 };
445
446 static const char *const dp_dc0_msg_type_gen7[16] = {
447 [GEN7_DATAPORT_DC_OWORD_BLOCK_READ] = "DC OWORD block read",
448 [GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ] =
449 "DC unaligned OWORD block read",
450 [GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ] = "DC OWORD dual block read",
451 [GEN7_DATAPORT_DC_DWORD_SCATTERED_READ] = "DC DWORD scattered read",
452 [GEN7_DATAPORT_DC_BYTE_SCATTERED_READ] = "DC byte scattered read",
453 [GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ] = "DC untyped surface read",
454 [GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP] = "DC untyped atomic",
455 [GEN7_DATAPORT_DC_MEMORY_FENCE] = "DC mfence",
456 [GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE] = "DC OWORD block write",
457 [GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE] = "DC OWORD dual block write",
458 [GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE] = "DC DWORD scatterd write",
459 [GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE] = "DC byte scattered write",
460 [GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
461 };
462
463 static const char *const dp_dc1_msg_type_hsw[16] = {
464 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ] = "untyped surface read",
465 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP] = "DC untyped atomic op",
466 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2] =
467 "DC untyped 4x2 atomic op",
468 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ] = "DC media block read",
469 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ] = "DC typed surface read",
470 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP] = "DC typed atomic",
471 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2] = "DC typed 4x2 atomic op",
472 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
473 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE] = "DC media block write",
474 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP] = "DC atomic counter op",
475 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2] =
476 "DC 4x2 atomic counter op",
477 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE] = "DC typed surface write",
478 };
479
480 static const char *const aop[16] = {
481 [BRW_AOP_AND] = "and",
482 [BRW_AOP_OR] = "or",
483 [BRW_AOP_XOR] = "xor",
484 [BRW_AOP_MOV] = "mov",
485 [BRW_AOP_INC] = "inc",
486 [BRW_AOP_DEC] = "dec",
487 [BRW_AOP_ADD] = "add",
488 [BRW_AOP_SUB] = "sub",
489 [BRW_AOP_REVSUB] = "revsub",
490 [BRW_AOP_IMAX] = "imax",
491 [BRW_AOP_IMIN] = "imin",
492 [BRW_AOP_UMAX] = "umax",
493 [BRW_AOP_UMIN] = "umin",
494 [BRW_AOP_CMPWR] = "cmpwr",
495 [BRW_AOP_PREDEC] = "predec",
496 };
497
498 static const char * const pixel_interpolator_msg_types[4] = {
499 [GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET] = "per_message_offset",
500 [GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE] = "sample_position",
501 [GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID] = "centroid",
502 [GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET] = "per_slot_offset",
503 };
504
505 static const char *const math_function[16] = {
506 [BRW_MATH_FUNCTION_INV] = "inv",
507 [BRW_MATH_FUNCTION_LOG] = "log",
508 [BRW_MATH_FUNCTION_EXP] = "exp",
509 [BRW_MATH_FUNCTION_SQRT] = "sqrt",
510 [BRW_MATH_FUNCTION_RSQ] = "rsq",
511 [BRW_MATH_FUNCTION_SIN] = "sin",
512 [BRW_MATH_FUNCTION_COS] = "cos",
513 [BRW_MATH_FUNCTION_SINCOS] = "sincos",
514 [BRW_MATH_FUNCTION_FDIV] = "fdiv",
515 [BRW_MATH_FUNCTION_POW] = "pow",
516 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod",
517 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intdiv",
518 [BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod",
519 [GEN8_MATH_FUNCTION_INVM] = "invm",
520 [GEN8_MATH_FUNCTION_RSQRTM] = "rsqrtm",
521 };
522
523 static const char *const math_saturate[2] = {
524 [0] = "",
525 [1] = "sat"
526 };
527
528 static const char *const math_signed[2] = {
529 [0] = "",
530 [1] = "signed"
531 };
532
533 static const char *const math_scalar[2] = {
534 [0] = "",
535 [1] = "scalar"
536 };
537
538 static const char *const math_precision[2] = {
539 [0] = "",
540 [1] = "partial_precision"
541 };
542
543 static const char *const gen5_urb_opcode[] = {
544 [0] = "urb_write",
545 [1] = "ff_sync",
546 };
547
548 static const char *const gen7_urb_opcode[] = {
549 [0] = "write HWord",
550 [1] = "write OWord",
551 [2] = "read HWord",
552 [3] = "read OWord",
553 [4] = "atomic mov", /* Gen7+ */
554 [5] = "atomic inc", /* Gen7+ */
555 [6] = "atomic add", /* Gen8+ */
556 [7] = "SIMD8 write", /* Gen8+ */
557 [8] = "SIMD8 read", /* Gen8+ */
558 /* [9-15] - reserved */
559 };
560
561 static const char *const urb_swizzle[4] = {
562 [BRW_URB_SWIZZLE_NONE] = "",
563 [BRW_URB_SWIZZLE_INTERLEAVE] = "interleave",
564 [BRW_URB_SWIZZLE_TRANSPOSE] = "transpose",
565 };
566
567 static const char *const urb_allocate[2] = {
568 [0] = "",
569 [1] = "allocate"
570 };
571
572 static const char *const urb_used[2] = {
573 [0] = "",
574 [1] = "used"
575 };
576
577 static const char *const urb_complete[2] = {
578 [0] = "",
579 [1] = "complete"
580 };
581
582 static const char *const sampler_target_format[4] = {
583 [0] = "F",
584 [2] = "UD",
585 [3] = "D"
586 };
587
588
589 static int column;
590
591 static int
592 string(FILE *file, const char *string)
593 {
594 fputs(string, file);
595 column += strlen(string);
596 return 0;
597 }
598
599 static int
600 format(FILE *f, const char *format, ...)
601 {
602 char buf[1024];
603 va_list args;
604 va_start(args, format);
605
606 vsnprintf(buf, sizeof(buf) - 1, format, args);
607 va_end(args);
608 string(f, buf);
609 return 0;
610 }
611
612 static int
613 newline(FILE *f)
614 {
615 putc('\n', f);
616 column = 0;
617 return 0;
618 }
619
620 static int
621 pad(FILE *f, int c)
622 {
623 do
624 string(f, " ");
625 while (column < c);
626 return 0;
627 }
628
629 static int
630 control(FILE *file, const char *name, const char *const ctrl[],
631 unsigned id, int *space)
632 {
633 if (!ctrl[id]) {
634 fprintf(file, "*** invalid %s value %d ", name, id);
635 return 1;
636 }
637 if (ctrl[id][0]) {
638 if (space && *space)
639 string(file, " ");
640 string(file, ctrl[id]);
641 if (space)
642 *space = 1;
643 }
644 return 0;
645 }
646
647 static int
648 print_opcode(FILE *file, int id)
649 {
650 if (!opcode_descs[id].name) {
651 format(file, "*** invalid opcode value %d ", id);
652 return 1;
653 }
654 string(file, opcode_descs[id].name);
655 return 0;
656 }
657
658 static int
659 reg(FILE *file, unsigned _reg_file, unsigned _reg_nr)
660 {
661 int err = 0;
662
663 /* Clear the Compr4 instruction compression bit. */
664 if (_reg_file == BRW_MESSAGE_REGISTER_FILE)
665 _reg_nr &= ~(1 << 7);
666
667 if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
668 switch (_reg_nr & 0xf0) {
669 case BRW_ARF_NULL:
670 string(file, "null");
671 return -1;
672 case BRW_ARF_ADDRESS:
673 format(file, "a%d", _reg_nr & 0x0f);
674 break;
675 case BRW_ARF_ACCUMULATOR:
676 format(file, "acc%d", _reg_nr & 0x0f);
677 break;
678 case BRW_ARF_FLAG:
679 format(file, "f%d", _reg_nr & 0x0f);
680 break;
681 case BRW_ARF_MASK:
682 format(file, "mask%d", _reg_nr & 0x0f);
683 break;
684 case BRW_ARF_MASK_STACK:
685 format(file, "msd%d", _reg_nr & 0x0f);
686 break;
687 case BRW_ARF_STATE:
688 format(file, "sr%d", _reg_nr & 0x0f);
689 break;
690 case BRW_ARF_CONTROL:
691 format(file, "cr%d", _reg_nr & 0x0f);
692 break;
693 case BRW_ARF_NOTIFICATION_COUNT:
694 format(file, "n%d", _reg_nr & 0x0f);
695 break;
696 case BRW_ARF_IP:
697 string(file, "ip");
698 return -1;
699 break;
700 default:
701 format(file, "ARF%d", _reg_nr);
702 break;
703 }
704 } else {
705 err |= control(file, "src reg file", reg_file, _reg_file, NULL);
706 format(file, "%d", _reg_nr);
707 }
708 return err;
709 }
710
711 static int
712 dest(FILE *file, struct brw_context *brw, brw_inst *inst)
713 {
714 int err = 0;
715
716 if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
717 if (brw_inst_dst_address_mode(brw, inst) == BRW_ADDRESS_DIRECT) {
718 err |= reg(file, brw_inst_dst_reg_file(brw, inst),
719 brw_inst_dst_da_reg_nr(brw, inst));
720 if (err == -1)
721 return 0;
722 if (brw_inst_dst_da1_subreg_nr(brw, inst))
723 format(file, ".%d", brw_inst_dst_da1_subreg_nr(brw, inst) /
724 reg_type_size[brw_inst_dst_reg_type(brw, inst)]);
725 string(file, "<");
726 err |= control(file, "horiz stride", horiz_stride,
727 brw_inst_dst_hstride(brw, inst), NULL);
728 string(file, ">");
729 err |= control(file, "dest reg encoding", reg_encoding,
730 brw_inst_dst_reg_type(brw, inst), NULL);
731 } else {
732 string(file, "g[a0");
733 if (brw_inst_dst_ia_subreg_nr(brw, inst))
734 format(file, ".%d", brw_inst_dst_ia_subreg_nr(brw, inst) /
735 reg_type_size[brw_inst_dst_reg_type(brw, inst)]);
736 if (brw_inst_dst_ia1_addr_imm(brw, inst))
737 format(file, " %d", brw_inst_dst_ia1_addr_imm(brw, inst));
738 string(file, "]<");
739 err |= control(file, "horiz stride", horiz_stride,
740 brw_inst_dst_hstride(brw, inst), NULL);
741 string(file, ">");
742 err |= control(file, "dest reg encoding", reg_encoding,
743 brw_inst_dst_reg_type(brw, inst), NULL);
744 }
745 } else {
746 if (brw_inst_dst_address_mode(brw, inst) == BRW_ADDRESS_DIRECT) {
747 err |= reg(file, brw_inst_dst_reg_file(brw, inst),
748 brw_inst_dst_da_reg_nr(brw, inst));
749 if (err == -1)
750 return 0;
751 if (brw_inst_dst_da16_subreg_nr(brw, inst))
752 format(file, ".%d", brw_inst_dst_da16_subreg_nr(brw, inst) /
753 reg_type_size[brw_inst_dst_reg_type(brw, inst)]);
754 string(file, "<1>");
755 err |= control(file, "writemask", writemask,
756 brw_inst_da16_writemask(brw, inst), NULL);
757 err |= control(file, "dest reg encoding", reg_encoding,
758 brw_inst_dst_reg_type(brw, inst), NULL);
759 } else {
760 err = 1;
761 string(file, "Indirect align16 address mode not supported");
762 }
763 }
764
765 return 0;
766 }
767
768 static int
769 dest_3src(FILE *file, struct brw_context *brw, brw_inst *inst)
770 {
771 int err = 0;
772 uint32_t reg_file;
773
774 if (brw->gen == 6 && brw_inst_3src_dst_reg_file(brw, inst))
775 reg_file = BRW_MESSAGE_REGISTER_FILE;
776 else
777 reg_file = BRW_GENERAL_REGISTER_FILE;
778
779 err |= reg(file, reg_file, brw_inst_3src_dst_reg_nr(brw, inst));
780 if (err == -1)
781 return 0;
782 if (brw_inst_3src_dst_subreg_nr(brw, inst))
783 format(file, ".%d", brw_inst_3src_dst_subreg_nr(brw, inst));
784 string(file, "<1>");
785 err |= control(file, "writemask", writemask,
786 brw_inst_3src_dst_writemask(brw, inst), NULL);
787 err |= control(file, "dest reg encoding", three_source_reg_encoding,
788 brw_inst_3src_dst_type(brw, inst), NULL);
789
790 return 0;
791 }
792
793 static int
794 src_align1_region(FILE *file,
795 unsigned _vert_stride, unsigned _width,
796 unsigned _horiz_stride)
797 {
798 int err = 0;
799 string(file, "<");
800 err |= control(file, "vert stride", vert_stride, _vert_stride, NULL);
801 string(file, ",");
802 err |= control(file, "width", width, _width, NULL);
803 string(file, ",");
804 err |= control(file, "horiz_stride", horiz_stride, _horiz_stride, NULL);
805 string(file, ">");
806 return err;
807 }
808
809 static int
810 src_da1(FILE *file,
811 const struct brw_context *brw,
812 unsigned opcode,
813 unsigned type, unsigned _reg_file,
814 unsigned _vert_stride, unsigned _width, unsigned _horiz_stride,
815 unsigned reg_num, unsigned sub_reg_num, unsigned __abs,
816 unsigned _negate)
817 {
818 int err = 0;
819
820 if (brw->gen >= 8 && is_logic_instruction(opcode))
821 err |= control(file, "bitnot", m_bitnot, _negate, NULL);
822 else
823 err |= control(file, "negate", m_negate, _negate, NULL);
824
825 err |= control(file, "abs", _abs, __abs, NULL);
826
827 err |= reg(file, _reg_file, reg_num);
828 if (err == -1)
829 return 0;
830 if (sub_reg_num)
831 format(file, ".%d", sub_reg_num / reg_type_size[type]); /* use formal style like spec */
832 src_align1_region(file, _vert_stride, _width, _horiz_stride);
833 err |= control(file, "src reg encoding", reg_encoding, type, NULL);
834 return err;
835 }
836
837 static int
838 src_ia1(FILE *file,
839 const struct brw_context *brw,
840 unsigned opcode,
841 unsigned type,
842 unsigned _reg_file,
843 int _addr_imm,
844 unsigned _addr_subreg_nr,
845 unsigned _negate,
846 unsigned __abs,
847 unsigned _addr_mode,
848 unsigned _horiz_stride, unsigned _width, unsigned _vert_stride)
849 {
850 int err = 0;
851
852 if (brw->gen >= 8 && is_logic_instruction(opcode))
853 err |= control(file, "bitnot", m_bitnot, _negate, NULL);
854 else
855 err |= control(file, "negate", m_negate, _negate, NULL);
856
857 err |= control(file, "abs", _abs, __abs, NULL);
858
859 string(file, "g[a0");
860 if (_addr_subreg_nr)
861 format(file, ".%d", _addr_subreg_nr);
862 if (_addr_imm)
863 format(file, " %d", _addr_imm);
864 string(file, "]");
865 src_align1_region(file, _vert_stride, _width, _horiz_stride);
866 err |= control(file, "src reg encoding", reg_encoding, type, NULL);
867 return err;
868 }
869
870 static int
871 src_swizzle(FILE *file, unsigned swiz)
872 {
873 unsigned x = BRW_GET_SWZ(swiz, BRW_CHANNEL_X);
874 unsigned y = BRW_GET_SWZ(swiz, BRW_CHANNEL_Y);
875 unsigned z = BRW_GET_SWZ(swiz, BRW_CHANNEL_Z);
876 unsigned w = BRW_GET_SWZ(swiz, BRW_CHANNEL_W);
877 int err = 0;
878
879 if (x == y && x == z && x == w) {
880 string(file, ".");
881 err |= control(file, "channel select", chan_sel, x, NULL);
882 } else if (swiz != BRW_SWIZZLE_XYZW) {
883 string(file, ".");
884 err |= control(file, "channel select", chan_sel, x, NULL);
885 err |= control(file, "channel select", chan_sel, y, NULL);
886 err |= control(file, "channel select", chan_sel, z, NULL);
887 err |= control(file, "channel select", chan_sel, w, NULL);
888 }
889 return err;
890 }
891
892 static int
893 src_da16(FILE *file,
894 const struct brw_context *brw,
895 unsigned opcode,
896 unsigned _reg_type,
897 unsigned _reg_file,
898 unsigned _vert_stride,
899 unsigned _reg_nr,
900 unsigned _subreg_nr,
901 unsigned __abs,
902 unsigned _negate,
903 unsigned swz_x, unsigned swz_y, unsigned swz_z, unsigned swz_w)
904 {
905 int err = 0;
906
907 if (brw->gen >= 8 && is_logic_instruction(opcode))
908 err |= control(file, "bitnot", m_bitnot, _negate, NULL);
909 else
910 err |= control(file, "negate", m_negate, _negate, NULL);
911
912 err |= control(file, "abs", _abs, __abs, NULL);
913
914 err |= reg(file, _reg_file, _reg_nr);
915 if (err == -1)
916 return 0;
917 if (_subreg_nr)
918 /* bit4 for subreg number byte addressing. Make this same meaning as
919 in da1 case, so output looks consistent. */
920 format(file, ".%d", 16 / reg_type_size[_reg_type]);
921 string(file, "<");
922 err |= control(file, "vert stride", vert_stride, _vert_stride, NULL);
923 string(file, ",4,1>");
924 err |= src_swizzle(file, BRW_SWIZZLE4(swz_x, swz_y, swz_z, swz_w));
925 err |= control(file, "src da16 reg type", reg_encoding, _reg_type, NULL);
926 return err;
927 }
928
929 static int
930 src0_3src(FILE *file, struct brw_context *brw, brw_inst *inst)
931 {
932 int err = 0;
933 unsigned src0_subreg_nr = brw_inst_3src_src0_subreg_nr(brw, inst);
934
935 err |= control(file, "negate", m_negate,
936 brw_inst_3src_src0_negate(brw, inst), NULL);
937 err |= control(file, "abs", _abs, brw_inst_3src_src0_abs(brw, inst), NULL);
938
939 err |= reg(file, BRW_GENERAL_REGISTER_FILE,
940 brw_inst_3src_src0_reg_nr(brw, inst));
941 if (err == -1)
942 return 0;
943 if (src0_subreg_nr)
944 format(file, ".%d", src0_subreg_nr);
945 if (brw_inst_3src_src0_rep_ctrl(brw, inst))
946 string(file, "<0,1,0>");
947 else
948 string(file, "<4,4,1>");
949 err |= control(file, "src da16 reg type", three_source_reg_encoding,
950 brw_inst_3src_src_type(brw, inst), NULL);
951 err |= src_swizzle(file, brw_inst_3src_src0_swizzle(brw, inst));
952 return err;
953 }
954
955 static int
956 src1_3src(FILE *file, struct brw_context *brw, brw_inst *inst)
957 {
958 int err = 0;
959 unsigned src1_subreg_nr = brw_inst_3src_src1_subreg_nr(brw, inst);
960
961 err |= control(file, "negate", m_negate,
962 brw_inst_3src_src1_negate(brw, inst), NULL);
963 err |= control(file, "abs", _abs, brw_inst_3src_src1_abs(brw, inst), NULL);
964
965 err |= reg(file, BRW_GENERAL_REGISTER_FILE,
966 brw_inst_3src_src1_reg_nr(brw, inst));
967 if (err == -1)
968 return 0;
969 if (src1_subreg_nr)
970 format(file, ".%d", src1_subreg_nr);
971 if (brw_inst_3src_src1_rep_ctrl(brw, inst))
972 string(file, "<0,1,0>");
973 else
974 string(file, "<4,4,1>");
975 err |= control(file, "src da16 reg type", three_source_reg_encoding,
976 brw_inst_3src_src_type(brw, inst), NULL);
977 err |= src_swizzle(file, brw_inst_3src_src1_swizzle(brw, inst));
978 return err;
979 }
980
981
982 static int
983 src2_3src(FILE *file, struct brw_context *brw, brw_inst *inst)
984 {
985 int err = 0;
986 unsigned src2_subreg_nr = brw_inst_3src_src2_subreg_nr(brw, inst);
987
988 err |= control(file, "negate", m_negate,
989 brw_inst_3src_src2_negate(brw, inst), NULL);
990 err |= control(file, "abs", _abs, brw_inst_3src_src2_abs(brw, inst), NULL);
991
992 err |= reg(file, BRW_GENERAL_REGISTER_FILE,
993 brw_inst_3src_src2_reg_nr(brw, inst));
994 if (err == -1)
995 return 0;
996 if (src2_subreg_nr)
997 format(file, ".%d", src2_subreg_nr);
998 if (brw_inst_3src_src2_rep_ctrl(brw, inst))
999 string(file, "<0,1,0>");
1000 else
1001 string(file, "<4,4,1>");
1002 err |= control(file, "src da16 reg type", three_source_reg_encoding,
1003 brw_inst_3src_src_type(brw, inst), NULL);
1004 err |= src_swizzle(file, brw_inst_3src_src2_swizzle(brw, inst));
1005 return err;
1006 }
1007
1008 static int
1009 imm(FILE *file, struct brw_context *brw, unsigned type, brw_inst *inst)
1010 {
1011 switch (type) {
1012 case BRW_HW_REG_TYPE_UD:
1013 format(file, "0x%08xUD", brw_inst_imm_ud(brw, inst));
1014 break;
1015 case BRW_HW_REG_TYPE_D:
1016 format(file, "%dD", brw_inst_imm_d(brw, inst));
1017 break;
1018 case BRW_HW_REG_TYPE_UW:
1019 format(file, "0x%04xUW", (uint16_t) brw_inst_imm_ud(brw, inst));
1020 break;
1021 case BRW_HW_REG_TYPE_W:
1022 format(file, "%dW", (int16_t) brw_inst_imm_d(brw, inst));
1023 break;
1024 case BRW_HW_REG_IMM_TYPE_UV:
1025 format(file, "0x%08xUV", brw_inst_imm_ud(brw, inst));
1026 break;
1027 case BRW_HW_REG_IMM_TYPE_VF:
1028 format(file, "Vector Float");
1029 break;
1030 case BRW_HW_REG_IMM_TYPE_V:
1031 format(file, "0x%08xV", brw_inst_imm_ud(brw, inst));
1032 break;
1033 case BRW_HW_REG_TYPE_F:
1034 format(file, "%-gF", brw_inst_imm_f(brw, inst));
1035 break;
1036 case GEN8_HW_REG_IMM_TYPE_DF:
1037 string(file, "Double IMM");
1038 break;
1039 case GEN8_HW_REG_IMM_TYPE_HF:
1040 string(file, "Half Float IMM");
1041 break;
1042 }
1043 return 0;
1044 }
1045
1046 static int
1047 src0(FILE *file, struct brw_context *brw, brw_inst *inst)
1048 {
1049 if (brw_inst_src0_reg_file(brw, inst) == BRW_IMMEDIATE_VALUE) {
1050 return imm(file, brw, brw_inst_src0_reg_type(brw, inst), inst);
1051 } else if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
1052 if (brw_inst_src0_address_mode(brw, inst) == BRW_ADDRESS_DIRECT) {
1053 return src_da1(file,
1054 brw,
1055 brw_inst_opcode(brw, inst),
1056 brw_inst_src0_reg_type(brw, inst),
1057 brw_inst_src0_reg_file(brw, inst),
1058 brw_inst_src0_vstride(brw, inst),
1059 brw_inst_src0_width(brw, inst),
1060 brw_inst_src0_hstride(brw, inst),
1061 brw_inst_src0_da_reg_nr(brw, inst),
1062 brw_inst_src0_da1_subreg_nr(brw, inst),
1063 brw_inst_src0_abs(brw, inst),
1064 brw_inst_src0_negate(brw, inst));
1065 } else {
1066 return src_ia1(file,
1067 brw,
1068 brw_inst_opcode(brw, inst),
1069 brw_inst_src0_reg_type(brw, inst),
1070 brw_inst_src0_reg_file(brw, inst),
1071 brw_inst_src0_ia1_addr_imm(brw, inst),
1072 brw_inst_src0_ia_subreg_nr(brw, inst),
1073 brw_inst_src0_negate(brw, inst),
1074 brw_inst_src0_abs(brw, inst),
1075 brw_inst_src0_address_mode(brw, inst),
1076 brw_inst_src0_hstride(brw, inst),
1077 brw_inst_src0_width(brw, inst),
1078 brw_inst_src0_vstride(brw, inst));
1079 }
1080 } else {
1081 if (brw_inst_src0_address_mode(brw, inst) == BRW_ADDRESS_DIRECT) {
1082 return src_da16(file,
1083 brw,
1084 brw_inst_opcode(brw, inst),
1085 brw_inst_src0_reg_type(brw, inst),
1086 brw_inst_src0_reg_file(brw, inst),
1087 brw_inst_src0_vstride(brw, inst),
1088 brw_inst_src0_da_reg_nr(brw, inst),
1089 brw_inst_src0_da16_subreg_nr(brw, inst),
1090 brw_inst_src0_abs(brw, inst),
1091 brw_inst_src0_negate(brw, inst),
1092 brw_inst_src0_da16_swiz_x(brw, inst),
1093 brw_inst_src0_da16_swiz_y(brw, inst),
1094 brw_inst_src0_da16_swiz_z(brw, inst),
1095 brw_inst_src0_da16_swiz_w(brw, inst));
1096 } else {
1097 string(file, "Indirect align16 address mode not supported");
1098 return 1;
1099 }
1100 }
1101 }
1102
1103 static int
1104 src1(FILE *file, struct brw_context *brw, brw_inst *inst)
1105 {
1106 if (brw_inst_src1_reg_file(brw, inst) == BRW_IMMEDIATE_VALUE) {
1107 return imm(file, brw, brw_inst_src1_reg_type(brw, inst), inst);
1108 } else if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
1109 if (brw_inst_src1_address_mode(brw, inst) == BRW_ADDRESS_DIRECT) {
1110 return src_da1(file,
1111 brw,
1112 brw_inst_opcode(brw, inst),
1113 brw_inst_src1_reg_type(brw, inst),
1114 brw_inst_src1_reg_file(brw, inst),
1115 brw_inst_src1_vstride(brw, inst),
1116 brw_inst_src1_width(brw, inst),
1117 brw_inst_src1_hstride(brw, inst),
1118 brw_inst_src1_da_reg_nr(brw, inst),
1119 brw_inst_src1_da1_subreg_nr(brw, inst),
1120 brw_inst_src1_abs(brw, inst),
1121 brw_inst_src1_negate(brw, inst));
1122 } else {
1123 return src_ia1(file,
1124 brw,
1125 brw_inst_opcode(brw, inst),
1126 brw_inst_src1_reg_type(brw, inst),
1127 brw_inst_src1_reg_file(brw, inst),
1128 brw_inst_src1_ia1_addr_imm(brw, inst),
1129 brw_inst_src1_ia_subreg_nr(brw, inst),
1130 brw_inst_src1_negate(brw, inst),
1131 brw_inst_src1_abs(brw, inst),
1132 brw_inst_src1_address_mode(brw, inst),
1133 brw_inst_src1_hstride(brw, inst),
1134 brw_inst_src1_width(brw, inst),
1135 brw_inst_src1_vstride(brw, inst));
1136 }
1137 } else {
1138 if (brw_inst_src1_address_mode(brw, inst) == BRW_ADDRESS_DIRECT) {
1139 return src_da16(file,
1140 brw,
1141 brw_inst_opcode(brw, inst),
1142 brw_inst_src1_reg_type(brw, inst),
1143 brw_inst_src1_reg_file(brw, inst),
1144 brw_inst_src1_vstride(brw, inst),
1145 brw_inst_src1_da_reg_nr(brw, inst),
1146 brw_inst_src1_da16_subreg_nr(brw, inst),
1147 brw_inst_src1_abs(brw, inst),
1148 brw_inst_src1_negate(brw, inst),
1149 brw_inst_src1_da16_swiz_x(brw, inst),
1150 brw_inst_src1_da16_swiz_y(brw, inst),
1151 brw_inst_src1_da16_swiz_z(brw, inst),
1152 brw_inst_src1_da16_swiz_w(brw, inst));
1153 } else {
1154 string(file, "Indirect align16 address mode not supported");
1155 return 1;
1156 }
1157 }
1158 }
1159
1160 static int
1161 qtr_ctrl(FILE *file, struct brw_context *brw, brw_inst *inst)
1162 {
1163 int qtr_ctl = brw_inst_qtr_control(brw, inst);
1164 int exec_size = 1 << brw_inst_exec_size(brw, inst);
1165
1166 if (exec_size == 8) {
1167 switch (qtr_ctl) {
1168 case 0:
1169 string(file, " 1Q");
1170 break;
1171 case 1:
1172 string(file, " 2Q");
1173 break;
1174 case 2:
1175 string(file, " 3Q");
1176 break;
1177 case 3:
1178 string(file, " 4Q");
1179 break;
1180 }
1181 } else if (exec_size == 16) {
1182 if (qtr_ctl < 2)
1183 string(file, " 1H");
1184 else
1185 string(file, " 2H");
1186 }
1187 return 0;
1188 }
1189
1190 int
1191 brw_disassemble_inst(FILE *file, struct brw_context *brw, brw_inst *inst,
1192 bool is_compacted)
1193 {
1194 int err = 0;
1195 int space = 0;
1196
1197 const enum opcode opcode = brw_inst_opcode(brw, inst);
1198
1199 if (brw_inst_pred_control(brw, inst)) {
1200 string(file, "(");
1201 err |= control(file, "predicate inverse", pred_inv,
1202 brw_inst_pred_inv(brw, inst), NULL);
1203 format(file, "f%d", brw->gen >= 7 ? brw_inst_flag_reg_nr(brw, inst) : 0);
1204 if (brw_inst_flag_subreg_nr(brw, inst))
1205 format(file, ".%d", brw_inst_flag_subreg_nr(brw, inst));
1206 if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
1207 err |= control(file, "predicate control align1", pred_ctrl_align1,
1208 brw_inst_pred_control(brw, inst), NULL);
1209 } else {
1210 err |= control(file, "predicate control align16", pred_ctrl_align16,
1211 brw_inst_pred_control(brw, inst), NULL);
1212 }
1213 string(file, ") ");
1214 }
1215
1216 err |= print_opcode(file, opcode);
1217 err |= control(file, "saturate", saturate, brw_inst_saturate(brw, inst),
1218 NULL);
1219
1220 err |= control(file, "debug control", debug_ctrl,
1221 brw_inst_debug_control(brw, inst), NULL);
1222
1223 if (opcode == BRW_OPCODE_MATH) {
1224 string(file, " ");
1225 err |= control(file, "function", math_function,
1226 brw_inst_math_function(brw, inst), NULL);
1227 } else if (opcode != BRW_OPCODE_SEND && opcode != BRW_OPCODE_SENDC) {
1228 err |= control(file, "conditional modifier", conditional_modifier,
1229 brw_inst_cond_modifier(brw, inst), NULL);
1230
1231 /* If we're using the conditional modifier, print which flags reg is
1232 * used for it. Note that on gen6+, the embedded-condition SEL and
1233 * control flow doesn't update flags.
1234 */
1235 if (brw_inst_cond_modifier(brw, inst) &&
1236 (brw->gen < 6 || (opcode != BRW_OPCODE_SEL &&
1237 opcode != BRW_OPCODE_IF &&
1238 opcode != BRW_OPCODE_WHILE))) {
1239 format(file, ".f%d",
1240 brw->gen >= 7 ? brw_inst_flag_reg_nr(brw, inst) : 0);
1241 if (brw_inst_flag_subreg_nr(brw, inst))
1242 format(file, ".%d", brw_inst_flag_subreg_nr(brw, inst));
1243 }
1244 }
1245
1246 if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) {
1247 string(file, "(");
1248 err |= control(file, "execution size", exec_size,
1249 brw_inst_exec_size(brw, inst), NULL);
1250 string(file, ")");
1251 }
1252
1253 if (opcode == BRW_OPCODE_SEND && brw->gen < 6)
1254 format(file, " %d", brw_inst_base_mrf(brw, inst));
1255
1256 if (has_uip(brw, opcode)) {
1257 /* Instructions that have UIP also have JIP. */
1258 pad(file, 16);
1259 format(file, "JIP: %d", brw_inst_jip(brw, inst));
1260 pad(file, 32);
1261 format(file, "UIP: %d", brw_inst_uip(brw, inst));
1262 } else if (has_jip(brw, opcode)) {
1263 pad(file, 16);
1264 if (brw->gen >= 7) {
1265 format(file, "JIP: %d", brw_inst_jip(brw, inst));
1266 } else {
1267 format(file, "JIP: %d", brw_inst_gen6_jump_count(brw, inst));
1268 }
1269 } else if (brw->gen < 6 && (opcode == BRW_OPCODE_BREAK ||
1270 opcode == BRW_OPCODE_CONTINUE ||
1271 opcode == BRW_OPCODE_ELSE)) {
1272 pad(file, 16);
1273 format(file, "Jump: %d", brw_inst_gen4_jump_count(brw, inst));
1274 pad(file, 32);
1275 format(file, "Pop: %d", brw_inst_gen4_pop_count(brw, inst));
1276 } else if (brw->gen < 6 && (opcode == BRW_OPCODE_IF ||
1277 opcode == BRW_OPCODE_IFF ||
1278 opcode == BRW_OPCODE_HALT)) {
1279 pad(file, 16);
1280 format(file, "Jump: %d", brw_inst_gen4_jump_count(brw, inst));
1281 } else if (brw->gen < 6 && opcode == BRW_OPCODE_ENDIF) {
1282 pad(file, 16);
1283 format(file, "Pop: %d", brw_inst_gen4_pop_count(brw, inst));
1284 } else if (opcode == BRW_OPCODE_JMPI) {
1285 pad(file, 16);
1286 err |= src1(file, brw, inst);
1287 } else if (opcode_descs[opcode].nsrc == 3) {
1288 pad(file, 16);
1289 err |= dest_3src(file, brw, inst);
1290
1291 pad(file, 32);
1292 err |= src0_3src(file, brw, inst);
1293
1294 pad(file, 48);
1295 err |= src1_3src(file, brw, inst);
1296
1297 pad(file, 64);
1298 err |= src2_3src(file, brw, inst);
1299 } else {
1300 if (opcode_descs[opcode].ndst > 0) {
1301 pad(file, 16);
1302 err |= dest(file, brw, inst);
1303 }
1304
1305 if (opcode_descs[opcode].nsrc > 0) {
1306 pad(file, 32);
1307 err |= src0(file, brw, inst);
1308 }
1309
1310 if (opcode_descs[opcode].nsrc > 1) {
1311 pad(file, 48);
1312 err |= src1(file, brw, inst);
1313 }
1314 }
1315
1316 if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC) {
1317 enum brw_message_target sfid = brw_inst_sfid(brw, inst);
1318
1319 if (brw_inst_src1_reg_file(brw, inst) != BRW_IMMEDIATE_VALUE) {
1320 /* show the indirect descriptor source */
1321 pad(file, 48);
1322 err |= src1(file, brw, inst);
1323 }
1324
1325 newline(file);
1326 pad(file, 16);
1327 space = 0;
1328
1329 fprintf(file, " ");
1330 err |= control(file, "SFID", brw->gen >= 6 ? gen6_sfid : gen4_sfid,
1331 sfid, &space);
1332
1333
1334 if (brw_inst_src1_reg_file(brw, inst) != BRW_IMMEDIATE_VALUE) {
1335 format(file, " indirect");
1336 } else {
1337 switch (sfid) {
1338 case BRW_SFID_MATH:
1339 err |= control(file, "math function", math_function,
1340 brw_inst_math_msg_function(brw, inst), &space);
1341 err |= control(file, "math saturate", math_saturate,
1342 brw_inst_math_msg_saturate(brw, inst), &space);
1343 err |= control(file, "math signed", math_signed,
1344 brw_inst_math_msg_signed_int(brw, inst), &space);
1345 err |= control(file, "math scalar", math_scalar,
1346 brw_inst_math_msg_data_type(brw, inst), &space);
1347 err |= control(file, "math precision", math_precision,
1348 brw_inst_math_msg_precision(brw, inst), &space);
1349 break;
1350 case BRW_SFID_SAMPLER:
1351 if (brw->gen >= 5) {
1352 format(file, " (%d, %d, %d, %d)",
1353 brw_inst_binding_table_index(brw, inst),
1354 brw_inst_sampler(brw, inst),
1355 brw_inst_sampler_msg_type(brw, inst),
1356 brw_inst_sampler_simd_mode(brw, inst));
1357 } else {
1358 format(file, " (%d, %d, %d, ",
1359 brw_inst_binding_table_index(brw, inst),
1360 brw_inst_sampler(brw, inst),
1361 brw_inst_sampler_msg_type(brw, inst));
1362 if (!brw->is_g4x) {
1363 err |= control(file, "sampler target format",
1364 sampler_target_format,
1365 brw_inst_sampler_return_format(brw, inst), NULL);
1366 }
1367 string(file, ")");
1368 }
1369 break;
1370 case GEN6_SFID_DATAPORT_SAMPLER_CACHE:
1371 /* aka BRW_SFID_DATAPORT_READ on Gen4-5 */
1372 if (brw->gen >= 6) {
1373 format(file, " (%d, %d, %d, %d)",
1374 brw_inst_binding_table_index(brw, inst),
1375 brw_inst_dp_msg_control(brw, inst),
1376 brw_inst_dp_msg_type(brw, inst),
1377 brw->gen >= 7 ? 0 : brw_inst_dp_write_commit(brw, inst));
1378 } else {
1379 format(file, " (%d, %d, %d)",
1380 brw_inst_binding_table_index(brw, inst),
1381 brw_inst_dp_read_msg_control(brw, inst),
1382 brw_inst_dp_read_msg_type(brw, inst));
1383 }
1384 break;
1385
1386 case GEN6_SFID_DATAPORT_RENDER_CACHE: {
1387 /* aka BRW_SFID_DATAPORT_WRITE on Gen4-5 */
1388 unsigned msg_type = brw_inst_dp_write_msg_type(brw, inst);
1389
1390 err |= control(file, "DP rc message type",
1391 brw->gen >= 6 ? dp_rc_msg_type_gen6
1392 : dp_write_port_msg_type,
1393 msg_type, &space);
1394
1395 bool is_rt_write = msg_type ==
1396 (brw->gen >= 6 ? GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
1397 : BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE);
1398
1399 if (is_rt_write) {
1400 err |= control(file, "RT message type", m_rt_write_subtype,
1401 brw_inst_rt_message_type(brw, inst), &space);
1402 if (brw->gen >= 6 && brw_inst_rt_slot_group(brw, inst))
1403 string(file, " Hi");
1404 if (brw_inst_rt_last(brw, inst))
1405 string(file, " LastRT");
1406 if (brw->gen < 7 && brw_inst_dp_write_commit(brw, inst))
1407 string(file, " WriteCommit");
1408 } else {
1409 format(file, " MsgCtrl = 0x%x",
1410 brw_inst_dp_write_msg_control(brw, inst));
1411 }
1412
1413 format(file, " Surface = %d", brw_inst_binding_table_index(brw, inst));
1414 break;
1415 }
1416
1417 case BRW_SFID_URB:
1418 format(file, " %d", brw_inst_urb_global_offset(brw, inst));
1419
1420 space = 1;
1421 if (brw->gen >= 7) {
1422 err |= control(file, "urb opcode", gen7_urb_opcode,
1423 brw_inst_urb_opcode(brw, inst), &space);
1424 } else if (brw->gen >= 5) {
1425 err |= control(file, "urb opcode", gen5_urb_opcode,
1426 brw_inst_urb_opcode(brw, inst), &space);
1427 }
1428 err |= control(file, "urb swizzle", urb_swizzle,
1429 brw_inst_urb_swizzle_control(brw, inst), &space);
1430 if (brw->gen < 7) {
1431 err |= control(file, "urb allocate", urb_allocate,
1432 brw_inst_urb_allocate(brw, inst), &space);
1433 err |= control(file, "urb used", urb_used,
1434 brw_inst_urb_used(brw, inst), &space);
1435 }
1436 if (brw->gen < 8) {
1437 err |= control(file, "urb complete", urb_complete,
1438 brw_inst_urb_complete(brw, inst), &space);
1439 }
1440 break;
1441 case BRW_SFID_THREAD_SPAWNER:
1442 break;
1443 case GEN7_SFID_DATAPORT_DATA_CACHE:
1444 if (brw->gen >= 7) {
1445 format(file, " (");
1446
1447 err |= control(file, "DP DC0 message type",
1448 dp_dc0_msg_type_gen7,
1449 brw_inst_dp_msg_type(brw, inst), &space);
1450
1451 format(file, ", %d, ", brw_inst_binding_table_index(brw, inst));
1452
1453 switch (brw_inst_dp_msg_type(brw, inst)) {
1454 case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
1455 control(file, "atomic op", aop,
1456 brw_inst_imm_ud(brw, inst) >> 8 & 0xf, &space);
1457 break;
1458 default:
1459 format(file, "%d", brw_inst_dp_msg_control(brw, inst));
1460 }
1461 format(file, ")");
1462 break;
1463 }
1464 /* FALLTHROUGH */
1465
1466 case HSW_SFID_DATAPORT_DATA_CACHE_1: {
1467 if (brw->gen >= 7) {
1468 format(file, " (");
1469
1470 unsigned msg_ctrl = brw_inst_dp_msg_control(brw, inst);
1471
1472 err |= control(file, "DP DC1 message type",
1473 dp_dc1_msg_type_hsw,
1474 brw_inst_dp_msg_type(brw, inst), &space);
1475
1476 format(file, ", Surface = %d, ",
1477 brw_inst_binding_table_index(brw, inst));
1478
1479 switch (brw_inst_dp_msg_type(brw, inst)) {
1480 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP:
1481 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP:
1482 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP:
1483 format(file, "SIMD%d,", (msg_ctrl & (1 << 4)) ? 8 : 16);
1484 /* fallthrough */
1485 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2:
1486 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2:
1487 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2:
1488 control(file, "atomic op", aop, msg_ctrl & 0xf, &space);
1489 break;
1490 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ:
1491 case HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE:
1492 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ:
1493 case HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE: {
1494 static const char *simd_modes[] = { "4x2", "16", "8" };
1495 format(file, "SIMD%s, Mask = 0x%x",
1496 simd_modes[msg_ctrl >> 4], msg_ctrl & 0xf);
1497 break;
1498 }
1499 default:
1500 format(file, "0x%x", msg_ctrl);
1501 }
1502 format(file, ")");
1503 break;
1504 }
1505 /* FALLTHROUGH */
1506 }
1507
1508 case GEN7_SFID_PIXEL_INTERPOLATOR:
1509 if (brw->gen >= 7) {
1510 format(file, " (%s, %s, 0x%02x)",
1511 brw_inst_pi_nopersp(brw, inst) ? "linear" : "persp",
1512 pixel_interpolator_msg_types[brw_inst_pi_message_type(brw, inst)],
1513 brw_inst_pi_message_data(brw, inst));
1514 break;
1515 }
1516 /* FALLTHROUGH */
1517
1518 default:
1519 format(file, "unsupported shared function ID %d", sfid);
1520 break;
1521 }
1522
1523 if (space)
1524 string(file, " ");
1525 format(file, "mlen %d", brw_inst_mlen(brw, inst));
1526 format(file, " rlen %d", brw_inst_rlen(brw, inst));
1527 }
1528 }
1529 pad(file, 64);
1530 if (opcode != BRW_OPCODE_NOP && opcode != BRW_OPCODE_NENOP) {
1531 string(file, "{");
1532 space = 1;
1533 err |= control(file, "access mode", access_mode,
1534 brw_inst_access_mode(brw, inst), &space);
1535 if (brw->gen >= 6) {
1536 err |= control(file, "write enable control", wectrl,
1537 brw_inst_mask_control(brw, inst), &space);
1538 } else {
1539 err |= control(file, "mask control", mask_ctrl,
1540 brw_inst_mask_control(brw, inst), &space);
1541 }
1542 err |= control(file, "dependency control", dep_ctrl,
1543 ((brw_inst_no_dd_check(brw, inst) << 1) |
1544 brw_inst_no_dd_clear(brw, inst)), &space);
1545
1546 if (brw->gen >= 6)
1547 err |= qtr_ctrl(file, brw, inst);
1548 else {
1549 if (brw_inst_qtr_control(brw, inst) == BRW_COMPRESSION_COMPRESSED &&
1550 opcode_descs[opcode].ndst > 0 &&
1551 brw_inst_dst_reg_file(brw, inst) == BRW_MESSAGE_REGISTER_FILE &&
1552 brw_inst_dst_da_reg_nr(brw, inst) & (1 << 7)) {
1553 format(file, " compr4");
1554 } else {
1555 err |= control(file, "compression control", compr_ctrl,
1556 brw_inst_qtr_control(brw, inst), &space);
1557 }
1558 }
1559
1560 err |= control(file, "compaction", cmpt_ctrl, is_compacted, &space);
1561 err |= control(file, "thread control", thread_ctrl,
1562 brw_inst_thread_control(brw, inst), &space);
1563 if (has_branch_ctrl(brw, opcode)) {
1564 err |= control(file, "branch ctrl", branch_ctrl,
1565 brw_inst_branch_control(brw, inst), &space);
1566 } else if (brw->gen >= 6) {
1567 err |= control(file, "acc write control", accwr,
1568 brw_inst_acc_wr_control(brw, inst), &space);
1569 }
1570 if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC)
1571 err |= control(file, "end of thread", end_of_thread,
1572 brw_inst_eot(brw, inst), &space);
1573 if (space)
1574 string(file, " ");
1575 string(file, "}");
1576 }
1577 string(file, ";");
1578 newline(file);
1579 return err;
1580 }