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e54172c6c78977ae6f6cb4b7c6d34ab2e3eafc50
[mesa.git] / src / mesa / drivers / dri / i965 / brw_disasm.c
1 /*
2 * Copyright © 2008 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23 #include <stdio.h>
24 #include <stdlib.h>
25 #include <string.h>
26 #include <getopt.h>
27 #include <unistd.h>
28 #include <stdarg.h>
29
30 #include "main/mtypes.h"
31
32 #include "brw_context.h"
33 #include "brw_defines.h"
34
35 const struct opcode_desc opcode_descs[128] = {
36 [BRW_OPCODE_MOV] = { .name = "mov", .nsrc = 1, .ndst = 1 },
37 [BRW_OPCODE_FRC] = { .name = "frc", .nsrc = 1, .ndst = 1 },
38 [BRW_OPCODE_RNDU] = { .name = "rndu", .nsrc = 1, .ndst = 1 },
39 [BRW_OPCODE_RNDD] = { .name = "rndd", .nsrc = 1, .ndst = 1 },
40 [BRW_OPCODE_RNDE] = { .name = "rnde", .nsrc = 1, .ndst = 1 },
41 [BRW_OPCODE_RNDZ] = { .name = "rndz", .nsrc = 1, .ndst = 1 },
42 [BRW_OPCODE_NOT] = { .name = "not", .nsrc = 1, .ndst = 1 },
43 [BRW_OPCODE_LZD] = { .name = "lzd", .nsrc = 1, .ndst = 1 },
44 [BRW_OPCODE_F32TO16] = { .name = "f32to16", .nsrc = 1, .ndst = 1 },
45 [BRW_OPCODE_F16TO32] = { .name = "f16to32", .nsrc = 1, .ndst = 1 },
46 [BRW_OPCODE_BFREV] = { .name = "bfrev", .nsrc = 1, .ndst = 1},
47 [BRW_OPCODE_FBH] = { .name = "fbh", .nsrc = 1, .ndst = 1},
48 [BRW_OPCODE_FBL] = { .name = "fbl", .nsrc = 1, .ndst = 1},
49 [BRW_OPCODE_CBIT] = { .name = "cbit", .nsrc = 1, .ndst = 1},
50
51 [BRW_OPCODE_MUL] = { .name = "mul", .nsrc = 2, .ndst = 1 },
52 [BRW_OPCODE_MAC] = { .name = "mac", .nsrc = 2, .ndst = 1 },
53 [BRW_OPCODE_MACH] = { .name = "mach", .nsrc = 2, .ndst = 1 },
54 [BRW_OPCODE_LINE] = { .name = "line", .nsrc = 2, .ndst = 1 },
55 [BRW_OPCODE_PLN] = { .name = "pln", .nsrc = 2, .ndst = 1 },
56 [BRW_OPCODE_MAD] = { .name = "mad", .nsrc = 3, .ndst = 1 },
57 [BRW_OPCODE_LRP] = { .name = "lrp", .nsrc = 3, .ndst = 1 },
58 [BRW_OPCODE_SAD2] = { .name = "sad2", .nsrc = 2, .ndst = 1 },
59 [BRW_OPCODE_SADA2] = { .name = "sada2", .nsrc = 2, .ndst = 1 },
60 [BRW_OPCODE_DP4] = { .name = "dp4", .nsrc = 2, .ndst = 1 },
61 [BRW_OPCODE_DPH] = { .name = "dph", .nsrc = 2, .ndst = 1 },
62 [BRW_OPCODE_DP3] = { .name = "dp3", .nsrc = 2, .ndst = 1 },
63 [BRW_OPCODE_DP2] = { .name = "dp2", .nsrc = 2, .ndst = 1 },
64 [BRW_OPCODE_MATH] = { .name = "math", .nsrc = 2, .ndst = 1 },
65
66 [BRW_OPCODE_AVG] = { .name = "avg", .nsrc = 2, .ndst = 1 },
67 [BRW_OPCODE_ADD] = { .name = "add", .nsrc = 2, .ndst = 1 },
68 [BRW_OPCODE_SEL] = { .name = "sel", .nsrc = 2, .ndst = 1 },
69 [BRW_OPCODE_AND] = { .name = "and", .nsrc = 2, .ndst = 1 },
70 [BRW_OPCODE_OR] = { .name = "or", .nsrc = 2, .ndst = 1 },
71 [BRW_OPCODE_XOR] = { .name = "xor", .nsrc = 2, .ndst = 1 },
72 [BRW_OPCODE_SHR] = { .name = "shr", .nsrc = 2, .ndst = 1 },
73 [BRW_OPCODE_SHL] = { .name = "shl", .nsrc = 2, .ndst = 1 },
74 [BRW_OPCODE_ASR] = { .name = "asr", .nsrc = 2, .ndst = 1 },
75 [BRW_OPCODE_CMP] = { .name = "cmp", .nsrc = 2, .ndst = 1 },
76 [BRW_OPCODE_CMPN] = { .name = "cmpn", .nsrc = 2, .ndst = 1 },
77 [BRW_OPCODE_BFE] = { .name = "bfe", .nsrc = 3, .ndst = 1},
78 [BRW_OPCODE_BFI1] = { .name = "bfi1", .nsrc = 2, .ndst = 1},
79 [BRW_OPCODE_BFI2] = { .name = "bfi2", .nsrc = 3, .ndst = 1},
80 [BRW_OPCODE_ADDC] = { .name = "addc", .nsrc = 2, .ndst = 1},
81 [BRW_OPCODE_SUBB] = { .name = "subb", .nsrc = 2, .ndst = 1},
82
83 [BRW_OPCODE_SEND] = { .name = "send", .nsrc = 1, .ndst = 1 },
84 [BRW_OPCODE_SENDC] = { .name = "sendc", .nsrc = 1, .ndst = 1 },
85 [BRW_OPCODE_NOP] = { .name = "nop", .nsrc = 0, .ndst = 0 },
86 [BRW_OPCODE_JMPI] = { .name = "jmpi", .nsrc = 0, .ndst = 0 },
87 [BRW_OPCODE_IF] = { .name = "if", .nsrc = 2, .ndst = 0 },
88 [BRW_OPCODE_IFF] = { .name = "iff", .nsrc = 2, .ndst = 1 },
89 [BRW_OPCODE_WHILE] = { .name = "while", .nsrc = 2, .ndst = 0 },
90 [BRW_OPCODE_ELSE] = { .name = "else", .nsrc = 2, .ndst = 0 },
91 [BRW_OPCODE_BREAK] = { .name = "break", .nsrc = 2, .ndst = 0 },
92 [BRW_OPCODE_CONTINUE] = { .name = "cont", .nsrc = 1, .ndst = 0 },
93 [BRW_OPCODE_HALT] = { .name = "halt", .nsrc = 1, .ndst = 0 },
94 [BRW_OPCODE_MSAVE] = { .name = "msave", .nsrc = 1, .ndst = 1 },
95 [BRW_OPCODE_PUSH] = { .name = "push", .nsrc = 1, .ndst = 1 },
96 [BRW_OPCODE_MRESTORE] = { .name = "mrest", .nsrc = 1, .ndst = 1 },
97 [BRW_OPCODE_POP] = { .name = "pop", .nsrc = 2, .ndst = 0 },
98 [BRW_OPCODE_WAIT] = { .name = "wait", .nsrc = 1, .ndst = 0 },
99 [BRW_OPCODE_DO] = { .name = "do", .nsrc = 0, .ndst = 0 },
100 [BRW_OPCODE_ENDIF] = { .name = "endif", .nsrc = 2, .ndst = 0 },
101 };
102 static const struct opcode_desc *opcode = opcode_descs;
103
104 const char * const conditional_modifier[16] = {
105 [BRW_CONDITIONAL_NONE] = "",
106 [BRW_CONDITIONAL_Z] = ".e",
107 [BRW_CONDITIONAL_NZ] = ".ne",
108 [BRW_CONDITIONAL_G] = ".g",
109 [BRW_CONDITIONAL_GE] = ".ge",
110 [BRW_CONDITIONAL_L] = ".l",
111 [BRW_CONDITIONAL_LE] = ".le",
112 [BRW_CONDITIONAL_R] = ".r",
113 [BRW_CONDITIONAL_O] = ".o",
114 [BRW_CONDITIONAL_U] = ".u",
115 };
116
117 static const char * const negate[2] = {
118 [0] = "",
119 [1] = "-",
120 };
121
122 static const char * const _abs[2] = {
123 [0] = "",
124 [1] = "(abs)",
125 };
126
127 static const char * const vert_stride[16] = {
128 [0] = "0",
129 [1] = "1",
130 [2] = "2",
131 [3] = "4",
132 [4] = "8",
133 [5] = "16",
134 [6] = "32",
135 [15] = "VxH",
136 };
137
138 static const char * const width[8] = {
139 [0] = "1",
140 [1] = "2",
141 [2] = "4",
142 [3] = "8",
143 [4] = "16",
144 };
145
146 static const char * const horiz_stride[4] = {
147 [0] = "0",
148 [1] = "1",
149 [2] = "2",
150 [3] = "4"
151 };
152
153 static const char * const chan_sel[4] = {
154 [0] = "x",
155 [1] = "y",
156 [2] = "z",
157 [3] = "w",
158 };
159
160 static const char * const debug_ctrl[2] = {
161 [0] = "",
162 [1] = ".breakpoint"
163 };
164
165 static const char * const saturate[2] = {
166 [0] = "",
167 [1] = ".sat"
168 };
169
170 static const char * const accwr[2] = {
171 [0] = "",
172 [1] = "AccWrEnable"
173 };
174
175 static const char * const wectrl[2] = {
176 [0] = "WE_normal",
177 [1] = "WE_all"
178 };
179
180 static const char * const exec_size[8] = {
181 [0] = "1",
182 [1] = "2",
183 [2] = "4",
184 [3] = "8",
185 [4] = "16",
186 [5] = "32"
187 };
188
189 static const char * const pred_inv[2] = {
190 [0] = "+",
191 [1] = "-"
192 };
193
194 static const char * const pred_ctrl_align16[16] = {
195 [1] = "",
196 [2] = ".x",
197 [3] = ".y",
198 [4] = ".z",
199 [5] = ".w",
200 [6] = ".any4h",
201 [7] = ".all4h",
202 };
203
204 static const char * const pred_ctrl_align1[16] = {
205 [1] = "",
206 [2] = ".anyv",
207 [3] = ".allv",
208 [4] = ".any2h",
209 [5] = ".all2h",
210 [6] = ".any4h",
211 [7] = ".all4h",
212 [8] = ".any8h",
213 [9] = ".all8h",
214 [10] = ".any16h",
215 [11] = ".all16h",
216 };
217
218 static const char * const thread_ctrl[4] = {
219 [0] = "",
220 [2] = "switch"
221 };
222
223 static const char * const compr_ctrl[4] = {
224 [0] = "",
225 [1] = "sechalf",
226 [2] = "compr",
227 [3] = "compr4",
228 };
229
230 static const char * const dep_ctrl[4] = {
231 [0] = "",
232 [1] = "NoDDClr",
233 [2] = "NoDDChk",
234 [3] = "NoDDClr,NoDDChk",
235 };
236
237 static const char * const mask_ctrl[4] = {
238 [0] = "",
239 [1] = "nomask",
240 };
241
242 static const char * const access_mode[2] = {
243 [0] = "align1",
244 [1] = "align16",
245 };
246
247 static const char * const reg_encoding[8] = {
248 [0] = "UD",
249 [1] = "D",
250 [2] = "UW",
251 [3] = "W",
252 [4] = "UB",
253 [5] = "B",
254 [7] = "F"
255 };
256
257 const char * const three_source_reg_encoding[] = {
258 [BRW_3SRC_TYPE_F] = "F",
259 [BRW_3SRC_TYPE_D] = "D",
260 [BRW_3SRC_TYPE_UD] = "UD",
261 };
262
263 const int reg_type_size[8] = {
264 [0] = 4,
265 [1] = 4,
266 [2] = 2,
267 [3] = 2,
268 [4] = 1,
269 [5] = 1,
270 [7] = 4
271 };
272
273 static const char * const reg_file[4] = {
274 [0] = "A",
275 [1] = "g",
276 [2] = "m",
277 [3] = "imm",
278 };
279
280 static const char * const writemask[16] = {
281 [0x0] = ".",
282 [0x1] = ".x",
283 [0x2] = ".y",
284 [0x3] = ".xy",
285 [0x4] = ".z",
286 [0x5] = ".xz",
287 [0x6] = ".yz",
288 [0x7] = ".xyz",
289 [0x8] = ".w",
290 [0x9] = ".xw",
291 [0xa] = ".yw",
292 [0xb] = ".xyw",
293 [0xc] = ".zw",
294 [0xd] = ".xzw",
295 [0xe] = ".yzw",
296 [0xf] = "",
297 };
298
299 static const char * const end_of_thread[2] = {
300 [0] = "",
301 [1] = "EOT"
302 };
303
304 static const char * const target_function[16] = {
305 [BRW_SFID_NULL] = "null",
306 [BRW_SFID_MATH] = "math",
307 [BRW_SFID_SAMPLER] = "sampler",
308 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
309 [BRW_SFID_DATAPORT_READ] = "read",
310 [BRW_SFID_DATAPORT_WRITE] = "write",
311 [BRW_SFID_URB] = "urb",
312 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
313 [BRW_SFID_VME] = "vme",
314 };
315
316 static const char * const target_function_gen6[16] = {
317 [BRW_SFID_NULL] = "null",
318 [BRW_SFID_MATH] = "math",
319 [BRW_SFID_SAMPLER] = "sampler",
320 [BRW_SFID_MESSAGE_GATEWAY] = "gateway",
321 [BRW_SFID_URB] = "urb",
322 [BRW_SFID_THREAD_SPAWNER] = "thread_spawner",
323 [GEN6_SFID_DATAPORT_SAMPLER_CACHE] = "sampler",
324 [GEN6_SFID_DATAPORT_RENDER_CACHE] = "render",
325 [GEN6_SFID_DATAPORT_CONSTANT_CACHE] = "const",
326 [GEN7_SFID_DATAPORT_DATA_CACHE] = "data",
327 [GEN7_SFID_PIXEL_INTERPOLATOR] = "pixel interp",
328 [HSW_SFID_DATAPORT_DATA_CACHE_1] = "dp data 1",
329 [HSW_SFID_CRE] = "cre",
330 };
331
332 static const char * const dp_rc_msg_type_gen6[16] = {
333 [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ] = "OWORD block read",
334 [GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ] = "RT UNORM read",
335 [GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ] = "OWORD dual block read",
336 [GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ] = "media block read",
337 [GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ] = "OWORD unaligned block read",
338 [GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ] = "DWORD scattered read",
339 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE] = "DWORD atomic write",
340 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE] = "OWORD block write",
341 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE] = "OWORD dual block write",
342 [GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE] = "media block write",
343 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE] = "DWORD scattered write",
344 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE] = "RT write",
345 [GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE] = "streamed VB write",
346 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE] = "RT UNORMc write",
347 };
348
349 static const char *const dp_dc0_msg_type_gen7[16] = {
350 [GEN7_DATAPORT_DC_OWORD_BLOCK_READ] = "DC OWORD block read",
351 [GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ] = "DC unaligned OWORD block read",
352 [GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ] = "DC OWORD dual block read",
353 [GEN7_DATAPORT_DC_DWORD_SCATTERED_READ] = "DC DWORD scattered read",
354 [GEN7_DATAPORT_DC_BYTE_SCATTERED_READ] = "DC byte scattered read",
355 [GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP] = "DC untyped atomic",
356 [GEN7_DATAPORT_DC_MEMORY_FENCE] = "DC mfence",
357 [GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE] = "DC OWORD block write",
358 [GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE] = "DC OWORD dual block write",
359 [GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE] = "DC DWORD scatterd write",
360 [GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE] = "DC byte scattered write",
361 [GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
362 };
363
364 static const char *const dp_dc1_msg_type_hsw[16] = {
365 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ] = "untyped surface read",
366 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP] = "DC untyped atomic op",
367 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2] = "DC untyped 4x2 atomic op",
368 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ] = "DC media block read",
369 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ] = "DC typed surface read",
370 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP] = "DC typed atomic",
371 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2] = "DC typed 4x2 atomic op",
372 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE] = "DC untyped surface write",
373 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE] = "DC media block write",
374 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP] = "DC atomic counter op",
375 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2] = "DC 4x2 atomic counter op",
376 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE] = "DC typed surface write",
377 };
378
379 static const char * const aop[16] = {
380 [BRW_AOP_AND] = "and",
381 [BRW_AOP_OR] = "or",
382 [BRW_AOP_XOR] = "xor",
383 [BRW_AOP_MOV] = "mov",
384 [BRW_AOP_INC] = "inc",
385 [BRW_AOP_DEC] = "dec",
386 [BRW_AOP_ADD] = "add",
387 [BRW_AOP_SUB] = "sub",
388 [BRW_AOP_REVSUB] = "revsub",
389 [BRW_AOP_IMAX] = "imax",
390 [BRW_AOP_IMIN] = "imin",
391 [BRW_AOP_UMAX] = "umax",
392 [BRW_AOP_UMIN] = "umin",
393 [BRW_AOP_CMPWR] = "cmpwr",
394 [BRW_AOP_PREDEC] = "predec",
395 };
396
397 static const char * const math_function[16] = {
398 [BRW_MATH_FUNCTION_INV] = "inv",
399 [BRW_MATH_FUNCTION_LOG] = "log",
400 [BRW_MATH_FUNCTION_EXP] = "exp",
401 [BRW_MATH_FUNCTION_SQRT] = "sqrt",
402 [BRW_MATH_FUNCTION_RSQ] = "rsq",
403 [BRW_MATH_FUNCTION_SIN] = "sin",
404 [BRW_MATH_FUNCTION_COS] = "cos",
405 [BRW_MATH_FUNCTION_SINCOS] = "sincos",
406 [BRW_MATH_FUNCTION_FDIV] = "fdiv",
407 [BRW_MATH_FUNCTION_POW] = "pow",
408 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER] = "intdivmod",
409 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT] = "intdiv",
410 [BRW_MATH_FUNCTION_INT_DIV_REMAINDER] = "intmod",
411 };
412
413 static const char * const math_saturate[2] = {
414 [0] = "",
415 [1] = "sat"
416 };
417
418 static const char * const math_signed[2] = {
419 [0] = "",
420 [1] = "signed"
421 };
422
423 static const char * const math_scalar[2] = {
424 [0] = "",
425 [1] = "scalar"
426 };
427
428 static const char * const math_precision[2] = {
429 [0] = "",
430 [1] = "partial_precision"
431 };
432
433 static const char * const urb_opcode[2] = {
434 [0] = "urb_write",
435 [1] = "ff_sync",
436 };
437
438 static const char * const urb_swizzle[4] = {
439 [BRW_URB_SWIZZLE_NONE] = "",
440 [BRW_URB_SWIZZLE_INTERLEAVE] = "interleave",
441 [BRW_URB_SWIZZLE_TRANSPOSE] = "transpose",
442 };
443
444 static const char * const urb_allocate[2] = {
445 [0] = "",
446 [1] = "allocate"
447 };
448
449 static const char * const urb_used[2] = {
450 [0] = "",
451 [1] = "used"
452 };
453
454 static const char * const urb_complete[2] = {
455 [0] = "",
456 [1] = "complete"
457 };
458
459 static const char * const sampler_target_format[4] = {
460 [0] = "F",
461 [2] = "UD",
462 [3] = "D"
463 };
464
465
466 static int column;
467
468 static int string (FILE *file, const char *string)
469 {
470 fputs (string, file);
471 column += strlen (string);
472 return 0;
473 }
474
475 static int format (FILE *f, const char *format, ...)
476 {
477 char buf[1024];
478 va_list args;
479 va_start (args, format);
480
481 vsnprintf (buf, sizeof (buf) - 1, format, args);
482 va_end (args);
483 string (f, buf);
484 return 0;
485 }
486
487 static int newline (FILE *f)
488 {
489 putc ('\n', f);
490 column = 0;
491 return 0;
492 }
493
494 static int pad (FILE *f, int c)
495 {
496 do
497 string (f, " ");
498 while (column < c);
499 return 0;
500 }
501
502 static int control (FILE *file, const char *name, const char * const ctrl[],
503 unsigned id, int *space)
504 {
505 if (!ctrl[id]) {
506 fprintf (file, "*** invalid %s value %d ",
507 name, id);
508 return 1;
509 }
510 if (ctrl[id][0])
511 {
512 if (space && *space)
513 string (file, " ");
514 string (file, ctrl[id]);
515 if (space)
516 *space = 1;
517 }
518 return 0;
519 }
520
521 static int print_opcode (FILE *file, int id)
522 {
523 if (!opcode[id].name) {
524 format (file, "*** invalid opcode value %d ", id);
525 return 1;
526 }
527 string (file, opcode[id].name);
528 return 0;
529 }
530
531 static int reg (FILE *file, unsigned _reg_file, unsigned _reg_nr)
532 {
533 int err = 0;
534
535 /* Clear the Compr4 instruction compression bit. */
536 if (_reg_file == BRW_MESSAGE_REGISTER_FILE)
537 _reg_nr &= ~(1 << 7);
538
539 if (_reg_file == BRW_ARCHITECTURE_REGISTER_FILE) {
540 switch (_reg_nr & 0xf0) {
541 case BRW_ARF_NULL:
542 string (file, "null");
543 return -1;
544 case BRW_ARF_ADDRESS:
545 format (file, "a%d", _reg_nr & 0x0f);
546 break;
547 case BRW_ARF_ACCUMULATOR:
548 format (file, "acc%d", _reg_nr & 0x0f);
549 break;
550 case BRW_ARF_FLAG:
551 format (file, "f%d", _reg_nr & 0x0f);
552 break;
553 case BRW_ARF_MASK:
554 format (file, "mask%d", _reg_nr & 0x0f);
555 break;
556 case BRW_ARF_MASK_STACK:
557 format (file, "msd%d", _reg_nr & 0x0f);
558 break;
559 case BRW_ARF_STATE:
560 format (file, "sr%d", _reg_nr & 0x0f);
561 break;
562 case BRW_ARF_CONTROL:
563 format (file, "cr%d", _reg_nr & 0x0f);
564 break;
565 case BRW_ARF_NOTIFICATION_COUNT:
566 format (file, "n%d", _reg_nr & 0x0f);
567 break;
568 case BRW_ARF_IP:
569 string (file, "ip");
570 return -1;
571 break;
572 default:
573 format (file, "ARF%d", _reg_nr);
574 break;
575 }
576 } else {
577 err |= control (file, "src reg file", reg_file, _reg_file, NULL);
578 format (file, "%d", _reg_nr);
579 }
580 return err;
581 }
582
583 static int dest (FILE *file, struct brw_instruction *inst)
584 {
585 int err = 0;
586
587 if (inst->header.access_mode == BRW_ALIGN_1)
588 {
589 if (inst->bits1.da1.dest_address_mode == BRW_ADDRESS_DIRECT)
590 {
591 err |= reg (file, inst->bits1.da1.dest_reg_file, inst->bits1.da1.dest_reg_nr);
592 if (err == -1)
593 return 0;
594 if (inst->bits1.da1.dest_subreg_nr)
595 format (file, ".%d", inst->bits1.da1.dest_subreg_nr /
596 reg_type_size[inst->bits1.da1.dest_reg_type]);
597 string (file, "<");
598 err |= control (file, "horiz stride", horiz_stride, inst->bits1.da1.dest_horiz_stride, NULL);
599 string (file, ">");
600 err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da1.dest_reg_type, NULL);
601 }
602 else
603 {
604 string (file, "g[a0");
605 if (inst->bits1.ia1.dest_subreg_nr)
606 format (file, ".%d", inst->bits1.ia1.dest_subreg_nr /
607 reg_type_size[inst->bits1.ia1.dest_reg_type]);
608 if (inst->bits1.ia1.dest_indirect_offset)
609 format (file, " %d", inst->bits1.ia1.dest_indirect_offset);
610 string (file, "]<");
611 err |= control (file, "horiz stride", horiz_stride, inst->bits1.ia1.dest_horiz_stride, NULL);
612 string (file, ">");
613 err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.ia1.dest_reg_type, NULL);
614 }
615 }
616 else
617 {
618 if (inst->bits1.da16.dest_address_mode == BRW_ADDRESS_DIRECT)
619 {
620 err |= reg (file, inst->bits1.da16.dest_reg_file, inst->bits1.da16.dest_reg_nr);
621 if (err == -1)
622 return 0;
623 if (inst->bits1.da16.dest_subreg_nr)
624 format (file, ".%d", inst->bits1.da16.dest_subreg_nr /
625 reg_type_size[inst->bits1.da16.dest_reg_type]);
626 string (file, "<1>");
627 err |= control (file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL);
628 err |= control (file, "dest reg encoding", reg_encoding, inst->bits1.da16.dest_reg_type, NULL);
629 }
630 else
631 {
632 err = 1;
633 string (file, "Indirect align16 address mode not supported");
634 }
635 }
636
637 return 0;
638 }
639
640 static int dest_3src (FILE *file, struct brw_instruction *inst)
641 {
642 int err = 0;
643 uint32_t reg_file;
644
645 if (inst->bits1.da3src.dest_reg_file)
646 reg_file = BRW_MESSAGE_REGISTER_FILE;
647 else
648 reg_file = BRW_GENERAL_REGISTER_FILE;
649
650 err |= reg (file, reg_file, inst->bits1.da3src.dest_reg_nr);
651 if (err == -1)
652 return 0;
653 if (inst->bits1.da3src.dest_subreg_nr)
654 format (file, ".%d", inst->bits1.da3src.dest_subreg_nr);
655 string (file, "<1>");
656 err |= control (file, "writemask", writemask, inst->bits1.da3src.dest_writemask, NULL);
657 err |= control (file, "dest reg encoding", three_source_reg_encoding,
658 inst->bits1.da3src.dst_type, NULL);
659
660 return 0;
661 }
662
663 static int src_align1_region (FILE *file,
664 unsigned _vert_stride, unsigned _width, unsigned _horiz_stride)
665 {
666 int err = 0;
667 string (file, "<");
668 err |= control (file, "vert stride", vert_stride, _vert_stride, NULL);
669 string (file, ",");
670 err |= control (file, "width", width, _width, NULL);
671 string (file, ",");
672 err |= control (file, "horiz_stride", horiz_stride, _horiz_stride, NULL);
673 string (file, ">");
674 return err;
675 }
676
677 static int src_da1 (FILE *file, unsigned type, unsigned _reg_file,
678 unsigned _vert_stride, unsigned _width, unsigned _horiz_stride,
679 unsigned reg_num, unsigned sub_reg_num, unsigned __abs, unsigned _negate)
680 {
681 int err = 0;
682 err |= control (file, "negate", negate, _negate, NULL);
683 err |= control (file, "abs", _abs, __abs, NULL);
684
685 err |= reg (file, _reg_file, reg_num);
686 if (err == -1)
687 return 0;
688 if (sub_reg_num)
689 format (file, ".%d", sub_reg_num / reg_type_size[type]); /* use formal style like spec */
690 src_align1_region (file, _vert_stride, _width, _horiz_stride);
691 err |= control (file, "src reg encoding", reg_encoding, type, NULL);
692 return err;
693 }
694
695 static int src_ia1 (FILE *file,
696 unsigned type,
697 unsigned _reg_file,
698 int _addr_imm,
699 unsigned _addr_subreg_nr,
700 unsigned _negate,
701 unsigned __abs,
702 unsigned _addr_mode,
703 unsigned _horiz_stride,
704 unsigned _width,
705 unsigned _vert_stride)
706 {
707 int err = 0;
708 err |= control (file, "negate", negate, _negate, NULL);
709 err |= control (file, "abs", _abs, __abs, NULL);
710
711 string (file, "g[a0");
712 if (_addr_subreg_nr)
713 format (file, ".%d", _addr_subreg_nr);
714 if (_addr_imm)
715 format (file, " %d", _addr_imm);
716 string (file, "]");
717 src_align1_region (file, _vert_stride, _width, _horiz_stride);
718 err |= control (file, "src reg encoding", reg_encoding, type, NULL);
719 return err;
720 }
721
722 static int src_da16 (FILE *file,
723 unsigned _reg_type,
724 unsigned _reg_file,
725 unsigned _vert_stride,
726 unsigned _reg_nr,
727 unsigned _subreg_nr,
728 unsigned __abs,
729 unsigned _negate,
730 unsigned swz_x,
731 unsigned swz_y,
732 unsigned swz_z,
733 unsigned swz_w)
734 {
735 int err = 0;
736 err |= control (file, "negate", negate, _negate, NULL);
737 err |= control (file, "abs", _abs, __abs, NULL);
738
739 err |= reg (file, _reg_file, _reg_nr);
740 if (err == -1)
741 return 0;
742 if (_subreg_nr)
743 /* bit4 for subreg number byte addressing. Make this same meaning as
744 in da1 case, so output looks consistent. */
745 format (file, ".%d", 16 / reg_type_size[_reg_type]);
746 string (file, "<");
747 err |= control (file, "vert stride", vert_stride, _vert_stride, NULL);
748 string (file, ",4,1>");
749 /*
750 * Three kinds of swizzle display:
751 * identity - nothing printed
752 * 1->all - print the single channel
753 * 1->1 - print the mapping
754 */
755 if (swz_x == BRW_CHANNEL_X &&
756 swz_y == BRW_CHANNEL_Y &&
757 swz_z == BRW_CHANNEL_Z &&
758 swz_w == BRW_CHANNEL_W)
759 {
760 ;
761 }
762 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
763 {
764 string (file, ".");
765 err |= control (file, "channel select", chan_sel, swz_x, NULL);
766 }
767 else
768 {
769 string (file, ".");
770 err |= control (file, "channel select", chan_sel, swz_x, NULL);
771 err |= control (file, "channel select", chan_sel, swz_y, NULL);
772 err |= control (file, "channel select", chan_sel, swz_z, NULL);
773 err |= control (file, "channel select", chan_sel, swz_w, NULL);
774 }
775 err |= control (file, "src da16 reg type", reg_encoding, _reg_type, NULL);
776 return err;
777 }
778
779 static int src0_3src (FILE *file, struct brw_instruction *inst)
780 {
781 int err = 0;
782 unsigned swz_x = (inst->bits2.da3src.src0_swizzle >> 0) & 0x3;
783 unsigned swz_y = (inst->bits2.da3src.src0_swizzle >> 2) & 0x3;
784 unsigned swz_z = (inst->bits2.da3src.src0_swizzle >> 4) & 0x3;
785 unsigned swz_w = (inst->bits2.da3src.src0_swizzle >> 6) & 0x3;
786
787 err |= control (file, "negate", negate, inst->bits1.da3src.src0_negate, NULL);
788 err |= control (file, "abs", _abs, inst->bits1.da3src.src0_abs, NULL);
789
790 err |= reg (file, BRW_GENERAL_REGISTER_FILE, inst->bits2.da3src.src0_reg_nr);
791 if (err == -1)
792 return 0;
793 if (inst->bits2.da3src.src0_subreg_nr)
794 format (file, ".%d", inst->bits2.da3src.src0_subreg_nr);
795 if (inst->bits2.da3src.src0_rep_ctrl)
796 string (file, "<0,1,0>");
797 else
798 string (file, "<4,4,1>");
799 err |= control (file, "src da16 reg type", three_source_reg_encoding,
800 inst->bits1.da3src.src_type, NULL);
801 /*
802 * Three kinds of swizzle display:
803 * identity - nothing printed
804 * 1->all - print the single channel
805 * 1->1 - print the mapping
806 */
807 if (swz_x == BRW_CHANNEL_X &&
808 swz_y == BRW_CHANNEL_Y &&
809 swz_z == BRW_CHANNEL_Z &&
810 swz_w == BRW_CHANNEL_W)
811 {
812 ;
813 }
814 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
815 {
816 string (file, ".");
817 err |= control (file, "channel select", chan_sel, swz_x, NULL);
818 }
819 else
820 {
821 string (file, ".");
822 err |= control (file, "channel select", chan_sel, swz_x, NULL);
823 err |= control (file, "channel select", chan_sel, swz_y, NULL);
824 err |= control (file, "channel select", chan_sel, swz_z, NULL);
825 err |= control (file, "channel select", chan_sel, swz_w, NULL);
826 }
827 return err;
828 }
829
830 static int src1_3src (FILE *file, struct brw_instruction *inst)
831 {
832 int err = 0;
833 unsigned swz_x = (inst->bits2.da3src.src1_swizzle >> 0) & 0x3;
834 unsigned swz_y = (inst->bits2.da3src.src1_swizzle >> 2) & 0x3;
835 unsigned swz_z = (inst->bits2.da3src.src1_swizzle >> 4) & 0x3;
836 unsigned swz_w = (inst->bits2.da3src.src1_swizzle >> 6) & 0x3;
837 unsigned src1_subreg_nr = (inst->bits2.da3src.src1_subreg_nr_low |
838 (inst->bits3.da3src.src1_subreg_nr_high << 2));
839
840 err |= control (file, "negate", negate, inst->bits1.da3src.src1_negate,
841 NULL);
842 err |= control (file, "abs", _abs, inst->bits1.da3src.src1_abs, NULL);
843
844 err |= reg (file, BRW_GENERAL_REGISTER_FILE,
845 inst->bits3.da3src.src1_reg_nr);
846 if (err == -1)
847 return 0;
848 if (src1_subreg_nr)
849 format (file, ".%d", src1_subreg_nr);
850 if (inst->bits2.da3src.src1_rep_ctrl)
851 string (file, "<0,1,0>");
852 else
853 string (file, "<4,4,1>");
854 err |= control (file, "src da16 reg type", three_source_reg_encoding,
855 inst->bits1.da3src.src_type, NULL);
856 /*
857 * Three kinds of swizzle display:
858 * identity - nothing printed
859 * 1->all - print the single channel
860 * 1->1 - print the mapping
861 */
862 if (swz_x == BRW_CHANNEL_X &&
863 swz_y == BRW_CHANNEL_Y &&
864 swz_z == BRW_CHANNEL_Z &&
865 swz_w == BRW_CHANNEL_W)
866 {
867 ;
868 }
869 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
870 {
871 string (file, ".");
872 err |= control (file, "channel select", chan_sel, swz_x, NULL);
873 }
874 else
875 {
876 string (file, ".");
877 err |= control (file, "channel select", chan_sel, swz_x, NULL);
878 err |= control (file, "channel select", chan_sel, swz_y, NULL);
879 err |= control (file, "channel select", chan_sel, swz_z, NULL);
880 err |= control (file, "channel select", chan_sel, swz_w, NULL);
881 }
882 return err;
883 }
884
885
886 static int src2_3src (FILE *file, struct brw_instruction *inst)
887 {
888 int err = 0;
889 unsigned swz_x = (inst->bits3.da3src.src2_swizzle >> 0) & 0x3;
890 unsigned swz_y = (inst->bits3.da3src.src2_swizzle >> 2) & 0x3;
891 unsigned swz_z = (inst->bits3.da3src.src2_swizzle >> 4) & 0x3;
892 unsigned swz_w = (inst->bits3.da3src.src2_swizzle >> 6) & 0x3;
893
894 err |= control (file, "negate", negate, inst->bits1.da3src.src2_negate,
895 NULL);
896 err |= control (file, "abs", _abs, inst->bits1.da3src.src2_abs, NULL);
897
898 err |= reg (file, BRW_GENERAL_REGISTER_FILE,
899 inst->bits3.da3src.src2_reg_nr);
900 if (err == -1)
901 return 0;
902 if (inst->bits3.da3src.src2_subreg_nr)
903 format (file, ".%d", inst->bits3.da3src.src2_subreg_nr);
904 if (inst->bits3.da3src.src2_rep_ctrl)
905 string (file, "<0,1,0>");
906 else
907 string (file, "<4,4,1>");
908 err |= control (file, "src da16 reg type", three_source_reg_encoding,
909 inst->bits1.da3src.src_type, NULL);
910 /*
911 * Three kinds of swizzle display:
912 * identity - nothing printed
913 * 1->all - print the single channel
914 * 1->1 - print the mapping
915 */
916 if (swz_x == BRW_CHANNEL_X &&
917 swz_y == BRW_CHANNEL_Y &&
918 swz_z == BRW_CHANNEL_Z &&
919 swz_w == BRW_CHANNEL_W)
920 {
921 ;
922 }
923 else if (swz_x == swz_y && swz_x == swz_z && swz_x == swz_w)
924 {
925 string (file, ".");
926 err |= control (file, "channel select", chan_sel, swz_x, NULL);
927 }
928 else
929 {
930 string (file, ".");
931 err |= control (file, "channel select", chan_sel, swz_x, NULL);
932 err |= control (file, "channel select", chan_sel, swz_y, NULL);
933 err |= control (file, "channel select", chan_sel, swz_z, NULL);
934 err |= control (file, "channel select", chan_sel, swz_w, NULL);
935 }
936 return err;
937 }
938
939 static int imm (FILE *file, unsigned type, struct brw_instruction *inst) {
940 switch (type) {
941 case BRW_HW_REG_TYPE_UD:
942 format (file, "0x%08xUD", inst->bits3.ud);
943 break;
944 case BRW_HW_REG_TYPE_D:
945 format (file, "%dD", inst->bits3.d);
946 break;
947 case BRW_HW_REG_TYPE_UW:
948 format (file, "0x%04xUW", (uint16_t) inst->bits3.ud);
949 break;
950 case BRW_HW_REG_TYPE_W:
951 format (file, "%dW", (int16_t) inst->bits3.d);
952 break;
953 case BRW_HW_REG_IMM_TYPE_UV:
954 format (file, "0x%08xUV", inst->bits3.ud);
955 break;
956 case BRW_HW_REG_IMM_TYPE_VF:
957 format (file, "Vector Float");
958 break;
959 case BRW_HW_REG_IMM_TYPE_V:
960 format (file, "0x%08xV", inst->bits3.ud);
961 break;
962 case BRW_HW_REG_TYPE_F:
963 format (file, "%-gF", inst->bits3.f);
964 }
965 return 0;
966 }
967
968 static int src0 (FILE *file, struct brw_instruction *inst)
969 {
970 if (inst->bits1.da1.src0_reg_file == BRW_IMMEDIATE_VALUE)
971 return imm (file, inst->bits1.da1.src0_reg_type,
972 inst);
973 else if (inst->header.access_mode == BRW_ALIGN_1)
974 {
975 if (inst->bits2.da1.src0_address_mode == BRW_ADDRESS_DIRECT)
976 {
977 return src_da1 (file,
978 inst->bits1.da1.src0_reg_type,
979 inst->bits1.da1.src0_reg_file,
980 inst->bits2.da1.src0_vert_stride,
981 inst->bits2.da1.src0_width,
982 inst->bits2.da1.src0_horiz_stride,
983 inst->bits2.da1.src0_reg_nr,
984 inst->bits2.da1.src0_subreg_nr,
985 inst->bits2.da1.src0_abs,
986 inst->bits2.da1.src0_negate);
987 }
988 else
989 {
990 return src_ia1 (file,
991 inst->bits1.ia1.src0_reg_type,
992 inst->bits1.ia1.src0_reg_file,
993 inst->bits2.ia1.src0_indirect_offset,
994 inst->bits2.ia1.src0_subreg_nr,
995 inst->bits2.ia1.src0_negate,
996 inst->bits2.ia1.src0_abs,
997 inst->bits2.ia1.src0_address_mode,
998 inst->bits2.ia1.src0_horiz_stride,
999 inst->bits2.ia1.src0_width,
1000 inst->bits2.ia1.src0_vert_stride);
1001 }
1002 }
1003 else
1004 {
1005 if (inst->bits2.da16.src0_address_mode == BRW_ADDRESS_DIRECT)
1006 {
1007 return src_da16 (file,
1008 inst->bits1.da16.src0_reg_type,
1009 inst->bits1.da16.src0_reg_file,
1010 inst->bits2.da16.src0_vert_stride,
1011 inst->bits2.da16.src0_reg_nr,
1012 inst->bits2.da16.src0_subreg_nr,
1013 inst->bits2.da16.src0_abs,
1014 inst->bits2.da16.src0_negate,
1015 inst->bits2.da16.src0_swz_x,
1016 inst->bits2.da16.src0_swz_y,
1017 inst->bits2.da16.src0_swz_z,
1018 inst->bits2.da16.src0_swz_w);
1019 }
1020 else
1021 {
1022 string (file, "Indirect align16 address mode not supported");
1023 return 1;
1024 }
1025 }
1026 }
1027
1028 static int src1 (FILE *file, struct brw_instruction *inst)
1029 {
1030 if (inst->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE)
1031 return imm (file, inst->bits1.da1.src1_reg_type,
1032 inst);
1033 else if (inst->header.access_mode == BRW_ALIGN_1)
1034 {
1035 if (inst->bits3.da1.src1_address_mode == BRW_ADDRESS_DIRECT)
1036 {
1037 return src_da1 (file,
1038 inst->bits1.da1.src1_reg_type,
1039 inst->bits1.da1.src1_reg_file,
1040 inst->bits3.da1.src1_vert_stride,
1041 inst->bits3.da1.src1_width,
1042 inst->bits3.da1.src1_horiz_stride,
1043 inst->bits3.da1.src1_reg_nr,
1044 inst->bits3.da1.src1_subreg_nr,
1045 inst->bits3.da1.src1_abs,
1046 inst->bits3.da1.src1_negate);
1047 }
1048 else
1049 {
1050 return src_ia1 (file,
1051 inst->bits1.ia1.src1_reg_type,
1052 inst->bits1.ia1.src1_reg_file,
1053 inst->bits3.ia1.src1_indirect_offset,
1054 inst->bits3.ia1.src1_subreg_nr,
1055 inst->bits3.ia1.src1_negate,
1056 inst->bits3.ia1.src1_abs,
1057 inst->bits3.ia1.src1_address_mode,
1058 inst->bits3.ia1.src1_horiz_stride,
1059 inst->bits3.ia1.src1_width,
1060 inst->bits3.ia1.src1_vert_stride);
1061 }
1062 }
1063 else
1064 {
1065 if (inst->bits3.da16.src1_address_mode == BRW_ADDRESS_DIRECT)
1066 {
1067 return src_da16 (file,
1068 inst->bits1.da16.src1_reg_type,
1069 inst->bits1.da16.src1_reg_file,
1070 inst->bits3.da16.src1_vert_stride,
1071 inst->bits3.da16.src1_reg_nr,
1072 inst->bits3.da16.src1_subreg_nr,
1073 inst->bits3.da16.src1_abs,
1074 inst->bits3.da16.src1_negate,
1075 inst->bits3.da16.src1_swz_x,
1076 inst->bits3.da16.src1_swz_y,
1077 inst->bits3.da16.src1_swz_z,
1078 inst->bits3.da16.src1_swz_w);
1079 }
1080 else
1081 {
1082 string (file, "Indirect align16 address mode not supported");
1083 return 1;
1084 }
1085 }
1086 }
1087
1088 static int qtr_ctrl(FILE *file, struct brw_instruction *inst)
1089 {
1090 int qtr_ctl = inst->header.compression_control;
1091 int exec_size = 1 << inst->header.execution_size;
1092
1093 if (exec_size == 8) {
1094 switch (qtr_ctl) {
1095 case 0:
1096 string (file, " 1Q");
1097 break;
1098 case 1:
1099 string (file, " 2Q");
1100 break;
1101 case 2:
1102 string (file, " 3Q");
1103 break;
1104 case 3:
1105 string (file, " 4Q");
1106 break;
1107 }
1108 } else if (exec_size == 16){
1109 if (qtr_ctl < 2)
1110 string (file, " 1H");
1111 else
1112 string (file, " 2H");
1113 }
1114 return 0;
1115 }
1116
1117 int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
1118 {
1119 int err = 0;
1120 int space = 0;
1121
1122 if (inst->header.predicate_control) {
1123 string (file, "(");
1124 err |= control (file, "predicate inverse", pred_inv, inst->header.predicate_inverse, NULL);
1125 format (file, "f%d", gen >= 7 ? inst->bits2.da1.flag_reg_nr : 0);
1126 if (inst->bits2.da1.flag_subreg_nr)
1127 format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
1128 if (inst->header.access_mode == BRW_ALIGN_1)
1129 err |= control (file, "predicate control align1", pred_ctrl_align1,
1130 inst->header.predicate_control, NULL);
1131 else
1132 err |= control (file, "predicate control align16", pred_ctrl_align16,
1133 inst->header.predicate_control, NULL);
1134 string (file, ") ");
1135 }
1136
1137 err |= print_opcode (file, inst->header.opcode);
1138 err |= control (file, "saturate", saturate, inst->header.saturate, NULL);
1139 err |= control (file, "debug control", debug_ctrl, inst->header.debug_control, NULL);
1140
1141 if (inst->header.opcode == BRW_OPCODE_MATH) {
1142 string (file, " ");
1143 err |= control (file, "function", math_function,
1144 inst->header.destreg__conditionalmod, NULL);
1145 } else if (inst->header.opcode != BRW_OPCODE_SEND &&
1146 inst->header.opcode != BRW_OPCODE_SENDC) {
1147 err |= control (file, "conditional modifier", conditional_modifier,
1148 inst->header.destreg__conditionalmod, NULL);
1149
1150 /* If we're using the conditional modifier, print which flags reg is
1151 * used for it. Note that on gen6+, the embedded-condition SEL and
1152 * control flow doesn't update flags.
1153 */
1154 if (inst->header.destreg__conditionalmod &&
1155 (gen < 6 || (inst->header.opcode != BRW_OPCODE_SEL &&
1156 inst->header.opcode != BRW_OPCODE_IF &&
1157 inst->header.opcode != BRW_OPCODE_WHILE))) {
1158 format (file, ".f%d", gen >= 7 ? inst->bits2.da1.flag_reg_nr : 0);
1159 if (inst->bits2.da1.flag_subreg_nr)
1160 format (file, ".%d", inst->bits2.da1.flag_subreg_nr);
1161 }
1162 }
1163
1164 if (inst->header.opcode != BRW_OPCODE_NOP) {
1165 string (file, "(");
1166 err |= control (file, "execution size", exec_size, inst->header.execution_size, NULL);
1167 string (file, ")");
1168 }
1169
1170 if (inst->header.opcode == BRW_OPCODE_SEND && gen < 6)
1171 format (file, " %d", inst->header.destreg__conditionalmod);
1172
1173 if (opcode[inst->header.opcode].nsrc == 3) {
1174 pad (file, 16);
1175 err |= dest_3src (file, inst);
1176
1177 pad (file, 32);
1178 err |= src0_3src (file, inst);
1179
1180 pad (file, 48);
1181 err |= src1_3src (file, inst);
1182
1183 pad (file, 64);
1184 err |= src2_3src (file, inst);
1185 } else {
1186 if (opcode[inst->header.opcode].ndst > 0) {
1187 pad (file, 16);
1188 err |= dest (file, inst);
1189 } else if (gen == 7 && (inst->header.opcode == BRW_OPCODE_ELSE ||
1190 inst->header.opcode == BRW_OPCODE_ENDIF ||
1191 inst->header.opcode == BRW_OPCODE_WHILE)) {
1192 format (file, " %d", inst->bits3.break_cont.jip);
1193 } else if (gen == 6 && (inst->header.opcode == BRW_OPCODE_IF ||
1194 inst->header.opcode == BRW_OPCODE_ELSE ||
1195 inst->header.opcode == BRW_OPCODE_ENDIF ||
1196 inst->header.opcode == BRW_OPCODE_WHILE)) {
1197 format (file, " %d", inst->bits1.branch_gen6.jump_count);
1198 } else if ((gen >= 6 && (inst->header.opcode == BRW_OPCODE_BREAK ||
1199 inst->header.opcode == BRW_OPCODE_CONTINUE ||
1200 inst->header.opcode == BRW_OPCODE_HALT)) ||
1201 (gen == 7 && inst->header.opcode == BRW_OPCODE_IF)) {
1202 format (file, " %d %d", inst->bits3.break_cont.uip, inst->bits3.break_cont.jip);
1203 } else if (inst->header.opcode == BRW_OPCODE_JMPI) {
1204 format (file, " %d", inst->bits3.d);
1205 }
1206
1207 if (opcode[inst->header.opcode].nsrc > 0) {
1208 pad (file, 32);
1209 err |= src0 (file, inst);
1210 }
1211 if (opcode[inst->header.opcode].nsrc > 1) {
1212 pad (file, 48);
1213 err |= src1 (file, inst);
1214 }
1215 }
1216
1217 if (inst->header.opcode == BRW_OPCODE_SEND ||
1218 inst->header.opcode == BRW_OPCODE_SENDC) {
1219 enum brw_message_target target;
1220
1221 if (gen >= 6)
1222 target = inst->header.destreg__conditionalmod;
1223 else if (gen == 5)
1224 target = inst->bits2.send_gen5.sfid;
1225 else
1226 target = inst->bits3.generic.msg_target;
1227
1228 newline (file);
1229 pad (file, 16);
1230 space = 0;
1231
1232 if (gen >= 6) {
1233 err |= control (file, "target function", target_function_gen6,
1234 target, &space);
1235 } else {
1236 err |= control (file, "target function", target_function,
1237 target, &space);
1238 }
1239
1240 switch (target) {
1241 case BRW_SFID_MATH:
1242 err |= control (file, "math function", math_function,
1243 inst->bits3.math.function, &space);
1244 err |= control (file, "math saturate", math_saturate,
1245 inst->bits3.math.saturate, &space);
1246 err |= control (file, "math signed", math_signed,
1247 inst->bits3.math.int_type, &space);
1248 err |= control (file, "math scalar", math_scalar,
1249 inst->bits3.math.data_type, &space);
1250 err |= control (file, "math precision", math_precision,
1251 inst->bits3.math.precision, &space);
1252 break;
1253 case BRW_SFID_SAMPLER:
1254 if (gen >= 7) {
1255 format (file, " (%d, %d, %d, %d)",
1256 inst->bits3.sampler_gen7.binding_table_index,
1257 inst->bits3.sampler_gen7.sampler,
1258 inst->bits3.sampler_gen7.msg_type,
1259 inst->bits3.sampler_gen7.simd_mode);
1260 } else if (gen >= 5) {
1261 format (file, " (%d, %d, %d, %d)",
1262 inst->bits3.sampler_gen5.binding_table_index,
1263 inst->bits3.sampler_gen5.sampler,
1264 inst->bits3.sampler_gen5.msg_type,
1265 inst->bits3.sampler_gen5.simd_mode);
1266 } else if (0 /* FINISHME: is_g4x */) {
1267 format (file, " (%d, %d)",
1268 inst->bits3.sampler_g4x.binding_table_index,
1269 inst->bits3.sampler_g4x.sampler);
1270 } else {
1271 format (file, " (%d, %d, ",
1272 inst->bits3.sampler.binding_table_index,
1273 inst->bits3.sampler.sampler);
1274 err |= control (file, "sampler target format",
1275 sampler_target_format,
1276 inst->bits3.sampler.return_format, NULL);
1277 string (file, ")");
1278 }
1279 break;
1280 case BRW_SFID_DATAPORT_READ:
1281 if (gen >= 6) {
1282 format (file, " (%d, %d, %d, %d)",
1283 inst->bits3.gen6_dp.binding_table_index,
1284 inst->bits3.gen6_dp.msg_control,
1285 inst->bits3.gen6_dp.msg_type,
1286 inst->bits3.gen6_dp.send_commit_msg);
1287 } else if (gen >= 5 /* FINISHME: || is_g4x */) {
1288 format (file, " (%d, %d, %d)",
1289 inst->bits3.dp_read_gen5.binding_table_index,
1290 inst->bits3.dp_read_gen5.msg_control,
1291 inst->bits3.dp_read_gen5.msg_type);
1292 } else {
1293 format (file, " (%d, %d, %d)",
1294 inst->bits3.dp_read.binding_table_index,
1295 inst->bits3.dp_read.msg_control,
1296 inst->bits3.dp_read.msg_type);
1297 }
1298 break;
1299
1300 case BRW_SFID_DATAPORT_WRITE:
1301 if (gen >= 7) {
1302 format (file, " (");
1303
1304 err |= control (file, "DP rc message type",
1305 dp_rc_msg_type_gen6,
1306 inst->bits3.gen7_dp.msg_type, &space);
1307
1308 format (file, ", %d, %d, %d)",
1309 inst->bits3.gen7_dp.binding_table_index,
1310 inst->bits3.gen7_dp.msg_control,
1311 inst->bits3.gen7_dp.msg_type);
1312 } else if (gen == 6) {
1313 format (file, " (");
1314
1315 err |= control (file, "DP rc message type",
1316 dp_rc_msg_type_gen6,
1317 inst->bits3.gen6_dp.msg_type, &space);
1318
1319 format (file, ", %d, %d, %d, %d)",
1320 inst->bits3.gen6_dp.binding_table_index,
1321 inst->bits3.gen6_dp.msg_control,
1322 inst->bits3.gen6_dp.msg_type,
1323 inst->bits3.gen6_dp.send_commit_msg);
1324 } else {
1325 format (file, " (%d, %d, %d, %d)",
1326 inst->bits3.dp_write.binding_table_index,
1327 (inst->bits3.dp_write.last_render_target << 3) |
1328 inst->bits3.dp_write.msg_control,
1329 inst->bits3.dp_write.msg_type,
1330 inst->bits3.dp_write.send_commit_msg);
1331 }
1332 break;
1333
1334 case BRW_SFID_URB:
1335 if (gen >= 5) {
1336 format (file, " %d", inst->bits3.urb_gen5.offset);
1337 } else {
1338 format (file, " %d", inst->bits3.urb.offset);
1339 }
1340
1341 space = 1;
1342 if (gen >= 5) {
1343 err |= control (file, "urb opcode", urb_opcode,
1344 inst->bits3.urb_gen5.opcode, &space);
1345 }
1346 err |= control (file, "urb swizzle", urb_swizzle,
1347 inst->bits3.urb.swizzle_control, &space);
1348 err |= control (file, "urb allocate", urb_allocate,
1349 inst->bits3.urb.allocate, &space);
1350 err |= control (file, "urb used", urb_used,
1351 inst->bits3.urb.used, &space);
1352 err |= control (file, "urb complete", urb_complete,
1353 inst->bits3.urb.complete, &space);
1354 break;
1355 case BRW_SFID_THREAD_SPAWNER:
1356 break;
1357 case GEN7_SFID_DATAPORT_DATA_CACHE:
1358 if (gen >= 7) {
1359 format (file, " (");
1360
1361 err |= control (file, "DP DC0 message type",
1362 dp_dc0_msg_type_gen7,
1363 inst->bits3.gen7_dp.msg_type, &space);
1364
1365 format (file, ", %d, ", inst->bits3.gen7_dp.binding_table_index);
1366
1367 switch (inst->bits3.gen7_dp.msg_type) {
1368 case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP:
1369 control (file, "atomic op", aop, inst->bits3.ud >> 8 & 0xf,
1370 &space);
1371 break;
1372 default:
1373 format (file, "%d", inst->bits3.gen7_dp.msg_control);
1374 }
1375 format (file, ")");
1376 break;
1377 }
1378 /* FALLTHROUGH */
1379
1380 case HSW_SFID_DATAPORT_DATA_CACHE_1:
1381 if (gen >= 7) {
1382 format (file, " (");
1383
1384 err |= control (file, "DP DC1 message type",
1385 dp_dc1_msg_type_hsw,
1386 inst->bits3.gen7_dp.msg_type, &space);
1387
1388 format (file, ", %d, ",
1389 inst->bits3.gen7_dp.binding_table_index);
1390
1391 switch (inst->bits3.gen7_dp.msg_type) {
1392 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP:
1393 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2:
1394 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP:
1395 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2:
1396 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP:
1397 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2:
1398 control (file, "atomic op", aop,
1399 inst->bits3.ud >> 8 & 0xf, &space);
1400 break;
1401 default:
1402 format (file, "%d", inst->bits3.gen7_dp.msg_control);
1403 }
1404 format (file, ")");
1405 break;
1406 }
1407 /* FALLTHROUGH */
1408
1409 default:
1410 format (file, "unsupported target %d", target);
1411 break;
1412 }
1413 if (space)
1414 string (file, " ");
1415 if (gen >= 5) {
1416 format (file, "mlen %d",
1417 inst->bits3.generic_gen5.msg_length);
1418 format (file, " rlen %d",
1419 inst->bits3.generic_gen5.response_length);
1420 } else {
1421 format (file, "mlen %d",
1422 inst->bits3.generic.msg_length);
1423 format (file, " rlen %d",
1424 inst->bits3.generic.response_length);
1425 }
1426 }
1427 pad (file, 64);
1428 if (inst->header.opcode != BRW_OPCODE_NOP) {
1429 string (file, "{");
1430 space = 1;
1431 err |= control(file, "access mode", access_mode, inst->header.access_mode, &space);
1432 if (gen >= 6)
1433 err |= control (file, "write enable control", wectrl, inst->header.mask_control, &space);
1434 else
1435 err |= control (file, "mask control", mask_ctrl, inst->header.mask_control, &space);
1436 err |= control (file, "dependency control", dep_ctrl, inst->header.dependency_control, &space);
1437
1438 if (gen >= 6)
1439 err |= qtr_ctrl (file, inst);
1440 else {
1441 if (inst->header.compression_control == BRW_COMPRESSION_COMPRESSED &&
1442 opcode[inst->header.opcode].ndst > 0 &&
1443 inst->bits1.da1.dest_reg_file == BRW_MESSAGE_REGISTER_FILE &&
1444 inst->bits1.da1.dest_reg_nr & (1 << 7)) {
1445 format (file, " compr4");
1446 } else {
1447 err |= control (file, "compression control", compr_ctrl,
1448 inst->header.compression_control, &space);
1449 }
1450 }
1451
1452 err |= control (file, "thread control", thread_ctrl, inst->header.thread_control, &space);
1453 if (gen >= 6)
1454 err |= control (file, "acc write control", accwr, inst->header.acc_wr_control, &space);
1455 if (inst->header.opcode == BRW_OPCODE_SEND ||
1456 inst->header.opcode == BRW_OPCODE_SENDC)
1457 err |= control (file, "end of thread", end_of_thread,
1458 inst->bits3.generic.end_of_thread, &space);
1459 if (space)
1460 string (file, " ");
1461 string (file, "}");
1462 }
1463 string (file, ";");
1464 newline (file);
1465 return err;
1466 }