2 * Copyright © 2008 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
30 #include "main/mtypes.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
40 [BRW_OPCODE_MOV
] = { .name
= "mov", .nsrc
= 1, .ndst
= 1 },
41 [BRW_OPCODE_FRC
] = { .name
= "frc", .nsrc
= 1, .ndst
= 1 },
42 [BRW_OPCODE_RNDU
] = { .name
= "rndu", .nsrc
= 1, .ndst
= 1 },
43 [BRW_OPCODE_RNDD
] = { .name
= "rndd", .nsrc
= 1, .ndst
= 1 },
44 [BRW_OPCODE_RNDE
] = { .name
= "rnde", .nsrc
= 1, .ndst
= 1 },
45 [BRW_OPCODE_RNDZ
] = { .name
= "rndz", .nsrc
= 1, .ndst
= 1 },
46 [BRW_OPCODE_NOT
] = { .name
= "not", .nsrc
= 1, .ndst
= 1 },
47 [BRW_OPCODE_LZD
] = { .name
= "lzd", .nsrc
= 1, .ndst
= 1 },
49 [BRW_OPCODE_MUL
] = { .name
= "mul", .nsrc
= 2, .ndst
= 1 },
50 [BRW_OPCODE_MAC
] = { .name
= "mac", .nsrc
= 2, .ndst
= 1 },
51 [BRW_OPCODE_MACH
] = { .name
= "mach", .nsrc
= 2, .ndst
= 1 },
52 [BRW_OPCODE_LINE
] = { .name
= "line", .nsrc
= 2, .ndst
= 1 },
53 [BRW_OPCODE_PLN
] = { .name
= "pln", .nsrc
= 2, .ndst
= 1 },
54 [BRW_OPCODE_SAD2
] = { .name
= "sad2", .nsrc
= 2, .ndst
= 1 },
55 [BRW_OPCODE_SADA2
] = { .name
= "sada2", .nsrc
= 2, .ndst
= 1 },
56 [BRW_OPCODE_DP4
] = { .name
= "dp4", .nsrc
= 2, .ndst
= 1 },
57 [BRW_OPCODE_DPH
] = { .name
= "dph", .nsrc
= 2, .ndst
= 1 },
58 [BRW_OPCODE_DP3
] = { .name
= "dp3", .nsrc
= 2, .ndst
= 1 },
59 [BRW_OPCODE_DP2
] = { .name
= "dp2", .nsrc
= 2, .ndst
= 1 },
60 [BRW_OPCODE_MATH
] = { .name
= "math", .nsrc
= 2, .ndst
= 1 },
62 [BRW_OPCODE_AVG
] = { .name
= "avg", .nsrc
= 2, .ndst
= 1 },
63 [BRW_OPCODE_ADD
] = { .name
= "add", .nsrc
= 2, .ndst
= 1 },
64 [BRW_OPCODE_SEL
] = { .name
= "sel", .nsrc
= 2, .ndst
= 1 },
65 [BRW_OPCODE_AND
] = { .name
= "and", .nsrc
= 2, .ndst
= 1 },
66 [BRW_OPCODE_OR
] = { .name
= "or", .nsrc
= 2, .ndst
= 1 },
67 [BRW_OPCODE_XOR
] = { .name
= "xor", .nsrc
= 2, .ndst
= 1 },
68 [BRW_OPCODE_SHR
] = { .name
= "shr", .nsrc
= 2, .ndst
= 1 },
69 [BRW_OPCODE_SHL
] = { .name
= "shl", .nsrc
= 2, .ndst
= 1 },
70 [BRW_OPCODE_ASR
] = { .name
= "asr", .nsrc
= 2, .ndst
= 1 },
71 [BRW_OPCODE_CMP
] = { .name
= "cmp", .nsrc
= 2, .ndst
= 1 },
72 [BRW_OPCODE_CMPN
] = { .name
= "cmpn", .nsrc
= 2, .ndst
= 1 },
74 [BRW_OPCODE_SEND
] = { .name
= "send", .nsrc
= 1, .ndst
= 1 },
75 [BRW_OPCODE_NOP
] = { .name
= "nop", .nsrc
= 0, .ndst
= 0 },
76 [BRW_OPCODE_JMPI
] = { .name
= "jmpi", .nsrc
= 1, .ndst
= 0 },
77 [BRW_OPCODE_IF
] = { .name
= "if", .nsrc
= 2, .ndst
= 0 },
78 [BRW_OPCODE_IFF
] = { .name
= "iff", .nsrc
= 2, .ndst
= 1 },
79 [BRW_OPCODE_WHILE
] = { .name
= "while", .nsrc
= 2, .ndst
= 0 },
80 [BRW_OPCODE_ELSE
] = { .name
= "else", .nsrc
= 2, .ndst
= 0 },
81 [BRW_OPCODE_BREAK
] = { .name
= "break", .nsrc
= 2, .ndst
= 0 },
82 [BRW_OPCODE_CONTINUE
] = { .name
= "cont", .nsrc
= 1, .ndst
= 0 },
83 [BRW_OPCODE_HALT
] = { .name
= "halt", .nsrc
= 1, .ndst
= 0 },
84 [BRW_OPCODE_MSAVE
] = { .name
= "msave", .nsrc
= 1, .ndst
= 1 },
85 [BRW_OPCODE_PUSH
] = { .name
= "push", .nsrc
= 1, .ndst
= 1 },
86 [BRW_OPCODE_MRESTORE
] = { .name
= "mrest", .nsrc
= 1, .ndst
= 1 },
87 [BRW_OPCODE_POP
] = { .name
= "pop", .nsrc
= 2, .ndst
= 0 },
88 [BRW_OPCODE_WAIT
] = { .name
= "wait", .nsrc
= 1, .ndst
= 0 },
89 [BRW_OPCODE_DO
] = { .name
= "do", .nsrc
= 0, .ndst
= 0 },
90 [BRW_OPCODE_ENDIF
] = { .name
= "endif", .nsrc
= 2, .ndst
= 0 },
93 char *conditional_modifier
[16] = {
94 [BRW_CONDITIONAL_NONE
] = "",
95 [BRW_CONDITIONAL_Z
] = ".e",
96 [BRW_CONDITIONAL_NZ
] = ".ne",
97 [BRW_CONDITIONAL_G
] = ".g",
98 [BRW_CONDITIONAL_GE
] = ".ge",
99 [BRW_CONDITIONAL_L
] = ".l",
100 [BRW_CONDITIONAL_LE
] = ".le",
101 [BRW_CONDITIONAL_R
] = ".r",
102 [BRW_CONDITIONAL_O
] = ".o",
103 [BRW_CONDITIONAL_U
] = ".u",
116 char *vert_stride
[16] = {
135 char *horiz_stride
[4] = {
142 char *chan_sel
[4] = {
149 char *dest_condmod
[16] = {
152 char *debug_ctrl
[2] = {
157 char *saturate
[2] = {
167 char *exec_size
[8] = {
176 char *pred_inv
[2] = {
181 char *pred_ctrl_align16
[16] = {
191 char *pred_ctrl_align1
[16] = {
205 char *thread_ctrl
[4] = {
210 char *compr_ctrl
[4] = {
217 char *dep_ctrl
[4] = {
221 [3] = "NoDDClr,NoDDChk",
224 char *mask_ctrl
[4] = {
229 char *access_mode
[2] = {
234 char *reg_encoding
[8] = {
244 int reg_type_size
[8] = {
254 char *imm_encoding
[8] = {
264 char *reg_file
[4] = {
271 char *writemask
[16] = {
290 char *end_of_thread
[2] = {
295 char *target_function
[16] = {
296 [BRW_MESSAGE_TARGET_NULL
] = "null",
297 [BRW_MESSAGE_TARGET_MATH
] = "math",
298 [BRW_MESSAGE_TARGET_SAMPLER
] = "sampler",
299 [BRW_MESSAGE_TARGET_GATEWAY
] = "gateway",
300 [BRW_MESSAGE_TARGET_DATAPORT_READ
] = "read",
301 [BRW_MESSAGE_TARGET_DATAPORT_WRITE
] = "write",
302 [BRW_MESSAGE_TARGET_URB
] = "urb",
303 [BRW_MESSAGE_TARGET_THREAD_SPAWNER
] = "thread_spawner"
306 char *math_function
[16] = {
307 [BRW_MATH_FUNCTION_INV
] = "inv",
308 [BRW_MATH_FUNCTION_LOG
] = "log",
309 [BRW_MATH_FUNCTION_EXP
] = "exp",
310 [BRW_MATH_FUNCTION_SQRT
] = "sqrt",
311 [BRW_MATH_FUNCTION_RSQ
] = "rsq",
312 [BRW_MATH_FUNCTION_SIN
] = "sin",
313 [BRW_MATH_FUNCTION_COS
] = "cos",
314 [BRW_MATH_FUNCTION_SINCOS
] = "sincos",
315 [BRW_MATH_FUNCTION_TAN
] = "tan",
316 [BRW_MATH_FUNCTION_POW
] = "pow",
317 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
] = "intdivmod",
318 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
] = "intmod",
319 [BRW_MATH_FUNCTION_INT_DIV_REMAINDER
] = "intdiv",
322 char *math_saturate
[2] = {
327 char *math_signed
[2] = {
332 char *math_scalar
[2] = {
337 char *math_precision
[2] = {
339 [1] = "partial_precision"
342 char *urb_opcode
[2] = {
347 char *urb_swizzle
[4] = {
348 [BRW_URB_SWIZZLE_NONE
] = "",
349 [BRW_URB_SWIZZLE_INTERLEAVE
] = "interleave",
350 [BRW_URB_SWIZZLE_TRANSPOSE
] = "transpose",
353 char *urb_allocate
[2] = {
358 char *urb_used
[2] = {
363 char *urb_complete
[2] = {
368 char *sampler_target_format
[4] = {
377 static int string (FILE *file
, char *string
)
379 fputs (string
, file
);
380 column
+= strlen (string
);
384 static int format (FILE *f
, char *format
, ...)
388 va_start (args
, format
);
390 vsnprintf (buf
, sizeof (buf
) - 1, format
, args
);
396 static int newline (FILE *f
)
403 static int pad (FILE *f
, int c
)
411 static int control (FILE *file
, char *name
, char *ctrl
[], GLuint id
, int *space
)
414 fprintf (file
, "*** invalid %s value %d ",
422 string (file
, ctrl
[id
]);
429 static int print_opcode (FILE *file
, int id
)
431 if (!opcode
[id
].name
) {
432 format (file
, "*** invalid opcode value %d ", id
);
435 string (file
, opcode
[id
].name
);
439 static int reg (FILE *file
, GLuint _reg_file
, GLuint _reg_nr
)
443 /* Clear the Compr4 instruction compression bit. */
444 if (_reg_file
== BRW_MESSAGE_REGISTER_FILE
)
445 _reg_nr
&= ~(1 << 7);
447 if (_reg_file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
448 switch (_reg_nr
& 0xf0) {
450 string (file
, "null");
452 case BRW_ARF_ADDRESS
:
453 format (file
, "a%d", _reg_nr
& 0x0f);
455 case BRW_ARF_ACCUMULATOR
:
456 format (file
, "acc%d", _reg_nr
& 0x0f);
459 format (file
, "mask%d", _reg_nr
& 0x0f);
461 case BRW_ARF_MASK_STACK
:
462 format (file
, "msd%d", _reg_nr
& 0x0f);
465 format (file
, "sr%d", _reg_nr
& 0x0f);
467 case BRW_ARF_CONTROL
:
468 format (file
, "cr%d", _reg_nr
& 0x0f);
470 case BRW_ARF_NOTIFICATION_COUNT
:
471 format (file
, "n%d", _reg_nr
& 0x0f);
478 format (file
, "ARF%d", _reg_nr
);
482 err
|= control (file
, "src reg file", reg_file
, _reg_file
, NULL
);
483 format (file
, "%d", _reg_nr
);
488 static int dest (FILE *file
, struct brw_instruction
*inst
)
492 if (inst
->header
.access_mode
== BRW_ALIGN_1
)
494 if (inst
->bits1
.da1
.dest_address_mode
== BRW_ADDRESS_DIRECT
)
496 err
|= reg (file
, inst
->bits1
.da1
.dest_reg_file
, inst
->bits1
.da1
.dest_reg_nr
);
499 if (inst
->bits1
.da1
.dest_subreg_nr
)
500 format (file
, ".%d", inst
->bits1
.da1
.dest_subreg_nr
/
501 reg_type_size
[inst
->bits1
.da1
.dest_reg_type
]);
502 format (file
, "<%d>", inst
->bits1
.da1
.dest_horiz_stride
);
503 err
|= control (file
, "dest reg encoding", reg_encoding
, inst
->bits1
.da1
.dest_reg_type
, NULL
);
507 string (file
, "g[a0");
508 if (inst
->bits1
.ia1
.dest_subreg_nr
)
509 format (file
, ".%d", inst
->bits1
.ia1
.dest_subreg_nr
/
510 reg_type_size
[inst
->bits1
.ia1
.dest_reg_type
]);
511 if (inst
->bits1
.ia1
.dest_indirect_offset
)
512 format (file
, " %d", inst
->bits1
.ia1
.dest_indirect_offset
);
514 format (file
, "<%d>", inst
->bits1
.ia1
.dest_horiz_stride
);
515 err
|= control (file
, "dest reg encoding", reg_encoding
, inst
->bits1
.ia1
.dest_reg_type
, NULL
);
520 if (inst
->bits1
.da16
.dest_address_mode
== BRW_ADDRESS_DIRECT
)
522 err
|= reg (file
, inst
->bits1
.da16
.dest_reg_file
, inst
->bits1
.da16
.dest_reg_nr
);
525 if (inst
->bits1
.da16
.dest_subreg_nr
)
526 format (file
, ".%d", inst
->bits1
.da16
.dest_subreg_nr
/
527 reg_type_size
[inst
->bits1
.da16
.dest_reg_type
]);
528 string (file
, "<1>");
529 err
|= control (file
, "writemask", writemask
, inst
->bits1
.da16
.dest_writemask
, NULL
);
530 err
|= control (file
, "dest reg encoding", reg_encoding
, inst
->bits1
.da16
.dest_reg_type
, NULL
);
535 string (file
, "Indirect align16 address mode not supported");
542 static int src_align1_region (FILE *file
,
543 GLuint _vert_stride
, GLuint _width
, GLuint _horiz_stride
)
547 err
|= control (file
, "vert stride", vert_stride
, _vert_stride
, NULL
);
549 err
|= control (file
, "width", width
, _width
, NULL
);
551 err
|= control (file
, "horiz_stride", horiz_stride
, _horiz_stride
, NULL
);
556 static int src_da1 (FILE *file
, GLuint type
, GLuint _reg_file
,
557 GLuint _vert_stride
, GLuint _width
, GLuint _horiz_stride
,
558 GLuint reg_num
, GLuint sub_reg_num
, GLuint __abs
, GLuint _negate
)
561 err
|= control (file
, "negate", negate
, _negate
, NULL
);
562 err
|= control (file
, "abs", _abs
, __abs
, NULL
);
564 err
|= reg (file
, _reg_file
, reg_num
);
568 format (file
, ".%d", sub_reg_num
/ reg_type_size
[type
]); /* use formal style like spec */
569 src_align1_region (file
, _vert_stride
, _width
, _horiz_stride
);
570 err
|= control (file
, "src reg encoding", reg_encoding
, type
, NULL
);
574 static int src_ia1 (FILE *file
,
578 GLuint _addr_subreg_nr
,
582 GLuint _horiz_stride
,
587 err
|= control (file
, "negate", negate
, _negate
, NULL
);
588 err
|= control (file
, "abs", _abs
, __abs
, NULL
);
590 string (file
, "g[a0");
592 format (file
, ".%d", _addr_subreg_nr
);
594 format (file
, " %d", _addr_imm
);
596 src_align1_region (file
, _vert_stride
, _width
, _horiz_stride
);
597 err
|= control (file
, "src reg encoding", reg_encoding
, type
, NULL
);
601 static int src_da16 (FILE *file
,
615 err
|= control (file
, "negate", negate
, _negate
, NULL
);
616 err
|= control (file
, "abs", _abs
, __abs
, NULL
);
618 err
|= reg (file
, _reg_file
, _reg_nr
);
622 /* bit4 for subreg number byte addressing. Make this same meaning as
623 in da1 case, so output looks consistent. */
624 format (file
, ".%d", 16 / reg_type_size
[_reg_type
]);
626 err
|= control (file
, "vert stride", vert_stride
, _vert_stride
, NULL
);
627 string (file
, ",4,1>");
629 * Three kinds of swizzle display:
630 * identity - nothing printed
631 * 1->all - print the single channel
632 * 1->1 - print the mapping
634 if (swz_x
== BRW_CHANNEL_X
&&
635 swz_y
== BRW_CHANNEL_Y
&&
636 swz_z
== BRW_CHANNEL_Z
&&
637 swz_w
== BRW_CHANNEL_W
)
641 else if (swz_x
== swz_y
&& swz_x
== swz_z
&& swz_x
== swz_w
)
644 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
649 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
650 err
|= control (file
, "channel select", chan_sel
, swz_y
, NULL
);
651 err
|= control (file
, "channel select", chan_sel
, swz_z
, NULL
);
652 err
|= control (file
, "channel select", chan_sel
, swz_w
, NULL
);
658 static int imm (FILE *file
, GLuint type
, struct brw_instruction
*inst
) {
660 case BRW_REGISTER_TYPE_UD
:
661 format (file
, "0x%08xUD", inst
->bits3
.ud
);
663 case BRW_REGISTER_TYPE_D
:
664 format (file
, "%dD", inst
->bits3
.d
);
666 case BRW_REGISTER_TYPE_UW
:
667 format (file
, "0x%04xUW", (uint16_t) inst
->bits3
.ud
);
669 case BRW_REGISTER_TYPE_W
:
670 format (file
, "%dW", (int16_t) inst
->bits3
.d
);
672 case BRW_REGISTER_TYPE_UB
:
673 format (file
, "0x%02xUB", (int8_t) inst
->bits3
.ud
);
675 case BRW_REGISTER_TYPE_VF
:
676 format (file
, "Vector Float");
678 case BRW_REGISTER_TYPE_V
:
679 format (file
, "0x%08xV", inst
->bits3
.ud
);
681 case BRW_REGISTER_TYPE_F
:
682 format (file
, "%-gF", inst
->bits3
.f
);
687 static int src0 (FILE *file
, struct brw_instruction
*inst
)
689 if (inst
->bits1
.da1
.src0_reg_file
== BRW_IMMEDIATE_VALUE
)
690 return imm (file
, inst
->bits1
.da1
.src0_reg_type
,
692 else if (inst
->header
.access_mode
== BRW_ALIGN_1
)
694 if (inst
->bits2
.da1
.src0_address_mode
== BRW_ADDRESS_DIRECT
)
696 return src_da1 (file
,
697 inst
->bits1
.da1
.src0_reg_type
,
698 inst
->bits1
.da1
.src0_reg_file
,
699 inst
->bits2
.da1
.src0_vert_stride
,
700 inst
->bits2
.da1
.src0_width
,
701 inst
->bits2
.da1
.src0_horiz_stride
,
702 inst
->bits2
.da1
.src0_reg_nr
,
703 inst
->bits2
.da1
.src0_subreg_nr
,
704 inst
->bits2
.da1
.src0_abs
,
705 inst
->bits2
.da1
.src0_negate
);
709 return src_ia1 (file
,
710 inst
->bits1
.ia1
.src0_reg_type
,
711 inst
->bits1
.ia1
.src0_reg_file
,
712 inst
->bits2
.ia1
.src0_indirect_offset
,
713 inst
->bits2
.ia1
.src0_subreg_nr
,
714 inst
->bits2
.ia1
.src0_negate
,
715 inst
->bits2
.ia1
.src0_abs
,
716 inst
->bits2
.ia1
.src0_address_mode
,
717 inst
->bits2
.ia1
.src0_horiz_stride
,
718 inst
->bits2
.ia1
.src0_width
,
719 inst
->bits2
.ia1
.src0_vert_stride
);
724 if (inst
->bits2
.da16
.src0_address_mode
== BRW_ADDRESS_DIRECT
)
726 return src_da16 (file
,
727 inst
->bits1
.da16
.src0_reg_type
,
728 inst
->bits1
.da16
.src0_reg_file
,
729 inst
->bits2
.da16
.src0_vert_stride
,
730 inst
->bits2
.da16
.src0_reg_nr
,
731 inst
->bits2
.da16
.src0_subreg_nr
,
732 inst
->bits2
.da16
.src0_abs
,
733 inst
->bits2
.da16
.src0_negate
,
734 inst
->bits2
.da16
.src0_swz_x
,
735 inst
->bits2
.da16
.src0_swz_y
,
736 inst
->bits2
.da16
.src0_swz_z
,
737 inst
->bits2
.da16
.src0_swz_w
);
741 string (file
, "Indirect align16 address mode not supported");
747 static int src1 (FILE *file
, struct brw_instruction
*inst
)
749 if (inst
->bits1
.da1
.src1_reg_file
== BRW_IMMEDIATE_VALUE
)
750 return imm (file
, inst
->bits1
.da1
.src1_reg_type
,
752 else if (inst
->header
.access_mode
== BRW_ALIGN_1
)
754 if (inst
->bits3
.da1
.src1_address_mode
== BRW_ADDRESS_DIRECT
)
756 return src_da1 (file
,
757 inst
->bits1
.da1
.src1_reg_type
,
758 inst
->bits1
.da1
.src1_reg_file
,
759 inst
->bits3
.da1
.src1_vert_stride
,
760 inst
->bits3
.da1
.src1_width
,
761 inst
->bits3
.da1
.src1_horiz_stride
,
762 inst
->bits3
.da1
.src1_reg_nr
,
763 inst
->bits3
.da1
.src1_subreg_nr
,
764 inst
->bits3
.da1
.src1_abs
,
765 inst
->bits3
.da1
.src1_negate
);
769 return src_ia1 (file
,
770 inst
->bits1
.ia1
.src1_reg_type
,
771 inst
->bits1
.ia1
.src1_reg_file
,
772 inst
->bits3
.ia1
.src1_indirect_offset
,
773 inst
->bits3
.ia1
.src1_subreg_nr
,
774 inst
->bits3
.ia1
.src1_negate
,
775 inst
->bits3
.ia1
.src1_abs
,
776 inst
->bits3
.ia1
.src1_address_mode
,
777 inst
->bits3
.ia1
.src1_horiz_stride
,
778 inst
->bits3
.ia1
.src1_width
,
779 inst
->bits3
.ia1
.src1_vert_stride
);
784 if (inst
->bits3
.da16
.src1_address_mode
== BRW_ADDRESS_DIRECT
)
786 return src_da16 (file
,
787 inst
->bits1
.da16
.src1_reg_type
,
788 inst
->bits1
.da16
.src1_reg_file
,
789 inst
->bits3
.da16
.src1_vert_stride
,
790 inst
->bits3
.da16
.src1_reg_nr
,
791 inst
->bits3
.da16
.src1_subreg_nr
,
792 inst
->bits3
.da16
.src1_abs
,
793 inst
->bits3
.da16
.src1_negate
,
794 inst
->bits3
.da16
.src1_swz_x
,
795 inst
->bits3
.da16
.src1_swz_y
,
796 inst
->bits3
.da16
.src1_swz_z
,
797 inst
->bits3
.da16
.src1_swz_w
);
801 string (file
, "Indirect align16 address mode not supported");
807 int brw_disasm (FILE *file
, struct brw_instruction
*inst
, int gen
)
812 if (inst
->header
.predicate_control
) {
814 err
|= control (file
, "predicate inverse", pred_inv
, inst
->header
.predicate_inverse
, NULL
);
816 if (inst
->bits2
.da1
.flag_reg_nr
)
817 format (file
, ".%d", inst
->bits2
.da1
.flag_reg_nr
);
818 if (inst
->header
.access_mode
== BRW_ALIGN_1
)
819 err
|= control (file
, "predicate control align1", pred_ctrl_align1
,
820 inst
->header
.predicate_control
, NULL
);
822 err
|= control (file
, "predicate control align16", pred_ctrl_align16
,
823 inst
->header
.predicate_control
, NULL
);
827 err
|= print_opcode (file
, inst
->header
.opcode
);
828 err
|= control (file
, "saturate", saturate
, inst
->header
.saturate
, NULL
);
829 err
|= control (file
, "debug control", debug_ctrl
, inst
->header
.debug_control
, NULL
);
831 if (inst
->header
.opcode
== BRW_OPCODE_MATH
) {
833 err
|= control (file
, "function", math_function
,
834 inst
->header
.destreg__conditionalmod
, NULL
);
835 } else if (inst
->header
.opcode
!= BRW_OPCODE_SEND
)
836 err
|= control (file
, "conditional modifier", conditional_modifier
,
837 inst
->header
.destreg__conditionalmod
, NULL
);
839 if (inst
->header
.opcode
!= BRW_OPCODE_NOP
) {
841 err
|= control (file
, "execution size", exec_size
, inst
->header
.execution_size
, NULL
);
845 if (inst
->header
.opcode
== BRW_OPCODE_SEND
)
846 format (file
, " %d", inst
->header
.destreg__conditionalmod
);
848 if (opcode
[inst
->header
.opcode
].ndst
> 0) {
850 err
|= dest (file
, inst
);
852 if (opcode
[inst
->header
.opcode
].nsrc
> 0) {
854 err
|= src0 (file
, inst
);
856 if (opcode
[inst
->header
.opcode
].nsrc
> 1) {
858 err
|= src1 (file
, inst
);
861 if (inst
->header
.opcode
== BRW_OPCODE_SEND
) {
865 target
= inst
->header
.destreg__conditionalmod
;
867 target
= inst
->bits2
.send_gen5
.sfid
;
869 target
= inst
->bits3
.generic
.msg_target
;
874 err
|= control (file
, "target function", target_function
,
878 case BRW_MESSAGE_TARGET_MATH
:
879 err
|= control (file
, "math function", math_function
,
880 inst
->bits3
.math
.function
, &space
);
881 err
|= control (file
, "math saturate", math_saturate
,
882 inst
->bits3
.math
.saturate
, &space
);
883 err
|= control (file
, "math signed", math_signed
,
884 inst
->bits3
.math
.int_type
, &space
);
885 err
|= control (file
, "math scalar", math_scalar
,
886 inst
->bits3
.math
.data_type
, &space
);
887 err
|= control (file
, "math precision", math_precision
,
888 inst
->bits3
.math
.precision
, &space
);
890 case BRW_MESSAGE_TARGET_SAMPLER
:
892 format (file
, " (%d, %d, %d, %d)",
893 inst
->bits3
.sampler_gen5
.binding_table_index
,
894 inst
->bits3
.sampler_gen5
.sampler
,
895 inst
->bits3
.sampler_gen5
.msg_type
,
896 inst
->bits3
.sampler_gen5
.simd_mode
);
897 } else if (0 /* FINISHME: is_g4x */) {
898 format (file
, " (%d, %d)",
899 inst
->bits3
.sampler_g4x
.binding_table_index
,
900 inst
->bits3
.sampler_g4x
.sampler
);
902 format (file
, " (%d, %d, ",
903 inst
->bits3
.sampler
.binding_table_index
,
904 inst
->bits3
.sampler
.sampler
);
905 err
|= control (file
, "sampler target format",
906 sampler_target_format
,
907 inst
->bits3
.sampler
.return_format
, NULL
);
911 case BRW_MESSAGE_TARGET_DATAPORT_READ
:
913 format (file
, " (%d, %d, %d, %d, %d, %d)",
914 inst
->bits3
.dp_render_cache
.binding_table_index
,
915 inst
->bits3
.dp_render_cache
.msg_control
,
916 inst
->bits3
.dp_render_cache
.msg_type
,
917 inst
->bits3
.dp_render_cache
.send_commit_msg
,
918 inst
->bits3
.dp_render_cache
.msg_length
,
919 inst
->bits3
.dp_render_cache
.response_length
);
920 } else if (gen
>= 5) {
921 format (file
, " (%d, %d, %d)",
922 inst
->bits3
.dp_read_gen5
.binding_table_index
,
923 inst
->bits3
.dp_read_gen5
.msg_control
,
924 inst
->bits3
.dp_read_gen5
.msg_type
);
926 format (file
, " (%d, %d, %d)",
927 inst
->bits3
.dp_read
.binding_table_index
,
928 inst
->bits3
.dp_read
.msg_control
,
929 inst
->bits3
.dp_read
.msg_type
);
932 case BRW_MESSAGE_TARGET_DATAPORT_WRITE
:
934 format (file
, " (%d, %d, %d, %d, %d, %d)",
935 inst
->bits3
.dp_render_cache
.binding_table_index
,
936 inst
->bits3
.dp_render_cache
.msg_control
,
937 inst
->bits3
.dp_render_cache
.msg_type
,
938 inst
->bits3
.dp_render_cache
.send_commit_msg
,
939 inst
->bits3
.dp_render_cache
.msg_length
,
940 inst
->bits3
.dp_render_cache
.response_length
);
942 format (file
, " (%d, %d, %d, %d)",
943 inst
->bits3
.dp_write
.binding_table_index
,
944 (inst
->bits3
.dp_write
.pixel_scoreboard_clear
<< 3) |
945 inst
->bits3
.dp_write
.msg_control
,
946 inst
->bits3
.dp_write
.msg_type
,
947 inst
->bits3
.dp_write
.send_commit_msg
);
950 case BRW_MESSAGE_TARGET_URB
:
952 format (file
, " %d", inst
->bits3
.urb_gen5
.offset
);
954 format (file
, " %d", inst
->bits3
.urb
.offset
);
959 err
|= control (file
, "urb opcode", urb_opcode
,
960 inst
->bits3
.urb_gen5
.opcode
, &space
);
962 err
|= control (file
, "urb swizzle", urb_swizzle
,
963 inst
->bits3
.urb
.swizzle_control
, &space
);
964 err
|= control (file
, "urb allocate", urb_allocate
,
965 inst
->bits3
.urb
.allocate
, &space
);
966 err
|= control (file
, "urb used", urb_used
,
967 inst
->bits3
.urb
.used
, &space
);
968 err
|= control (file
, "urb complete", urb_complete
,
969 inst
->bits3
.urb
.complete
, &space
);
971 format (file
, " mlen %d, rlen %d\n",
972 inst
->bits3
.urb_gen5
.msg_length
,
973 inst
->bits3
.urb_gen5
.response_length
);
976 case BRW_MESSAGE_TARGET_THREAD_SPAWNER
:
979 format (file
, "unsupported target %d", target
);
985 format (file
, "mlen %d",
986 inst
->bits3
.generic_gen5
.msg_length
);
987 format (file
, " rlen %d",
988 inst
->bits3
.generic_gen5
.response_length
);
990 format (file
, "mlen %d",
991 inst
->bits3
.generic
.msg_length
);
992 format (file
, " rlen %d",
993 inst
->bits3
.generic
.response_length
);
997 if (inst
->header
.opcode
!= BRW_OPCODE_NOP
) {
1000 err
|= control(file
, "access mode", access_mode
, inst
->header
.access_mode
, &space
);
1001 err
|= control (file
, "mask control", mask_ctrl
, inst
->header
.mask_control
, &space
);
1002 err
|= control (file
, "dependency control", dep_ctrl
, inst
->header
.dependency_control
, &space
);
1004 if (inst
->header
.compression_control
== BRW_COMPRESSION_COMPRESSED
&&
1005 opcode
[inst
->header
.opcode
].ndst
> 0 &&
1006 inst
->bits1
.da1
.dest_reg_file
== BRW_MESSAGE_REGISTER_FILE
&&
1007 inst
->bits1
.da1
.dest_reg_nr
& (1 << 7)) {
1008 format (file
, " compr4");
1010 err
|= control (file
, "compression control", compr_ctrl
,
1011 inst
->header
.compression_control
, &space
);
1013 err
|= control (file
, "thread control", thread_ctrl
, inst
->header
.thread_control
, &space
);
1015 err
|= control (file
, "acc write control", accwr
, inst
->header
.acc_wr_control
, &space
);
1016 if (inst
->header
.opcode
== BRW_OPCODE_SEND
)
1017 err
|= control (file
, "end of thread", end_of_thread
,
1018 inst
->bits3
.generic
.end_of_thread
, &space
);