2 * Copyright © 2008 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
30 #include "main/mtypes.h"
32 #include "brw_context.h"
33 #include "brw_defines.h"
35 const struct opcode_desc opcode_descs
[128] = {
36 [BRW_OPCODE_MOV
] = { .name
= "mov", .nsrc
= 1, .ndst
= 1 },
37 [BRW_OPCODE_FRC
] = { .name
= "frc", .nsrc
= 1, .ndst
= 1 },
38 [BRW_OPCODE_RNDU
] = { .name
= "rndu", .nsrc
= 1, .ndst
= 1 },
39 [BRW_OPCODE_RNDD
] = { .name
= "rndd", .nsrc
= 1, .ndst
= 1 },
40 [BRW_OPCODE_RNDE
] = { .name
= "rnde", .nsrc
= 1, .ndst
= 1 },
41 [BRW_OPCODE_RNDZ
] = { .name
= "rndz", .nsrc
= 1, .ndst
= 1 },
42 [BRW_OPCODE_NOT
] = { .name
= "not", .nsrc
= 1, .ndst
= 1 },
43 [BRW_OPCODE_LZD
] = { .name
= "lzd", .nsrc
= 1, .ndst
= 1 },
44 [BRW_OPCODE_F32TO16
] = { .name
= "f32to16", .nsrc
= 1, .ndst
= 1 },
45 [BRW_OPCODE_F16TO32
] = { .name
= "f16to32", .nsrc
= 1, .ndst
= 1 },
46 [BRW_OPCODE_BFREV
] = { .name
= "bfrev", .nsrc
= 1, .ndst
= 1},
47 [BRW_OPCODE_FBH
] = { .name
= "fbh", .nsrc
= 1, .ndst
= 1},
48 [BRW_OPCODE_FBL
] = { .name
= "fbl", .nsrc
= 1, .ndst
= 1},
49 [BRW_OPCODE_CBIT
] = { .name
= "cbit", .nsrc
= 1, .ndst
= 1},
51 [BRW_OPCODE_MUL
] = { .name
= "mul", .nsrc
= 2, .ndst
= 1 },
52 [BRW_OPCODE_MAC
] = { .name
= "mac", .nsrc
= 2, .ndst
= 1 },
53 [BRW_OPCODE_MACH
] = { .name
= "mach", .nsrc
= 2, .ndst
= 1 },
54 [BRW_OPCODE_LINE
] = { .name
= "line", .nsrc
= 2, .ndst
= 1 },
55 [BRW_OPCODE_PLN
] = { .name
= "pln", .nsrc
= 2, .ndst
= 1 },
56 [BRW_OPCODE_MAD
] = { .name
= "mad", .nsrc
= 3, .ndst
= 1 },
57 [BRW_OPCODE_LRP
] = { .name
= "lrp", .nsrc
= 3, .ndst
= 1 },
58 [BRW_OPCODE_SAD2
] = { .name
= "sad2", .nsrc
= 2, .ndst
= 1 },
59 [BRW_OPCODE_SADA2
] = { .name
= "sada2", .nsrc
= 2, .ndst
= 1 },
60 [BRW_OPCODE_DP4
] = { .name
= "dp4", .nsrc
= 2, .ndst
= 1 },
61 [BRW_OPCODE_DPH
] = { .name
= "dph", .nsrc
= 2, .ndst
= 1 },
62 [BRW_OPCODE_DP3
] = { .name
= "dp3", .nsrc
= 2, .ndst
= 1 },
63 [BRW_OPCODE_DP2
] = { .name
= "dp2", .nsrc
= 2, .ndst
= 1 },
64 [BRW_OPCODE_MATH
] = { .name
= "math", .nsrc
= 2, .ndst
= 1 },
66 [BRW_OPCODE_AVG
] = { .name
= "avg", .nsrc
= 2, .ndst
= 1 },
67 [BRW_OPCODE_ADD
] = { .name
= "add", .nsrc
= 2, .ndst
= 1 },
68 [BRW_OPCODE_SEL
] = { .name
= "sel", .nsrc
= 2, .ndst
= 1 },
69 [BRW_OPCODE_AND
] = { .name
= "and", .nsrc
= 2, .ndst
= 1 },
70 [BRW_OPCODE_OR
] = { .name
= "or", .nsrc
= 2, .ndst
= 1 },
71 [BRW_OPCODE_XOR
] = { .name
= "xor", .nsrc
= 2, .ndst
= 1 },
72 [BRW_OPCODE_SHR
] = { .name
= "shr", .nsrc
= 2, .ndst
= 1 },
73 [BRW_OPCODE_SHL
] = { .name
= "shl", .nsrc
= 2, .ndst
= 1 },
74 [BRW_OPCODE_ASR
] = { .name
= "asr", .nsrc
= 2, .ndst
= 1 },
75 [BRW_OPCODE_CMP
] = { .name
= "cmp", .nsrc
= 2, .ndst
= 1 },
76 [BRW_OPCODE_CMPN
] = { .name
= "cmpn", .nsrc
= 2, .ndst
= 1 },
77 [BRW_OPCODE_BFE
] = { .name
= "bfe", .nsrc
= 3, .ndst
= 1},
78 [BRW_OPCODE_BFI1
] = { .name
= "bfi1", .nsrc
= 2, .ndst
= 1},
79 [BRW_OPCODE_BFI2
] = { .name
= "bfi2", .nsrc
= 3, .ndst
= 1},
80 [BRW_OPCODE_ADDC
] = { .name
= "addc", .nsrc
= 2, .ndst
= 1},
81 [BRW_OPCODE_SUBB
] = { .name
= "subb", .nsrc
= 2, .ndst
= 1},
83 [BRW_OPCODE_SEND
] = { .name
= "send", .nsrc
= 1, .ndst
= 1 },
84 [BRW_OPCODE_SENDC
] = { .name
= "sendc", .nsrc
= 1, .ndst
= 1 },
85 [BRW_OPCODE_NOP
] = { .name
= "nop", .nsrc
= 0, .ndst
= 0 },
86 [BRW_OPCODE_JMPI
] = { .name
= "jmpi", .nsrc
= 0, .ndst
= 0 },
87 [BRW_OPCODE_IF
] = { .name
= "if", .nsrc
= 2, .ndst
= 0 },
88 [BRW_OPCODE_IFF
] = { .name
= "iff", .nsrc
= 2, .ndst
= 1 },
89 [BRW_OPCODE_WHILE
] = { .name
= "while", .nsrc
= 2, .ndst
= 0 },
90 [BRW_OPCODE_ELSE
] = { .name
= "else", .nsrc
= 2, .ndst
= 0 },
91 [BRW_OPCODE_BREAK
] = { .name
= "break", .nsrc
= 2, .ndst
= 0 },
92 [BRW_OPCODE_CONTINUE
] = { .name
= "cont", .nsrc
= 1, .ndst
= 0 },
93 [BRW_OPCODE_HALT
] = { .name
= "halt", .nsrc
= 1, .ndst
= 0 },
94 [BRW_OPCODE_MSAVE
] = { .name
= "msave", .nsrc
= 1, .ndst
= 1 },
95 [BRW_OPCODE_PUSH
] = { .name
= "push", .nsrc
= 1, .ndst
= 1 },
96 [BRW_OPCODE_MRESTORE
] = { .name
= "mrest", .nsrc
= 1, .ndst
= 1 },
97 [BRW_OPCODE_POP
] = { .name
= "pop", .nsrc
= 2, .ndst
= 0 },
98 [BRW_OPCODE_WAIT
] = { .name
= "wait", .nsrc
= 1, .ndst
= 0 },
99 [BRW_OPCODE_DO
] = { .name
= "do", .nsrc
= 0, .ndst
= 0 },
100 [BRW_OPCODE_ENDIF
] = { .name
= "endif", .nsrc
= 2, .ndst
= 0 },
102 static const struct opcode_desc
*opcode
= opcode_descs
;
104 const char * const conditional_modifier
[16] = {
105 [BRW_CONDITIONAL_NONE
] = "",
106 [BRW_CONDITIONAL_Z
] = ".e",
107 [BRW_CONDITIONAL_NZ
] = ".ne",
108 [BRW_CONDITIONAL_G
] = ".g",
109 [BRW_CONDITIONAL_GE
] = ".ge",
110 [BRW_CONDITIONAL_L
] = ".l",
111 [BRW_CONDITIONAL_LE
] = ".le",
112 [BRW_CONDITIONAL_R
] = ".r",
113 [BRW_CONDITIONAL_O
] = ".o",
114 [BRW_CONDITIONAL_U
] = ".u",
117 static const char * const negate
[2] = {
122 static const char * const _abs
[2] = {
127 static const char * const vert_stride
[16] = {
138 static const char * const width
[8] = {
146 static const char * const horiz_stride
[4] = {
153 static const char * const chan_sel
[4] = {
160 static const char * const debug_ctrl
[2] = {
165 static const char * const saturate
[2] = {
170 static const char * const cmpt_ctrl
[2] = {
175 static const char * const accwr
[2] = {
180 static const char * const wectrl
[2] = {
185 static const char * const exec_size
[8] = {
194 static const char * const pred_inv
[2] = {
199 static const char * const pred_ctrl_align16
[16] = {
209 static const char * const pred_ctrl_align1
[16] = {
223 static const char * const thread_ctrl
[4] = {
228 static const char * const compr_ctrl
[4] = {
235 static const char * const dep_ctrl
[4] = {
239 [3] = "NoDDClr,NoDDChk",
242 static const char * const mask_ctrl
[4] = {
247 static const char * const access_mode
[2] = {
252 static const char * const reg_encoding
[8] = {
262 const char * const three_source_reg_encoding
[] = {
263 [BRW_3SRC_TYPE_F
] = "F",
264 [BRW_3SRC_TYPE_D
] = "D",
265 [BRW_3SRC_TYPE_UD
] = "UD",
268 const int reg_type_size
[8] = {
278 static const char * const reg_file
[4] = {
285 static const char * const writemask
[16] = {
304 static const char * const end_of_thread
[2] = {
309 static const char * const target_function
[16] = {
310 [BRW_SFID_NULL
] = "null",
311 [BRW_SFID_MATH
] = "math",
312 [BRW_SFID_SAMPLER
] = "sampler",
313 [BRW_SFID_MESSAGE_GATEWAY
] = "gateway",
314 [BRW_SFID_DATAPORT_READ
] = "read",
315 [BRW_SFID_DATAPORT_WRITE
] = "write",
316 [BRW_SFID_URB
] = "urb",
317 [BRW_SFID_THREAD_SPAWNER
] = "thread_spawner",
318 [BRW_SFID_VME
] = "vme",
321 static const char * const target_function_gen6
[16] = {
322 [BRW_SFID_NULL
] = "null",
323 [BRW_SFID_MATH
] = "math",
324 [BRW_SFID_SAMPLER
] = "sampler",
325 [BRW_SFID_MESSAGE_GATEWAY
] = "gateway",
326 [BRW_SFID_URB
] = "urb",
327 [BRW_SFID_THREAD_SPAWNER
] = "thread_spawner",
328 [GEN6_SFID_DATAPORT_SAMPLER_CACHE
] = "sampler",
329 [GEN6_SFID_DATAPORT_RENDER_CACHE
] = "render",
330 [GEN6_SFID_DATAPORT_CONSTANT_CACHE
] = "const",
331 [GEN7_SFID_DATAPORT_DATA_CACHE
] = "data",
332 [GEN7_SFID_PIXEL_INTERPOLATOR
] = "pixel interp",
333 [HSW_SFID_DATAPORT_DATA_CACHE_1
] = "dp data 1",
334 [HSW_SFID_CRE
] = "cre",
337 static const char * const dp_rc_msg_type_gen6
[16] = {
338 [BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
] = "OWORD block read",
339 [GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ
] = "RT UNORM read",
340 [GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
] = "OWORD dual block read",
341 [GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ
] = "media block read",
342 [GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ
] = "OWORD unaligned block read",
343 [GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ
] = "DWORD scattered read",
344 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE
] = "DWORD atomic write",
345 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE
] = "OWORD block write",
346 [GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE
] = "OWORD dual block write",
347 [GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE
] = "media block write",
348 [GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE
] = "DWORD scattered write",
349 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
] = "RT write",
350 [GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE
] = "streamed VB write",
351 [GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE
] = "RT UNORMc write",
354 static const char *const dp_dc0_msg_type_gen7
[16] = {
355 [GEN7_DATAPORT_DC_OWORD_BLOCK_READ
] = "DC OWORD block read",
356 [GEN7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ
] = "DC unaligned OWORD block read",
357 [GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ
] = "DC OWORD dual block read",
358 [GEN7_DATAPORT_DC_DWORD_SCATTERED_READ
] = "DC DWORD scattered read",
359 [GEN7_DATAPORT_DC_BYTE_SCATTERED_READ
] = "DC byte scattered read",
360 [GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP
] = "DC untyped atomic",
361 [GEN7_DATAPORT_DC_MEMORY_FENCE
] = "DC mfence",
362 [GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE
] = "DC OWORD block write",
363 [GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE
] = "DC OWORD dual block write",
364 [GEN7_DATAPORT_DC_DWORD_SCATTERED_WRITE
] = "DC DWORD scatterd write",
365 [GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE
] = "DC byte scattered write",
366 [GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE
] = "DC untyped surface write",
369 static const char *const dp_dc1_msg_type_hsw
[16] = {
370 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ
] = "untyped surface read",
371 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP
] = "DC untyped atomic op",
372 [HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2
] = "DC untyped 4x2 atomic op",
373 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ
] = "DC media block read",
374 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ
] = "DC typed surface read",
375 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP
] = "DC typed atomic",
376 [HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2
] = "DC typed 4x2 atomic op",
377 [HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE
] = "DC untyped surface write",
378 [HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE
] = "DC media block write",
379 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP
] = "DC atomic counter op",
380 [HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2
] = "DC 4x2 atomic counter op",
381 [HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE
] = "DC typed surface write",
384 static const char * const aop
[16] = {
385 [BRW_AOP_AND
] = "and",
387 [BRW_AOP_XOR
] = "xor",
388 [BRW_AOP_MOV
] = "mov",
389 [BRW_AOP_INC
] = "inc",
390 [BRW_AOP_DEC
] = "dec",
391 [BRW_AOP_ADD
] = "add",
392 [BRW_AOP_SUB
] = "sub",
393 [BRW_AOP_REVSUB
] = "revsub",
394 [BRW_AOP_IMAX
] = "imax",
395 [BRW_AOP_IMIN
] = "imin",
396 [BRW_AOP_UMAX
] = "umax",
397 [BRW_AOP_UMIN
] = "umin",
398 [BRW_AOP_CMPWR
] = "cmpwr",
399 [BRW_AOP_PREDEC
] = "predec",
402 static const char * const math_function
[16] = {
403 [BRW_MATH_FUNCTION_INV
] = "inv",
404 [BRW_MATH_FUNCTION_LOG
] = "log",
405 [BRW_MATH_FUNCTION_EXP
] = "exp",
406 [BRW_MATH_FUNCTION_SQRT
] = "sqrt",
407 [BRW_MATH_FUNCTION_RSQ
] = "rsq",
408 [BRW_MATH_FUNCTION_SIN
] = "sin",
409 [BRW_MATH_FUNCTION_COS
] = "cos",
410 [BRW_MATH_FUNCTION_SINCOS
] = "sincos",
411 [BRW_MATH_FUNCTION_FDIV
] = "fdiv",
412 [BRW_MATH_FUNCTION_POW
] = "pow",
413 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER
] = "intdivmod",
414 [BRW_MATH_FUNCTION_INT_DIV_QUOTIENT
] = "intdiv",
415 [BRW_MATH_FUNCTION_INT_DIV_REMAINDER
] = "intmod",
418 static const char * const math_saturate
[2] = {
423 static const char * const math_signed
[2] = {
428 static const char * const math_scalar
[2] = {
433 static const char * const math_precision
[2] = {
435 [1] = "partial_precision"
438 static const char * const urb_opcode
[2] = {
443 static const char * const urb_swizzle
[4] = {
444 [BRW_URB_SWIZZLE_NONE
] = "",
445 [BRW_URB_SWIZZLE_INTERLEAVE
] = "interleave",
446 [BRW_URB_SWIZZLE_TRANSPOSE
] = "transpose",
449 static const char * const urb_allocate
[2] = {
454 static const char * const urb_used
[2] = {
459 static const char * const urb_complete
[2] = {
464 static const char * const sampler_target_format
[4] = {
473 static int string (FILE *file
, const char *string
)
475 fputs (string
, file
);
476 column
+= strlen (string
);
480 static int format (FILE *f
, const char *format
, ...)
484 va_start (args
, format
);
486 vsnprintf (buf
, sizeof (buf
) - 1, format
, args
);
492 static int newline (FILE *f
)
499 static int pad (FILE *f
, int c
)
507 static int control (FILE *file
, const char *name
, const char * const ctrl
[],
508 unsigned id
, int *space
)
511 fprintf (file
, "*** invalid %s value %d ",
519 string (file
, ctrl
[id
]);
526 static int print_opcode (FILE *file
, int id
)
528 if (!opcode
[id
].name
) {
529 format (file
, "*** invalid opcode value %d ", id
);
532 string (file
, opcode
[id
].name
);
536 static int reg (FILE *file
, unsigned _reg_file
, unsigned _reg_nr
)
540 /* Clear the Compr4 instruction compression bit. */
541 if (_reg_file
== BRW_MESSAGE_REGISTER_FILE
)
542 _reg_nr
&= ~(1 << 7);
544 if (_reg_file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
545 switch (_reg_nr
& 0xf0) {
547 string (file
, "null");
549 case BRW_ARF_ADDRESS
:
550 format (file
, "a%d", _reg_nr
& 0x0f);
552 case BRW_ARF_ACCUMULATOR
:
553 format (file
, "acc%d", _reg_nr
& 0x0f);
556 format (file
, "f%d", _reg_nr
& 0x0f);
559 format (file
, "mask%d", _reg_nr
& 0x0f);
561 case BRW_ARF_MASK_STACK
:
562 format (file
, "msd%d", _reg_nr
& 0x0f);
565 format (file
, "sr%d", _reg_nr
& 0x0f);
567 case BRW_ARF_CONTROL
:
568 format (file
, "cr%d", _reg_nr
& 0x0f);
570 case BRW_ARF_NOTIFICATION_COUNT
:
571 format (file
, "n%d", _reg_nr
& 0x0f);
578 format (file
, "ARF%d", _reg_nr
);
582 err
|= control (file
, "src reg file", reg_file
, _reg_file
, NULL
);
583 format (file
, "%d", _reg_nr
);
588 static int dest (FILE *file
, struct brw_instruction
*inst
)
592 if (inst
->header
.access_mode
== BRW_ALIGN_1
)
594 if (inst
->bits1
.da1
.dest_address_mode
== BRW_ADDRESS_DIRECT
)
596 err
|= reg (file
, inst
->bits1
.da1
.dest_reg_file
, inst
->bits1
.da1
.dest_reg_nr
);
599 if (inst
->bits1
.da1
.dest_subreg_nr
)
600 format (file
, ".%d", inst
->bits1
.da1
.dest_subreg_nr
/
601 reg_type_size
[inst
->bits1
.da1
.dest_reg_type
]);
603 err
|= control (file
, "horiz stride", horiz_stride
, inst
->bits1
.da1
.dest_horiz_stride
, NULL
);
605 err
|= control (file
, "dest reg encoding", reg_encoding
, inst
->bits1
.da1
.dest_reg_type
, NULL
);
609 string (file
, "g[a0");
610 if (inst
->bits1
.ia1
.dest_subreg_nr
)
611 format (file
, ".%d", inst
->bits1
.ia1
.dest_subreg_nr
/
612 reg_type_size
[inst
->bits1
.ia1
.dest_reg_type
]);
613 if (inst
->bits1
.ia1
.dest_indirect_offset
)
614 format (file
, " %d", inst
->bits1
.ia1
.dest_indirect_offset
);
616 err
|= control (file
, "horiz stride", horiz_stride
, inst
->bits1
.ia1
.dest_horiz_stride
, NULL
);
618 err
|= control (file
, "dest reg encoding", reg_encoding
, inst
->bits1
.ia1
.dest_reg_type
, NULL
);
623 if (inst
->bits1
.da16
.dest_address_mode
== BRW_ADDRESS_DIRECT
)
625 err
|= reg (file
, inst
->bits1
.da16
.dest_reg_file
, inst
->bits1
.da16
.dest_reg_nr
);
628 if (inst
->bits1
.da16
.dest_subreg_nr
)
629 format (file
, ".%d", inst
->bits1
.da16
.dest_subreg_nr
/
630 reg_type_size
[inst
->bits1
.da16
.dest_reg_type
]);
631 string (file
, "<1>");
632 err
|= control (file
, "writemask", writemask
, inst
->bits1
.da16
.dest_writemask
, NULL
);
633 err
|= control (file
, "dest reg encoding", reg_encoding
, inst
->bits1
.da16
.dest_reg_type
, NULL
);
638 string (file
, "Indirect align16 address mode not supported");
645 static int dest_3src (FILE *file
, struct brw_instruction
*inst
)
650 if (inst
->bits1
.da3src
.dest_reg_file
)
651 reg_file
= BRW_MESSAGE_REGISTER_FILE
;
653 reg_file
= BRW_GENERAL_REGISTER_FILE
;
655 err
|= reg (file
, reg_file
, inst
->bits1
.da3src
.dest_reg_nr
);
658 if (inst
->bits1
.da3src
.dest_subreg_nr
)
659 format (file
, ".%d", inst
->bits1
.da3src
.dest_subreg_nr
);
660 string (file
, "<1>");
661 err
|= control (file
, "writemask", writemask
, inst
->bits1
.da3src
.dest_writemask
, NULL
);
662 err
|= control (file
, "dest reg encoding", three_source_reg_encoding
,
663 inst
->bits1
.da3src
.dst_type
, NULL
);
668 static int src_align1_region (FILE *file
,
669 unsigned _vert_stride
, unsigned _width
, unsigned _horiz_stride
)
673 err
|= control (file
, "vert stride", vert_stride
, _vert_stride
, NULL
);
675 err
|= control (file
, "width", width
, _width
, NULL
);
677 err
|= control (file
, "horiz_stride", horiz_stride
, _horiz_stride
, NULL
);
682 static int src_da1 (FILE *file
, unsigned type
, unsigned _reg_file
,
683 unsigned _vert_stride
, unsigned _width
, unsigned _horiz_stride
,
684 unsigned reg_num
, unsigned sub_reg_num
, unsigned __abs
, unsigned _negate
)
687 err
|= control (file
, "negate", negate
, _negate
, NULL
);
688 err
|= control (file
, "abs", _abs
, __abs
, NULL
);
690 err
|= reg (file
, _reg_file
, reg_num
);
694 format (file
, ".%d", sub_reg_num
/ reg_type_size
[type
]); /* use formal style like spec */
695 src_align1_region (file
, _vert_stride
, _width
, _horiz_stride
);
696 err
|= control (file
, "src reg encoding", reg_encoding
, type
, NULL
);
700 static int src_ia1 (FILE *file
,
704 unsigned _addr_subreg_nr
,
708 unsigned _horiz_stride
,
710 unsigned _vert_stride
)
713 err
|= control (file
, "negate", negate
, _negate
, NULL
);
714 err
|= control (file
, "abs", _abs
, __abs
, NULL
);
716 string (file
, "g[a0");
718 format (file
, ".%d", _addr_subreg_nr
);
720 format (file
, " %d", _addr_imm
);
722 src_align1_region (file
, _vert_stride
, _width
, _horiz_stride
);
723 err
|= control (file
, "src reg encoding", reg_encoding
, type
, NULL
);
727 static int src_da16 (FILE *file
,
730 unsigned _vert_stride
,
741 err
|= control (file
, "negate", negate
, _negate
, NULL
);
742 err
|= control (file
, "abs", _abs
, __abs
, NULL
);
744 err
|= reg (file
, _reg_file
, _reg_nr
);
748 /* bit4 for subreg number byte addressing. Make this same meaning as
749 in da1 case, so output looks consistent. */
750 format (file
, ".%d", 16 / reg_type_size
[_reg_type
]);
752 err
|= control (file
, "vert stride", vert_stride
, _vert_stride
, NULL
);
753 string (file
, ",4,1>");
755 * Three kinds of swizzle display:
756 * identity - nothing printed
757 * 1->all - print the single channel
758 * 1->1 - print the mapping
760 if (swz_x
== BRW_CHANNEL_X
&&
761 swz_y
== BRW_CHANNEL_Y
&&
762 swz_z
== BRW_CHANNEL_Z
&&
763 swz_w
== BRW_CHANNEL_W
)
767 else if (swz_x
== swz_y
&& swz_x
== swz_z
&& swz_x
== swz_w
)
770 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
775 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
776 err
|= control (file
, "channel select", chan_sel
, swz_y
, NULL
);
777 err
|= control (file
, "channel select", chan_sel
, swz_z
, NULL
);
778 err
|= control (file
, "channel select", chan_sel
, swz_w
, NULL
);
780 err
|= control (file
, "src da16 reg type", reg_encoding
, _reg_type
, NULL
);
784 static int src0_3src (FILE *file
, struct brw_instruction
*inst
)
787 unsigned swz_x
= (inst
->bits2
.da3src
.src0_swizzle
>> 0) & 0x3;
788 unsigned swz_y
= (inst
->bits2
.da3src
.src0_swizzle
>> 2) & 0x3;
789 unsigned swz_z
= (inst
->bits2
.da3src
.src0_swizzle
>> 4) & 0x3;
790 unsigned swz_w
= (inst
->bits2
.da3src
.src0_swizzle
>> 6) & 0x3;
792 err
|= control (file
, "negate", negate
, inst
->bits1
.da3src
.src0_negate
, NULL
);
793 err
|= control (file
, "abs", _abs
, inst
->bits1
.da3src
.src0_abs
, NULL
);
795 err
|= reg (file
, BRW_GENERAL_REGISTER_FILE
, inst
->bits2
.da3src
.src0_reg_nr
);
798 if (inst
->bits2
.da3src
.src0_subreg_nr
)
799 format (file
, ".%d", inst
->bits2
.da3src
.src0_subreg_nr
);
800 if (inst
->bits2
.da3src
.src0_rep_ctrl
)
801 string (file
, "<0,1,0>");
803 string (file
, "<4,4,1>");
804 err
|= control (file
, "src da16 reg type", three_source_reg_encoding
,
805 inst
->bits1
.da3src
.src_type
, NULL
);
807 * Three kinds of swizzle display:
808 * identity - nothing printed
809 * 1->all - print the single channel
810 * 1->1 - print the mapping
812 if (swz_x
== BRW_CHANNEL_X
&&
813 swz_y
== BRW_CHANNEL_Y
&&
814 swz_z
== BRW_CHANNEL_Z
&&
815 swz_w
== BRW_CHANNEL_W
)
819 else if (swz_x
== swz_y
&& swz_x
== swz_z
&& swz_x
== swz_w
)
822 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
827 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
828 err
|= control (file
, "channel select", chan_sel
, swz_y
, NULL
);
829 err
|= control (file
, "channel select", chan_sel
, swz_z
, NULL
);
830 err
|= control (file
, "channel select", chan_sel
, swz_w
, NULL
);
835 static int src1_3src (FILE *file
, struct brw_instruction
*inst
)
838 unsigned swz_x
= (inst
->bits2
.da3src
.src1_swizzle
>> 0) & 0x3;
839 unsigned swz_y
= (inst
->bits2
.da3src
.src1_swizzle
>> 2) & 0x3;
840 unsigned swz_z
= (inst
->bits2
.da3src
.src1_swizzle
>> 4) & 0x3;
841 unsigned swz_w
= (inst
->bits2
.da3src
.src1_swizzle
>> 6) & 0x3;
842 unsigned src1_subreg_nr
= (inst
->bits2
.da3src
.src1_subreg_nr_low
|
843 (inst
->bits3
.da3src
.src1_subreg_nr_high
<< 2));
845 err
|= control (file
, "negate", negate
, inst
->bits1
.da3src
.src1_negate
,
847 err
|= control (file
, "abs", _abs
, inst
->bits1
.da3src
.src1_abs
, NULL
);
849 err
|= reg (file
, BRW_GENERAL_REGISTER_FILE
,
850 inst
->bits3
.da3src
.src1_reg_nr
);
854 format (file
, ".%d", src1_subreg_nr
);
855 if (inst
->bits2
.da3src
.src1_rep_ctrl
)
856 string (file
, "<0,1,0>");
858 string (file
, "<4,4,1>");
859 err
|= control (file
, "src da16 reg type", three_source_reg_encoding
,
860 inst
->bits1
.da3src
.src_type
, NULL
);
862 * Three kinds of swizzle display:
863 * identity - nothing printed
864 * 1->all - print the single channel
865 * 1->1 - print the mapping
867 if (swz_x
== BRW_CHANNEL_X
&&
868 swz_y
== BRW_CHANNEL_Y
&&
869 swz_z
== BRW_CHANNEL_Z
&&
870 swz_w
== BRW_CHANNEL_W
)
874 else if (swz_x
== swz_y
&& swz_x
== swz_z
&& swz_x
== swz_w
)
877 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
882 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
883 err
|= control (file
, "channel select", chan_sel
, swz_y
, NULL
);
884 err
|= control (file
, "channel select", chan_sel
, swz_z
, NULL
);
885 err
|= control (file
, "channel select", chan_sel
, swz_w
, NULL
);
891 static int src2_3src (FILE *file
, struct brw_instruction
*inst
)
894 unsigned swz_x
= (inst
->bits3
.da3src
.src2_swizzle
>> 0) & 0x3;
895 unsigned swz_y
= (inst
->bits3
.da3src
.src2_swizzle
>> 2) & 0x3;
896 unsigned swz_z
= (inst
->bits3
.da3src
.src2_swizzle
>> 4) & 0x3;
897 unsigned swz_w
= (inst
->bits3
.da3src
.src2_swizzle
>> 6) & 0x3;
899 err
|= control (file
, "negate", negate
, inst
->bits1
.da3src
.src2_negate
,
901 err
|= control (file
, "abs", _abs
, inst
->bits1
.da3src
.src2_abs
, NULL
);
903 err
|= reg (file
, BRW_GENERAL_REGISTER_FILE
,
904 inst
->bits3
.da3src
.src2_reg_nr
);
907 if (inst
->bits3
.da3src
.src2_subreg_nr
)
908 format (file
, ".%d", inst
->bits3
.da3src
.src2_subreg_nr
);
909 if (inst
->bits3
.da3src
.src2_rep_ctrl
)
910 string (file
, "<0,1,0>");
912 string (file
, "<4,4,1>");
913 err
|= control (file
, "src da16 reg type", three_source_reg_encoding
,
914 inst
->bits1
.da3src
.src_type
, NULL
);
916 * Three kinds of swizzle display:
917 * identity - nothing printed
918 * 1->all - print the single channel
919 * 1->1 - print the mapping
921 if (swz_x
== BRW_CHANNEL_X
&&
922 swz_y
== BRW_CHANNEL_Y
&&
923 swz_z
== BRW_CHANNEL_Z
&&
924 swz_w
== BRW_CHANNEL_W
)
928 else if (swz_x
== swz_y
&& swz_x
== swz_z
&& swz_x
== swz_w
)
931 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
936 err
|= control (file
, "channel select", chan_sel
, swz_x
, NULL
);
937 err
|= control (file
, "channel select", chan_sel
, swz_y
, NULL
);
938 err
|= control (file
, "channel select", chan_sel
, swz_z
, NULL
);
939 err
|= control (file
, "channel select", chan_sel
, swz_w
, NULL
);
944 static int imm (FILE *file
, unsigned type
, struct brw_instruction
*inst
) {
946 case BRW_HW_REG_TYPE_UD
:
947 format (file
, "0x%08xUD", inst
->bits3
.ud
);
949 case BRW_HW_REG_TYPE_D
:
950 format (file
, "%dD", inst
->bits3
.d
);
952 case BRW_HW_REG_TYPE_UW
:
953 format (file
, "0x%04xUW", (uint16_t) inst
->bits3
.ud
);
955 case BRW_HW_REG_TYPE_W
:
956 format (file
, "%dW", (int16_t) inst
->bits3
.d
);
958 case BRW_HW_REG_IMM_TYPE_UV
:
959 format (file
, "0x%08xUV", inst
->bits3
.ud
);
961 case BRW_HW_REG_IMM_TYPE_VF
:
962 format (file
, "Vector Float");
964 case BRW_HW_REG_IMM_TYPE_V
:
965 format (file
, "0x%08xV", inst
->bits3
.ud
);
967 case BRW_HW_REG_TYPE_F
:
968 format (file
, "%-gF", inst
->bits3
.f
);
973 static int src0 (FILE *file
, struct brw_instruction
*inst
)
975 if (inst
->bits1
.da1
.src0_reg_file
== BRW_IMMEDIATE_VALUE
)
976 return imm (file
, inst
->bits1
.da1
.src0_reg_type
,
978 else if (inst
->header
.access_mode
== BRW_ALIGN_1
)
980 if (inst
->bits2
.da1
.src0_address_mode
== BRW_ADDRESS_DIRECT
)
982 return src_da1 (file
,
983 inst
->bits1
.da1
.src0_reg_type
,
984 inst
->bits1
.da1
.src0_reg_file
,
985 inst
->bits2
.da1
.src0_vert_stride
,
986 inst
->bits2
.da1
.src0_width
,
987 inst
->bits2
.da1
.src0_horiz_stride
,
988 inst
->bits2
.da1
.src0_reg_nr
,
989 inst
->bits2
.da1
.src0_subreg_nr
,
990 inst
->bits2
.da1
.src0_abs
,
991 inst
->bits2
.da1
.src0_negate
);
995 return src_ia1 (file
,
996 inst
->bits1
.ia1
.src0_reg_type
,
997 inst
->bits1
.ia1
.src0_reg_file
,
998 inst
->bits2
.ia1
.src0_indirect_offset
,
999 inst
->bits2
.ia1
.src0_subreg_nr
,
1000 inst
->bits2
.ia1
.src0_negate
,
1001 inst
->bits2
.ia1
.src0_abs
,
1002 inst
->bits2
.ia1
.src0_address_mode
,
1003 inst
->bits2
.ia1
.src0_horiz_stride
,
1004 inst
->bits2
.ia1
.src0_width
,
1005 inst
->bits2
.ia1
.src0_vert_stride
);
1010 if (inst
->bits2
.da16
.src0_address_mode
== BRW_ADDRESS_DIRECT
)
1012 return src_da16 (file
,
1013 inst
->bits1
.da16
.src0_reg_type
,
1014 inst
->bits1
.da16
.src0_reg_file
,
1015 inst
->bits2
.da16
.src0_vert_stride
,
1016 inst
->bits2
.da16
.src0_reg_nr
,
1017 inst
->bits2
.da16
.src0_subreg_nr
,
1018 inst
->bits2
.da16
.src0_abs
,
1019 inst
->bits2
.da16
.src0_negate
,
1020 inst
->bits2
.da16
.src0_swz_x
,
1021 inst
->bits2
.da16
.src0_swz_y
,
1022 inst
->bits2
.da16
.src0_swz_z
,
1023 inst
->bits2
.da16
.src0_swz_w
);
1027 string (file
, "Indirect align16 address mode not supported");
1033 static int src1 (FILE *file
, struct brw_instruction
*inst
)
1035 if (inst
->bits1
.da1
.src1_reg_file
== BRW_IMMEDIATE_VALUE
)
1036 return imm (file
, inst
->bits1
.da1
.src1_reg_type
,
1038 else if (inst
->header
.access_mode
== BRW_ALIGN_1
)
1040 if (inst
->bits3
.da1
.src1_address_mode
== BRW_ADDRESS_DIRECT
)
1042 return src_da1 (file
,
1043 inst
->bits1
.da1
.src1_reg_type
,
1044 inst
->bits1
.da1
.src1_reg_file
,
1045 inst
->bits3
.da1
.src1_vert_stride
,
1046 inst
->bits3
.da1
.src1_width
,
1047 inst
->bits3
.da1
.src1_horiz_stride
,
1048 inst
->bits3
.da1
.src1_reg_nr
,
1049 inst
->bits3
.da1
.src1_subreg_nr
,
1050 inst
->bits3
.da1
.src1_abs
,
1051 inst
->bits3
.da1
.src1_negate
);
1055 return src_ia1 (file
,
1056 inst
->bits1
.ia1
.src1_reg_type
,
1057 inst
->bits1
.ia1
.src1_reg_file
,
1058 inst
->bits3
.ia1
.src1_indirect_offset
,
1059 inst
->bits3
.ia1
.src1_subreg_nr
,
1060 inst
->bits3
.ia1
.src1_negate
,
1061 inst
->bits3
.ia1
.src1_abs
,
1062 inst
->bits3
.ia1
.src1_address_mode
,
1063 inst
->bits3
.ia1
.src1_horiz_stride
,
1064 inst
->bits3
.ia1
.src1_width
,
1065 inst
->bits3
.ia1
.src1_vert_stride
);
1070 if (inst
->bits3
.da16
.src1_address_mode
== BRW_ADDRESS_DIRECT
)
1072 return src_da16 (file
,
1073 inst
->bits1
.da16
.src1_reg_type
,
1074 inst
->bits1
.da16
.src1_reg_file
,
1075 inst
->bits3
.da16
.src1_vert_stride
,
1076 inst
->bits3
.da16
.src1_reg_nr
,
1077 inst
->bits3
.da16
.src1_subreg_nr
,
1078 inst
->bits3
.da16
.src1_abs
,
1079 inst
->bits3
.da16
.src1_negate
,
1080 inst
->bits3
.da16
.src1_swz_x
,
1081 inst
->bits3
.da16
.src1_swz_y
,
1082 inst
->bits3
.da16
.src1_swz_z
,
1083 inst
->bits3
.da16
.src1_swz_w
);
1087 string (file
, "Indirect align16 address mode not supported");
1093 static int qtr_ctrl(FILE *file
, struct brw_instruction
*inst
)
1095 int qtr_ctl
= inst
->header
.compression_control
;
1096 int exec_size
= 1 << inst
->header
.execution_size
;
1098 if (exec_size
== 8) {
1101 string (file
, " 1Q");
1104 string (file
, " 2Q");
1107 string (file
, " 3Q");
1110 string (file
, " 4Q");
1113 } else if (exec_size
== 16){
1115 string (file
, " 1H");
1117 string (file
, " 2H");
1123 brw_disassemble_inst(FILE *file
,
1124 struct brw_instruction
*inst
, int gen
, bool is_compacted
)
1129 if (inst
->header
.predicate_control
) {
1131 err
|= control (file
, "predicate inverse", pred_inv
, inst
->header
.predicate_inverse
, NULL
);
1132 format (file
, "f%d", gen
>= 7 ? inst
->bits2
.da1
.flag_reg_nr
: 0);
1133 if (inst
->bits2
.da1
.flag_subreg_nr
)
1134 format (file
, ".%d", inst
->bits2
.da1
.flag_subreg_nr
);
1135 if (inst
->header
.access_mode
== BRW_ALIGN_1
)
1136 err
|= control (file
, "predicate control align1", pred_ctrl_align1
,
1137 inst
->header
.predicate_control
, NULL
);
1139 err
|= control (file
, "predicate control align16", pred_ctrl_align16
,
1140 inst
->header
.predicate_control
, NULL
);
1141 string (file
, ") ");
1144 err
|= print_opcode (file
, inst
->header
.opcode
);
1145 err
|= control (file
, "saturate", saturate
, inst
->header
.saturate
, NULL
);
1147 err
|= control (file
, "debug control", debug_ctrl
, inst
->header
.debug_control
, NULL
);
1149 if (inst
->header
.opcode
== BRW_OPCODE_MATH
) {
1151 err
|= control (file
, "function", math_function
,
1152 inst
->header
.destreg__conditionalmod
, NULL
);
1153 } else if (inst
->header
.opcode
!= BRW_OPCODE_SEND
&&
1154 inst
->header
.opcode
!= BRW_OPCODE_SENDC
) {
1155 err
|= control (file
, "conditional modifier", conditional_modifier
,
1156 inst
->header
.destreg__conditionalmod
, NULL
);
1158 /* If we're using the conditional modifier, print which flags reg is
1159 * used for it. Note that on gen6+, the embedded-condition SEL and
1160 * control flow doesn't update flags.
1162 if (inst
->header
.destreg__conditionalmod
&&
1163 (gen
< 6 || (inst
->header
.opcode
!= BRW_OPCODE_SEL
&&
1164 inst
->header
.opcode
!= BRW_OPCODE_IF
&&
1165 inst
->header
.opcode
!= BRW_OPCODE_WHILE
))) {
1166 format (file
, ".f%d", gen
>= 7 ? inst
->bits2
.da1
.flag_reg_nr
: 0);
1167 if (inst
->bits2
.da1
.flag_subreg_nr
)
1168 format (file
, ".%d", inst
->bits2
.da1
.flag_subreg_nr
);
1172 if (inst
->header
.opcode
!= BRW_OPCODE_NOP
) {
1174 err
|= control (file
, "execution size", exec_size
, inst
->header
.execution_size
, NULL
);
1178 if (inst
->header
.opcode
== BRW_OPCODE_SEND
&& gen
< 6)
1179 format (file
, " %d", inst
->header
.destreg__conditionalmod
);
1181 if (opcode
[inst
->header
.opcode
].nsrc
== 3) {
1183 err
|= dest_3src (file
, inst
);
1186 err
|= src0_3src (file
, inst
);
1189 err
|= src1_3src (file
, inst
);
1192 err
|= src2_3src (file
, inst
);
1194 if (opcode
[inst
->header
.opcode
].ndst
> 0) {
1196 err
|= dest (file
, inst
);
1197 } else if (gen
== 7 && (inst
->header
.opcode
== BRW_OPCODE_ELSE
||
1198 inst
->header
.opcode
== BRW_OPCODE_ENDIF
||
1199 inst
->header
.opcode
== BRW_OPCODE_WHILE
)) {
1200 format (file
, " %d", inst
->bits3
.break_cont
.jip
);
1201 } else if (gen
== 6 && (inst
->header
.opcode
== BRW_OPCODE_IF
||
1202 inst
->header
.opcode
== BRW_OPCODE_ELSE
||
1203 inst
->header
.opcode
== BRW_OPCODE_ENDIF
||
1204 inst
->header
.opcode
== BRW_OPCODE_WHILE
)) {
1205 format (file
, " %d", inst
->bits1
.branch_gen6
.jump_count
);
1206 } else if ((gen
>= 6 && (inst
->header
.opcode
== BRW_OPCODE_BREAK
||
1207 inst
->header
.opcode
== BRW_OPCODE_CONTINUE
||
1208 inst
->header
.opcode
== BRW_OPCODE_HALT
)) ||
1209 (gen
== 7 && inst
->header
.opcode
== BRW_OPCODE_IF
)) {
1210 format (file
, " %d %d", inst
->bits3
.break_cont
.uip
, inst
->bits3
.break_cont
.jip
);
1211 } else if (inst
->header
.opcode
== BRW_OPCODE_JMPI
) {
1212 format (file
, " %d", inst
->bits3
.d
);
1215 if (opcode
[inst
->header
.opcode
].nsrc
> 0) {
1217 err
|= src0 (file
, inst
);
1219 if (opcode
[inst
->header
.opcode
].nsrc
> 1) {
1221 err
|= src1 (file
, inst
);
1225 if (inst
->header
.opcode
== BRW_OPCODE_SEND
||
1226 inst
->header
.opcode
== BRW_OPCODE_SENDC
) {
1227 enum brw_message_target target
;
1230 target
= inst
->header
.destreg__conditionalmod
;
1232 target
= inst
->bits2
.send_gen5
.sfid
;
1234 target
= inst
->bits3
.generic
.msg_target
;
1240 fprintf (file
, " ");
1242 err
|= control (file
, "target function", target_function_gen6
,
1245 err
|= control (file
, "target function", target_function
,
1251 err
|= control (file
, "math function", math_function
,
1252 inst
->bits3
.math
.function
, &space
);
1253 err
|= control (file
, "math saturate", math_saturate
,
1254 inst
->bits3
.math
.saturate
, &space
);
1255 err
|= control (file
, "math signed", math_signed
,
1256 inst
->bits3
.math
.int_type
, &space
);
1257 err
|= control (file
, "math scalar", math_scalar
,
1258 inst
->bits3
.math
.data_type
, &space
);
1259 err
|= control (file
, "math precision", math_precision
,
1260 inst
->bits3
.math
.precision
, &space
);
1262 case BRW_SFID_SAMPLER
:
1264 format (file
, " (%d, %d, %d, %d)",
1265 inst
->bits3
.sampler_gen7
.binding_table_index
,
1266 inst
->bits3
.sampler_gen7
.sampler
,
1267 inst
->bits3
.sampler_gen7
.msg_type
,
1268 inst
->bits3
.sampler_gen7
.simd_mode
);
1269 } else if (gen
>= 5) {
1270 format (file
, " (%d, %d, %d, %d)",
1271 inst
->bits3
.sampler_gen5
.binding_table_index
,
1272 inst
->bits3
.sampler_gen5
.sampler
,
1273 inst
->bits3
.sampler_gen5
.msg_type
,
1274 inst
->bits3
.sampler_gen5
.simd_mode
);
1275 } else if (0 /* FINISHME: is_g4x */) {
1276 format (file
, " (%d, %d)",
1277 inst
->bits3
.sampler_g4x
.binding_table_index
,
1278 inst
->bits3
.sampler_g4x
.sampler
);
1280 format (file
, " (%d, %d, ",
1281 inst
->bits3
.sampler
.binding_table_index
,
1282 inst
->bits3
.sampler
.sampler
);
1283 err
|= control (file
, "sampler target format",
1284 sampler_target_format
,
1285 inst
->bits3
.sampler
.return_format
, NULL
);
1289 case BRW_SFID_DATAPORT_READ
:
1291 format (file
, " (%d, %d, %d, %d)",
1292 inst
->bits3
.gen6_dp
.binding_table_index
,
1293 inst
->bits3
.gen6_dp
.msg_control
,
1294 inst
->bits3
.gen6_dp
.msg_type
,
1295 inst
->bits3
.gen6_dp
.send_commit_msg
);
1296 } else if (gen
>= 5 /* FINISHME: || is_g4x */) {
1297 format (file
, " (%d, %d, %d)",
1298 inst
->bits3
.dp_read_gen5
.binding_table_index
,
1299 inst
->bits3
.dp_read_gen5
.msg_control
,
1300 inst
->bits3
.dp_read_gen5
.msg_type
);
1302 format (file
, " (%d, %d, %d)",
1303 inst
->bits3
.dp_read
.binding_table_index
,
1304 inst
->bits3
.dp_read
.msg_control
,
1305 inst
->bits3
.dp_read
.msg_type
);
1309 case BRW_SFID_DATAPORT_WRITE
:
1311 format (file
, " (");
1313 err
|= control (file
, "DP rc message type",
1314 dp_rc_msg_type_gen6
,
1315 inst
->bits3
.gen7_dp
.msg_type
, &space
);
1317 format (file
, ", %d, %d, %d)",
1318 inst
->bits3
.gen7_dp
.binding_table_index
,
1319 inst
->bits3
.gen7_dp
.msg_control
,
1320 inst
->bits3
.gen7_dp
.msg_type
);
1321 } else if (gen
== 6) {
1322 format (file
, " (");
1324 err
|= control (file
, "DP rc message type",
1325 dp_rc_msg_type_gen6
,
1326 inst
->bits3
.gen6_dp
.msg_type
, &space
);
1328 format (file
, ", %d, %d, %d, %d)",
1329 inst
->bits3
.gen6_dp
.binding_table_index
,
1330 inst
->bits3
.gen6_dp
.msg_control
,
1331 inst
->bits3
.gen6_dp
.msg_type
,
1332 inst
->bits3
.gen6_dp
.send_commit_msg
);
1334 format (file
, " (%d, %d, %d, %d)",
1335 inst
->bits3
.dp_write
.binding_table_index
,
1336 (inst
->bits3
.dp_write
.last_render_target
<< 3) |
1337 inst
->bits3
.dp_write
.msg_control
,
1338 inst
->bits3
.dp_write
.msg_type
,
1339 inst
->bits3
.dp_write
.send_commit_msg
);
1345 format (file
, " %d", inst
->bits3
.urb_gen5
.offset
);
1347 format (file
, " %d", inst
->bits3
.urb
.offset
);
1352 err
|= control (file
, "urb opcode", urb_opcode
,
1353 inst
->bits3
.urb_gen5
.opcode
, &space
);
1355 err
|= control (file
, "urb swizzle", urb_swizzle
,
1356 inst
->bits3
.urb
.swizzle_control
, &space
);
1357 err
|= control (file
, "urb allocate", urb_allocate
,
1358 inst
->bits3
.urb
.allocate
, &space
);
1359 err
|= control (file
, "urb used", urb_used
,
1360 inst
->bits3
.urb
.used
, &space
);
1361 err
|= control (file
, "urb complete", urb_complete
,
1362 inst
->bits3
.urb
.complete
, &space
);
1364 case BRW_SFID_THREAD_SPAWNER
:
1366 case GEN7_SFID_DATAPORT_DATA_CACHE
:
1368 format (file
, " (");
1370 err
|= control (file
, "DP DC0 message type",
1371 dp_dc0_msg_type_gen7
,
1372 inst
->bits3
.gen7_dp
.msg_type
, &space
);
1374 format (file
, ", %d, ", inst
->bits3
.gen7_dp
.binding_table_index
);
1376 switch (inst
->bits3
.gen7_dp
.msg_type
) {
1377 case GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP
:
1378 control (file
, "atomic op", aop
, inst
->bits3
.ud
>> 8 & 0xf,
1382 format (file
, "%d", inst
->bits3
.gen7_dp
.msg_control
);
1389 case HSW_SFID_DATAPORT_DATA_CACHE_1
:
1391 format (file
, " (");
1393 err
|= control (file
, "DP DC1 message type",
1394 dp_dc1_msg_type_hsw
,
1395 inst
->bits3
.gen7_dp
.msg_type
, &space
);
1397 format (file
, ", %d, ",
1398 inst
->bits3
.gen7_dp
.binding_table_index
);
1400 switch (inst
->bits3
.gen7_dp
.msg_type
) {
1401 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP
:
1402 case HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2
:
1403 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP
:
1404 case HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2
:
1405 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP
:
1406 case HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2
:
1407 control (file
, "atomic op", aop
,
1408 inst
->bits3
.ud
>> 8 & 0xf, &space
);
1411 format (file
, "%d", inst
->bits3
.gen7_dp
.msg_control
);
1419 format (file
, "unsupported target %d", target
);
1425 format (file
, "mlen %d",
1426 inst
->bits3
.generic_gen5
.msg_length
);
1427 format (file
, " rlen %d",
1428 inst
->bits3
.generic_gen5
.response_length
);
1430 format (file
, "mlen %d",
1431 inst
->bits3
.generic
.msg_length
);
1432 format (file
, " rlen %d",
1433 inst
->bits3
.generic
.response_length
);
1437 if (inst
->header
.opcode
!= BRW_OPCODE_NOP
) {
1440 err
|= control(file
, "access mode", access_mode
, inst
->header
.access_mode
, &space
);
1442 err
|= control (file
, "write enable control", wectrl
, inst
->header
.mask_control
, &space
);
1444 err
|= control (file
, "mask control", mask_ctrl
, inst
->header
.mask_control
, &space
);
1445 err
|= control (file
, "dependency control", dep_ctrl
, inst
->header
.dependency_control
, &space
);
1448 err
|= qtr_ctrl (file
, inst
);
1450 if (inst
->header
.compression_control
== BRW_COMPRESSION_COMPRESSED
&&
1451 opcode
[inst
->header
.opcode
].ndst
> 0 &&
1452 inst
->bits1
.da1
.dest_reg_file
== BRW_MESSAGE_REGISTER_FILE
&&
1453 inst
->bits1
.da1
.dest_reg_nr
& (1 << 7)) {
1454 format (file
, " compr4");
1456 err
|= control (file
, "compression control", compr_ctrl
,
1457 inst
->header
.compression_control
, &space
);
1461 err
|= control (file
, "compaction control", cmpt_ctrl
, is_compacted
, &space
);
1462 err
|= control (file
, "thread control", thread_ctrl
, inst
->header
.thread_control
, &space
);
1464 err
|= control (file
, "acc write control", accwr
, inst
->header
.acc_wr_control
, &space
);
1465 if (inst
->header
.opcode
== BRW_OPCODE_SEND
||
1466 inst
->header
.opcode
== BRW_OPCODE_SENDC
)
1467 err
|= control (file
, "end of thread", end_of_thread
,
1468 inst
->bits3
.generic
.end_of_thread
, &space
);