2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <sys/errno.h>
28 #include "main/context.h"
29 #include "main/condrender.h"
30 #include "main/samplerobj.h"
31 #include "main/state.h"
32 #include "main/enums.h"
33 #include "main/macros.h"
34 #include "main/transformfeedback.h"
35 #include "main/framebuffer.h"
37 #include "vbo/vbo_context.h"
38 #include "swrast/swrast.h"
39 #include "swrast_setup/swrast_setup.h"
40 #include "drivers/common/meta.h"
41 #include "util/bitscan.h"
43 #include "brw_blorp.h"
45 #include "brw_defines.h"
46 #include "compiler/brw_eu_defines.h"
47 #include "brw_context.h"
48 #include "brw_state.h"
50 #include "intel_batchbuffer.h"
51 #include "intel_buffers.h"
52 #include "intel_fbo.h"
53 #include "intel_mipmap_tree.h"
54 #include "intel_buffer_objects.h"
56 #define FILE_DEBUG_FLAG DEBUG_PRIMS
59 static const GLenum reduced_prim
[GL_POLYGON
+1] = {
60 [GL_POINTS
] = GL_POINTS
,
61 [GL_LINES
] = GL_LINES
,
62 [GL_LINE_LOOP
] = GL_LINES
,
63 [GL_LINE_STRIP
] = GL_LINES
,
64 [GL_TRIANGLES
] = GL_TRIANGLES
,
65 [GL_TRIANGLE_STRIP
] = GL_TRIANGLES
,
66 [GL_TRIANGLE_FAN
] = GL_TRIANGLES
,
67 [GL_QUADS
] = GL_TRIANGLES
,
68 [GL_QUAD_STRIP
] = GL_TRIANGLES
,
69 [GL_POLYGON
] = GL_TRIANGLES
72 /* When the primitive changes, set a state bit and re-validate. Not
73 * the nicest and would rather deal with this by having all the
74 * programs be immune to the active primitive (ie. cope with all
75 * possibilities). That may not be realistic however.
78 brw_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
80 struct gl_context
*ctx
= &brw
->ctx
;
81 uint32_t hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
83 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
85 /* Slight optimization to avoid the GS program when not needed:
87 if (prim
->mode
== GL_QUAD_STRIP
&&
88 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
89 ctx
->Polygon
.FrontMode
== GL_FILL
&&
90 ctx
->Polygon
.BackMode
== GL_FILL
)
91 hw_prim
= _3DPRIM_TRISTRIP
;
93 if (prim
->mode
== GL_QUADS
&& prim
->count
== 4 &&
94 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
95 ctx
->Polygon
.FrontMode
== GL_FILL
&&
96 ctx
->Polygon
.BackMode
== GL_FILL
) {
97 hw_prim
= _3DPRIM_TRIFAN
;
100 if (hw_prim
!= brw
->primitive
) {
101 brw
->primitive
= hw_prim
;
102 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
104 if (reduced_prim
[prim
->mode
] != brw
->reduced_primitive
) {
105 brw
->reduced_primitive
= reduced_prim
[prim
->mode
];
106 brw
->ctx
.NewDriverState
|= BRW_NEW_REDUCED_PRIMITIVE
;
112 gen6_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
114 const struct gl_context
*ctx
= &brw
->ctx
;
117 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
119 if (prim
->mode
== GL_PATCHES
) {
120 hw_prim
= _3DPRIM_PATCHLIST(ctx
->TessCtrlProgram
.patch_vertices
);
122 hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
125 if (hw_prim
!= brw
->primitive
) {
126 brw
->primitive
= hw_prim
;
127 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
128 if (prim
->mode
== GL_PATCHES
)
129 brw
->ctx
.NewDriverState
|= BRW_NEW_PATCH_PRIMITIVE
;
135 * The hardware is capable of removing dangling vertices on its own; however,
136 * prior to Gen6, we sometimes convert quads into trifans (and quad strips
137 * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
138 * This function manually trims dangling vertices from a draw call involving
139 * quads so that those dangling vertices won't get drawn when we convert to
143 trim(GLenum prim
, GLuint length
)
145 if (prim
== GL_QUAD_STRIP
)
146 return length
> 3 ? (length
- length
% 2) : 0;
147 else if (prim
== GL_QUADS
)
148 return length
- length
% 4;
155 brw_emit_prim(struct brw_context
*brw
,
156 const struct _mesa_prim
*prim
,
158 struct brw_transform_feedback_object
*xfb_obj
,
161 int verts_per_instance
;
162 int vertex_access_type
;
165 DBG("PRIM: %s %d %d\n", _mesa_enum_to_string(prim
->mode
),
166 prim
->start
, prim
->count
);
168 int start_vertex_location
= prim
->start
;
169 int base_vertex_location
= prim
->basevertex
;
172 vertex_access_type
= brw
->gen
>= 7 ?
173 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
174 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
;
175 start_vertex_location
+= brw
->ib
.start_vertex_offset
;
176 base_vertex_location
+= brw
->vb
.start_vertex_bias
;
178 vertex_access_type
= brw
->gen
>= 7 ?
179 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
:
180 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
181 start_vertex_location
+= brw
->vb
.start_vertex_bias
;
184 /* We only need to trim the primitive count on pre-Gen6. */
186 verts_per_instance
= trim(prim
->mode
, prim
->count
);
188 verts_per_instance
= prim
->count
;
190 /* If nothing to emit, just return. */
191 if (verts_per_instance
== 0 && !prim
->is_indirect
&& !xfb_obj
)
194 /* If we're set to always flush, do it before and after the primitive emit.
195 * We want to catch both missed flushes that hurt instruction/state cache
196 * and missed flushes of the render cache as it heads to other parts of
197 * the besides the draw code.
199 if (brw
->always_flush_cache
)
200 brw_emit_mi_flush(brw
);
202 /* If indirect, emit a bunch of loads from the indirect BO. */
204 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
206 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
,
207 xfb_obj
->prim_count_bo
,
208 I915_GEM_DOMAIN_VERTEX
, 0,
209 stream
* sizeof(uint32_t));
211 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (9 - 2));
212 OUT_BATCH(GEN7_3DPRIM_INSTANCE_COUNT
);
213 OUT_BATCH(prim
->num_instances
);
214 OUT_BATCH(GEN7_3DPRIM_START_VERTEX
);
216 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
218 OUT_BATCH(GEN7_3DPRIM_START_INSTANCE
);
221 } else if (prim
->is_indirect
) {
222 struct gl_buffer_object
*indirect_buffer
= brw
->ctx
.DrawIndirectBuffer
;
223 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
224 intel_buffer_object(indirect_buffer
),
225 prim
->indirect_offset
, 5 * sizeof(GLuint
));
227 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
229 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
, bo
,
230 I915_GEM_DOMAIN_VERTEX
, 0,
231 prim
->indirect_offset
+ 0);
232 brw_load_register_mem(brw
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
,
233 I915_GEM_DOMAIN_VERTEX
, 0,
234 prim
->indirect_offset
+ 4);
236 brw_load_register_mem(brw
, GEN7_3DPRIM_START_VERTEX
, bo
,
237 I915_GEM_DOMAIN_VERTEX
, 0,
238 prim
->indirect_offset
+ 8);
240 brw_load_register_mem(brw
, GEN7_3DPRIM_BASE_VERTEX
, bo
,
241 I915_GEM_DOMAIN_VERTEX
, 0,
242 prim
->indirect_offset
+ 12);
243 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
244 I915_GEM_DOMAIN_VERTEX
, 0,
245 prim
->indirect_offset
+ 16);
247 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
248 I915_GEM_DOMAIN_VERTEX
, 0,
249 prim
->indirect_offset
+ 12);
251 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
252 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
260 BEGIN_BATCH(brw
->gen
>= 7 ? 7 : 6);
263 const int predicate_enable
=
264 (brw
->predicate
.state
== BRW_PREDICATE_STATE_USE_BIT
)
265 ? GEN7_3DPRIM_PREDICATE_ENABLE
: 0;
267 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2) | indirect_flag
| predicate_enable
);
268 OUT_BATCH(hw_prim
| vertex_access_type
);
270 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
271 hw_prim
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
274 OUT_BATCH(verts_per_instance
);
275 OUT_BATCH(start_vertex_location
);
276 OUT_BATCH(prim
->num_instances
);
277 OUT_BATCH(prim
->base_instance
);
278 OUT_BATCH(base_vertex_location
);
281 if (brw
->always_flush_cache
)
282 brw_emit_mi_flush(brw
);
287 brw_merge_inputs(struct brw_context
*brw
,
288 const struct gl_vertex_array
*arrays
[])
290 const struct gl_context
*ctx
= &brw
->ctx
;
293 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
294 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
295 brw
->vb
.buffers
[i
].bo
= NULL
;
297 brw
->vb
.nr_buffers
= 0;
299 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
300 brw
->vb
.inputs
[i
].buffer
= -1;
301 brw
->vb
.inputs
[i
].glarray
= arrays
[i
];
304 if (brw
->gen
< 8 && !brw
->is_haswell
) {
305 uint64_t mask
= ctx
->VertexProgram
._Current
->info
.inputs_read
;
306 /* Prior to Haswell, the hardware can't natively support GL_FIXED or
307 * 2_10_10_10_REV vertex formats. Set appropriate workaround flags.
310 uint8_t wa_flags
= 0;
312 i
= u_bit_scan64(&mask
);
314 switch (brw
->vb
.inputs
[i
].glarray
->Type
) {
317 wa_flags
= brw
->vb
.inputs
[i
].glarray
->Size
;
320 case GL_INT_2_10_10_10_REV
:
321 wa_flags
|= BRW_ATTRIB_WA_SIGN
;
324 case GL_UNSIGNED_INT_2_10_10_10_REV
:
325 if (brw
->vb
.inputs
[i
].glarray
->Format
== GL_BGRA
)
326 wa_flags
|= BRW_ATTRIB_WA_BGRA
;
328 if (brw
->vb
.inputs
[i
].glarray
->Normalized
)
329 wa_flags
|= BRW_ATTRIB_WA_NORMALIZE
;
330 else if (!brw
->vb
.inputs
[i
].glarray
->Integer
)
331 wa_flags
|= BRW_ATTRIB_WA_SCALE
;
336 if (brw
->vb
.attrib_wa_flags
[i
] != wa_flags
) {
337 brw
->vb
.attrib_wa_flags
[i
] = wa_flags
;
338 brw
->ctx
.NewDriverState
|= BRW_NEW_VS_ATTRIB_WORKAROUNDS
;
345 intel_disable_rb_aux_buffer(struct brw_context
*brw
, const struct brw_bo
*bo
)
347 const struct gl_framebuffer
*fb
= brw
->ctx
.DrawBuffer
;
350 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
351 const struct intel_renderbuffer
*irb
=
352 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
354 if (irb
&& irb
->mt
->bo
== bo
) {
355 found
= brw
->draw_aux_buffer_disabled
[i
] = true;
363 * \brief Resolve buffers before drawing.
365 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
366 * enabled depth texture, and flush the render cache for any dirty textures.
369 brw_predraw_resolve_inputs(struct brw_context
*brw
)
371 struct gl_context
*ctx
= &brw
->ctx
;
372 struct intel_texture_object
*tex_obj
;
374 memset(brw
->draw_aux_buffer_disabled
, 0,
375 sizeof(brw
->draw_aux_buffer_disabled
));
377 /* Resolve depth buffer and render cache of each enabled texture. */
378 int maxEnabledUnit
= ctx
->Texture
._MaxEnabledTexImageUnit
;
379 for (int i
= 0; i
<= maxEnabledUnit
; i
++) {
380 if (!ctx
->Texture
.Unit
[i
]._Current
)
382 tex_obj
= intel_texture_object(ctx
->Texture
.Unit
[i
]._Current
);
383 if (!tex_obj
|| !tex_obj
->mt
)
387 intel_miptree_prepare_texture(brw
, tex_obj
->mt
, tex_obj
->_Format
,
390 if (!aux_supported
&& brw
->gen
>= 9 &&
391 intel_disable_rb_aux_buffer(brw
, tex_obj
->mt
->bo
)) {
392 perf_debug("Sampling renderbuffer with non-compressible format - "
393 "turning off compression");
396 brw_render_cache_set_check_flush(brw
, tex_obj
->mt
->bo
);
398 if (tex_obj
->base
.StencilSampling
||
399 tex_obj
->mt
->format
== MESA_FORMAT_S_UINT8
) {
400 intel_update_r8stencil(brw
, tex_obj
->mt
);
404 /* Resolve color for each active shader image. */
405 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
406 const struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[i
];
408 if (unlikely(prog
&& prog
->info
.num_images
)) {
409 for (unsigned j
= 0; j
< prog
->info
.num_images
; j
++) {
410 struct gl_image_unit
*u
=
411 &ctx
->ImageUnits
[prog
->sh
.ImageUnits
[j
]];
412 tex_obj
= intel_texture_object(u
->TexObj
);
414 if (tex_obj
&& tex_obj
->mt
) {
415 intel_miptree_prepare_image(brw
, tex_obj
->mt
);
417 if (intel_miptree_is_lossless_compressed(brw
, tex_obj
->mt
) &&
418 intel_disable_rb_aux_buffer(brw
, tex_obj
->mt
->bo
)) {
419 perf_debug("Using renderbuffer as shader image - turning "
420 "off lossless compression");
423 brw_render_cache_set_check_flush(brw
, tex_obj
->mt
->bo
);
431 brw_predraw_resolve_framebuffer(struct brw_context
*brw
)
433 struct gl_context
*ctx
= &brw
->ctx
;
434 struct intel_renderbuffer
*depth_irb
;
436 /* Resolve the depth buffer's HiZ buffer. */
437 depth_irb
= intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
438 if (depth_irb
&& depth_irb
->mt
) {
439 intel_miptree_prepare_depth(brw
, depth_irb
->mt
,
442 depth_irb
->layer_count
);
445 /* Resolve color buffers for non-coherent framebuffer fetch. */
446 if (!ctx
->Extensions
.MESA_shader_framebuffer_fetch
&&
447 ctx
->FragmentProgram
._Current
&&
448 ctx
->FragmentProgram
._Current
->info
.outputs_read
) {
449 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
451 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
452 const struct intel_renderbuffer
*irb
=
453 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
456 intel_miptree_prepare_fb_fetch(brw
, irb
->mt
, irb
->mt_level
,
457 irb
->mt_layer
, irb
->layer_count
);
462 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
463 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
464 struct intel_renderbuffer
*irb
=
465 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
467 if (irb
== NULL
|| irb
->mt
== NULL
)
470 intel_miptree_prepare_render(brw
, irb
->mt
, irb
->mt_level
,
471 irb
->mt_layer
, irb
->layer_count
,
472 ctx
->Color
.sRGBEnabled
);
477 * \brief Call this after drawing to mark which buffers need resolving
479 * If the depth buffer was written to and if it has an accompanying HiZ
480 * buffer, then mark that it needs a depth resolve.
482 * If the color buffer is a multisample window system buffer, then
483 * mark that it needs a downsample.
485 * Also mark any render targets which will be textured as needing a render
489 brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw
)
491 struct gl_context
*ctx
= &brw
->ctx
;
492 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
494 struct intel_renderbuffer
*front_irb
= NULL
;
495 struct intel_renderbuffer
*back_irb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
496 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
497 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
498 struct gl_renderbuffer_attachment
*depth_att
= &fb
->Attachment
[BUFFER_DEPTH
];
500 if (_mesa_is_front_buffer_drawing(fb
))
501 front_irb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
504 front_irb
->need_downsample
= true;
506 back_irb
->need_downsample
= true;
508 bool depth_written
= brw_depth_writes_enabled(brw
);
509 if (depth_att
->Layered
) {
510 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
513 depth_irb
->layer_count
,
516 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
518 depth_irb
->mt_layer
, 1,
522 brw_render_cache_set_add_bo(brw
, depth_irb
->mt
->bo
);
525 if (ctx
->Extensions
.ARB_stencil_texturing
&&
526 stencil_irb
&& brw
->stencil_write_enabled
) {
527 brw_render_cache_set_add_bo(brw
, stencil_irb
->mt
->bo
);
530 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
531 struct intel_renderbuffer
*irb
=
532 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
537 brw_render_cache_set_add_bo(brw
, irb
->mt
->bo
);
538 intel_miptree_finish_render(brw
, irb
->mt
, irb
->mt_level
,
539 irb
->mt_layer
, irb
->layer_count
);
544 intel_renderbuffer_move_temp_back(struct brw_context
*brw
,
545 struct intel_renderbuffer
*irb
)
547 if (irb
->align_wa_mt
== NULL
)
550 brw_render_cache_set_check_flush(brw
, irb
->align_wa_mt
->bo
);
552 intel_miptree_copy_slice(brw
, irb
->align_wa_mt
, 0, 0,
554 irb
->Base
.Base
.TexImage
->Level
, irb
->mt_layer
);
556 intel_miptree_reference(&irb
->align_wa_mt
, NULL
);
558 /* Finally restore the x,y to correspond to full miptree. */
559 intel_renderbuffer_set_draw_offset(irb
);
561 /* Make sure render surface state gets re-emitted with updated miptree. */
562 brw
->NewGLState
|= _NEW_BUFFERS
;
566 brw_postdraw_reconcile_align_wa_slices(struct brw_context
*brw
)
568 struct gl_context
*ctx
= &brw
->ctx
;
569 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
571 struct intel_renderbuffer
*depth_irb
=
572 intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
573 struct intel_renderbuffer
*stencil_irb
=
574 intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
576 if (depth_irb
&& depth_irb
->align_wa_mt
)
577 intel_renderbuffer_move_temp_back(brw
, depth_irb
);
579 if (stencil_irb
&& stencil_irb
->align_wa_mt
)
580 intel_renderbuffer_move_temp_back(brw
, stencil_irb
);
582 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
583 struct intel_renderbuffer
*irb
=
584 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
586 if (!irb
|| irb
->align_wa_mt
== NULL
)
589 intel_renderbuffer_move_temp_back(brw
, irb
);
593 /* May fail if out of video memory for texture or vbo upload, or on
594 * fallback conditions.
597 brw_try_draw_prims(struct gl_context
*ctx
,
598 const struct gl_vertex_array
*arrays
[],
599 const struct _mesa_prim
*prims
,
601 const struct _mesa_index_buffer
*ib
,
602 bool index_bounds_valid
,
605 struct brw_transform_feedback_object
*xfb_obj
,
607 struct gl_buffer_object
*indirect
)
609 struct brw_context
*brw
= brw_context(ctx
);
611 bool fail_next
= false;
614 _mesa_update_state(ctx
);
616 /* We have to validate the textures *before* checking for fallbacks;
617 * otherwise, the software fallback won't be able to rely on the
618 * texture state, the firstLevel and lastLevel fields won't be
619 * set in the intel texture object (they'll both be 0), and the
620 * software fallback will segfault if it attempts to access any
621 * texture level other than level 0.
623 brw_validate_textures(brw
);
625 /* Find the highest sampler unit used by each shader program. A bit-count
626 * won't work since ARB programs use the texture unit number as the sampler
629 brw
->wm
.base
.sampler_count
=
630 util_last_bit(ctx
->FragmentProgram
._Current
->SamplersUsed
);
631 brw
->gs
.base
.sampler_count
= ctx
->GeometryProgram
._Current
?
632 util_last_bit(ctx
->GeometryProgram
._Current
->SamplersUsed
) : 0;
633 brw
->tes
.base
.sampler_count
= ctx
->TessEvalProgram
._Current
?
634 util_last_bit(ctx
->TessEvalProgram
._Current
->SamplersUsed
) : 0;
635 brw
->tcs
.base
.sampler_count
= ctx
->TessCtrlProgram
._Current
?
636 util_last_bit(ctx
->TessCtrlProgram
._Current
->SamplersUsed
) : 0;
637 brw
->vs
.base
.sampler_count
=
638 util_last_bit(ctx
->VertexProgram
._Current
->SamplersUsed
);
640 intel_prepare_render(brw
);
642 /* This workaround has to happen outside of brw_upload_render_state()
643 * because it may flush the batchbuffer for a blit, affecting the state
646 brw_workaround_depthstencil_alignment(brw
, 0);
648 /* Resolves must occur after updating renderbuffers, updating context state,
649 * and finalizing textures but before setting up any hardware state for
652 brw_predraw_resolve_inputs(brw
);
653 brw_predraw_resolve_framebuffer(brw
);
655 /* Bind all inputs, derive varying and size information:
657 brw_merge_inputs(brw
, arrays
);
660 brw
->ctx
.NewDriverState
|= BRW_NEW_INDICES
;
662 brw
->vb
.index_bounds_valid
= index_bounds_valid
;
663 brw
->vb
.min_index
= min_index
;
664 brw
->vb
.max_index
= max_index
;
665 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
667 for (i
= 0; i
< nr_prims
; i
++) {
668 int estimated_max_prim_size
;
669 const int sampler_state_size
= 16;
671 estimated_max_prim_size
= 512; /* batchbuffer commands */
672 estimated_max_prim_size
+= BRW_MAX_TEX_UNIT
*
673 (sampler_state_size
+ sizeof(struct gen5_sampler_default_color
));
674 estimated_max_prim_size
+= 1024; /* gen6 VS push constants */
675 estimated_max_prim_size
+= 1024; /* gen6 WM push constants */
676 estimated_max_prim_size
+= 512; /* misc. pad */
678 /* Flush the batch if it's approaching full, so that we don't wrap while
679 * we've got validated state that needs to be in the same batch as the
682 intel_batchbuffer_require_space(brw
, estimated_max_prim_size
, RENDER_RING
);
683 intel_batchbuffer_save_state(brw
);
685 if (brw
->num_instances
!= prims
[i
].num_instances
||
686 brw
->basevertex
!= prims
[i
].basevertex
||
687 brw
->baseinstance
!= prims
[i
].base_instance
) {
688 brw
->num_instances
= prims
[i
].num_instances
;
689 brw
->basevertex
= prims
[i
].basevertex
;
690 brw
->baseinstance
= prims
[i
].base_instance
;
691 if (i
> 0) { /* For i == 0 we just did this before the loop */
692 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
693 brw_merge_inputs(brw
, arrays
);
697 /* Determine if we need to flag BRW_NEW_VERTICES for updating the
698 * gl_BaseVertexARB or gl_BaseInstanceARB values. For indirect draw, we
699 * always flag if the shader uses one of the values. For direct draws,
700 * we only flag if the values change.
702 const int new_basevertex
=
703 prims
[i
].indexed
? prims
[i
].basevertex
: prims
[i
].start
;
704 const int new_baseinstance
= prims
[i
].base_instance
;
705 const struct brw_vs_prog_data
*vs_prog_data
=
706 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
708 const bool uses_draw_parameters
=
709 vs_prog_data
->uses_basevertex
||
710 vs_prog_data
->uses_baseinstance
;
712 if ((uses_draw_parameters
&& prims
[i
].is_indirect
) ||
713 (vs_prog_data
->uses_basevertex
&&
714 brw
->draw
.params
.gl_basevertex
!= new_basevertex
) ||
715 (vs_prog_data
->uses_baseinstance
&&
716 brw
->draw
.params
.gl_baseinstance
!= new_baseinstance
))
717 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
720 brw
->draw
.params
.gl_basevertex
= new_basevertex
;
721 brw
->draw
.params
.gl_baseinstance
= new_baseinstance
;
722 brw_bo_unreference(brw
->draw
.draw_params_bo
);
724 if (prims
[i
].is_indirect
) {
725 /* Point draw_params_bo at the indirect buffer. */
726 brw
->draw
.draw_params_bo
=
727 intel_buffer_object(ctx
->DrawIndirectBuffer
)->buffer
;
728 brw_bo_reference(brw
->draw
.draw_params_bo
);
729 brw
->draw
.draw_params_offset
=
730 prims
[i
].indirect_offset
+ (prims
[i
].indexed
? 12 : 8);
732 /* Set draw_params_bo to NULL so brw_prepare_vertices knows it
733 * has to upload gl_BaseVertex and such if they're needed.
735 brw
->draw
.draw_params_bo
= NULL
;
736 brw
->draw
.draw_params_offset
= 0;
739 /* gl_DrawID always needs its own vertex buffer since it's not part of
740 * the indirect parameter buffer. If the program uses gl_DrawID we need
741 * to flag BRW_NEW_VERTICES. For the first iteration, we don't have
742 * valid vs_prog_data, but we always flag BRW_NEW_VERTICES before
745 brw
->draw
.gl_drawid
= prims
[i
].draw_id
;
746 brw_bo_unreference(brw
->draw
.draw_id_bo
);
747 brw
->draw
.draw_id_bo
= NULL
;
748 if (i
> 0 && vs_prog_data
->uses_drawid
)
749 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
752 brw_set_prim(brw
, &prims
[i
]);
754 gen6_set_prim(brw
, &prims
[i
]);
758 /* Note that before the loop, brw->ctx.NewDriverState was set to != 0, and
759 * that the state updated in the loop outside of this block is that in
760 * *_set_prim or intel_batchbuffer_flush(), which only impacts
761 * brw->ctx.NewDriverState.
763 if (brw
->ctx
.NewDriverState
) {
764 brw
->no_batch_wrap
= true;
765 brw_upload_render_state(brw
);
768 brw_emit_prim(brw
, &prims
[i
], brw
->primitive
, xfb_obj
, stream
);
770 brw
->no_batch_wrap
= false;
772 if (!brw_batch_has_aperture_space(brw
, 0)) {
774 intel_batchbuffer_reset_to_saved(brw
);
775 intel_batchbuffer_flush(brw
);
779 int ret
= intel_batchbuffer_flush(brw
);
780 WARN_ONCE(ret
== -ENOSPC
,
781 "i965: Single primitive emit exceeded "
782 "available aperture space\n");
786 /* Now that we know we haven't run out of aperture space, we can safely
787 * reset the dirty bits.
789 if (brw
->ctx
.NewDriverState
)
790 brw_render_state_finished(brw
);
793 if (brw
->always_flush_batch
)
794 intel_batchbuffer_flush(brw
);
796 brw_program_cache_check_size(brw
);
797 brw_postdraw_reconcile_align_wa_slices(brw
);
798 brw_postdraw_set_buffers_need_resolve(brw
);
804 brw_draw_prims(struct gl_context
*ctx
,
805 const struct _mesa_prim
*prims
,
807 const struct _mesa_index_buffer
*ib
,
808 GLboolean index_bounds_valid
,
811 struct gl_transform_feedback_object
*gl_xfb_obj
,
813 struct gl_buffer_object
*indirect
)
815 struct brw_context
*brw
= brw_context(ctx
);
816 const struct gl_vertex_array
**arrays
= ctx
->Array
._DrawArrays
;
817 struct brw_transform_feedback_object
*xfb_obj
=
818 (struct brw_transform_feedback_object
*) gl_xfb_obj
;
820 if (!brw_check_conditional_render(brw
))
823 /* Handle primitive restart if needed */
824 if (brw_handle_primitive_restart(ctx
, prims
, nr_prims
, ib
, indirect
)) {
825 /* The draw was handled, so we can exit now */
829 /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
830 * won't support all the extensions we support.
832 if (ctx
->RenderMode
!= GL_RENDER
) {
833 perf_debug("%s render mode not supported in hardware\n",
834 _mesa_enum_to_string(ctx
->RenderMode
));
835 _swsetup_Wakeup(ctx
);
837 _tnl_draw_prims(ctx
, prims
, nr_prims
, ib
,
838 index_bounds_valid
, min_index
, max_index
, NULL
, 0, NULL
);
842 /* If we're going to have to upload any of the user's vertex arrays, then
843 * get the minimum and maximum of their index buffer so we know what range
846 if (!index_bounds_valid
&& !vbo_all_varyings_in_vbos(arrays
)) {
847 perf_debug("Scanning index buffer to compute index buffer bounds. "
848 "Use glDrawRangeElements() to avoid this.\n");
849 vbo_get_minmax_indices(ctx
, prims
, ib
, &min_index
, &max_index
, nr_prims
);
850 index_bounds_valid
= true;
853 /* Try drawing with the hardware, but don't do anything else if we can't
854 * manage it. swrast doesn't support our featureset, so we can't fall back
857 brw_try_draw_prims(ctx
, arrays
, prims
, nr_prims
, ib
, index_bounds_valid
,
858 min_index
, max_index
, xfb_obj
, stream
, indirect
);
862 brw_draw_init(struct brw_context
*brw
)
864 struct gl_context
*ctx
= &brw
->ctx
;
865 struct vbo_context
*vbo
= vbo_context(ctx
);
867 /* Register our drawing function:
869 vbo
->draw_prims
= brw_draw_prims
;
871 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++)
872 brw
->vb
.inputs
[i
].buffer
= -1;
873 brw
->vb
.nr_buffers
= 0;
874 brw
->vb
.nr_enabled
= 0;
878 brw_draw_destroy(struct brw_context
*brw
)
882 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
883 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
884 brw
->vb
.buffers
[i
].bo
= NULL
;
886 brw
->vb
.nr_buffers
= 0;
888 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
889 brw
->vb
.enabled
[i
]->buffer
= -1;
891 brw
->vb
.nr_enabled
= 0;
893 brw_bo_unreference(brw
->ib
.bo
);