2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <sys/errno.h>
28 #include "main/blend.h"
29 #include "main/context.h"
30 #include "main/condrender.h"
31 #include "main/samplerobj.h"
32 #include "main/state.h"
33 #include "main/enums.h"
34 #include "main/macros.h"
35 #include "main/transformfeedback.h"
36 #include "main/framebuffer.h"
37 #include "main/varray.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "drivers/common/meta.h"
43 #include "util/bitscan.h"
44 #include "util/bitset.h"
46 #include "brw_blorp.h"
48 #include "brw_defines.h"
49 #include "compiler/brw_eu_defines.h"
50 #include "brw_context.h"
51 #include "brw_state.h"
53 #include "intel_batchbuffer.h"
54 #include "intel_buffers.h"
55 #include "intel_fbo.h"
56 #include "intel_mipmap_tree.h"
57 #include "intel_buffer_objects.h"
59 #define FILE_DEBUG_FLAG DEBUG_PRIMS
62 static const GLenum reduced_prim
[GL_POLYGON
+1] = {
63 [GL_POINTS
] = GL_POINTS
,
64 [GL_LINES
] = GL_LINES
,
65 [GL_LINE_LOOP
] = GL_LINES
,
66 [GL_LINE_STRIP
] = GL_LINES
,
67 [GL_TRIANGLES
] = GL_TRIANGLES
,
68 [GL_TRIANGLE_STRIP
] = GL_TRIANGLES
,
69 [GL_TRIANGLE_FAN
] = GL_TRIANGLES
,
70 [GL_QUADS
] = GL_TRIANGLES
,
71 [GL_QUAD_STRIP
] = GL_TRIANGLES
,
72 [GL_POLYGON
] = GL_TRIANGLES
75 /* When the primitive changes, set a state bit and re-validate. Not
76 * the nicest and would rather deal with this by having all the
77 * programs be immune to the active primitive (ie. cope with all
78 * possibilities). That may not be realistic however.
81 brw_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
83 struct gl_context
*ctx
= &brw
->ctx
;
84 uint32_t hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
86 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
88 /* Slight optimization to avoid the GS program when not needed:
90 if (prim
->mode
== GL_QUAD_STRIP
&&
91 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
92 ctx
->Polygon
.FrontMode
== GL_FILL
&&
93 ctx
->Polygon
.BackMode
== GL_FILL
)
94 hw_prim
= _3DPRIM_TRISTRIP
;
96 if (prim
->mode
== GL_QUADS
&& prim
->count
== 4 &&
97 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
98 ctx
->Polygon
.FrontMode
== GL_FILL
&&
99 ctx
->Polygon
.BackMode
== GL_FILL
) {
100 hw_prim
= _3DPRIM_TRIFAN
;
103 if (hw_prim
!= brw
->primitive
) {
104 brw
->primitive
= hw_prim
;
105 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
107 if (reduced_prim
[prim
->mode
] != brw
->reduced_primitive
) {
108 brw
->reduced_primitive
= reduced_prim
[prim
->mode
];
109 brw
->ctx
.NewDriverState
|= BRW_NEW_REDUCED_PRIMITIVE
;
115 gen6_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
117 const struct gl_context
*ctx
= &brw
->ctx
;
120 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
122 if (prim
->mode
== GL_PATCHES
) {
123 hw_prim
= _3DPRIM_PATCHLIST(ctx
->TessCtrlProgram
.patch_vertices
);
125 hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
128 if (hw_prim
!= brw
->primitive
) {
129 brw
->primitive
= hw_prim
;
130 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
131 if (prim
->mode
== GL_PATCHES
)
132 brw
->ctx
.NewDriverState
|= BRW_NEW_PATCH_PRIMITIVE
;
138 * The hardware is capable of removing dangling vertices on its own; however,
139 * prior to Gen6, we sometimes convert quads into trifans (and quad strips
140 * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
141 * This function manually trims dangling vertices from a draw call involving
142 * quads so that those dangling vertices won't get drawn when we convert to
146 trim(GLenum prim
, GLuint length
)
148 if (prim
== GL_QUAD_STRIP
)
149 return length
> 3 ? (length
- length
% 2) : 0;
150 else if (prim
== GL_QUADS
)
151 return length
- length
% 4;
158 brw_emit_prim(struct brw_context
*brw
,
159 const struct _mesa_prim
*prim
,
161 struct brw_transform_feedback_object
*xfb_obj
,
164 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
165 int verts_per_instance
;
166 int vertex_access_type
;
169 DBG("PRIM: %s %d %d\n", _mesa_enum_to_string(prim
->mode
),
170 prim
->start
, prim
->count
);
172 int start_vertex_location
= prim
->start
;
173 int base_vertex_location
= prim
->basevertex
;
176 vertex_access_type
= devinfo
->gen
>= 7 ?
177 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
178 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
;
179 start_vertex_location
+= brw
->ib
.start_vertex_offset
;
180 base_vertex_location
+= brw
->vb
.start_vertex_bias
;
182 vertex_access_type
= devinfo
->gen
>= 7 ?
183 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
:
184 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
185 start_vertex_location
+= brw
->vb
.start_vertex_bias
;
188 /* We only need to trim the primitive count on pre-Gen6. */
189 if (devinfo
->gen
< 6)
190 verts_per_instance
= trim(prim
->mode
, prim
->count
);
192 verts_per_instance
= prim
->count
;
194 /* If nothing to emit, just return. */
195 if (verts_per_instance
== 0 && !prim
->is_indirect
&& !xfb_obj
)
198 /* If we're set to always flush, do it before and after the primitive emit.
199 * We want to catch both missed flushes that hurt instruction/state cache
200 * and missed flushes of the render cache as it heads to other parts of
201 * the besides the draw code.
203 if (brw
->always_flush_cache
)
204 brw_emit_mi_flush(brw
);
206 /* If indirect, emit a bunch of loads from the indirect BO. */
208 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
210 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
,
211 xfb_obj
->prim_count_bo
,
212 stream
* sizeof(uint32_t));
214 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (9 - 2));
215 OUT_BATCH(GEN7_3DPRIM_INSTANCE_COUNT
);
216 OUT_BATCH(prim
->num_instances
);
217 OUT_BATCH(GEN7_3DPRIM_START_VERTEX
);
219 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
221 OUT_BATCH(GEN7_3DPRIM_START_INSTANCE
);
224 } else if (prim
->is_indirect
) {
225 struct gl_buffer_object
*indirect_buffer
= brw
->ctx
.DrawIndirectBuffer
;
226 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
227 intel_buffer_object(indirect_buffer
),
228 prim
->indirect_offset
, 5 * sizeof(GLuint
), false);
230 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
232 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
, bo
,
233 prim
->indirect_offset
+ 0);
234 brw_load_register_mem(brw
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
,
235 prim
->indirect_offset
+ 4);
237 brw_load_register_mem(brw
, GEN7_3DPRIM_START_VERTEX
, bo
,
238 prim
->indirect_offset
+ 8);
240 brw_load_register_mem(brw
, GEN7_3DPRIM_BASE_VERTEX
, bo
,
241 prim
->indirect_offset
+ 12);
242 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
243 prim
->indirect_offset
+ 16);
245 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
246 prim
->indirect_offset
+ 12);
247 brw_load_register_imm32(brw
, GEN7_3DPRIM_BASE_VERTEX
, 0);
253 BEGIN_BATCH(devinfo
->gen
>= 7 ? 7 : 6);
255 if (devinfo
->gen
>= 7) {
256 const int predicate_enable
=
257 (brw
->predicate
.state
== BRW_PREDICATE_STATE_USE_BIT
)
258 ? GEN7_3DPRIM_PREDICATE_ENABLE
: 0;
260 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2) | indirect_flag
| predicate_enable
);
261 OUT_BATCH(hw_prim
| vertex_access_type
);
263 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
264 hw_prim
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
267 OUT_BATCH(verts_per_instance
);
268 OUT_BATCH(start_vertex_location
);
269 OUT_BATCH(prim
->num_instances
);
270 OUT_BATCH(prim
->base_instance
);
271 OUT_BATCH(base_vertex_location
);
274 if (brw
->always_flush_cache
)
275 brw_emit_mi_flush(brw
);
280 brw_merge_inputs(struct brw_context
*brw
,
281 const struct gl_vertex_array
*arrays
)
283 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
284 const struct gl_context
*ctx
= &brw
->ctx
;
287 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
288 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
289 brw
->vb
.buffers
[i
].bo
= NULL
;
291 brw
->vb
.nr_buffers
= 0;
293 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
294 brw
->vb
.inputs
[i
].buffer
= -1;
295 brw
->vb
.inputs
[i
].glarray
= &arrays
[i
];
298 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
299 uint64_t mask
= ctx
->VertexProgram
._Current
->info
.inputs_read
;
300 /* Prior to Haswell, the hardware can't natively support GL_FIXED or
301 * 2_10_10_10_REV vertex formats. Set appropriate workaround flags.
304 const struct gl_array_attributes
*glattrib
;
305 uint8_t wa_flags
= 0;
307 i
= u_bit_scan64(&mask
);
308 glattrib
= brw
->vb
.inputs
[i
].glarray
->VertexAttrib
;
310 switch (glattrib
->Type
) {
313 wa_flags
= glattrib
->Size
;
316 case GL_INT_2_10_10_10_REV
:
317 wa_flags
|= BRW_ATTRIB_WA_SIGN
;
320 case GL_UNSIGNED_INT_2_10_10_10_REV
:
321 if (glattrib
->Format
== GL_BGRA
)
322 wa_flags
|= BRW_ATTRIB_WA_BGRA
;
324 if (glattrib
->Normalized
)
325 wa_flags
|= BRW_ATTRIB_WA_NORMALIZE
;
326 else if (!glattrib
->Integer
)
327 wa_flags
|= BRW_ATTRIB_WA_SCALE
;
332 if (brw
->vb
.attrib_wa_flags
[i
] != wa_flags
) {
333 brw
->vb
.attrib_wa_flags
[i
] = wa_flags
;
334 brw
->ctx
.NewDriverState
|= BRW_NEW_VS_ATTRIB_WORKAROUNDS
;
340 /* Disable auxiliary buffers if a renderbuffer is also bound as a texture
341 * or shader image. This causes a self-dependency, where both rendering
342 * and sampling may concurrently read or write the CCS buffer, causing
346 intel_disable_rb_aux_buffer(struct brw_context
*brw
,
347 bool *draw_aux_buffer_disabled
,
348 struct intel_mipmap_tree
*tex_mt
,
349 unsigned min_level
, unsigned num_levels
,
352 const struct gl_framebuffer
*fb
= brw
->ctx
.DrawBuffer
;
355 /* We only need to worry about color compression and fast clears. */
356 if (tex_mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
357 tex_mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
360 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
361 const struct intel_renderbuffer
*irb
=
362 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
364 if (irb
&& irb
->mt
->bo
== tex_mt
->bo
&&
365 irb
->mt_level
>= min_level
&&
366 irb
->mt_level
< min_level
+ num_levels
) {
367 found
= draw_aux_buffer_disabled
[i
] = true;
372 perf_debug("Disabling CCS because a renderbuffer is also bound %s.\n",
380 mark_textures_used_for_txf(BITSET_WORD
*used_for_txf
,
381 const struct gl_program
*prog
)
386 unsigned mask
= prog
->SamplersUsed
& prog
->info
.textures_used_by_txf
;
388 int s
= u_bit_scan(&mask
);
389 BITSET_SET(used_for_txf
, prog
->SamplerUnits
[s
]);
394 * \brief Resolve buffers before drawing.
396 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
397 * enabled depth texture, and flush the render cache for any dirty textures.
400 brw_predraw_resolve_inputs(struct brw_context
*brw
, bool rendering
,
401 bool *draw_aux_buffer_disabled
)
403 struct gl_context
*ctx
= &brw
->ctx
;
404 struct intel_texture_object
*tex_obj
;
406 BITSET_DECLARE(used_for_txf
, MAX_COMBINED_TEXTURE_IMAGE_UNITS
);
407 memset(used_for_txf
, 0, sizeof(used_for_txf
));
409 mark_textures_used_for_txf(used_for_txf
, ctx
->VertexProgram
._Current
);
410 mark_textures_used_for_txf(used_for_txf
, ctx
->TessCtrlProgram
._Current
);
411 mark_textures_used_for_txf(used_for_txf
, ctx
->TessEvalProgram
._Current
);
412 mark_textures_used_for_txf(used_for_txf
, ctx
->GeometryProgram
._Current
);
413 mark_textures_used_for_txf(used_for_txf
, ctx
->FragmentProgram
._Current
);
415 mark_textures_used_for_txf(used_for_txf
, ctx
->ComputeProgram
._Current
);
418 /* Resolve depth buffer and render cache of each enabled texture. */
419 int maxEnabledUnit
= ctx
->Texture
._MaxEnabledTexImageUnit
;
420 for (int i
= 0; i
<= maxEnabledUnit
; i
++) {
421 if (!ctx
->Texture
.Unit
[i
]._Current
)
423 tex_obj
= intel_texture_object(ctx
->Texture
.Unit
[i
]._Current
);
424 if (!tex_obj
|| !tex_obj
->mt
)
427 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, i
);
428 enum isl_format view_format
=
429 translate_tex_format(brw
, tex_obj
->_Format
, sampler
->sRGBDecode
);
431 unsigned min_level
, min_layer
, num_levels
, num_layers
;
432 if (tex_obj
->base
.Immutable
) {
433 min_level
= tex_obj
->base
.MinLevel
;
434 num_levels
= MIN2(tex_obj
->base
.NumLevels
, tex_obj
->_MaxLevel
+ 1);
435 min_layer
= tex_obj
->base
.MinLayer
;
436 num_layers
= tex_obj
->base
.Target
!= GL_TEXTURE_3D
?
437 tex_obj
->base
.NumLayers
: INTEL_REMAINING_LAYERS
;
439 min_level
= tex_obj
->base
.BaseLevel
;
440 num_levels
= tex_obj
->_MaxLevel
- tex_obj
->base
.BaseLevel
+ 1;
442 num_layers
= INTEL_REMAINING_LAYERS
;
446 intel_disable_rb_aux_buffer(brw
, draw_aux_buffer_disabled
,
447 tex_obj
->mt
, min_level
, num_levels
,
451 intel_miptree_prepare_texture(brw
, tex_obj
->mt
, view_format
,
452 min_level
, num_levels
,
453 min_layer
, num_layers
);
455 /* If any programs are using it with texelFetch, we may need to also do
456 * a prepare with an sRGB format to ensure texelFetch works "properly".
458 if (BITSET_TEST(used_for_txf
, i
)) {
459 enum isl_format txf_format
=
460 translate_tex_format(brw
, tex_obj
->_Format
, GL_DECODE_EXT
);
461 if (txf_format
!= view_format
) {
462 intel_miptree_prepare_texture(brw
, tex_obj
->mt
, txf_format
,
463 min_level
, num_levels
,
464 min_layer
, num_layers
);
468 brw_cache_flush_for_read(brw
, tex_obj
->mt
->bo
);
470 if (tex_obj
->base
.StencilSampling
||
471 tex_obj
->mt
->format
== MESA_FORMAT_S_UINT8
) {
472 intel_update_r8stencil(brw
, tex_obj
->mt
);
476 /* Resolve color for each active shader image. */
477 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
478 const struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[i
];
480 if (unlikely(prog
&& prog
->info
.num_images
)) {
481 for (unsigned j
= 0; j
< prog
->info
.num_images
; j
++) {
482 struct gl_image_unit
*u
=
483 &ctx
->ImageUnits
[prog
->sh
.ImageUnits
[j
]];
484 tex_obj
= intel_texture_object(u
->TexObj
);
486 if (tex_obj
&& tex_obj
->mt
) {
488 intel_disable_rb_aux_buffer(brw
, draw_aux_buffer_disabled
,
490 "as a shader image");
493 intel_miptree_prepare_image(brw
, tex_obj
->mt
);
495 brw_cache_flush_for_read(brw
, tex_obj
->mt
->bo
);
503 brw_predraw_resolve_framebuffer(struct brw_context
*brw
,
504 bool *draw_aux_buffer_disabled
)
506 struct gl_context
*ctx
= &brw
->ctx
;
507 struct intel_renderbuffer
*depth_irb
;
509 /* Resolve the depth buffer's HiZ buffer. */
510 depth_irb
= intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
511 if (depth_irb
&& depth_irb
->mt
) {
512 intel_miptree_prepare_depth(brw
, depth_irb
->mt
,
515 depth_irb
->layer_count
);
518 /* Resolve color buffers for non-coherent framebuffer fetch. */
519 if (!ctx
->Extensions
.EXT_shader_framebuffer_fetch
&&
520 ctx
->FragmentProgram
._Current
&&
521 ctx
->FragmentProgram
._Current
->info
.outputs_read
) {
522 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
524 /* This is only used for non-coherent framebuffer fetch, so we don't
525 * need to worry about CCS_E and can simply pass 'false' below.
527 assert(brw
->screen
->devinfo
.gen
< 9);
529 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
530 const struct intel_renderbuffer
*irb
=
531 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
534 intel_miptree_prepare_texture(brw
, irb
->mt
, irb
->mt
->surf
.format
,
536 irb
->mt_layer
, irb
->layer_count
);
541 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
542 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
543 struct intel_renderbuffer
*irb
=
544 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
546 if (irb
== NULL
|| irb
->mt
== NULL
)
549 mesa_format mesa_format
=
550 _mesa_get_render_format(ctx
, intel_rb_format(irb
));
551 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
552 bool blend_enabled
= ctx
->Color
.BlendEnabled
& (1 << i
);
553 enum isl_aux_usage aux_usage
=
554 intel_miptree_render_aux_usage(brw
, irb
->mt
, isl_format
,
556 draw_aux_buffer_disabled
[i
]);
557 if (brw
->draw_aux_usage
[i
] != aux_usage
) {
558 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
559 brw
->draw_aux_usage
[i
] = aux_usage
;
562 intel_miptree_prepare_render(brw
, irb
->mt
, irb
->mt_level
,
563 irb
->mt_layer
, irb
->layer_count
,
566 brw_cache_flush_for_render(brw
, irb
->mt
->bo
,
567 isl_format
, aux_usage
);
572 * \brief Call this after drawing to mark which buffers need resolving
574 * If the depth buffer was written to and if it has an accompanying HiZ
575 * buffer, then mark that it needs a depth resolve.
577 * If the color buffer is a multisample window system buffer, then
578 * mark that it needs a downsample.
580 * Also mark any render targets which will be textured as needing a render
584 brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw
)
586 struct gl_context
*ctx
= &brw
->ctx
;
587 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
589 struct intel_renderbuffer
*front_irb
= NULL
;
590 struct intel_renderbuffer
*back_irb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
591 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
592 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
593 struct gl_renderbuffer_attachment
*depth_att
= &fb
->Attachment
[BUFFER_DEPTH
];
595 if (_mesa_is_front_buffer_drawing(fb
))
596 front_irb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
599 front_irb
->need_downsample
= true;
601 back_irb
->need_downsample
= true;
603 bool depth_written
= brw_depth_writes_enabled(brw
);
604 if (depth_att
->Layered
) {
605 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
608 depth_irb
->layer_count
,
611 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
613 depth_irb
->mt_layer
, 1,
617 brw_depth_cache_add_bo(brw
, depth_irb
->mt
->bo
);
620 if (stencil_irb
&& brw
->stencil_write_enabled
)
621 brw_depth_cache_add_bo(brw
, stencil_irb
->mt
->bo
);
623 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
624 struct intel_renderbuffer
*irb
=
625 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
630 mesa_format mesa_format
=
631 _mesa_get_render_format(ctx
, intel_rb_format(irb
));
632 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
633 enum isl_aux_usage aux_usage
= brw
->draw_aux_usage
[i
];
635 brw_render_cache_add_bo(brw
, irb
->mt
->bo
, isl_format
, aux_usage
);
637 intel_miptree_finish_render(brw
, irb
->mt
, irb
->mt_level
,
638 irb
->mt_layer
, irb
->layer_count
,
644 intel_renderbuffer_move_temp_back(struct brw_context
*brw
,
645 struct intel_renderbuffer
*irb
)
647 if (irb
->align_wa_mt
== NULL
)
650 brw_cache_flush_for_read(brw
, irb
->align_wa_mt
->bo
);
652 intel_miptree_copy_slice(brw
, irb
->align_wa_mt
, 0, 0,
654 irb
->Base
.Base
.TexImage
->Level
, irb
->mt_layer
);
656 intel_miptree_reference(&irb
->align_wa_mt
, NULL
);
658 /* Finally restore the x,y to correspond to full miptree. */
659 intel_renderbuffer_set_draw_offset(irb
);
661 /* Make sure render surface state gets re-emitted with updated miptree. */
662 brw
->NewGLState
|= _NEW_BUFFERS
;
666 brw_postdraw_reconcile_align_wa_slices(struct brw_context
*brw
)
668 struct gl_context
*ctx
= &brw
->ctx
;
669 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
671 struct intel_renderbuffer
*depth_irb
=
672 intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
673 struct intel_renderbuffer
*stencil_irb
=
674 intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
676 if (depth_irb
&& depth_irb
->align_wa_mt
)
677 intel_renderbuffer_move_temp_back(brw
, depth_irb
);
679 if (stencil_irb
&& stencil_irb
->align_wa_mt
)
680 intel_renderbuffer_move_temp_back(brw
, stencil_irb
);
682 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
683 struct intel_renderbuffer
*irb
=
684 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
686 if (!irb
|| irb
->align_wa_mt
== NULL
)
689 intel_renderbuffer_move_temp_back(brw
, irb
);
694 brw_prepare_drawing(struct gl_context
*ctx
,
695 const struct gl_vertex_array
*arrays
,
696 const struct _mesa_index_buffer
*ib
,
697 bool index_bounds_valid
,
701 struct brw_context
*brw
= brw_context(ctx
);
704 _mesa_update_state(ctx
);
706 /* We have to validate the textures *before* checking for fallbacks;
707 * otherwise, the software fallback won't be able to rely on the
708 * texture state, the firstLevel and lastLevel fields won't be
709 * set in the intel texture object (they'll both be 0), and the
710 * software fallback will segfault if it attempts to access any
711 * texture level other than level 0.
713 brw_validate_textures(brw
);
715 /* Find the highest sampler unit used by each shader program. A bit-count
716 * won't work since ARB programs use the texture unit number as the sampler
719 brw
->wm
.base
.sampler_count
=
720 util_last_bit(ctx
->FragmentProgram
._Current
->SamplersUsed
);
721 brw
->gs
.base
.sampler_count
= ctx
->GeometryProgram
._Current
?
722 util_last_bit(ctx
->GeometryProgram
._Current
->SamplersUsed
) : 0;
723 brw
->tes
.base
.sampler_count
= ctx
->TessEvalProgram
._Current
?
724 util_last_bit(ctx
->TessEvalProgram
._Current
->SamplersUsed
) : 0;
725 brw
->tcs
.base
.sampler_count
= ctx
->TessCtrlProgram
._Current
?
726 util_last_bit(ctx
->TessCtrlProgram
._Current
->SamplersUsed
) : 0;
727 brw
->vs
.base
.sampler_count
=
728 util_last_bit(ctx
->VertexProgram
._Current
->SamplersUsed
);
730 intel_prepare_render(brw
);
732 /* This workaround has to happen outside of brw_upload_render_state()
733 * because it may flush the batchbuffer for a blit, affecting the state
736 brw_workaround_depthstencil_alignment(brw
, 0);
738 /* Resolves must occur after updating renderbuffers, updating context state,
739 * and finalizing textures but before setting up any hardware state for
742 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
] = { };
743 brw_predraw_resolve_inputs(brw
, true, draw_aux_buffer_disabled
);
744 brw_predraw_resolve_framebuffer(brw
, draw_aux_buffer_disabled
);
746 /* Bind all inputs, derive varying and size information:
748 brw_merge_inputs(brw
, arrays
);
751 brw
->ctx
.NewDriverState
|= BRW_NEW_INDICES
;
753 brw
->vb
.index_bounds_valid
= index_bounds_valid
;
754 brw
->vb
.min_index
= min_index
;
755 brw
->vb
.max_index
= max_index
;
756 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
760 brw_finish_drawing(struct gl_context
*ctx
)
762 struct brw_context
*brw
= brw_context(ctx
);
764 if (brw
->always_flush_batch
)
765 intel_batchbuffer_flush(brw
);
767 brw_program_cache_check_size(brw
);
768 brw_postdraw_reconcile_align_wa_slices(brw
);
769 brw_postdraw_set_buffers_need_resolve(brw
);
771 if (brw
->draw
.draw_params_count_bo
) {
772 brw_bo_unreference(brw
->draw
.draw_params_count_bo
);
773 brw
->draw
.draw_params_count_bo
= NULL
;
777 /* May fail if out of video memory for texture or vbo upload, or on
778 * fallback conditions.
781 brw_draw_single_prim(struct gl_context
*ctx
,
782 const struct gl_vertex_array
*arrays
,
783 const struct _mesa_prim
*prim
,
785 struct brw_transform_feedback_object
*xfb_obj
,
787 struct gl_buffer_object
*indirect
)
789 struct brw_context
*brw
= brw_context(ctx
);
790 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
791 bool fail_next
= false;
793 /* Flag BRW_NEW_DRAW_CALL on every draw. This allows us to have
794 * atoms that happen on every draw call.
796 brw
->ctx
.NewDriverState
|= BRW_NEW_DRAW_CALL
;
798 /* Flush the batch if the batch/state buffers are nearly full. We can
799 * grow them if needed, but this is not free, so we'd like to avoid it.
801 intel_batchbuffer_require_space(brw
, 1500, RENDER_RING
);
802 brw_require_statebuffer_space(brw
, 2400);
803 intel_batchbuffer_save_state(brw
);
805 if (brw
->num_instances
!= prim
->num_instances
||
806 brw
->basevertex
!= prim
->basevertex
||
807 brw
->baseinstance
!= prim
->base_instance
) {
808 brw
->num_instances
= prim
->num_instances
;
809 brw
->basevertex
= prim
->basevertex
;
810 brw
->baseinstance
= prim
->base_instance
;
811 if (prim_id
> 0) { /* For i == 0 we just did this before the loop */
812 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
813 brw_merge_inputs(brw
, arrays
);
817 /* Determine if we need to flag BRW_NEW_VERTICES for updating the
818 * gl_BaseVertexARB or gl_BaseInstanceARB values. For indirect draw, we
819 * always flag if the shader uses one of the values. For direct draws,
820 * we only flag if the values change.
822 const int new_basevertex
=
823 prim
->indexed
? prim
->basevertex
: prim
->start
;
824 const int new_baseinstance
= prim
->base_instance
;
825 const struct brw_vs_prog_data
*vs_prog_data
=
826 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
828 const bool uses_draw_parameters
=
829 vs_prog_data
->uses_basevertex
||
830 vs_prog_data
->uses_baseinstance
;
832 if ((uses_draw_parameters
&& prim
->is_indirect
) ||
833 (vs_prog_data
->uses_basevertex
&&
834 brw
->draw
.params
.gl_basevertex
!= new_basevertex
) ||
835 (vs_prog_data
->uses_baseinstance
&&
836 brw
->draw
.params
.gl_baseinstance
!= new_baseinstance
))
837 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
840 brw
->draw
.params
.gl_basevertex
= new_basevertex
;
841 brw
->draw
.params
.gl_baseinstance
= new_baseinstance
;
842 brw_bo_unreference(brw
->draw
.draw_params_bo
);
844 if (prim
->is_indirect
) {
845 /* Point draw_params_bo at the indirect buffer. */
846 brw
->draw
.draw_params_bo
=
847 intel_buffer_object(ctx
->DrawIndirectBuffer
)->buffer
;
848 brw_bo_reference(brw
->draw
.draw_params_bo
);
849 brw
->draw
.draw_params_offset
=
850 prim
->indirect_offset
+ (prim
->indexed
? 12 : 8);
852 /* Set draw_params_bo to NULL so brw_prepare_vertices knows it
853 * has to upload gl_BaseVertex and such if they're needed.
855 brw
->draw
.draw_params_bo
= NULL
;
856 brw
->draw
.draw_params_offset
= 0;
859 /* gl_DrawID always needs its own vertex buffer since it's not part of
860 * the indirect parameter buffer. If the program uses gl_DrawID we need
861 * to flag BRW_NEW_VERTICES. For the first iteration, we don't have
862 * valid vs_prog_data, but we always flag BRW_NEW_VERTICES before
865 brw
->draw
.gl_drawid
= prim
->draw_id
;
866 brw_bo_unreference(brw
->draw
.draw_id_bo
);
867 brw
->draw
.draw_id_bo
= NULL
;
868 if (prim_id
> 0 && vs_prog_data
->uses_drawid
)
869 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
871 if (devinfo
->gen
< 6)
872 brw_set_prim(brw
, prim
);
874 gen6_set_prim(brw
, prim
);
878 /* Note that before the loop, brw->ctx.NewDriverState was set to != 0, and
879 * that the state updated in the loop outside of this block is that in
880 * *_set_prim or intel_batchbuffer_flush(), which only impacts
881 * brw->ctx.NewDriverState.
883 if (brw
->ctx
.NewDriverState
) {
884 brw
->batch
.no_wrap
= true;
885 brw_upload_render_state(brw
);
888 brw_emit_prim(brw
, prim
, brw
->primitive
, xfb_obj
, stream
);
890 brw
->batch
.no_wrap
= false;
892 if (!brw_batch_has_aperture_space(brw
, 0)) {
894 intel_batchbuffer_reset_to_saved(brw
);
895 intel_batchbuffer_flush(brw
);
899 int ret
= intel_batchbuffer_flush(brw
);
900 WARN_ONCE(ret
== -ENOSPC
,
901 "i965: Single primitive emit exceeded "
902 "available aperture space\n");
906 /* Now that we know we haven't run out of aperture space, we can safely
907 * reset the dirty bits.
909 if (brw
->ctx
.NewDriverState
)
910 brw_render_state_finished(brw
);
917 all_varyings_in_vbos(const struct gl_vertex_array
*arrays
)
921 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++)
922 if (arrays
[i
].BufferBinding
->Stride
&&
923 arrays
[i
].BufferBinding
->BufferObj
->Name
== 0)
932 brw_draw_prims(struct gl_context
*ctx
,
933 const struct _mesa_prim
*prims
,
935 const struct _mesa_index_buffer
*ib
,
936 GLboolean index_bounds_valid
,
939 struct gl_transform_feedback_object
*gl_xfb_obj
,
941 struct gl_buffer_object
*indirect
)
944 struct brw_context
*brw
= brw_context(ctx
);
945 const struct gl_vertex_array
*arrays
;
946 int predicate_state
= brw
->predicate
.state
;
947 struct brw_transform_feedback_object
*xfb_obj
=
948 (struct brw_transform_feedback_object
*) gl_xfb_obj
;
950 /* The initial pushdown of the inputs array into the drivers */
951 _mesa_set_drawing_arrays(ctx
, brw
->vb
.draw_arrays
.inputs
);
952 arrays
= ctx
->Array
._DrawArrays
;
953 _vbo_update_inputs(ctx
, &brw
->vb
.draw_arrays
);
955 if (!brw_check_conditional_render(brw
))
958 /* Handle primitive restart if needed */
959 if (brw_handle_primitive_restart(ctx
, prims
, nr_prims
, ib
, indirect
)) {
960 /* The draw was handled, so we can exit now */
964 /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
965 * won't support all the extensions we support.
967 if (ctx
->RenderMode
!= GL_RENDER
) {
968 perf_debug("%s render mode not supported in hardware\n",
969 _mesa_enum_to_string(ctx
->RenderMode
));
970 _swsetup_Wakeup(ctx
);
972 _tnl_draw_prims(ctx
, prims
, nr_prims
, ib
,
973 index_bounds_valid
, min_index
, max_index
, NULL
, 0, NULL
);
977 /* If we're going to have to upload any of the user's vertex arrays, then
978 * get the minimum and maximum of their index buffer so we know what range
981 if (!index_bounds_valid
&& !all_varyings_in_vbos(arrays
)) {
982 perf_debug("Scanning index buffer to compute index buffer bounds. "
983 "Use glDrawRangeElements() to avoid this.\n");
984 vbo_get_minmax_indices(ctx
, prims
, ib
, &min_index
, &max_index
, nr_prims
);
985 index_bounds_valid
= true;
988 brw_prepare_drawing(ctx
, arrays
, ib
, index_bounds_valid
, min_index
,
990 /* Try drawing with the hardware, but don't do anything else if we can't
991 * manage it. swrast doesn't support our featureset, so we can't fall back
995 for (i
= 0; i
< nr_prims
; i
++) {
996 /* Implementation of ARB_indirect_parameters via predicates */
997 if (brw
->draw
.draw_params_count_bo
) {
998 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_FLUSH_ENABLE
);
1000 /* Upload the current draw count from the draw parameters buffer to
1001 * MI_PREDICATE_SRC0.
1003 brw_load_register_mem(brw
, MI_PREDICATE_SRC0
,
1004 brw
->draw
.draw_params_count_bo
,
1005 brw
->draw
.draw_params_count_offset
);
1006 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
1007 brw_load_register_imm32(brw
, MI_PREDICATE_SRC0
+ 4, 0);
1008 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
1009 brw_load_register_imm64(brw
, MI_PREDICATE_SRC1
, prims
[i
].draw_id
);
1012 if (i
== 0 && brw
->predicate
.state
!= BRW_PREDICATE_STATE_USE_BIT
) {
1013 OUT_BATCH(GEN7_MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
1014 MI_PREDICATE_COMBINEOP_SET
|
1015 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
);
1017 OUT_BATCH(GEN7_MI_PREDICATE
|
1018 MI_PREDICATE_LOADOP_LOAD
| MI_PREDICATE_COMBINEOP_XOR
|
1019 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
);
1023 brw
->predicate
.state
= BRW_PREDICATE_STATE_USE_BIT
;
1026 brw_draw_single_prim(ctx
, arrays
, &prims
[i
], i
, xfb_obj
, stream
,
1030 brw_finish_drawing(ctx
);
1031 brw
->predicate
.state
= predicate_state
;
1035 brw_draw_indirect_prims(struct gl_context
*ctx
,
1037 struct gl_buffer_object
*indirect_data
,
1038 GLsizeiptr indirect_offset
,
1039 unsigned draw_count
,
1041 struct gl_buffer_object
*indirect_params
,
1042 GLsizeiptr indirect_params_offset
,
1043 const struct _mesa_index_buffer
*ib
)
1045 struct brw_context
*brw
= brw_context(ctx
);
1046 struct _mesa_prim
*prim
;
1049 prim
= calloc(draw_count
, sizeof(*prim
));
1051 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "gl%sDraw%sIndirect%s",
1052 (draw_count
> 1) ? "Multi" : "",
1053 ib
? "Elements" : "Arrays",
1054 indirect_params
? "CountARB" : "");
1059 prim
[draw_count
- 1].end
= 1;
1060 for (i
= 0; i
< draw_count
; ++i
, indirect_offset
+= stride
) {
1061 prim
[i
].mode
= mode
;
1062 prim
[i
].indexed
= ib
!= NULL
;
1063 prim
[i
].indirect_offset
= indirect_offset
;
1064 prim
[i
].is_indirect
= 1;
1065 prim
[i
].draw_id
= i
;
1068 if (indirect_params
) {
1069 brw
->draw
.draw_params_count_bo
=
1070 intel_buffer_object(indirect_params
)->buffer
;
1071 brw_bo_reference(brw
->draw
.draw_params_count_bo
);
1072 brw
->draw
.draw_params_count_offset
= indirect_params_offset
;
1075 brw_draw_prims(ctx
, prim
, draw_count
,
1084 brw_init_draw_functions(struct dd_function_table
*functions
)
1086 /* Register our drawing function:
1088 functions
->Draw
= brw_draw_prims
;
1089 functions
->DrawIndirect
= brw_draw_indirect_prims
;
1093 brw_draw_init(struct brw_context
*brw
)
1095 /* Keep our list of gl_vertex_array inputs */
1096 _vbo_init_inputs(&brw
->vb
.draw_arrays
);
1098 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++)
1099 brw
->vb
.inputs
[i
].buffer
= -1;
1100 brw
->vb
.nr_buffers
= 0;
1101 brw
->vb
.nr_enabled
= 0;
1105 brw_draw_destroy(struct brw_context
*brw
)
1109 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
1110 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
1111 brw
->vb
.buffers
[i
].bo
= NULL
;
1113 brw
->vb
.nr_buffers
= 0;
1115 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
1116 brw
->vb
.enabled
[i
]->buffer
= -1;
1118 brw
->vb
.nr_enabled
= 0;
1120 brw_bo_unreference(brw
->ib
.bo
);