1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include <sys/errno.h>
30 #include "main/glheader.h"
31 #include "main/context.h"
32 #include "main/condrender.h"
33 #include "main/samplerobj.h"
34 #include "main/state.h"
35 #include "main/enums.h"
36 #include "main/macros.h"
37 #include "main/transformfeedback.h"
39 #include "vbo/vbo_context.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "drivers/common/meta.h"
44 #include "brw_blorp.h"
46 #include "brw_defines.h"
47 #include "brw_context.h"
48 #include "brw_state.h"
50 #include "intel_batchbuffer.h"
51 #include "intel_buffers.h"
52 #include "intel_fbo.h"
53 #include "intel_mipmap_tree.h"
54 #include "intel_buffer_objects.h"
56 #define FILE_DEBUG_FLAG DEBUG_PRIMS
58 const GLuint prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1] = {
70 _3DPRIM_LINESTRIP_ADJ
,
76 static const GLenum reduced_prim
[GL_POLYGON
+1] = {
90 /* When the primitive changes, set a state bit and re-validate. Not
91 * the nicest and would rather deal with this by having all the
92 * programs be immune to the active primitive (ie. cope with all
93 * possibilities). That may not be realistic however.
95 static void brw_set_prim(struct brw_context
*brw
,
96 const struct _mesa_prim
*prim
)
98 struct gl_context
*ctx
= &brw
->ctx
;
99 uint32_t hw_prim
= prim_to_hw_prim
[prim
->mode
];
101 DBG("PRIM: %s\n", _mesa_lookup_enum_by_nr(prim
->mode
));
103 /* Slight optimization to avoid the GS program when not needed:
105 if (prim
->mode
== GL_QUAD_STRIP
&&
106 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
107 ctx
->Polygon
.FrontMode
== GL_FILL
&&
108 ctx
->Polygon
.BackMode
== GL_FILL
)
109 hw_prim
= _3DPRIM_TRISTRIP
;
111 if (prim
->mode
== GL_QUADS
&& prim
->count
== 4 &&
112 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
113 ctx
->Polygon
.FrontMode
== GL_FILL
&&
114 ctx
->Polygon
.BackMode
== GL_FILL
) {
115 hw_prim
= _3DPRIM_TRIFAN
;
118 if (hw_prim
!= brw
->primitive
) {
119 brw
->primitive
= hw_prim
;
120 brw
->state
.dirty
.brw
|= BRW_NEW_PRIMITIVE
;
122 if (reduced_prim
[prim
->mode
] != brw
->reduced_primitive
) {
123 brw
->reduced_primitive
= reduced_prim
[prim
->mode
];
124 brw
->state
.dirty
.brw
|= BRW_NEW_REDUCED_PRIMITIVE
;
129 static void gen6_set_prim(struct brw_context
*brw
,
130 const struct _mesa_prim
*prim
)
134 DBG("PRIM: %s\n", _mesa_lookup_enum_by_nr(prim
->mode
));
136 hw_prim
= prim_to_hw_prim
[prim
->mode
];
138 if (hw_prim
!= brw
->primitive
) {
139 brw
->primitive
= hw_prim
;
140 brw
->state
.dirty
.brw
|= BRW_NEW_PRIMITIVE
;
146 * The hardware is capable of removing dangling vertices on its own; however,
147 * prior to Gen6, we sometimes convert quads into trifans (and quad strips
148 * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
149 * This function manually trims dangling vertices from a draw call involving
150 * quads so that those dangling vertices won't get drawn when we convert to
153 static GLuint
trim(GLenum prim
, GLuint length
)
155 if (prim
== GL_QUAD_STRIP
)
156 return length
> 3 ? (length
- length
% 2) : 0;
157 else if (prim
== GL_QUADS
)
158 return length
- length
% 4;
164 static void brw_emit_prim(struct brw_context
*brw
,
165 const struct _mesa_prim
*prim
,
168 int verts_per_instance
;
169 int vertex_access_type
;
170 int start_vertex_location
;
171 int base_vertex_location
;
174 DBG("PRIM: %s %d %d\n", _mesa_lookup_enum_by_nr(prim
->mode
),
175 prim
->start
, prim
->count
);
177 start_vertex_location
= prim
->start
;
178 base_vertex_location
= prim
->basevertex
;
180 vertex_access_type
= brw
->gen
>= 7 ?
181 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
182 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
;
183 start_vertex_location
+= brw
->ib
.start_vertex_offset
;
184 base_vertex_location
+= brw
->vb
.start_vertex_bias
;
186 vertex_access_type
= brw
->gen
>= 7 ?
187 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
:
188 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
189 start_vertex_location
+= brw
->vb
.start_vertex_bias
;
192 /* We only need to trim the primitive count on pre-Gen6. */
194 verts_per_instance
= trim(prim
->mode
, prim
->count
);
196 verts_per_instance
= prim
->count
;
198 /* If nothing to emit, just return. */
199 if (verts_per_instance
== 0 && !prim
->is_indirect
)
202 /* If we're set to always flush, do it before and after the primitive emit.
203 * We want to catch both missed flushes that hurt instruction/state cache
204 * and missed flushes of the render cache as it heads to other parts of
205 * the besides the draw code.
207 if (brw
->always_flush_cache
) {
208 intel_batchbuffer_emit_mi_flush(brw
);
211 /* If indirect, emit a bunch of loads from the indirect BO. */
212 if (prim
->is_indirect
) {
213 struct gl_buffer_object
*indirect_buffer
= brw
->ctx
.DrawIndirectBuffer
;
214 drm_intel_bo
*bo
= intel_bufferobj_buffer(brw
,
215 intel_buffer_object(indirect_buffer
),
216 prim
->indirect_offset
, 5 * sizeof(GLuint
));
218 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
220 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
, bo
,
221 I915_GEM_DOMAIN_VERTEX
, 0,
222 prim
->indirect_offset
+ 0);
223 brw_load_register_mem(brw
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
,
224 I915_GEM_DOMAIN_VERTEX
, 0,
225 prim
->indirect_offset
+ 4);
227 brw_load_register_mem(brw
, GEN7_3DPRIM_START_VERTEX
, bo
,
228 I915_GEM_DOMAIN_VERTEX
, 0,
229 prim
->indirect_offset
+ 8);
231 brw_load_register_mem(brw
, GEN7_3DPRIM_BASE_VERTEX
, bo
,
232 I915_GEM_DOMAIN_VERTEX
, 0,
233 prim
->indirect_offset
+ 12);
234 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
235 I915_GEM_DOMAIN_VERTEX
, 0,
236 prim
->indirect_offset
+ 16);
238 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
239 I915_GEM_DOMAIN_VERTEX
, 0,
240 prim
->indirect_offset
+ 12);
242 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
243 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
255 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2) | indirect_flag
);
256 OUT_BATCH(hw_prim
| vertex_access_type
);
259 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
260 hw_prim
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
263 OUT_BATCH(verts_per_instance
);
264 OUT_BATCH(start_vertex_location
);
265 OUT_BATCH(prim
->num_instances
);
266 OUT_BATCH(prim
->base_instance
);
267 OUT_BATCH(base_vertex_location
);
270 /* Only used on Sandybridge; harmless to set elsewhere. */
271 brw
->batch
.need_workaround_flush
= true;
273 if (brw
->always_flush_cache
) {
274 intel_batchbuffer_emit_mi_flush(brw
);
279 static void brw_merge_inputs( struct brw_context
*brw
,
280 const struct gl_client_array
*arrays
[])
284 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
285 drm_intel_bo_unreference(brw
->vb
.buffers
[i
].bo
);
286 brw
->vb
.buffers
[i
].bo
= NULL
;
288 brw
->vb
.nr_buffers
= 0;
290 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
291 brw
->vb
.inputs
[i
].buffer
= -1;
292 brw
->vb
.inputs
[i
].glarray
= arrays
[i
];
297 * \brief Resolve buffers before drawing.
299 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
300 * enabled depth texture, and flush the render cache for any dirty textures.
302 * (In the future, this will also perform MSAA resolves).
305 brw_predraw_resolve_buffers(struct brw_context
*brw
)
307 struct gl_context
*ctx
= &brw
->ctx
;
308 struct intel_renderbuffer
*depth_irb
;
309 struct intel_texture_object
*tex_obj
;
311 /* Resolve the depth buffer's HiZ buffer. */
312 depth_irb
= intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
314 intel_renderbuffer_resolve_hiz(brw
, depth_irb
);
316 /* Resolve depth buffer and render cache of each enabled texture. */
317 int maxEnabledUnit
= ctx
->Texture
._MaxEnabledTexImageUnit
;
318 for (int i
= 0; i
<= maxEnabledUnit
; i
++) {
319 if (!ctx
->Texture
.Unit
[i
]._Current
)
321 tex_obj
= intel_texture_object(ctx
->Texture
.Unit
[i
]._Current
);
322 if (!tex_obj
|| !tex_obj
->mt
)
324 intel_miptree_all_slices_resolve_depth(brw
, tex_obj
->mt
);
325 intel_miptree_resolve_color(brw
, tex_obj
->mt
);
326 brw_render_cache_set_check_flush(brw
, tex_obj
->mt
->bo
);
331 * \brief Call this after drawing to mark which buffers need resolving
333 * If the depth buffer was written to and if it has an accompanying HiZ
334 * buffer, then mark that it needs a depth resolve.
336 * If the color buffer is a multisample window system buffer, then
337 * mark that it needs a downsample.
339 * Also mark any render targets which will be textured as needing a render
342 static void brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw
)
344 struct gl_context
*ctx
= &brw
->ctx
;
345 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
347 struct intel_renderbuffer
*front_irb
= NULL
;
348 struct intel_renderbuffer
*back_irb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
349 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
350 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
351 struct gl_renderbuffer_attachment
*depth_att
= &fb
->Attachment
[BUFFER_DEPTH
];
353 if (brw_is_front_buffer_drawing(fb
))
354 front_irb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
357 front_irb
->need_downsample
= true;
359 back_irb
->need_downsample
= true;
360 if (depth_irb
&& ctx
->Depth
.Mask
) {
361 intel_renderbuffer_att_set_needs_depth_resolve(depth_att
);
362 brw_render_cache_set_add_bo(brw
, depth_irb
->mt
->bo
);
365 if (ctx
->Extensions
.ARB_stencil_texturing
&&
366 stencil_irb
&& ctx
->Stencil
._WriteEnabled
) {
367 brw_render_cache_set_add_bo(brw
, stencil_irb
->mt
->bo
);
370 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
371 struct intel_renderbuffer
*irb
=
372 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
375 brw_render_cache_set_add_bo(brw
, irb
->mt
->bo
);
379 /* May fail if out of video memory for texture or vbo upload, or on
380 * fallback conditions.
382 static bool brw_try_draw_prims( struct gl_context
*ctx
,
383 const struct gl_client_array
*arrays
[],
384 const struct _mesa_prim
*prims
,
386 const struct _mesa_index_buffer
*ib
,
389 struct gl_buffer_object
*indirect
)
391 struct brw_context
*brw
= brw_context(ctx
);
394 bool fail_next
= false;
397 _mesa_update_state( ctx
);
399 /* Find the highest sampler unit used by each shader program. A bit-count
400 * won't work since ARB programs use the texture unit number as the sampler
403 brw
->wm
.base
.sampler_count
=
404 _mesa_fls(ctx
->FragmentProgram
._Current
->Base
.SamplersUsed
);
405 brw
->gs
.base
.sampler_count
= ctx
->GeometryProgram
._Current
?
406 _mesa_fls(ctx
->GeometryProgram
._Current
->Base
.SamplersUsed
) : 0;
407 brw
->vs
.base
.sampler_count
=
408 _mesa_fls(ctx
->VertexProgram
._Current
->Base
.SamplersUsed
);
410 /* We have to validate the textures *before* checking for fallbacks;
411 * otherwise, the software fallback won't be able to rely on the
412 * texture state, the firstLevel and lastLevel fields won't be
413 * set in the intel texture object (they'll both be 0), and the
414 * software fallback will segfault if it attempts to access any
415 * texture level other than level 0.
417 brw_validate_textures( brw
);
419 intel_prepare_render(brw
);
421 /* This workaround has to happen outside of brw_upload_state() because it
422 * may flush the batchbuffer for a blit, affecting the state flags.
424 brw_workaround_depthstencil_alignment(brw
, 0);
426 /* Resolves must occur after updating renderbuffers, updating context state,
427 * and finalizing textures but before setting up any hardware state for
430 brw_predraw_resolve_buffers(brw
);
432 /* Bind all inputs, derive varying and size information:
434 brw_merge_inputs( brw
, arrays
);
437 brw
->state
.dirty
.brw
|= BRW_NEW_INDICES
;
439 brw
->vb
.min_index
= min_index
;
440 brw
->vb
.max_index
= max_index
;
441 brw
->state
.dirty
.brw
|= BRW_NEW_VERTICES
;
443 for (i
= 0; i
< nr_prims
; i
++) {
444 int estimated_max_prim_size
;
446 estimated_max_prim_size
= 512; /* batchbuffer commands */
447 estimated_max_prim_size
+= (BRW_MAX_TEX_UNIT
*
448 (sizeof(struct brw_sampler_state
) +
449 sizeof(struct gen5_sampler_default_color
)));
450 estimated_max_prim_size
+= 1024; /* gen6 VS push constants */
451 estimated_max_prim_size
+= 1024; /* gen6 WM push constants */
452 estimated_max_prim_size
+= 512; /* misc. pad */
454 /* Flush the batch if it's approaching full, so that we don't wrap while
455 * we've got validated state that needs to be in the same batch as the
458 intel_batchbuffer_require_space(brw
, estimated_max_prim_size
, RENDER_RING
);
459 intel_batchbuffer_save_state(brw
);
461 if (brw
->num_instances
!= prims
[i
].num_instances
||
462 brw
->basevertex
!= prims
[i
].basevertex
) {
463 brw
->num_instances
= prims
[i
].num_instances
;
464 brw
->basevertex
= prims
[i
].basevertex
;
465 if (i
> 0) { /* For i == 0 we just did this before the loop */
466 brw
->state
.dirty
.brw
|= BRW_NEW_VERTICES
;
467 brw_merge_inputs(brw
, arrays
);
471 brw_set_prim(brw
, &prims
[i
]);
473 gen6_set_prim(brw
, &prims
[i
]);
476 /* Note that before the loop, brw->state.dirty.brw was set to != 0, and
477 * that the state updated in the loop outside of this block is that in
478 * *_set_prim or intel_batchbuffer_flush(), which only impacts
479 * brw->state.dirty.brw.
481 if (brw
->state
.dirty
.brw
) {
482 brw
->no_batch_wrap
= true;
483 brw_upload_state(brw
);
486 brw_emit_prim(brw
, &prims
[i
], brw
->primitive
);
488 brw
->no_batch_wrap
= false;
490 if (dri_bufmgr_check_aperture_space(&brw
->batch
.bo
, 1)) {
492 intel_batchbuffer_reset_to_saved(brw
);
493 intel_batchbuffer_flush(brw
);
497 if (intel_batchbuffer_flush(brw
) == -ENOSPC
) {
498 static bool warned
= false;
501 fprintf(stderr
, "i965: Single primitive emit exceeded"
502 "available aperture space\n");
511 /* Now that we know we haven't run out of aperture space, we can safely
512 * reset the dirty bits.
514 if (brw
->state
.dirty
.brw
)
515 brw_clear_dirty_bits(brw
);
518 if (brw
->always_flush_batch
)
519 intel_batchbuffer_flush(brw
);
521 brw_state_cache_check_size(brw
);
522 brw_postdraw_set_buffers_need_resolve(brw
);
527 void brw_draw_prims( struct gl_context
*ctx
,
528 const struct _mesa_prim
*prims
,
530 const struct _mesa_index_buffer
*ib
,
531 GLboolean index_bounds_valid
,
534 struct gl_transform_feedback_object
*unused_tfb_object
,
535 struct gl_buffer_object
*indirect
)
537 struct brw_context
*brw
= brw_context(ctx
);
538 const struct gl_client_array
**arrays
= ctx
->Array
._DrawArrays
;
540 assert(unused_tfb_object
== NULL
);
542 if (!_mesa_check_conditional_render(ctx
))
545 /* Handle primitive restart if needed */
546 if (brw_handle_primitive_restart(ctx
, prims
, nr_prims
, ib
, indirect
)) {
547 /* The draw was handled, so we can exit now */
551 /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
552 * won't support all the extensions we support.
554 if (ctx
->RenderMode
!= GL_RENDER
) {
555 perf_debug("%s render mode not supported in hardware\n",
556 _mesa_lookup_enum_by_nr(ctx
->RenderMode
));
557 _swsetup_Wakeup(ctx
);
559 _tnl_draw_prims(ctx
, prims
, nr_prims
, ib
,
560 index_bounds_valid
, min_index
, max_index
, NULL
, NULL
);
564 /* If we're going to have to upload any of the user's vertex arrays, then
565 * get the minimum and maximum of their index buffer so we know what range
568 if (!index_bounds_valid
&& !vbo_all_varyings_in_vbos(arrays
)) {
569 perf_debug("Scanning index buffer to compute index buffer bounds. "
570 "Use glDrawRangeElements() to avoid this.\n");
571 vbo_get_minmax_indices(ctx
, prims
, ib
, &min_index
, &max_index
, nr_prims
);
574 /* Try drawing with the hardware, but don't do anything else if we can't
575 * manage it. swrast doesn't support our featureset, so we can't fall back
578 brw_try_draw_prims(ctx
, arrays
, prims
, nr_prims
, ib
, min_index
, max_index
, indirect
);
581 void brw_draw_init( struct brw_context
*brw
)
583 struct gl_context
*ctx
= &brw
->ctx
;
584 struct vbo_context
*vbo
= vbo_context(ctx
);
587 /* Register our drawing function:
589 vbo
->draw_prims
= brw_draw_prims
;
591 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++)
592 brw
->vb
.inputs
[i
].buffer
= -1;
593 brw
->vb
.nr_buffers
= 0;
594 brw
->vb
.nr_enabled
= 0;
597 void brw_draw_destroy( struct brw_context
*brw
)
601 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
602 drm_intel_bo_unreference(brw
->vb
.buffers
[i
].bo
);
603 brw
->vb
.buffers
[i
].bo
= NULL
;
605 brw
->vb
.nr_buffers
= 0;
607 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
608 brw
->vb
.enabled
[i
]->buffer
= -1;
610 brw
->vb
.nr_enabled
= 0;
612 drm_intel_bo_unreference(brw
->ib
.bo
);