1 /**************************************************************************
3 * Copyright 2003 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include <sys/errno.h>
30 #include "main/glheader.h"
31 #include "main/context.h"
32 #include "main/condrender.h"
33 #include "main/samplerobj.h"
34 #include "main/state.h"
35 #include "main/enums.h"
36 #include "main/macros.h"
37 #include "main/transformfeedback.h"
39 #include "vbo/vbo_context.h"
40 #include "swrast/swrast.h"
41 #include "swrast_setup/swrast_setup.h"
42 #include "drivers/common/meta.h"
44 #include "brw_blorp.h"
46 #include "brw_defines.h"
47 #include "brw_context.h"
48 #include "brw_state.h"
50 #include "intel_batchbuffer.h"
51 #include "intel_buffers.h"
52 #include "intel_fbo.h"
53 #include "intel_mipmap_tree.h"
54 #include "intel_regions.h"
55 #include "intel_buffer_objects.h"
57 #define FILE_DEBUG_FLAG DEBUG_PRIMS
59 const GLuint prim_to_hw_prim
[GL_TRIANGLE_STRIP_ADJACENCY
+1] = {
71 _3DPRIM_LINESTRIP_ADJ
,
77 static const GLenum reduced_prim
[GL_POLYGON
+1] = {
91 /* When the primitive changes, set a state bit and re-validate. Not
92 * the nicest and would rather deal with this by having all the
93 * programs be immune to the active primitive (ie. cope with all
94 * possibilities). That may not be realistic however.
96 static void brw_set_prim(struct brw_context
*brw
,
97 const struct _mesa_prim
*prim
)
99 struct gl_context
*ctx
= &brw
->ctx
;
100 uint32_t hw_prim
= prim_to_hw_prim
[prim
->mode
];
102 DBG("PRIM: %s\n", _mesa_lookup_enum_by_nr(prim
->mode
));
104 /* Slight optimization to avoid the GS program when not needed:
106 if (prim
->mode
== GL_QUAD_STRIP
&&
107 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
108 ctx
->Polygon
.FrontMode
== GL_FILL
&&
109 ctx
->Polygon
.BackMode
== GL_FILL
)
110 hw_prim
= _3DPRIM_TRISTRIP
;
112 if (prim
->mode
== GL_QUADS
&& prim
->count
== 4 &&
113 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
114 ctx
->Polygon
.FrontMode
== GL_FILL
&&
115 ctx
->Polygon
.BackMode
== GL_FILL
) {
116 hw_prim
= _3DPRIM_TRIFAN
;
119 if (hw_prim
!= brw
->primitive
) {
120 brw
->primitive
= hw_prim
;
121 brw
->state
.dirty
.brw
|= BRW_NEW_PRIMITIVE
;
123 if (reduced_prim
[prim
->mode
] != brw
->reduced_primitive
) {
124 brw
->reduced_primitive
= reduced_prim
[prim
->mode
];
125 brw
->state
.dirty
.brw
|= BRW_NEW_REDUCED_PRIMITIVE
;
130 static void gen6_set_prim(struct brw_context
*brw
,
131 const struct _mesa_prim
*prim
)
135 DBG("PRIM: %s\n", _mesa_lookup_enum_by_nr(prim
->mode
));
137 hw_prim
= prim_to_hw_prim
[prim
->mode
];
139 if (hw_prim
!= brw
->primitive
) {
140 brw
->primitive
= hw_prim
;
141 brw
->state
.dirty
.brw
|= BRW_NEW_PRIMITIVE
;
147 * The hardware is capable of removing dangling vertices on its own; however,
148 * prior to Gen6, we sometimes convert quads into trifans (and quad strips
149 * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
150 * This function manually trims dangling vertices from a draw call involving
151 * quads so that those dangling vertices won't get drawn when we convert to
154 static GLuint
trim(GLenum prim
, GLuint length
)
156 if (prim
== GL_QUAD_STRIP
)
157 return length
> 3 ? (length
- length
% 2) : 0;
158 else if (prim
== GL_QUADS
)
159 return length
- length
% 4;
165 static void brw_emit_prim(struct brw_context
*brw
,
166 const struct _mesa_prim
*prim
,
169 int verts_per_instance
;
170 int vertex_access_type
;
171 int start_vertex_location
;
172 int base_vertex_location
;
175 DBG("PRIM: %s %d %d\n", _mesa_lookup_enum_by_nr(prim
->mode
),
176 prim
->start
, prim
->count
);
178 start_vertex_location
= prim
->start
;
179 base_vertex_location
= prim
->basevertex
;
181 vertex_access_type
= brw
->gen
>= 7 ?
182 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
183 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
;
184 start_vertex_location
+= brw
->ib
.start_vertex_offset
;
185 base_vertex_location
+= brw
->vb
.start_vertex_bias
;
187 vertex_access_type
= brw
->gen
>= 7 ?
188 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
:
189 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
190 start_vertex_location
+= brw
->vb
.start_vertex_bias
;
193 /* We only need to trim the primitive count on pre-Gen6. */
195 verts_per_instance
= trim(prim
->mode
, prim
->count
);
197 verts_per_instance
= prim
->count
;
199 /* If nothing to emit, just return. */
200 if (verts_per_instance
== 0 && !prim
->is_indirect
)
203 /* If we're set to always flush, do it before and after the primitive emit.
204 * We want to catch both missed flushes that hurt instruction/state cache
205 * and missed flushes of the render cache as it heads to other parts of
206 * the besides the draw code.
208 if (brw
->always_flush_cache
) {
209 intel_batchbuffer_emit_mi_flush(brw
);
212 /* If indirect, emit a bunch of loads from the indirect BO. */
213 if (prim
->is_indirect
) {
214 struct gl_buffer_object
*indirect_buffer
= brw
->ctx
.DrawIndirectBuffer
;
215 drm_intel_bo
*bo
= intel_bufferobj_buffer(brw
,
216 intel_buffer_object(indirect_buffer
),
217 prim
->indirect_offset
, 5 * sizeof(GLuint
));
219 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
221 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
, bo
,
222 I915_GEM_DOMAIN_VERTEX
, 0,
223 prim
->indirect_offset
+ 0);
224 brw_load_register_mem(brw
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
,
225 I915_GEM_DOMAIN_VERTEX
, 0,
226 prim
->indirect_offset
+ 4);
228 brw_load_register_mem(brw
, GEN7_3DPRIM_START_VERTEX
, bo
,
229 I915_GEM_DOMAIN_VERTEX
, 0,
230 prim
->indirect_offset
+ 8);
232 brw_load_register_mem(brw
, GEN7_3DPRIM_BASE_VERTEX
, bo
,
233 I915_GEM_DOMAIN_VERTEX
, 0,
234 prim
->indirect_offset
+ 12);
235 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
236 I915_GEM_DOMAIN_VERTEX
, 0,
237 prim
->indirect_offset
+ 16);
239 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
240 I915_GEM_DOMAIN_VERTEX
, 0,
241 prim
->indirect_offset
+ 12);
243 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (3 - 2));
244 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
256 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2) | indirect_flag
);
257 OUT_BATCH(hw_prim
| vertex_access_type
);
260 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
261 hw_prim
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
264 OUT_BATCH(verts_per_instance
);
265 OUT_BATCH(start_vertex_location
);
266 OUT_BATCH(prim
->num_instances
);
267 OUT_BATCH(prim
->base_instance
);
268 OUT_BATCH(base_vertex_location
);
271 /* Only used on Sandybridge; harmless to set elsewhere. */
272 brw
->batch
.need_workaround_flush
= true;
274 if (brw
->always_flush_cache
) {
275 intel_batchbuffer_emit_mi_flush(brw
);
280 static void brw_merge_inputs( struct brw_context
*brw
,
281 const struct gl_client_array
*arrays
[])
285 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
286 drm_intel_bo_unreference(brw
->vb
.buffers
[i
].bo
);
287 brw
->vb
.buffers
[i
].bo
= NULL
;
289 brw
->vb
.nr_buffers
= 0;
291 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
292 brw
->vb
.inputs
[i
].buffer
= -1;
293 brw
->vb
.inputs
[i
].glarray
= arrays
[i
];
294 brw
->vb
.inputs
[i
].attrib
= (gl_vert_attrib
) i
;
299 * \brief Resolve buffers before drawing.
301 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
302 * enabled depth texture, and flush the render cache for any dirty textures.
304 * (In the future, this will also perform MSAA resolves).
307 brw_predraw_resolve_buffers(struct brw_context
*brw
)
309 struct gl_context
*ctx
= &brw
->ctx
;
310 struct intel_renderbuffer
*depth_irb
;
311 struct intel_texture_object
*tex_obj
;
313 /* Resolve the depth buffer's HiZ buffer. */
314 depth_irb
= intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
316 intel_renderbuffer_resolve_hiz(brw
, depth_irb
);
318 /* Resolve depth buffer and render cache of each enabled texture. */
319 for (int i
= 0; i
< ctx
->Const
.MaxCombinedTextureImageUnits
; i
++) {
320 if (!ctx
->Texture
.Unit
[i
]._ReallyEnabled
)
322 tex_obj
= intel_texture_object(ctx
->Texture
.Unit
[i
]._Current
);
323 if (!tex_obj
|| !tex_obj
->mt
)
325 intel_miptree_all_slices_resolve_depth(brw
, tex_obj
->mt
);
326 intel_miptree_resolve_color(brw
, tex_obj
->mt
);
327 brw_render_cache_set_check_flush(brw
, tex_obj
->mt
->region
->bo
);
332 * \brief Call this after drawing to mark which buffers need resolving
334 * If the depth buffer was written to and if it has an accompanying HiZ
335 * buffer, then mark that it needs a depth resolve.
337 * If the color buffer is a multisample window system buffer, then
338 * mark that it needs a downsample.
340 * Also mark any render targets which will be textured as needing a render
343 static void brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw
)
345 struct gl_context
*ctx
= &brw
->ctx
;
346 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
348 struct intel_renderbuffer
*front_irb
= NULL
;
349 struct intel_renderbuffer
*back_irb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
350 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
351 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
352 struct gl_renderbuffer_attachment
*depth_att
= &fb
->Attachment
[BUFFER_DEPTH
];
354 if (brw_is_front_buffer_drawing(fb
))
355 front_irb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
358 front_irb
->need_downsample
= true;
360 back_irb
->need_downsample
= true;
361 if (depth_irb
&& ctx
->Depth
.Mask
) {
362 intel_renderbuffer_att_set_needs_depth_resolve(depth_att
);
363 brw_render_cache_set_add_bo(brw
, depth_irb
->mt
->region
->bo
);
366 if (ctx
->Extensions
.ARB_stencil_texturing
&&
367 stencil_irb
&& ctx
->Stencil
._WriteEnabled
) {
368 brw_render_cache_set_add_bo(brw
, stencil_irb
->mt
->region
->bo
);
371 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
372 struct intel_renderbuffer
*irb
=
373 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
376 brw_render_cache_set_add_bo(brw
, irb
->mt
->region
->bo
);
380 /* May fail if out of video memory for texture or vbo upload, or on
381 * fallback conditions.
383 static bool brw_try_draw_prims( struct gl_context
*ctx
,
384 const struct gl_client_array
*arrays
[],
385 const struct _mesa_prim
*prims
,
387 const struct _mesa_index_buffer
*ib
,
390 struct gl_buffer_object
*indirect
)
392 struct brw_context
*brw
= brw_context(ctx
);
395 bool fail_next
= false;
398 _mesa_update_state( ctx
);
400 /* Find the highest sampler unit used by each shader program. A bit-count
401 * won't work since ARB programs use the texture unit number as the sampler
404 brw
->wm
.base
.sampler_count
=
405 _mesa_fls(ctx
->FragmentProgram
._Current
->Base
.SamplersUsed
);
406 brw
->gs
.base
.sampler_count
= ctx
->GeometryProgram
._Current
?
407 _mesa_fls(ctx
->GeometryProgram
._Current
->Base
.SamplersUsed
) : 0;
408 brw
->vs
.base
.sampler_count
=
409 _mesa_fls(ctx
->VertexProgram
._Current
->Base
.SamplersUsed
);
411 /* We have to validate the textures *before* checking for fallbacks;
412 * otherwise, the software fallback won't be able to rely on the
413 * texture state, the firstLevel and lastLevel fields won't be
414 * set in the intel texture object (they'll both be 0), and the
415 * software fallback will segfault if it attempts to access any
416 * texture level other than level 0.
418 brw_validate_textures( brw
);
420 intel_prepare_render(brw
);
422 /* This workaround has to happen outside of brw_upload_state() because it
423 * may flush the batchbuffer for a blit, affecting the state flags.
425 brw_workaround_depthstencil_alignment(brw
, 0);
427 /* Resolves must occur after updating renderbuffers, updating context state,
428 * and finalizing textures but before setting up any hardware state for
431 brw_predraw_resolve_buffers(brw
);
433 /* Bind all inputs, derive varying and size information:
435 brw_merge_inputs( brw
, arrays
);
438 brw
->state
.dirty
.brw
|= BRW_NEW_INDICES
;
440 brw
->vb
.min_index
= min_index
;
441 brw
->vb
.max_index
= max_index
;
442 brw
->state
.dirty
.brw
|= BRW_NEW_VERTICES
;
444 for (i
= 0; i
< nr_prims
; i
++) {
445 int estimated_max_prim_size
;
447 estimated_max_prim_size
= 512; /* batchbuffer commands */
448 estimated_max_prim_size
+= (BRW_MAX_TEX_UNIT
*
449 (sizeof(struct brw_sampler_state
) +
450 sizeof(struct gen5_sampler_default_color
)));
451 estimated_max_prim_size
+= 1024; /* gen6 VS push constants */
452 estimated_max_prim_size
+= 1024; /* gen6 WM push constants */
453 estimated_max_prim_size
+= 512; /* misc. pad */
455 /* Flush the batch if it's approaching full, so that we don't wrap while
456 * we've got validated state that needs to be in the same batch as the
459 intel_batchbuffer_require_space(brw
, estimated_max_prim_size
, RENDER_RING
);
460 intel_batchbuffer_save_state(brw
);
462 if (brw
->num_instances
!= prims
[i
].num_instances
) {
463 brw
->num_instances
= prims
[i
].num_instances
;
464 brw
->state
.dirty
.brw
|= BRW_NEW_VERTICES
;
465 brw_merge_inputs(brw
, arrays
);
467 if (brw
->basevertex
!= prims
[i
].basevertex
) {
468 brw
->basevertex
= prims
[i
].basevertex
;
469 brw
->state
.dirty
.brw
|= BRW_NEW_VERTICES
;
470 brw_merge_inputs(brw
, arrays
);
473 brw_set_prim(brw
, &prims
[i
]);
475 gen6_set_prim(brw
, &prims
[i
]);
478 /* Note that before the loop, brw->state.dirty.brw was set to != 0, and
479 * that the state updated in the loop outside of this block is that in
480 * *_set_prim or intel_batchbuffer_flush(), which only impacts
481 * brw->state.dirty.brw.
483 if (brw
->state
.dirty
.brw
) {
484 brw
->no_batch_wrap
= true;
485 brw_upload_state(brw
);
488 brw_emit_prim(brw
, &prims
[i
], brw
->primitive
);
490 brw
->no_batch_wrap
= false;
492 if (dri_bufmgr_check_aperture_space(&brw
->batch
.bo
, 1)) {
494 intel_batchbuffer_reset_to_saved(brw
);
495 intel_batchbuffer_flush(brw
);
499 if (intel_batchbuffer_flush(brw
) == -ENOSPC
) {
500 static bool warned
= false;
503 fprintf(stderr
, "i965: Single primitive emit exceeded"
504 "available aperture space\n");
513 /* Now that we know we haven't run out of aperture space, we can safely
514 * reset the dirty bits.
516 if (brw
->state
.dirty
.brw
)
517 brw_clear_dirty_bits(brw
);
520 if (brw
->always_flush_batch
)
521 intel_batchbuffer_flush(brw
);
523 brw_state_cache_check_size(brw
);
524 brw_postdraw_set_buffers_need_resolve(brw
);
529 void brw_draw_prims( struct gl_context
*ctx
,
530 const struct _mesa_prim
*prims
,
532 const struct _mesa_index_buffer
*ib
,
533 GLboolean index_bounds_valid
,
536 struct gl_transform_feedback_object
*unused_tfb_object
,
537 struct gl_buffer_object
*indirect
)
539 struct brw_context
*brw
= brw_context(ctx
);
540 const struct gl_client_array
**arrays
= ctx
->Array
._DrawArrays
;
542 assert(unused_tfb_object
== NULL
);
544 if (!_mesa_check_conditional_render(ctx
))
547 /* Handle primitive restart if needed */
548 if (brw_handle_primitive_restart(ctx
, prims
, nr_prims
, ib
, indirect
)) {
549 /* The draw was handled, so we can exit now */
553 /* If we're going to have to upload any of the user's vertex arrays, then
554 * get the minimum and maximum of their index buffer so we know what range
557 if (!vbo_all_varyings_in_vbos(arrays
) && !index_bounds_valid
) {
558 perf_debug("Scanning index buffer to compute index buffer bounds. "
559 "Use glDrawRangeElements() to avoid this.\n");
560 vbo_get_minmax_indices(ctx
, prims
, ib
, &min_index
, &max_index
, nr_prims
);
563 /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
564 * won't support all the extensions we support.
566 if (ctx
->RenderMode
!= GL_RENDER
) {
567 perf_debug("%s render mode not supported in hardware\n",
568 _mesa_lookup_enum_by_nr(ctx
->RenderMode
));
569 _swsetup_Wakeup(ctx
);
571 _tnl_draw_prims(ctx
, arrays
, prims
, nr_prims
, ib
, min_index
, max_index
);
575 /* Try drawing with the hardware, but don't do anything else if we can't
576 * manage it. swrast doesn't support our featureset, so we can't fall back
579 brw_try_draw_prims(ctx
, arrays
, prims
, nr_prims
, ib
, min_index
, max_index
, indirect
);
582 void brw_draw_init( struct brw_context
*brw
)
584 struct gl_context
*ctx
= &brw
->ctx
;
585 struct vbo_context
*vbo
= vbo_context(ctx
);
588 /* Register our drawing function:
590 vbo
->draw_prims
= brw_draw_prims
;
592 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++)
593 brw
->vb
.inputs
[i
].buffer
= -1;
594 brw
->vb
.nr_buffers
= 0;
595 brw
->vb
.nr_enabled
= 0;
598 void brw_draw_destroy( struct brw_context
*brw
)
602 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
603 drm_intel_bo_unreference(brw
->vb
.buffers
[i
].bo
);
604 brw
->vb
.buffers
[i
].bo
= NULL
;
606 brw
->vb
.nr_buffers
= 0;
608 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
609 brw
->vb
.enabled
[i
]->buffer
= -1;
611 brw
->vb
.nr_enabled
= 0;
613 drm_intel_bo_unreference(brw
->ib
.bo
);